ISL89161FBEAZ [INTERSIL]
High Speed, Dual Channel, 6A, 4.5 to 16VOUT, Power MOSFET Driver; 高速，双通道， 6A ， 4.5〜 16VOUT ，功率MOSFET驱动器
| 型号： | ISL89161FBEAZ |
| 厂家： | 
Intersil |
| 描述： | High Speed, Dual Channel, 6A, 4.5 to 16VOUT, Power MOSFET Driver |
| 文件： | 总14页 (文件大小：252K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Speed, Dual Channel, 6A, 4.5 to 16V ,
OUT
Power MOSFET Driver
ISL89160, ISL89161, ISL89162 Features
• Dual output, 6A peak current (sink and source)
The ISL89160, ISL89162, and ISL89162 are high-speed,
6A, dual channel MOSFET drivers. These parts are
identical to the ISL89163, ISL89164, ISL89165 drivers
but without the enable inputs for each channel.
• Typical ON-resistance <1Ω
• Specified Miller plateau drive currents
• Very low thermal impedance (θ = 3°C/W)
JC
Precision thresholds on all logic inputs allow the use of
external RC circuits to generate accurate and stable time
delays on both inputs, INA and INB. This capability is
very useful for dead time control.
• 3.3V to 5V Logic Inputs with Hysteresis are VDD
tolerant
• Precision threshold inputs for time delays with
external RC components
At high switching frequencies, these MOSFET drivers
use very little bias current. Separate, non-overlapping
drive circuits are used to drive each CMOS output FET
to prevent shoot-thru currents in the output stage.
• ~ 20ns rise and fall time driving a 10nF load.
• Low operating bias currents
• Pb-Free (RoHs Compliant)
The undervoltage lock-out (UV) insures that driver
outputs remain off (low) until VDD is sufficiently high for
correct logic control. This prevents unexpected behaviour
when VDD is being turned on or turned off.
Applications
• Synchronous Rectifier (SR) Driver
• Switch mode power supplies
• Motor Drives, Class D amplifiers, UPS, Inverters
• Pulse Transformer driver
• Clock/Line driver
Related Literature
• AN1602 “ISL8916xA, ISL8916xB, ISL8916xC,
Evaluation Board User’s Guide”
• AN1603 “ISL6752_54 Evaluation Board Application
Note”
Typical Application
Temp Stable Logic Thresholds
3.5
VDD
3.0
NC
2.5
NC
POSITIVE THRESHOLD
8
7
6
5
1
2
3
4
INA
OUTA
2.0
1.5
EPAD
GND
INB
OUTB
4.7µF
NEGATIVE THRESHOLD
1.0
0.5
0.0
-45
-20
5
30
55
80
105
130
TEMPERATURE (°C)
November 2, 2010
FN7719.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774|
1
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
Copyright Intersil Americas Inc. 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL89160, ISL89161, ISL89162
Block Diagram
VDD
Separate FET drives, with
non-overlapping outputs,
prevent shoot-thru
For options A and B, the UV
comparator holds off the
For clarity, only one
channel is shown
outputs until VDD ~> 3.3VDC
.
currents in the output
CMOS FETs resulting with
very low high frequency
operating currents.
For option C, the UV release
is ~> 6.5V
ISL89160
INx
OUTx
10k
ISL89161,
ISL89162
EPAD
GND
For proper thermal and electrical
performance, the EPAD must be
connected to the PCB ground plane.
Pin Configurations
Pin Descriptions
ISL89160FR, ISL89160FB
(8 LD TDFN, EPSOIC)
TOP VIEW
ISL89161FR, ISL89161FB
(8 LD TDFN, EPSOIC)
TOP VIEW
PIN
NUMBER SYMBOL
DESCRIPTION
1
NC
No Connect. This pin may be left open
or connected to 0V or VDD
NC
INA
NC
8
7
6
5
1
2
3
4
NC
/INA
GND
/INB
NC
8
7
6
5
1
2
3
4
2
INA or
/INA
Channel A input, 0V to VDD
OUTA
VDD
OUTB
OUTA
VDD
OUTB
GND
INB
3
4
GND
Power Ground, 0V
INB or
/INB
Channel B enable, 0V to VDD
5
6
7
8
OUTB
VDD
OUTA
NC
Channel B output
ISL89162FR, ISL89162FB
(8 LD TDFN, EPSOIC)
TOP VIEW
Power input, 4.5V to 16V
Channel A output, 0V to VDD
NC
/INA
GND
INB
NC
8
7
6
5
1
2
3
4
No Connect. This pin may be left open
or connected to 0V or VDD
OUTA
VDD
OUTB
EPAD
Power Ground, 0V
FN7719.0
November 2, 2010
2
ISL89160, ISL89161, ISL89162
Ordering Information
PART NUMBER
PART
TEMP RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
(Notes 1, 2, 3)
MARKING
INPUT CONFIGURATION
non-inverting
ISL89160FRTAZ
ISL89161FRTAZ
ISL89162FRTAZ
ISL89160FBEAZ
ISL89161FBEAZ
ISL89162FBEAZ
NOTES:
160A
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
8 Ld 3x3 TDFN
8 Ld 3x3 TDFN
8 Ld 3x3 TDFN
8 Ld EPSOIC
8 Ld EPSOIC
8 Ld EPSOIC
L8.3x3I
161A
inverting
L8.3x3I
L8.3x3I
M8.15D
M8.15D
M8.15D
162A
inverting + non-inverting
non-inverting
89160 FBEAZ
89161 FBEAZ
89162 FBEAZ
inverting
inverting + non-inverting
1. Add “-T*”, suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL89160, ISL89161, ISL89162. For more
information on MSL, please see Technical Brief TB363.
FN7719.0
November 2, 2010
3
ISL89160, ISL89161, ISL89162
Absolute Maximum Ratings
Thermal Information
Supply Voltage, V
DD
Logic Inputs (INA, INB) . . . . . . . . GND - 0.3v to V
Outputs (OUTA, OUTB). . . . . . . . . GND - 0.3v to V
Relative to GND . . . . . . . . -0.3V to 18V
Thermal Resistance (Typical)
θ
(°C/W) θ (°C/W)
JC
JA
+ 0.3V
+ 0.3V
DD
DD
8 Ld TDFN Package (Notes 4, 5). . .
8 Ld EPSOIC Package (Notes 4, 5) .
44
42
3
3
Average Output Current (Note 6) . . . . . . . . . . . . . . . 150mA
Max Power Dissipation at +25°C in Free Air . . . . . . . . .2.27W
Max Power Dissipation at +25°C with Copper Plane . . .33.3W
Storage Temperature Range . . . . . . . . . . . . -65°C to +150°C
Operating Junction Temp Range . . . . . . . . . -40°C to +125°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
ESD Ratings
Human Body Model Class 2 (Tested per JESD22-A114E) 2000V
Machine Model Class B (Tested per JESD22-A115-A) . . . 200V
Charged Device Model Class IV . . . . . . . . . . . . . . . . . 1000V
Latch-Up
Maximum Recommended Operating
Conditions
(Tested per JESD-78B; Class 2, Level A)
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA
Junction Temperature. . . . . . . . . . . . . . . . . -40°C to +125°C
Supply Voltage, V
Relative to GND . . . . . . . . . 4.5V to 16V
DD
Logic Inputs (INA, INB) . . . . . . . . . . . . . . . . . . . 0V to VDD
Outputs (OUTA, OUTB). . . . . . . . . . . . . . . . . . . . 0V to VDD
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
JA
features. See Tech Brief TB379 for details.
5. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
6. The average output current, when driving a power MOSFET or similar capacitive load, is the average of the rectified output
current. The peak output currents of this driver are self limiting by transconductance or r
and do not required any
DS(ON)
external components to minimize the peaks. If the output is driving a non-capacitive load, such as an LED, maximum output
current must be limited by external means to less than the specified absolute maximum.
DC Electrical Specifications
V
= 12V, GND = 0V, No load on OUTA or OUTB, unless otherwise specified.
DD
Boldface limits apply over the operating junction temperature range,
-40°C to +125°C.
T = +25°C
T = -40°C to +125°C
J
J
MIN
MIN TYP MAX (Note 7)
MAX
(Note 7) UNITS
PARAMETERS
POWER SUPPLY
Voltage Range
SYMBOL
TEST CONDITIONS
V
-
-
-
-
5
-
-
4.5
16
-
V
DD
INx = GND
-
-
mA
mA
V
Quiescent Current
I
DD
DD
INA = INB = 1MHz, square wave
25
-
UNDERVOLTAGE
VDD Undervoltage
Lock-out (Note 9)
-
-
3.3
-
-
-
-
-
-
V
INA = INB = True (Note 10)
V
UV
Hysteresis
~25
mV
INPUTs
Input Range for INA, INB
V
-
-
-
-
-
GND
1.12
V
V
V
IN
DD
Logic 0 Threshold
for INA, INB
V
Nominally 37% x 3.3V
Nominally 63% x 3.3V
1.22
1.32
IL
IH
IN
IN
Logic 1 Threshold
for INA, INB
V
C
-
-
-
2.08
-
-
-
1.98
-
2.18
-
V
Input Capacitance of
INA, INB (Note 8)
2
-
pF
µA
Input Bias Current
for INA, INB
I
GND<V <V
IN
-10
+10
DD
FN7719.0
November 2, 2010
4
ISL89160, ISL89161, ISL89162
DC Electrical Specifications
V
= 12V, GND = 0V, No load on OUTA or OUTB, unless otherwise specified.
DD
Boldface limits apply over the operating junction temperature range,
-40°C to +125°C. (Continued)
T = +25°C
T = -40°C to +125°C
J
J
MIN
MIN TYP MAX (Note 7)
MAX
(Note 7) UNITS
PARAMETERS
OUTPUTS
SYMBOL
TEST CONDITIONS
V
V
OHA
OHB
High Level Output Voltage
Low Level Output Voltage
-
-
-
-
-
-
V
- 0.1
V
V
V
DD
DD
V
V
OLA
OLB
GND
GND + 0.1
Peak Output Source
Current
I
V
V
(initial) = 0V, C
LOAD
= 10nF
= 10nF
-
-
-6
-
-
-
-
-
-
A
A
O
O
O
O
Peak Output Sink Current
NOTES:
I
(initial) =12V, C
LOAD
+6
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
8. This parameter is taken from the simulation models for the input FET. The actual capacitance on this input will be dominated
by the PCB parasitic capacitance.
9. A 200µs delay further inhibits the release of the output state when the UV positive going threshold is crossed.
10. The true state of a specific part number is defined by the input logic symbol.
AC Electrical Specifications
V
= 12V, GND = 0V, No Load on OUTA or OUTB, Unless Otherwise Specified.
DD
Boldface limits apply over the operating junction temperature range,
-40°C to +125°C.
T = -40°C
J
TEST
CONDITIONS
/NOTES
T = +25°C
J
to +125°C
PARAMETERS
SYMBOL
MIN TYP MAX
MIN
MAX
UNITS
Output Rise Time (see Figure 2)
t
C
= 10nF,
-
-
-
-
-
-
20
20
25
25
25
25
-
-
-
-
-
-
-
-
-
-
-
-
40
ns
R
LOAD
10% to 90%
Output Fall Time (see Figure 2)
t
C
= 10nF,
LOAD
40
50
50
50
50
ns
ns
ns
ns
ns
F
90% to 10%
Output Rising Edge Propagation Delay for
Non-Inverting Inputs (see Figure 1)
t
t
No load
RDLYn
Output Rising Edge Propagation Delay with
Inverting Inputs (see Figure 1)
t
No load
No load
No load
RDLYi
FDLYn
Output Falling Edge Propagation Delay with
Non-Inverting Inputs (see Figure 1)
Output Falling Edge Propagation Delay with
Inverting Inputs (see Figure 1)
t
FDLYi
Rising Propagation Matching (see Figure 1)
Falling Propagation Matching (see Figure 1)
t
-
-
-
<1ns
<1ns
6
-
-
-
-
-
-
-
-
-
ns
ns
A
RM
t
FM
Miller Plateau Sink Current
(See Test Circuit Figure 3)
-I
-I
-I
V
V
= 10V,
MP
MP
MP
DD
MILLER
= 5V
= 3V
= 2V
V
V
= 10V,
-
-
4.7
3.7
-
-
-
-
-
-
A
A
DD
MILLER
V
V
= 10V,
DD
MILLER
FN7719.0
November 2, 2010
5
ISL89160, ISL89161, ISL89162
AC Electrical Specifications
V
= 12V, GND = 0V, No Load on OUTA or OUTB, Unless Otherwise Specified.
DD
Boldface limits apply over the operating junction temperature range,
-40°C to +125°C. (Continued)
T = -40°C
J
TEST
CONDITIONS
/NOTES
T = +25°C
J
to +125°C
PARAMETERS
SYMBOL
MIN TYP MAX
MIN
MAX
UNITS
Miller Plateau Source Current
(See Test Circuit Figure 4)
I
I
I
V
V
= 10V,
-
-
-
5.2
5.8
6.9
-
-
-
-
-
-
-
A
MP
MP
MP
DD
MILLER
= 5V
= 3V
= 2V
V
V
= 10V,
-
-
A
A
DD
MILLER
V
V
= 10V,
DD
MILLER
Test Waveforms and Circuits
3.3V*
0V
50%
tRDLY
50%
tFDLY
INA,
INB
90%
/OUTA
OUTA
tRDLY
tFDLY
OUTA
10%
/OUTB
OUTB
OR
OUTB
tR
tF
tRM
tFM
* logic levels: A option = 3.3V, B option = 5.0V, C option = VDD
FIGURE 1. PROP DELAYS AND MATCHING
FIGURE 2. RISE/FALL TIMES
10V
ISL8916x 10V
ISL8916x
200ns
0.1µF
10k
0.1µF
10k
VMILLER
VMILLER
10µF
10µF
200ns
10nF
+ISENSE
+ISENSE
10nF
50m
50m
-ISENSE
-ISENSE
FIGURE 3. MILLER PLATEAU SINK CURRENT TEST
CIRCUIT
FIGURE 4. MILLER PLATEAU SOURCE CURRENT TEST
CIRCUIT
FN7719.0
November 2, 2010
6
ISL89160, ISL89161, ISL89162
Test Waveforms and Circuits
Current through
0.1 Resistor
10V
0A
IMP
Ω
VMILLER
VOUT
VOUT
VMILLER
-IMP
0V
Current through
Ω
0.1
Resistor
0
200ns
200ns
FIGURE 5. MILLER PLATEAU SINK CURRENT
FIGURE 6. MILLER PLATEAU SOURCE CURRENT
Typical Performance Curves
3.5
35
+125°C
+125°C
30
25
20
15
10
5
+25°C
-40°C
3.0
+25°C
-40°C
2.5
2.0
4
8
12
16
4
8
12
16
V
V
DD
DD
FIGURE 8. I
vs V
(1 MHz)
DD
FIGURE 7. I
vs V
(STATIC)
DD
DD
DD
50
40
30
20
10
0
1.1
1.0
16V
V
LOW
OUT
NO LOAD
0.9
0.8
0.7
10V
V
HIGH
OUT
12V
5V
0.6
0.5
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
FREQUENCY (MHz)
-45
-20
5
30
TEMPERATURE (°C)
FIGURE 10. r vs TEMPERATURE
55
80
105
130
FIGURE 9. I
vs FREQUENCY (+25°C)
DD
DS(ON)
FN7719.0
November 2, 2010
7
ISL89160, ISL89161, ISL89162
Typical Performance Curves(Continued)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
25
20
15
FALL TIME, C
= 10nF
LOAD
POSITIVE THRESHOLD
NEGATIVE THRESHOLD
RISE TIME, C
LOAD
= 10nF
-45
-20
5
30
55
80
105
130
-45
-20
5
30
TEMPERATURE (°C)
FIGURE 12. OUTPUT RISE/FALL TIME
55
80
105
130
TEMPERATURE (°C)
FIGURE 11. INPUT THRESHOLDS
30
OUTPUT FALLING PROP DELAY
OUTPUT RISING PROP DELAY
25
20
15
5
7
9
11
DD
13
15
V
FIGURE 13. PROPAGATION DELAY vs V
DD
Fast rising (or falling) output drive current of the
Functional Description
Overview
The ISL89160, ISL89161, ISL89162 drivers incorporate
several features including precision input logic
thresholds, undervoltage lock-out, and fast rising high
output drive currents.
ISL89160, ISL89161, ISL89162 minimizes the turn-on
(off) delay due to the input capacitance of the driven FET.
The switching transition period at the Miller plateau is
also minimized by the high drive currents. (See the
specified Miller plateau currents in the AC Electrical
Specifications on page 5).
The precision input thresholds facilitate the use of an
external RC network to delay the rising or falling
propagation of the driver output. This is a useful feature
to create dead times for bridge applications to prevent
shoot through.
Application Information
Precision Thresholds for Time Delays
The nominal input negative transition threshold is 1.22V
and the positive transition threshold is 2.08V (37% and
63% of 3.3V).
To prevent unexpected glitches on the output of the
ISL89160, ISL89161, ISL89162 during power-on or
D
power-off when V
is very low, the Undervoltage (UV)
DD
INx
lock-out prevents the outputs of the ISL89160,
ISL89161, ISL89162 driver from turning on. The UV
lock-out forces the driver outputs to be low when
VDD < ~3.2 VDC regardless of the input logic level.
OUTx
Rdel
cdel
FIGURE 14. DELAY USING RCD NETWORK
FN7719.0
November 2, 2010
8
ISL89160, ISL89161, ISL89162
In Figure 14, R
del
and C delay the rising edge of the
del
12
10
8
input signal. For the falling edge of the input signal, the
diode shorts out the resistor resulting in a minimal falling
edge delay. If the diode polarity is reversed, the falling
edge is delayed and the rising delay is minimal.
V
= 64V
DS
V
DS
= 40V
The 37% and 63% thresholds were chosen to simplify
the calculations for the desired time delays. When using
an RC circuit to generate a time delay, the delay is simply
T (secs) = R (ohms) x C (farads). Please note that this
equation only applies if the input logic voltage amplitude
is 3.3V. If the logic high amplitude is higher than 3.3V,
the equations in EQ 1 can be used for more precise delay
calculations.
6
4
2
High level of the logic signal into the RC
Positive going threshold
V
V
= 5V
0
H
0
2
4
6
8
10 12 14 16 18 20 22 24
GATE CHARGE (nC)
= 63% × 3.3V
THRESH
Q
g,
Low level of the logic signal into the RC
V
R
C
t
= 0.1V
FIGURE 15. MOSFET GATE CHARGE vs GATE VOLTAGE
L
Timing values
= 100Ω
Figure 15 illustrates how the gate charge varies with
the gate voltage in a typical power MOSFET. In this
example, the total gate charge for V = 10V is 21.5nC
del
del
= 1nF
= –R
V
– V
⎛
⎜
⎝
⎞
L
THRESH
gs
--------------------------------------------
C
× LN
+ 1
⎟
del
del del
V
– V
when V
DS
= 40V. This is the charge that a driver must
⎠
H
L
source to turn-on the MOSFET and must sink to
turn-off the MOSFET.
t
= 51.731ns
Nominal delay time
del
(EQ. 1)
Equation 2 shows calculating the power dissipation of
the driver:
In this example, the high input logic voltage is 5V, the
positive threshold is 63% of 3.3V and the low level input
logic is 0.1V. Note the rising edge propagation delay
of the driver must be added to this value.
R
gate
--------------------------------------------
P
= 2 • Q • freq • V
•
+ I (freq) • V
D
c
GS
DD
DD
R
+ r
DS(ON)
gate
(EQ. 2)
The minimum recommended value of C is 100pF. The
parasitic capacitance of the PCB and any attached scope
probes will introduce significant delay errors if smaller
values are used. Larger values of C will further minimize
errors.
where:
freq = Switching frequency,
= V bias of the ISL89160, ISL89161, ISL89162
V
GS
DD
Q = Gate charge for V
c
GS
Acceptable values of R are primarily effected by the
source resistance of the logic inputs. Generally, 100Ω
resistors or larger are usable. A practical maximum
value, limited by contamination on the PCB, is 1MΩ.
I
(freq) = Bias current at the switching frequency
DD
(see Figure 7)
r
= ON-resistance of the driver
DS(ON)
R
= External gate resistance (if any).
Power Dissipation of the Driver
gate
The power dissipation of the ISL89160, ISL89161,
ISL89162 is dominated by the losses associated with the
gate charge of the driven bridge FETs and the switching
frequency. The internal bias current also contributes to
the total dissipation but is usually not significant as
compared to the gate charge losses.
Note that the gate power dissipation is proportionally
shared with the external gate resistor and the output
r
. When sizing an external gate resistor, do not
DS(ON)
overlook the power dissipated by this resistor.
FN7719.0
November 2, 2010
9
ISL89160, ISL89161, ISL89162
Typical Application Circuit
Vbridge
ZVS Full Bridge
SQR
PWM
LL
L
R
L
QUL
QUR
VGUL
VGUR
U1A
SQR
ISL89162
LR
T2
T1A
T1B
VLL
U1B
QLL
QLR
Red dashed lines
emphasize the
resonant
switching delay
of the low-side
bridge FETs
VLR
VGLL
VGLR
VGLL
LL
LR
U2A
½ ISL89160
U2B
½ ISL89160
VGUL
VGLR
VGUR
LL: lower left
LR: lower right
UL: upper left
UR: upper right
GLL: gate lower left
This is an example of how the ISL89160, ISL89161,
ISL89162, MOSFET drivers can be applied in a zero
voltage switching full bridge. Two main signals are
required: a 50% duty cycle square wave (SQR) and a
• When practical, minimize impedances in low level
signal circuits. The noise, magnetically induced on a
10k resistor, is 10x larger than the noise on a 1k
resistor.
PWM signal synchronized to the edges of the SQR input.
An ISL89162 is used to drive T1 with alternating half
• Be aware of magnetic fields emanating from
transformers and inductors. Gaps in these structures
are especially bad for emitting flux.
cycles driving Q and Q . An ISL89160 is used to drive
UL UR
Q
and Q also with alternating half cycles. Unlike the
LR
LL
two high-side bridge FETs, the two low side bridge FETs
are turned on with a rising edge delay. The delay is setup
by the RCD network on the inputs to the ISL89160. The
duration of the delay is chosen to turn on the low-side
FETs when the voltage on their respective drains is at the
resonant valley. For a complete description of the ZVS
topology, refer to AN1603 “ISL6752_54 Evaluation Board
Application Note”.
• If you must have traces close to magnetic devices,
align the traces so that they are parallel to the flux
lines to minimize coupling.
• The use of low inductance components such as chip
resistors and chip capacitors is highly recommended.
• Use decoupling capacitors to reduce the influence of
parasitic inductance in the VDD and GND leads. To
be effective, these caps must also have the shortest
possible conduction paths. If vias are used, connect
several paralleled vias to reduce the inductance of
the vias.
General PCB Layout Guidelines
The AC performance of the ISL89160, ISL89161,
ISL89162 depends significantly on the design of the PC
board. The following layout design guidelines are
recommended to achieve optimum performance:
• It may be necessary to add resistance to dampen
resonating parasitic circuits especially on OUTA and
OUTB. If an external gate resistor is unacceptable,
then the layout must be improved to minimize lead
inductance.
• Place the driver as close as possible to the driven
power FET.
• Understand where the switching power currents flow.
The high amplitude di/dt currents of the driven
power FET will induce significant voltage transients
on the associated traces.
• Keep high dv/dt nodes away from low level circuits.
Guard banding can be used to shunt away dv/dt
injected currents from sensitive circuits. This is
especially true for control circuits that source the
input signals to the ISL89163/164/165.
• Keep power loops as short as possible by paralleling
the source and return traces.
• Avoid having a signal ground plane under a high
amplitude dv/dt circuit. This will inject di/dt currents
into the signal ground paths.
• Use planes where practical; they are usually more
effective than parallel traces.
• Avoid paralleling high amplitude di/dt traces with low
level signal lines. High di/dt will induce currents and
consequently, noise voltages in the low level signal
lines.
• Do power dissipation and voltage drop calculations of
the power traces. Many PCB/CAD programs have
built in tools for calculation of trace resistance.
FN7719.0
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ISL89160, ISL89161, ISL89162
• Large power components (Power FETs, Electrolytic
caps, power resistors, etc.) will have internal
parasitic inductance which cannot be eliminated. This
must be accounted for in the PCB layout and circuit
design.
• If you simulate your circuits, consider including
parasitic components especially parasitic inductance.
General EPAD Heatsinking
Considerations
The thermal pad is electrically connected to the GND
supply through the IC substrate. The epad of the
ISL89163/164/165 has two main functions: to provide a
quiet Gnd for the input threshold comparators and to
provide heat sinking for the IC. The EPAD must be
connected to a ground plane and no switching currents
from the driven FET should pass through the ground
plane under the IC.
Figure 16 is a PCB layout example of how to use vias to
remove heat from the IC through the epad.
EPAD GND
PLANE
EPAD GND
PLANE
BOTTOM
LAYER
COMPONENT LAYER
FIGURE 16. TYPICAL PCB PATTERN FOR THERMAL
VIAS
For maximum heatsinking, it is recommended that a
ground plane, connected to the EPAD, be added to both
sides of the PCB. A via array, within the area of the EPAD,
will conduct heat from the EPAD to the gnd plane on the
bottom layer. The number of vias and the size of the gnd
planes required for adequate heatsinking is determined
by the power dissipated by the ISL89160, ISL89161,
ISL89162, the air flow and the maximum temperature of
the air around the IC.
FN7719.0
November 2, 2010
11
ISL89160, ISL89161, ISL89162
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
CHANGE
11/2/10
FN7719.0
Initial Release
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISL89160, ISL89161, ISL89162
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/sear
FN7719.0
November 2, 2010
12
ISL89160, ISL89161, ISL89162
Package Outline Drawing
L8.3x3I
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 1 6/09
2X 1.950
3.00
A
6X 0.65
B
5
8
(4X)
0.15
1.64 +0.10/ - 0.15
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
4
1
4
8X 0.30
0.10 M C A B
8X 0.400 ± 0.10
TOP VIEW
2.38
+0.10/ - 0.15
BOTTOM VIEW
SEE DETAIL "X"
( 2.38 )
( 1.95)
C
0.10
C
Max 0.80
0.08
C
SIDE VIEW
( 8X 0.60)
(1.64)
( 2.80 )
PIN 1
5
C
0 . 2 REF
(6x 0.65)
0 . 00 MIN.
0 . 05 MAX.
( 8 X 0.30)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN7719.0
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ISL89160, ISL89161, ISL89162
Small Outline Exposed Pad Plastic Packages (EPSOIC)
M8.15D
N
8 LEAD NARROW BODY SMALL OUTLINE EXPOSED PAD
PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
MIN
1.52
0.10
0.36
0.19
4.80
3.811
MAX
1.72
0.25
0.46
0.25
4.98
3.99
NOTES
A
A1
B
C
D
E
e
0.059
0.003
0.0138
0.0075
0.189
0.150
0.067
0.009
0.0192
0.0098
0.196
0.157
-
1
2
3
-
TOP VIEW
9
-
L
3
SEATING PLANE
A
4
-A-
D
0.050 BSC
1.27 BSC
-
h x 45°
H
h
0.230
0.010
0.016
0.244
0.019
0.050
5.84
0.25
0.41
6.20
0.50
1.27
-
-C-
5
α
L
6
e
B
A1
C
N
8
8
7
0.10(0.004)
0°
8°
0°
8°
-
11
α
P
0.25(0.010) M
SIDE VIEW
C A M B S
0.118
0.078
0.137
0.099
3.00
2.00
3.50
2.50
P1
11
Rev. 0 5/07
NOTES:
1
2
3
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
P1
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
N
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
P
BOTTOM VIEW
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
11. Dimensions “P” and “P1” are thermal and/or electrical enhanced
variations. Values shown are maximum size of exposed pad
within lead count and body size.
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7719.0
November 2, 2010
14
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