ISL9001IRCZ-T [INTERSIL]
LDO with Low ISUPPLY, High PSRR; LDO具有低ISUPPLY ，高PSRR
| 型号： | ISL9001IRCZ-T |
| 厂家： | 
Intersil |
| 描述： | LDO with Low ISUPPLY, High PSRR |
| 文件： | 总11页 (文件大小：265K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL9001
®
heet
March 28, 2008
FN9231.2
LDO with Low I
, High PSRR
Features
SUPPLY
ISL9001 is a high performance Low Dropout linear regulator
capable of sourcing 300mA current. It has a low standby
current and high-PSRR and is stable with an output
capacitance of 1µF to 10µF with an ESR of up to 200mΩ.
• 300mA high performance LDO
• Excellent transient response to large current steps
• Excellent load regulation: <0.1% voltage change across
full range of load current
The ISL9001 has a very high PSRR of 90dB and outputs
• High PSRR: 90dB @ 1kHz
noise less than 30µV
. A reference bypass pin allows
RMS
connection of a noise-filtering capacitor for low-noise and
high-PSRR applications. When coupled with a no load
quiescent current of 25µA (typical), and 0.1µA shutdown
current, the ISL9001 is an ideal choice for portable wireless
equipment.
• Wide input voltage capability: 2.3V to 6.5V
• Extremely low quiescent current: 25µA
• Low dropout voltage: typically 200mV @ 300mA
• Low output noise: typically 30µV
@ 100µA (1.5V)
RMS
The ISL9001 provides a power-good signal with delay time
programmable with an external capacitor.
• Stable with 1µF to 10µF ceramic capacitors
• Soft-start to limit input current surge during enable
• Current limit and overheat protection
Several different fixed voltage outputs are standard. Output
voltage options for each LDO range are from 1.5V to 3.3V.
Other output voltage options may be available upon request.
• Delayed POR, programmable with external capacitor
• ±1.8% accuracy over all operating conditions
• Tiny 2mmx3mm 8 Ld DFN package
Pinout
ISL9001
(8 LD 2x3 DFN)
TOP VIEW
• -40°C to +85°C operating temperature range
• Pb-free (RoHS compliant)
VIN
EN
1
2
3
4
8
7
6
5
VO
Applications
POR
NC
• PDAs, cell phones and smart phones
• Portable instruments, MP3 players
• Handheld devices, including medical handhelds
CBYP
CPOR
GND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2006, 2008. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ISL9001
Ordering Information
PART NUMBER
(Notes 1, 2)
VO VOLTAGE
(V) (Note 3)
PACKAGE
(Pb-Free)
PART MARKING
TEMP RANGE (°C)
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
PKG. DWG. #
L8.2x3
ISL9001IRNZ-T
ISL9001IRMZ-T
ISL9001IRLZ-T
ISL9001IRKZ-T
ISL9001IRJZ-T
ISL9001IRRZ-T
ISL9001IRFZ-T
ISL9001IRCZ-T
ISL9001IRBZ-T
NOTES:
EAA
EBA
ECA
EDA
EEA
EFA
EGA
EHA
EJA
3.3
8 Ld 2x3 DFN
8 Ld 2x3 DFN
8 Ld 2x3 DFN
8 Ld 2x3 DFN
8 Ld 2x3 DFN
8 Ld 2x3 DFN
8 Ld 2x3 DFN
8 Ld 2x3 DFN
8 Ld 2x3 DFN
3.0
L8.2x3
L8.2x3
L8.2x3
L8.2x3
L8.2x3
L8.2x3
L8.2x3
L8.2x3
2.9
2.85
2.8
2.6
2.5
1.8
1.5
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte
tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC
J STD-020.
2. Please refer to TB347 for details on reel specifications.
3. For other output voltages, contact Intersil Marketing.
FN9231.2
March 28, 2008
2
ISL9001
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.1V
VO Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.6V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (VIN+0.3)V
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . .2500V
Machine Model (Per EIAJ ED-4701 Method C-111). . . . . . . .200V
Thermal Resistance (Notes 4, 5)
θ
(°C/W)
69
θ
(°C/W)
10
JA
JC
8 Ld 2x3 DFN Package . . . . . . . . . . . .
Junction Temperature Range . . . . . . . . . . . . . . . . .-40°C to +125°C
Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range (T ) . . . . . . . . . . . . . . .-40°C to +85°C
A
Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3V to 6.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
5. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature
range of the device as follows: T = -40°C to +85°C; V = (V + 0.5V) to 5.5V with a minimum V of 2.3V;
A
IN
O
IN
C
= 1µF; C = 1µF.
IN
O
MIN
(Note 8)
MAX
TYP (Note 8) UNITS
PARAMETER
DC CHARACTERISTICS
Supply Voltage
SYMBOL
TEST CONDITIONS
V
2.3
6.5
V
IN
Ground Current
Quiescent condition: I = 0µA
O
I
LDO active
LDO disabled @ +25°C
25
0.1
2.1
1.8
32
1.0
µA
µA
V
DD
Shutdown Current
UVLO Threshold
I
DDS
V
1.9
1.6
2.3
UV+
V
2.0
V
UV-
Regulation Voltage Accuracy
Initial accuracy at V = V + 0.5V, I = 10mA, T = +25°C
IN
-0.7
-0.8
-1.8
+0.7
+0.8
+1.8
%
%
%
O
O
J
V
= V + 0.5V to 5.5V, I = 10µA to 300mA, T = +25°C
O O J
IN
V
= V + 0.5V to 5.5V, I = 10µA to 300mA, T = -40°C
IN
O
O
J
to +125°C
Maximum Output Current
Internal Current Limit
I
Continuous
300
350
mA
mA
mV
mV
mV
°C
MAX
I
V
V
V
T
475
300
250
200
145
110
600
500
400
325
LIM
Dropout Voltage (Note 7)
I
I
I
= 300mA; V < 2.5V
O
DO1
DO2
DO3
SD+
O
O
O
= 300mA; 2.5V ≤ V ≤ 2.8V
O
= 300mA; V > 2.8V
O
Thermal Shutdown Temperature
T
°C
SD-
AC CHARACTERISTICS
Ripple Rejection (Note 6)
I
= 10mA, V = 2.8V (min), V = 1.8V, C
IN BYP
= 0.1µF
O
O
@ 1kHz
90
70
50
30
dB
dB
dB
@ 10kHz
@ 100kHz
Output Noise Voltage (Note 6)
I
= 100µA, V = 1.5V, T = +25°C, C
BYP
= 0.1µF
µV
RMS
O
O
A
BW = 10Hz to 100kHz
FN9231.2
March 28, 2008
3
ISL9001
Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature
range of the device as follows: T = -40°C to +85°C; V = (V + 0.5V) to 5.5V with a minimum V of 2.3V;
A
IN
O
IN
C
= 1µF; C = 1µF. (Continued)
IN
O
MIN
(Note 8)
MAX
TYP (Note 8) UNITS
PARAMETER
SYMBOL
TEST CONDITIONS
DEVICE START-UP CHARACTERISTICS
Device Enable Time
t
Time from assertion of the ENx pin to when the output
voltage reaches 95% of the VO (nom)
250
30
500
60
µs
EN
LDO Soft-start Ramp Rate
t
Slope of linear portion of LDO output voltage ramp during
start-up
µs/V
SSR
EN PIN CHARACTERISTICS
Input Low Voltage
V
-0.3
1.4
0.5
V
V
IL
Input High Voltage
V
V
+ 0.3
IN
IH
Input Leakage Current
Pin Capacitance
I , I
IL IH
0.1
µA
pF
C
Informative
5
PIN
POR PIN CHARACTERISTICS
POR Thresholds
V
As a percentage of nominal output voltage
91
87
94
90
97
93
%
%
POR+
V
POR-
POR Delay
t
t
C
= 0.01µF
POR
100
200
25
300
ms
µs
V
PLH
PHL
POR Pin Output Low Voltage
V
@ I = 1.0mA
OL
0.2
OL
POR Pin Internal Pull-up
Resistance
R
78
100
180
kΩ
POR
NOTES:
6. Limits established by characterization and are not production tested.
7. VOx = 0.98*VOx(NOM); Valid for VOx greater than 1.85V.
8. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested.
EN
t
EN
V
POR+
V
POR+
V
V
POR-
POR-
<t
PHL
VO
t
t
PLH
PHL
POR
FIGURE 1. TIMING PARAMETER DEFINITION
FN9231.2
March 28, 2008
4
ISL9001
Typical Performance Curves
0.8
0.10
0.08
0.06
0.04
0.02
0.00
-0.02
-0.04
-0.06
-0.08
-0.10
V
V
= 3.8V
= 3.3V
IN
O
V
I
= 3.3V
O
= 0mA
0.6
0.4
LOAD
0.2
-40°C
-40°C
0.0
-0.2
+25°C
+25°C
+85°C
-0.4
-0.6
-0.8
+85°C
3.4
3.8
4.2
4.6
5.0
5.4
5.8
6.2
6.6
0
50
100
150
200
250
300
350
400
LOAD CURRENT - I (mA)
INPUT VOLTAGE (V)
O
FIGURE 2. OUTPUT VOLTAGE vs INPUT VOLTAGE (3.3V
OUTPUT)
FIGURE 3. OUTPUT VOLTAGE CHANGE vs LOAD CURRENT
0.10
3.4
V
V
= 3.8V
= 3.3V
= 0mA
IN
O
V
= 3.3V
O
0.08
0.06
0.04
0.02
0.00
-0.02
-0.04
-0.06
I
= 0mA
O
I
3.3
3.2
3.1
3.0
2.9
2.8
LOAD
I
= 150mA
O
I
= 300mA
O
-0.08
-0.10
3.1
3.6
4.1
4.6
5.1
5.6
6.1
6.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
INPUT VOLTAGE (V)
FIGURE 4. OUTPUT VOLTAGE CHANGE vs TEMPERATURE
FIGURE 5. OUTPUT VOLTAGE vs INPUT VOLTAGE (3.3V
OUTPUT)
2.9
350
300
250
V
= 2.8V
O
I
= 0mA
O
2.8
2.7
2.6
2.5
2.4
2.3
V
= 2.8V
O
I
= 150mA
O
200
150
100
50
V
= 3.3V
O
I
= 300mA
O
0
0
50
100
150
200
250
300
350
400
2.6
3.1
3.6
4.1
4.6
5.1
5.6
6.1 6.5
INPUT VOLTAGE (V)
OUTPUT LOAD (mA)
FIGURE 6. OUTPUT VOLTAGE vs INPUT VOLTAGE (2.8V
OUTPUT)
FIGURE 7. DROPOUT VOLTAGE vs LOAD CURRENT
FN9231.2
March 28, 2008
5
ISL9001
Typical Performance Curves (Continued)
40
35
30
25
20
15
10
350
V
= 3.3V
O
300
250
200
150
100
50
+125°C
+25°C
+85°C
+25°C
-40°C
-40°C
V
= 3.3V
O
0
0
50
100
150
200
250
300
350
400
3.0
3.5
4.0
4.58
5.0
5.5
6.0
6.5
OUTPUT LOAD (mA)
INPUT VOLTAGE (V)
FIGURE 8. DROPOUT VOLTAGE vs LOAD CURRENT
FIGURE 9. GROUND CURRENT vs INPUT VOLTAGE
40
200
180
160
140
120
100
80
35
30
25
20
+25°C
+85°C
-40°C
60
V
V
= 3.8V
= 3.3V
IN
O
40
V
V
= 3.8V
= 3.3V
IN
15
10
O
I
= 0µA
LOAD
20
0
0
50
100
150
200
250
300
350
400
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
LOAD CURRENT (mA)
FIGURE 10. GROUND CURRENT vs LOAD
FIGURE 11. GROUND CURRENT vs TEMPERATURE
V
V
= 5.0V
= 2.85V
IN
O
V
= 2.85V
= 150mA
O
I
L
I
= 150mA
= 1µF
L
C
C
5
4
3
2
1
0
L
3
2
1
0
5
0
= 0.01µF
BYP
V
IN
V
O
POR
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8 2.0
0
0.5
1.0 1.5
2.0 2.5
TIME (s)
3.0 3.5
4.0 4.5
5.0
TIME (ms)
FIGURE 12. POWER-UP/POWER-DOWN
FIGURE 13. TURN ON/TURN OFF RESPONSE
FN9231.2
March 28, 2008
6
ISL9001
Typical Performance Curves (Continued)
V
= 3.3V
O
V
= 2.8V
O
I
= 300mA
LOAD
I
= 300mA
LOAD
C
C
= 1µF
LOAD
= 0.01µF
C
C
= 1µF
LOAD
= 0.01µF
BYP
BYP
4.3V
3.6V
4.2V
3.5V
10mV/DIV
10mV/DIV
400µs/DIV
400µs/DIV
FIGURE 14. LINE TRANSIENT RESPONSE, 3.3V OUTPUT
FIGURE 15. LINE TRANSIENT RESPONSE, 2.8V OUTPUT
1000
100
10
V
(25mV/DIV)
O
V
= 1.8V
= 2.8V
O
V
V
= 3.6V
= 1.8V
IN
O
V
IN
I
= 10mA
LOAD
C
C
C
= 0.1µF
BYP
1
300mA
100µA
= 1µF
IN
= 1µF
I
LOAD
LOAD
0.1
10
100
1k
10k
100k
1M
100µs/DIV
FREQUENCY (Hz)
FIGURE 16. LOAD TRANSIENT RESPONSE
FIGURE 17. SPECTRAL NOISE DENSITY vs FREQUENCY
100
90
80
70
60
50
40
30
20
10
V
V
= 3.6V
= 1.8V
= 10mA
IN
O
I
O
C
= 0.1µF
BYP
C
= 1µF
LOAD
0
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 18. PSRR vs FREQUENCY
FN9231.2
March 28, 2008
7
ISL9001
Pin Description
PIN
NUMBER
PIN NAME
DESCRIPTION
1
VIN
Supply Voltage/LDO Input:
Connect a 1µF capacitor to GND.
2
3
EN
LDO Enable.
CBYP
Reference Bypass Capacitor Pin:
Optionally connect capacitor of value 0.01µF to 0.1µF between this pin and GND to achieve lowest noise and
highest PSRR.
4
CPOR
POR Delay Setting Capacitor Pin:
Connect a capacitor between this pin and GND to delay the POR output release after the output reaches 94% of
its specified voltage level. (200ms delay per 0.01µF).
5
6
7
GND
NC
GND is the connection to system ground. Connect to PCB Ground plane.
Do not connect.
POR
Open-drain POR Output (active-low):
Internally connected to VO through 100kΩ resistor.
8
VO
LDO Output:
Connect capacitor of value 1µF to 10µF to GND (1µF recommended).
Typical Application
ISL9001
8
7
1
2
VIN (2.3V TO 5V)
ON
V
VIN
EN
VO
POR
OUT
V
OK
OUT
RESET
(200ms DELAY,
C4 = 0.01µF)
ENABLE
OFF
V
TOO LOW
3
4
OUT
CBYP
CPOR
5
C3
GND
C1
C2
C4
C1, C3: 1µF X5R CERAMIC CAPACITOR
C2: 0.1µF X7R CERAMIC CAPACITOR
C4: 0.01µF X7R CERAMIC CAPACITOR
FN9231.2
March 28, 2008
8
ISL9001
Block Diagram
VIN
VO
SHORT CIRCUIT,
THERMAL PROTECTION,
SOFT-START
CONTROL
LOGIC
UVLO
+
-
EN
+
-
1.0V
VO
GND
POR
POR
1.0V
0.94V
0.9V
BANDGAP AND
TEMPERATURE
SENSOR
VOLTAGE AND
REFERENCE
GENERATOR
DELAY
GND
CPOR
CBYP
During operation, whenever the VIN voltage drops below
about 1.84V, the ISL9001 immediately disables the LDO
output. When VIN rises back above 2.1V, the device
re-initiates its start-up sequence and LDO operation will
resume automatically.
Functional Description
The ISL9001 contains all circuitry required to implement a
high performance LDO. High performance is achieved
through a circuit that delivers fast transient response to
varying load conditions. In a quiescent condition, the
ISL9001 adjusts its biasing to achieve the lowest standby
current consumption.
Reference Generation
The reference generation circuitry includes a trimmed
bandgap, a trimmed voltage reference divider, a trimmed
current reference generator, and an RC noise filter. The filter
includes the external capacitor connected to the CBYP pin.
A 0.01µF capacitor connected to CBYP implements a 100Hz
lowpass filter, and is recommended for most high
The device also integrates current limit protection, smart
thermal shutdown protection, and soft-start. Smart Thermal
shutdown protects the device against overheating.
Power Control
The ISL9001 has an enable pin (EN) to control power to the
LDO output. When EN is low, the device is in shutdown
mode. During this condition, all on-chip circuits are off, and
the device draws minimum current, typically less than 0.1µA.
When the enable pin is asserted, the device first polls the
output of the UVLO detector to ensure that VIN voltage is at
least about 2.1V. Once verified, the device initiates a start-up
sequence. During the start-up sequence, trim settings are
first read and latched. Then, sequentially, the bandgap,
reference voltage and current generation circuitry power-up.
Once the references are stable, a fast-start circuit quickly
charges the external reference bypass capacitor (connected
to the CBYP pin) to the proper operating voltage. Once the
bypass capacitor has been charged, the LDO powers up.
performance applications. For the lowest noise application, a
0.1µF CBYP capacitor should be used. This filters the
reference noise to below the 10Hz to 1kHz frequency band,
which is crucial in many noise-sensitive applications.
The bandgap generates a zero temperature coefficient (TC)
voltage for the reference divider. The reference divider
provides the regulation reference, POR detection thresholds,
and other voltage references required for current generation
and over-temperature detection.
The current generator outputs references required for
adaptive biasing as well as references for LDO output
current limit and thermal shutdown determination.
FN9231.2
March 28, 2008
9
ISL9001
LDO Regulation and Programmable Output Divider
Overheat Detection
The LDO Regulator is implemented with a high-gain
operational amplifier driving a PMOS pass transistor. The
design of the ISL9001 provides a regulator that has low
quiescent current, fast transient response, and overall
stability across all operating and load current conditions.
LDO stability is guaranteed for a 1µF to 10µF output
capacitor that has a tolerance better than 20% and ESR less
than 200mΩ. The design is performance-optimized for a 1µF
capacitor. Unless limited by the application, use of an output
capacitor value above 4.7µF is not recommended as LDO
performance improvement is minimal.
The bandgap outputs a proportional-to-temperature current
that is indicative of the temperature of the silicon. This
current is compared with references to determine if the
device is in danger of damage due to overheating. When the
die temperature reaches about +140°C, if the LDO is
sourcing more than 50mA it shuts down until the die cools
sufficiently. Once the die temperature falls back below about
+110°C, the disabled LDO is re-enabled and soft-start
automatically takes place.
Soft-start circuitry integrated into each LDO limits the initial
ramp-up rate to about 30µs/V to minimize current surge. The
ISL9001 provides short-circuit protection by limiting the
output current to about 425mA.
The LDO uses an independently trimmed 1V reference as its
input. An internal resistor divider drops the LDO output
voltage down to 1V. This is compared to the 1V reference for
regulation. The resistor division ratio is programmed in the
factory.
Power-On Reset Generation
The ISL9001 has a Power-on Reset signal generation
circuit, which indicates that output power is good. The POR
signal is generated as follows.
A POR comparator continuously monitors the output of the
LDO. The LDO enters a power-good state when the output
voltage is above 94% of the expected output voltage for a
period exceeding the LDO PGOOD entry delay time (see the
following). In the power-good state, the open-drain POR
output is in a high-impedance state. An internal 100kΩ
pull-up resistor pulls the pin up to the LDO output voltage. An
external resistor can be added between the POR output and
the LDO output for a faster rise time, however, the POR
output should not connect through an external resistor to a
supply greater than the LDO voltage.
The power-good state is exited when the LDO output falls
below 90% of the expected output voltage for a period longer
than the PGOOD exit delay time. While power-good is false,
the ISL9001 pulls the POR pin low.
The PGOOD entry and exit delays are determined by the
value of an external capacitor connected to the CPOR pin.
For a 0.01µF capacitor, the entry and exit delays are 200ms
and 25µs respectively. Larger or smaller capacitor values will
yield proportionately longer or shorter delay times. The POR
exit delay should never be allowed to be less than 10µs to
ensure sufficient immunity against transient induced false
POR triggering.
FN9231.2
March 28, 2008
10
ISL9001
Dual Flat No-Lead Plastic Package (DFN)
2X
L8.2x3
0.15
C A
8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
A
D
2X
MILLIMETERS
0.15
C B
SYMBOL
MIN
0.80
NOMINAL
MAX
1.00
NOTES
A
A1
A3
b
0.90
-
-
0.20
1.50
1.65
-
0.20 REF
0.25
0.05
-
E
-
6
INDEX
AREA
0.32
1.75
1.90
5,8
D
2.00 BSC
1.65
-
B
A
D2
E
7,8
TOP VIEW
3.00 BSC
1.80
-
// 0.10
0.08
C
E2
e
7,8
0.50 BSC
-
-
C
k
0.20
0.30
-
-
SIDE VIEW
A3
7
C
SEATING
PLANE
L
0.40
0.50
8
N
8
2
D2
D2/2
2
8
Nd
4
3
(DATUM B)
Rev. 0 6/04
NOTES:
1
NX k
6
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
INDEX
AREA
3. Nd refers to the number of terminals on D.
(DATUM A)
E2
4. All dimensions are in millimeters. Angles are in degrees.
E2/2
5. Dimension b applies to the metallized terminal and is measured
between 0.25mm and 0.30mm from the terminal tip.
NX L
8
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
N
N-1
e
NX b
5
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
0.10
M
C A B
(Nd-1)Xe
REF.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
BOTTOM VIEW
C
L
(A1)
NX (b)
5
L
SECTION "C-C"
C C
TERMINAL TIP
e
FOR EVEN TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9231.2
March 28, 2008
11
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