ISL9003AIEJZ-T [INTERSIL]
Low Noise LDO with Low IQ, High PSRR; 低噪声LDO具有低IQ ，高PSRR
| 型号： | ISL9003AIEJZ-T |
| 厂家： | 
Intersil |
| 描述： | Low Noise LDO with Low IQ, High PSRR |
| 文件： | 总11页 (文件大小：206K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL9003A
®
Data Sheet
December 21, 2006
FN6299.1
Low Noise LDO with Low I , High PSRR
Q
Features
ISL9003A is a high performance single low noise, high
PSRR LDO that delivers a continuous 150mA of load
current. It has a low standby current and is stable with 1μF of
MLCC output capacitance with an ESR of up to 200mΩ.
• High performance LDO with 150mA continuous output
• Excellent transient response to large current steps
• Excellent load regulation:
<0.1% voltage change across full range of load current
The ISL9003A has a very high PSRR of 90dB and output
• Very high PSRR: >90dB @ 1kHz
noise is 20μV
(typical). When coupled with a no load
RMS
quiescent current of 31μA (typical), and 0.5μA shutdown
current, the ISL9003A is an ideal choice for portable wireless
equipment.
• Wide input voltage capability: 2.3V to 6.5V
• Extremely low quiescent current: 31μA
• Low dropout voltage: typically 200mV @ 150mA
The ISL9003A comes in many fixed voltage options with
±1.8% output voltage accuracy over temperature, line and
load. Other output voltage options are available on request.
• Low output noise: typically 20μV
RMS
@ 100μA (1.5V)
• Stable with 1µF to 4.7μF ceramic capacitors
• Shutdown pin turns off LDO with 1μA (max) standby
current
Pinouts
ISL9003A
(5 LD SC-70)
TOP VIEW
• Soft-start limits input current surge during enable
• Current limit and overheat protection
VO
VIN
GND
EN
1
2
3
5
• ±1.8% accuracy over all operating conditions
• 5 Ld SC-70 package or 6 Ld μTDFN package
• -40°C to +85°C operating temperature range
• Pb-free plus anneal available (RoHS compliant)
CBYP
4
ISL9003A
(6 LD 1.6x1.6 μTDFN )
Applications
TOP VIEW
• PDAs, cell phones and smart phones
• Portable instruments, MP3 players
• Handheld devices including medical handhelds
VIN
NC
EN
VO
GND
1
2
3
6
5
CBYP
4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2006. All Rights Reserved.
1
All other trademarks mentioned are the property of their respective owners.
ISL9003A
Ordering Information
V
VOLTAGE
(V)
(Note 1)
PACKAGE
Tape and Reel
(Pb-free)
O
PART NUMBER
TEMP. RANGE
(°C)
PKG.
(Note 2)
ISL9003AIENZ-T
ISL9003AIEMZ-T
ISL9003AIEKZ-T
ISL9003AIEJZ-T
ISL9003AIEHZ-T
ISL9003AIEFZ-T
ISL9003AIECZ-T
ISL9003AIEBZ-T
ISL9003AIRUBZ-T
ISL9003AIRUCZ-T
ISL9003AIRUFZ-T
ISL9003AIRUHZ-T
ISL9003AIRUJZ-T
ISL9003AIRUKZ-T
ISL9003AIRUMZ-T
ISL9003AIRUNZ-T
NOTES:
PART MARKING
DWG. #
CBK
CBJ
CCE
CCD
CCC
CCB
CBY
CBW
L
3.3
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
5 Ld SC-70
P5.049
3.0
5 Ld SC-70
5 Ld SC-70
5 Ld SC-70
5 Ld SC-70
5 Ld SC-70
5 Ld SC-70
5 Ld SC-70
6 Ld µTDFN
6 Ld µTDFN
6 Ld µTDFN
6 Ld µTDFN
6 Ld µTDFN
6 Ld µTDFN
6 Ld µTDFN
6 Ld µTDFN
P5.049
2.85
2.8
P5.049
P5.049
2.75
2.5
P5.049
P5.049
1.8
P5.049
1.5
P5.049
1.5
L6.1.6x1.6A
L6.1.6x1.6A
L6.1.6x1.6A
L6.1.6x1.6A
L6.1.6x1.6A
L6.1.6x1.6A
L6.1.6x1.6A
L6.1.6x1.6A
G
1.8
F
2.5
H
2.75
2.8
J
K
2.85
3.0
M
N
3.30
1. For other output voltages, contact Intersil Marketing.
2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN6299.1
December 21, 2006
2
ISL9003A
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.1V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VIN+0.3V)
Thermal Resistance
θ
(°C/W)
JA
5 Ld SC-70 Package (Note 3) . . . . . . . . . . . . . . . . .
6 Ld μTDFN Package (Note 4) . . . . . . . . . . . . . . . .
231
125
Junction Temperature Range . . . . . . . . . . . . . . . . .-40°C to +125°C
Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Recommended Operating Conditions
Ambient Temperature Range (T ) . . . . . . . . . . . . . . .-40°C to +85°C
A
Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 to 6.5V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
4. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature range
of the device as follows: T = -40°C to +85°C; V = (V +0.5V) to 6.5V with a minimum V of 2.3V; C = 1μF;
A
IN
O
IN
IN
C
= 1μF; C = 0.01μF
O
BYP
PARAMETER
DC CHARACTERISTICS
Supply Voltage
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
V
2.3
6.5
40
V
μA
μA
μA
V
IN
Ground Current
I
Output Enabled; I = 0μA; V < 4.2V
IN
31
DD
O
Output Enabled; I = 0μA; Full voltage range
57
O
Shutdown Current
UVLO Threshold
I
0.5
2.1
1.8
1.2
DDS
V
1.9
1.6
2.3
UV+
V
2.0
V
UV-
Regulation Voltage Accuracy
Initial accuracy at V = V +0.5V, I = 10mA, T = +25°C
IN
-0.7
-0.8
+0.7
+0.8
+1.8
%
O
O
J
V
V
= V +0.5V to 6.5V, I = 10μA to150mA, T = +25°C
%
IN
IN
O
O
J
= V +0.5V to 6.5V, I = 10μA to 150mA, T = -40°C to +125°C -1.8
%
O
O
J
Maximum Output Current
Internal Current Limit
I
Continuous
150
175
mA
mA
mV
mV
mV
°C
°C
MAX
I
V
V
V
T
265
300
250
200
140
110
355
500
400
325
LIM
Drop-out Voltage (Note 6)
I
I
I
= 150mA; V < 2.5V
O
DO1
DO2
DO3
SD+
O
O
O
= 150mA; 2.5V ≤ V ≤ 2.8V
O
= 150mA; 2.8V < V
O
Thermal Shutdown Temperature
T
SD-
AC CHARACTERISTICS
Ripple Rejection (Note 5)
I
= 10mA, V = 2.8V(min), V = 1.8V, C
= 0.1µF
O
IN
O
BYP
@ 1kHz
90
70
50
dB
dB
dB
@ 10kHz
@ 100kHz
Output Noise Voltage (Note 5)
V
= 1.5V, T = +25°C, C = 0.1µF
BYP
O
A
BW = 10Hz to 100kHz, I = 100μA
20
30
μV
μV
O
RMS
RMS
BW = 10Hz to 100kHz, I = 10mA
O
DEVICE START-UP CHARACTERISTICS
Device Enable TIme
T
Time from assertion of the EN pin to when the output voltage
reaches 95% of the VO(nom).
250
30
500
60
μs
EN
LDO Soft-start Ramp Rate
T
Slope of linear portion of LDO output voltage ramp during start-up
μs/V
SSR
FN6299.1
December 21, 2006
3
ISL9003A
Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature range
of the device as follows: T = -40°C to +85°C; V = (V +0.5V) to 6.5V with a minimum V of 2.3V; C = 1μF;
A
IN
O
IN
IN
C
= 1μF; C
= 0.01μF (Continued)
O
BYP
PARAMETER
EN PIN CHARACTERISTICS
Input Low Voltage
Input High Voltage
Input Leakage Current
Pin Capacitance
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
V
-0.3
1.4
0.4
V
V
IL
V
V
+0.3
IH
IN
I , I
IL IH
0.1
μA
pF
C
Informative
5
PIN
NOTES:
5. Guaranteed by design and characterization
6. V = 0.98 * V (NOM); Valid for V greater than 1.85V.
O
O
O
Typical Performance Curves
0.8
0.6
0.4
0.2
0.1
V
= 3.3V
V
I
= 3.3V
O
O
= 0mA
+25°C
LOAD
I
= 0mA
O
0.0
0.2
+25°C
0.0
-0.1
-0.2
-0.3
-0.4
I
= 75mA
O
+85°C
-0.2
-0.4
-0.6
-0.8
I
= 150mA
O
-40°C
3.3
3.8
4.3
4.8
5.3
5.8
6.3
3.4
3.8
4.2
4.6
5.0
5.4
5.8
6.2
6.6
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
FIGURE 2. OUTPUT VOLTAGECHANGE (%) vs INPUT
VOLTAGE (3.3V OUTPUT)
FIGURE 1. OUTPUT VOLTAGE vs INPUT VOLTAGE
(3.3V OUTPUT)
1.0
0.10
V
V
= 3.8V
= 3.3V
IN
O
V
V
= 3.8V
= 3.3V
0.8
0.6
0.08
0.06
0.04
0.02
0.00
-0.02
-0.04
-0.06
IN
O
0.4
I
= 0mA
O
0.2
-40°C
I
= 75mA
O
0.0
+25°C
-0.2
-0.4
-0.6
-0.8
-1.0
I
= 150mA
O
+85°C
-0.08
-0.10
-40
-25
0
25
55
85
0
25
50
75
100
125
150
175
TEMPERATURE (°C)
LOAD CURRENT - I (mA)
O
FIGURE 3. OUTPUT VOLTAGE vs LOAD CURRENT
FIGURE 4. OUTPUT VOLTAGE vs TEMPERATURE
FN6299.1
December 21, 2006
4
ISL9003A
Typical Performance Curves (Continued)
2.9
2.8
2.7
2.6
2.5
2.4
2.3
3.4
3.3
3.2
V
= 3.3V
O
3.1
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
+25°C
I
= 0mA
O
I
= 0mA
O
I
= 75mA
O
I
= 75mA
O
I
= 150mA
O
I
= 150mA
O
V
= 2.8V
O
+25°C
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
2.6
3.1
3.6
4.1
4.6
5.1
5.6
6.1
6.6
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
FIGURE 6. DROPOUT VOLTAGE vs INPUT VOLTAGE
(2.8V OUTPUT)
FIGURE 5. DROPOUT VOLTAGE vs INPUT VOLTAGE
(3.3V OUTPUT)
250
200
150
225
V
= 3.3V
O
200
175
150
125
100
75
+25°C
+85°C
V
= 2.8V
O
V
= 3.3V
O
100
50
0
-40°C
50
25
0
0
25
50
75
100
125
150
175
0
25
50
75
100
125
150
175
OUTPUT LOAD (mA)
OUTPUT LOAD (mA)
FIGURE 7. DROPOUT VOLTAGE vs LOAD CURRENT
FIGURE 8. DROPOUT VOLTAGE vs LOAD CURRENT
140
120
100
80
60
V
V
= 3.8V
= 3.3V
IN
O
50
40
30
20
10
0
+85°C
+25°C
+25°C
+85°C
-40°C
60
40
-40°C
20
V
I
= 3.3V
= 0µA
O
O
0
1.5
2.0
2.5 3.0
3.5
4.0
4.5
5.0
5.5
6.0 6.5
0
25
50
75
100
125
150
175
LOAD CURRENT (mA)
INPUT VOLTAGE (V)
FIGURE 10. GROUND CURRENT vs LOAD
FIGURE 9. GROUND CURRENT vs INPUT VOLTAGE
FN6299.1
December 21, 2006
5
ISL9003A
Typical Performance Curves (Continued)
100
I
= 150mA
90
80
70
60
50
40
30
20
L
V
V
= 5.0V
= 3.3V
= 150mA
IN
O
3
2
1
0
5
0
I
L
C
= 1µF
L
I
= 75mA
L
V
V
= 3.8V
= 3.3V
IN
O
I
= 0mA
L
0
100 200 300 400 500 600 700 800 900 1000
TIME (µs)
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
FIGURE 11. GROUND CURRENT vs TEMPERATURE
FIGURE 12. TURN ON/TURN OFF RESPONSE
V
I
= 3.3V
V
I
= 2.8V
O
O
= 150mA
= 150mA
LOAD
LOAD
C
C
= 1μF
= 0.01μF
C
C
= 1μF
= 0.01μF
LOAD
LOAD
BYP
BYP
4.3V
3.6V
4.2V
3.5V
10mV/DIV
10mV/DIV
400μs/DIV
400μs/DIV
FIGURE 13. LINE TRANSIENT RESPONSE, 3.3V OUTPUT
FIGURE 14. LINE TRANSIENT RESPONSE, 2.8V OUTPUT
110
100
V
= 3.3V
= 3.8V
O
90
80
70
60
50
40
30
20
10
10mA
V
IN
50mA
I
LOAD
100mA
100μA
V
V
= 3.9V
= 1.8V
IN
O
VO (10mV/DIV)
1.0 ms/DIV
C
= 0.1μF
BYP
C
= 1μF
LOAD
0.1k
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 15. LOAD TRANSIENT RESPONSE
FIGURE 16. PSRR vs FREQUENCY
FN6299.1
December 21, 2006
6
ISL9003A
Typical Performance Curves (Continued)
2.000
1.000
10mA
0.100
V
V
= 3.9V
= 1.8V
IN
O
100μA
0.010
0.001
C
C
C
= 0.1μF
BYP
= 1μF
IN
LOAD
= 1μF
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 17. SPECTRAL NOISE DENSITY vs FREQUENCY
Pin Description
5 LD SC-70 6 LD µTDFN
PIN #
PIN #
PIN NAME
VIN
DESCRIPTION
Supply Voltage/LDO Input. Connect a 1μF capacitor to GND.
GND is the connection to system ground. Connect to PCB Ground plane.
Output Enable. When this signal goes high, the LDO is turned on.
1
2
3
4
6
2
4
3
GND
EN
CBYP
Reference Bypass Capacitor Pin. Optionally connect capacitor of value 0.01µF to 1µF between this pin
and GND to tune in the desired noise and PSRR performance.
5
-
1
5
VO
NC
LDO Output. Connect a 1µF capacitor of value to GND.
No Connect.
Typical Application
ISL9003A (SC-70)
5
4
1
2
3
VIN (2.3-5V)
ON
VOUT
VIN
GND
EN
VO
ENABLE
OFF
CBYP
C3
C1
C2
C1, C2: 1µF X5R CERAMIC CAPACITOR
C3: 0.1µF X5R CERAMIC CAPACITOR
ISL9003A (µTDFN)
6
1
VIN (2.3-5V)
VOUT
VO
VIN
NC
EN
5
4
2
3
GND
CBYP
ON
ENABLE
OFF
C3
C2
C1, C2: 1µF X5R CERAMIC CAPACITOR
C3: 0.1µF X5R CERAMIC CAPACITOR
C1
FN6299.1
December 21, 2006
7
ISL9003A
Block Diagram
VIN
VO
SHORT CIRCUIT,
THERMAL PROTECTION,
SOFT-START
CONTROL
LOGIC
UVLO
GND
SD
+
-
1.0V
0.94V
0.9V
BANDGAP AND
TEMPERATURE
SENSOR
VOLTAGE AND
REFERENCE
GENERATOR
GND
CBYP
Reference Generation
Functional Description
The reference generation circuitry includes a trimmed
bandgap, a trimmed voltage reference divider, a trimmed
current reference generator, and an RC noise filter. The filter
includes the external capacitor connected to the CBYP pin.
A 0.01μF capacitor connected CBYP implements a 100Hz
lowpass filter, and is recommended for most high
The ISL9003A contains all circuitry required to implement a
high performance LDO. High performance is achieved
through a circuit that delivers fast transient response to
varying load conditions. In a quiescent condition, the
ISL9003A adjusts its biasing to achieve the lowest standby
current consumption.
performance applications. For the lowest noise application, a
0.1μF or greater CBYP capacitor should be used. This filters
the reference noise to below the 10Hz – 1kHz frequency
band, which is crucial in many noise-sensitive applications.
The device also integrates current limit protection, smart
thermal shutdown protection, and soft-start. Smart Thermal
shutdown protects the device against overheating. Soft-start
minimizes start-up input current surges without causing
excessive device turn-on time.
The bandgap generates a zero temperature coefficient (TC)
voltage for the regulator reference and other voltage
references required for current generation and over-
temperature detection.
Power Control
The ISL9003A has an enable pin, EN, to control power to the
LDO output. When EN is low, the device is in shutdown
mode. In this condition, all on-chip circuits are off, and the
device draws minimum current, typically less than 0.3μA.
When the EN pin goes high, the device first polls the output
of the UVLO detector to ensure that VIN voltage is at least
2.1V (typical). Once verified, the device initiates a start-up
sequence. During the start-up sequence, trim settings are
first read and latched. Then, sequentially, the bandgap,
reference voltage and current generation circuitry turn on.
Once the references are stable, the LDO powers up.
A current generator provides references required for
adaptive biasing as well as references for LDO output
current limit and thermal shutdown determination.
LDO Regulation and Programmable Output Divider
The LDO Regulator is implemented with a high-gain
operational amplifier driving a PMOS pass transistor. The
design of the ISL9003A provides a regulator that has low
quiescent current, fast transient response, and overall
stability across all operating and load current conditions.
LDO stability is guaranteed for a 1μF to 4.7μF output
capacitor that has a tolerance better than 20% and ESR less
than 200mΩ. The design is performance-optimized for a 1μF
capacitor. Unless limited by the application, use of an output
capacitor value above 4.7μF is not recommended as LDO
performance improvement is minimal.
During operation, whenever the VIN voltage drops below
about 1.84V, the ISL9003A immediately disables the LDO
output. When VIN rises back above 2.1V (assuming the EN
pin is high), the device re-initiates its start-up sequence and
LDO operation resumes automatically.
FN6299.1
December 21, 2006
8
ISL9003A
Soft-start circuitry integrated into each LDO limits the initial
ramp-up rate to about 30μs/V to minimize current surge. The
ISL9003A provides short-circuit protection by limiting the
output current to about 265mA (typ).
The LDO uses an independently trimmed 1V reference as its
input. An internal resistor divider drops the LDO output
voltage down to 1V. This is compared to the 1V reference for
regulation. The resistor division ratio is programmed in the
factory.
Overheat Detection
The bandgap outputs a proportional-to-temperature current
that is indicative of the temperature of the silicon. This
current is compared with references to determine if the
device is in danger of damage due to overheating. When the
die temperature reaches about +140°C, the LDO
momentarily shuts down until the die cools sufficiently. In the
overheat condition, if the LDO sources more than 50mA it
will be shut off. Once the die temperature falls back below
about +110°C, the disabled LDO is re-enabled and soft-start
automatically takes place.
FN6299.1
December 21, 2006
9
ISL9003A
Ultra Thin Dual Flat No-Lead Plastic Package (UTDFN)
L6.1.6x1.6A
6 LEAD ULTRA THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
A
A
E
B
6
4
MILLIMETERS
SYMBOL
MIN
0.45
-
NOMINAL
0.50
MAX
0.55
0.05
NOTES
D
PIN 1
A
A1
A3
b
-
REFERENCE
2X
0.15 C
-
-
1
3
0.127 REF
0.20
-
2X
0.15 C
TOP VIEW
A1
0.15
1.55
0.40
1.55
0.95
0.25
1.65
0.50
1.65
1.05
-
D
1.60
4
e
1.00 REF
D2
E
0.45
-
4
6
1.60
4
L
E2
e
1.00
-
CO.2
D2
0.50 BSC
0.30
-
DAP SIZE 1.30 x 0.76
L
0.25
0.35
-
3
1
b 6X
0.10 M C A B
Rev. 1 6/06
E2
BOTTOM VIEW
NOTES:
1. Dimensions are in mm. Angles in degrees.
2. Coplanarity applies to the exposed pad as well as the terminals.
Coplanarity shall not exceed 0.08mm.
DETAIL A
3. Warpage shall not exceed 0.10mm.
0.10 C
0.08 C
4. Package length/package width are considered as special
characteristics.
6X
5. JEDEC Reference MO-229.
C
6. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
A3
SEATING
PLANE
SIDE VIEW
0.127±0.008
0.127 +0.058
-0.008
TERMINAL THICKNESS
A1
DETAIL A
0.25
0.50
1.00
1.00
0.45
2.00
0.30
1.25
6
LAND PATTERN
FN6299.1
December 21, 2006
10
ISL9003A
Small Outline Transistor Plastic Packages (SC70-5)
D
P5.049
VIEW C
5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
INCHES MILLIMETERS
MIN
e1
SYMBOL
MAX
0.043
0.004
0.039
0.012
0.010
0.009
0.009
0.085
0.094
0.053
MIN
0.80
0.00
0.80
0.15
0.15
0.08
0.08
1.85
1.80
1.15
MAX
1.10
0.10
1.00
0.30
0.25
0.22
0.20
2.15
2.40
1.35
NOTES
5
1
4
A
A1
A2
b
0.031
0.000
0.031
0.006
0.006
0.003
0.003
0.073
0.071
0.045
-
-
-
-
E
C
L
C
E1
L
2
3
b
b1
c
e
6
6
3
-
C
L
c1
D
0.20 (0.008) M
C
C
C
L
E
E1
e
3
-
SEATING
PLANE
0.0256 Ref
0.0512 Ref
0.010 0.018
0.65 Ref
1.30 Ref
0.26 0.46
A2
A1
A
e1
L
-
-C-
4
-
L1
L2
0.017 Ref.
0.420 Ref.
0.10 (0.004)
C
0.006 BSC
o
0.15 BSC
o
o
o
0
8
0
8
-
α
N
b
WITH
5
5
5
PLATING
b1
R
0.004
0.004
-
0.10
0.15
-
R1
0.010
0.25
c
c1
Rev. 2 9/03
NOTES:
BASE METAL
1. Dimensioning and tolerances per ASME Y14.5M-1994.
2. Package conforms to EIAJ SC70 and JEDEC MO-203AA.
4X θ1
3. Dimensions D and E1 are exclusive of mold flash, protrusions,
or gate burrs.
R1
4. Footlength L measured at reference to gauge plane.
5. “N” is the number of terminal positions.
R
6. These Dimensions apply to the flat section of the lead between
0.08mm and 0.15mm from the lead tip.
GAUGE PLANE
SEATING
PLANE
7. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only.
L
C
α
L2
L1
4X θ1
VIEW C
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6299.1
December 21, 2006
11
相关型号：
©2020 ICPDF网 联系我们和版权申明