ISL9011 [INTERSIL]

Dual LDO with Low Noise, Low IQ, and High PSRR; 双路LDO具有低噪声,低智商,和高PSRR
ISL9011
型号: ISL9011
厂家: Intersil    Intersil
描述:

Dual LDO with Low Noise, Low IQ, and High PSRR
双路LDO具有低噪声,低智商,和高PSRR

文件: 总12页 (文件大小:286K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
ISL9011  
®
Data Sheet  
October 13, 2005  
FN9219.1  
Dual LDO with Low Noise, Low I , and  
Q
Features  
High PSRR  
• Integrates two high performance LDOs  
- VO1 - 150mA output  
ISL9011 is a high performance dual LDO capable of  
sourcing 150mA current from channel 1 and 300mA from  
channel 2. The device has a low standby current and high-  
PSRR and is stable with output capacitance of 1µF to 10µF  
with ESR of up to 200m.  
- VO2 - 300mA output  
• Excellent transient response to large current steps  
• Excellent load regulation:  
• <1% voltage change across full range of load current  
• High PSRR: 70dB @ 1kHz  
A reference bypass pin allows an external capacitor for  
adjusting a noise filter for low noise and high PSRR  
applications.  
• Wide input voltage capability: 2.3V - 6.5V  
• Extremely low quiescent current: 45µA (both LDOs active)  
• Low dropout voltage: typically 120mV @ 150mA  
• Low output noise: typically 30µVrms @ 100µA (1.5V)  
• Stable with 1-10µF ceramic capacitors  
The quiescent current is typically only 45µA with both LDO’s  
enabled and active. Separate enable pins control each  
individual LDO output. When both enable pins are low, the  
device is in shutdown, typically drawing less than 0.1µA.  
Several combinations of voltage outputs are standard.  
Others are available on request. Output voltage options for  
each LDO range from 1.2V to 3.6V.  
• Separate enable pins for each LDO  
• Soft-start to limit input current surge during enable  
• Current limit and overheat protection  
Pinout  
ISL9011  
10 LD 3X3 DFN  
TOP VIEW  
• ±1.8% accuracy over all operating conditions  
• Tiny 10 Ld 3x3mm DFN package  
• -40°C to +85°C operating temperature range  
• Pin compatible with Micrel MIC2211  
1
2
3
4
5
10 VO1  
VIN  
EN1  
9
8
7
6
VO2  
NC  
• Pb-free plus anneal available (RoHS compliant)  
EN2  
NC  
CBYP  
NC  
Applications  
GND  
• PDAs, Cell Phones and Smart Phones  
• Portable Instruments, MP3 Players  
• Handheld Devices including Medical Handhelds  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
Copyright © Intersil Americas Inc. 2005. All Rights Reserved.  
1
All other trademarks mentioned are the property of their respective owners.  
ISL9011  
Ordering Information  
PART NUMBER  
PACKAGE  
(Pb-free)  
(Notes 1, 2, 3)  
PART MARKING VO1 VOLTAGE VO2 VOLTAGE TEMP RANGE (°C)  
PKG. DWG. #  
ISL9011IRVVZ  
DAAL  
DAAM  
DTAA  
DVAA  
DAAN  
DAAP  
DANA  
DBBJ  
DAAR  
DAAS  
DAAT  
DAMA  
DAAV  
DAAW  
DWAA  
DYAA  
DABA  
DAEA  
DAAY  
DALA  
DBBA  
DAKA  
DBCA  
DAJA  
DBDA  
DACA  
DBEA  
DAHA  
DBFA  
DBGA  
DBHA  
DBJA  
DBKA  
DADA  
DBLA  
DBMA  
DBNA  
DBPA  
DAGA  
3.6V  
3.3V  
3.3V  
3.3V  
3.3V  
3.0V  
3.0V  
3.0V  
3.0V  
3.0V  
3.0V  
2.9V  
2.9V  
2.85V  
2.85V  
2.85V  
2.85V  
2.85V  
2.8V  
2.8V  
2.8V  
2.8V  
2.8V  
2.8V  
2.8V  
2.8V  
2.7V  
2.7V  
2.6V  
2.6V  
2.6V  
2.5V  
2.5V  
2.5V  
2.5V  
2.5V  
2.0V  
1.9V  
1.85V  
3.6V  
3.3V  
2.8V  
2.5V  
1.8V  
3.3V  
3.0V  
2.85V  
2.8V  
2.7V  
1.6V  
2.9V  
1.5V  
3.3V  
2.85V  
2.8V  
2.5V  
1.8V  
3.3V  
3.0V  
2.8V  
2.6V  
2.5V  
1.8V  
1.6V  
1.5V  
3.0V  
1.8V  
3.0V  
2.85V  
1.8V  
3.3V  
3.0V  
2.8V  
1.9V  
1.8V  
3.0V  
2.8V  
2.9V  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
ISL9011IRNNZ  
ISL9011IRNJZ  
ISL9011IRNFZ  
ISL9011IRNCZ  
ISL9011IRMNZ  
ISL9011IRMMZ  
ISL9011IRMKZ  
ISL9011IRMJZ  
ISL9011IRMGZ  
ISL9011IRMSZ  
ISL9011IRLLZ  
ISL9011IRLBZ  
ISL9011IRKNZ  
ISL9011IRKKZ  
ISL9011IRKJZ  
ISL9011IRKFZ  
ISL9011IRKCZ  
ISL9011IRJNZ  
ISL9011IRJMZ  
ISL9011IRJJZ  
ISL9011IRJRZ  
ISL9011IRJFZ  
ISL9011IRJCZ  
ISL9011IRJSZ  
ISL9011IRJBZ  
ISL9011IRGMZ  
ISL9011IRGCZ  
ISL9011IRRMZ  
ISL9011IRRKZ  
ISL9011IRRCZ  
ISL9011IRFNZ  
ISL9011IRFMZ  
ISL9011IRFJZ  
ISL9011IRFTZ  
ISL9011IRFCZ  
ISL9011IRDMZ  
ISL9011IRTJZ  
ISL9011IRPLZ  
FN9219.1  
October 13, 2005  
2
ISL9011  
Ordering Information (Continued)  
PART NUMBER  
PACKAGE  
(Pb-free)  
(Notes 1, 2, 3)  
PART MARKING VO1 VOLTAGE VO2 VOLTAGE TEMP RANGE (°C)  
PKG. DWG. #  
ISL9011IRCNZ  
DBRA  
DBSA  
DBTA  
DBVA  
DBWA  
DBYA  
DBBB  
DBBC  
DBBD  
DBBE  
DBBF  
DBBG  
DAFA  
DBBH  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.6V  
1.6V  
1.6V  
1.5V  
1.5V  
1.5V  
1.5V  
1.5V  
3.3V  
3.0V  
2.9V  
2.8V  
2.6V  
2.5V  
3.3V  
2.9V  
2.8V  
3.1V  
2.9V  
2.85V  
2.8V  
1.8V  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
10 Ld 3x3 DFN L10.3x3C  
ISL9011IRCMZ  
ISL9011IRCLZ  
ISL9011IRCJZ  
ISL9011IRCRZ  
ISL9011IRCFZ  
ISL9011IRSNZ  
ISL9011IRSLZ  
ISL9011IRSJZ  
ISL9011IRBUZ  
ISL9011IRBLZ  
ISL9011IRBKZ  
ISL9011IRBJZ  
ISL9011IRBCZ  
NOTES:  
1. Add -T to part number for tape and reel.  
2. For other output voltages, contact Intersil Marketing.  
3. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate  
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are  
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.  
4. Standard products are listed in Bold text. Contact Intersil Marketing on the availability and lead time of other listed devices.  
FN9219.1  
3
October 13, 2005  
ISL9011  
Absolute Maximum Ratings  
Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.1V  
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (V +0.3)V  
IN  
Thermal Information  
Thermal Resistance (Notes 5, 6)  
3x3 DFN Package . . . . . . . . . . . . . . . .  
θ
(°C/W)  
50  
θ
(°C/W)  
10  
JA  
JC  
Junction Temperature Range . . . . . . . . . . . . . . . . .-40°C to +125°C  
Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C  
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C  
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C  
Recommended Operating Conditions  
Ambient Temperature Range (T ) . . . . . . . . . . . . . . . .-40°C to 85°C  
A
Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3V to 6.5V  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the  
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTES:  
5. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See  
JA  
Tech Brief TB379.  
6. θ , “case temperature” location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379.  
JC  
Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature  
range of the device as follows:  
T
= -40°C to +85°C; V = (V +1.0V) to 6.5V with a minimum V of 2.3V; C = 1µF; C = 1µF;  
BYP  
A
IN  
O
IN  
IN  
O
C
= 0.01µF  
PARAMETER  
DC CHARACTERISTICS  
Supply Voltage  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
V
2.3  
6.5  
V
IN  
Ground Current  
Quiescent condition: I = 0µA; I = 0µA  
O1 O2  
I
One LDO active  
Both LDO active  
@25°C  
25  
45  
40  
60  
µA  
µA  
µA  
V
DD1  
DD2  
DDS  
I
Shutdown Current  
UVLO Threshold  
I
0.1  
2.1  
1.8  
1.0  
2.3  
2.0  
+1.8  
V
1.9  
1.6  
UV+  
V
V
UV-  
Regulation Voltage Accuracy  
Variation from nominal voltage output, V = V +0.5 to 5.5V,  
IN  
-1.8  
%
O
T = -40°C to 125°C  
J
Line Regulation  
Load Regulation  
V
= (V  
+1.0V relative to highest output voltage) to 5.5V  
OUT  
-0.2  
0
0.2  
0.7  
1.0  
%/V  
%
IN  
I
I
= 100µA to 150mA (VO1 and VO2)  
= 100µA to 300mA (VO2)  
0.1  
OUT  
OUT  
%
Maximum Output Current  
I
VO1: Continuous  
VO2: Continuous  
150  
300  
350  
mA  
mA  
mA  
mV  
mV  
mV  
mV  
°C  
MAX  
Internal Current Limit  
I
V
V
V
V
T
475  
125  
300  
250  
200  
145  
110  
600  
200  
500  
400  
325  
LIM  
Dropout Voltage (Note 8)  
I
I
I
I
= 150mA; V > 2.1V (VO1)  
O
DO1  
DO2  
DO3  
DO4  
SD+  
O
O
O
O
= 300mA; V < 2.5V (VO2)  
O
= 300mA; 2.5V V 2.8V (VO2)  
O
= 300mA; V > 2.8V (VO2)  
O
Thermal Shutdown Temperature  
T
°C  
SD-  
AC CHARACTERISTICS  
Ripple Rejection (Note 7)  
I
= 10mA, V = 2.8V(min), V = 1.8V, C  
IN  
= 0.1µF  
BYP  
O
O
@ 1kHz  
70  
55  
40  
30  
dB  
dB  
@ 10kHz  
@ 100kHz  
dB  
Output Noise Voltage (Note 7)  
I
= 100µA, V = 1.5V, T = 25°C, C  
BYP  
= 0.1µF  
µVrms  
O
O
A
BW = 10Hz to 100kHz (Note 7)  
FN9219.1  
4
October 13, 2005  
ISL9011  
Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature  
range of the device as follows:  
T
= -40°C to +85°C; V = (V +1.0V) to 6.5V with a minimum V of 2.3V; C = 1µF; C = 1µF;  
BYP  
A
IN  
O
IN  
IN  
O
C
= 0.01µF (Continued)  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
DEVICE START-UP CHARACTERISTICS  
Device Enable TIme  
T
Time from assertion of the ENx pin to when the output voltage  
reaches 95% of the VO(nom)  
250  
30  
500  
60  
µs  
EN  
LDO Soft-start Ramp Rate  
T
Slope of linear portion of LDO output voltage ramp during start-  
up  
µs/V  
SSR  
EN1, EN2 PIN CHARACTERISTICS  
Input Low Voltage  
V
-0.3  
1.4  
0.5  
V
V
IL  
Input High Voltage  
Input Leakage Current  
Pin Capacitance  
V
V
+0.3  
IN  
IH  
I , I  
IL IH  
0.1  
µA  
pF  
C
Informative  
5
PIN  
NOTES:  
7. Guaranteed by design and characterization.  
8. VOx = 0.98 * VOx(NOM); Valid for VOx greater than 1.85V.  
FN9219.1  
5
October 13, 2005  
ISL9011  
Typical Performance Curves  
0.10  
0.08  
0.06  
0.04  
0.02  
0.00  
-0.02  
-0.04  
-0.06  
-0.08  
-0.10  
0.8  
0.6  
0.4  
VIN = 3.8V  
VO = 3.3V  
VO = 3.3V  
= 0mA  
I
LOAD  
0.2  
-40°C  
-40°C  
25°C  
25°C  
0.0  
-0.2  
85°C  
-0.4  
-0.6  
-0.8  
85°C  
0
50  
100  
150  
200  
250  
300  
350  
400  
3.4  
3.8  
4.2  
4.6  
5.0  
5.4  
5.8  
6.2  
6.6  
LOAD CURRENT - I (mA)  
O
INPUT VOLTAGE (V)  
FIGURE 1. OUTPUT VOLTAGE vs INPUT VOLTAGE (3.3V  
OUTPUT)  
FIGURE 2. OUTPUT VOLTAGE CHANGE vs LOAD CURRENT  
0.10  
3.4  
VIN = 3.8V  
VO1 = 3.3V  
0.08  
VO = 3.3V  
I
= 0mA  
O
3.3  
3.2  
3.1  
3.0  
2.9  
2.8  
I
= 0mA  
LOAD  
0.06  
0.04  
0.02  
0.00  
-0.02  
-0.04  
-0.06  
I
= 150mA  
O
-0.08  
-0.10  
3.1  
3.6  
4.1  
4.6  
5.1  
5.6  
6.1  
6.5  
-40 -25 -10  
5
20 35 50 65 80 95 110 125  
TEMPERATURE (°C)  
INPUT VOLTAGE (V)  
FIGURE 3. OUTPUT VOLTAGE CHANGE vs TEMPERATURE  
FIGURE 4. OUTPUT VOLTAGE vs INPUT VOLTAGE  
(VO1 = 3.3V)  
2.9  
350  
300  
VO2 = 2.8V  
I
= 0mA  
O
2.8  
2.7  
2.6  
2.5  
2.4  
2.3  
250  
VO2 = 2.8V  
I
= 150mA  
O
200  
150  
100  
I
= 300mA  
O
VO1 = 3.3V  
50  
0
2.6  
3.1  
3.6  
4.1  
4.6  
5.1  
5.6  
6.1 6.5  
0
50  
100  
150  
200  
250  
300  
350  
400  
INPUT VOLTAGE (V)  
OUTPUT LOAD (mA)  
FIGURE 5. OUTPUT VOLTAGE vs INPUT VOLTAGE  
(VO2 = 2.8V)  
FIGURE 6. DROPOUT VOLTAGE vs LOAD CURRENT  
FN9219.1  
6
October 13, 2005  
ISL9011  
Typical Performance Curves (Continued)  
55  
50  
45  
40  
35  
30  
25  
175  
VO1 = 3.3V  
150  
125  
125°C  
25°C  
85°C  
25°C  
-40°C  
100  
75  
50  
25  
0
-40°C  
VO1 = 3.3V  
VO2 = 2.8V  
I
(BOTH CHANNELS) = 0µA  
O
3.0  
3.5  
4.0  
4.58  
5.0  
5.5  
6.0  
6.5  
0
25  
50  
75  
100  
125  
150  
175  
200  
OUTPUT LOAD (mA)  
INPUT VOLTAGE (V)  
FIGURE 7. VO1 DROPOUT VOLTAGE vs LOAD CURRENT  
FIGURE 8. GROUND CURRENT vs INPUT VOLTAGE  
55  
200  
180  
160  
140  
50  
45  
40  
25°C  
85°C  
120  
100  
80  
60  
40  
20  
0
-40°C  
35  
VIN = 3.8V  
VIN = 3.8V  
VO1 = 3.3V  
VO2 = 2.8V  
VO = 3.3V  
30  
25  
I
= 0µA  
LOAD  
BOTH OUTPUTS ON  
0
50  
100  
150  
200  
250  
300  
350  
400  
-40 -25 -10  
5
20 35 50 65 80 95 110 125  
TEMPERATURE (°C)  
LOAD CURRENT (mA)  
FIGURE 10. GROUND CURRENT vs TEMPERATURE  
FIGURE 9. GROUND CURRENT vs LOAD  
VO1 = 3.3V  
VO2 = 2.8V  
L
VO2 (10mV/DIV)  
5
4
3
2
1
0
I 1 = 150mA  
VIN = 5.0V  
VIN  
VO1  
I 2 = 300mA  
L
3
VO1 = 3.3V  
VO2 = 2.8V  
I 1 = 150mA  
L
2
1
0
5
0
I 2 = 300mA  
L
C -1, C -2 = 1µF  
L
L
VO2  
C
= 0.01µF  
BYP  
0
100 200 300 400 500 600 700 800 900 1000  
TIME (µs)  
0
1
2
3
4
5
6
7
8
9
10  
TIME (s)  
FIGURE 11. POWER-UP/POWER-DOWN  
FIGURE 12. TURN-ON/TURN-OFF RESPONSE  
FN9219.1  
7
October 13, 2005  
ISL9011  
Typical Performance Curves (Continued)  
VO1 = 3.3V  
LOAD  
VO2 = 2.8V  
I = 300mA  
LOAD  
I
= 150mA  
C
C
= 1µF  
C
C
= 1µF  
LOAD  
= 0.01µF  
LOAD  
= 0.01µF  
BYP  
BYP  
4.3V  
3.6V  
4.2V  
3.5V  
10mV/DIV  
10mV/DIV  
400µs/DIV  
400µs/DIV  
FIGURE 13. LINE TRANSIENT RESPONSE, 3.3V OUTPUT  
FIGURE 14. LINE TRANSIENT RESPONSE, 2.8V OUTPUT  
100  
VIN = 3.6V  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
VO = 1.8V  
I
= 10mA  
O
VO (25mV/DIV)  
C
C
= 0.1µF  
BYP  
= 1µF  
LOAD  
VO = 1.8V  
VIN = 2.8V  
300mA  
I
LOAD  
100µA  
0.1  
1
10  
100  
1000  
100µs/DIV  
FREQUENCY (kHz)  
FIGURE 16. PSRR vs FREQUENCY  
FIGURE 15. LOAD TRANSIENT RESPONSE  
1000  
100  
10  
VIN = 3.6V  
VO = 1.8V  
I
= 10mA  
LOAD  
C
C
C
= 0.1µF  
= 1µF  
BYP  
1
IN  
= 1µF  
LOAD  
0.1  
10  
100  
1K  
10K  
100K  
1M  
FREQUENCY (Hz)  
FIGURE 17. SPECTRAL NOISE DENSITY vs FREQUENCY  
FN9219.1  
8
October 13, 2005  
ISL9011  
Pin Description  
PIN  
PIN #  
NAME  
TYPE  
DESCRIPTION  
1
VIN  
Analog I/O  
Supply Voltage / LDO Input:  
Connect a 1µF capacitor to GND.  
2
3
4
EN1  
EN2  
Low Voltage Compatible  
CMOS Input  
LDO-1 Enable.  
Low Voltage Compatible  
CMOS Input  
LDO-2 Enable.  
CBYP  
Analog I/O  
Reference Bypass Capacitor Pin:  
Optionally connect capacitor of value 0.01µF to 1µF between this pin and GND to tune in the  
desired noise and PSRR performance.  
5, 7, 8  
NC  
NC  
No Connection  
6
9
GND  
VO2  
Ground  
GND is the connection to system ground. Connect to PCB Ground plane.  
Analog I/O  
LDO-2 Output:  
Connect capacitor of value 1µF to 10µF to GND (1µF recommended).  
10  
VO1  
Analog I/O  
LDO-1 Output:  
Connect capacitor of value 1µF to 10µF to GND (1µF recommended).  
Typical Application  
ISL9011  
10  
9
1
2
VIN (2.3-6.5V)  
ON  
Vout 1  
Vout 2  
VIN  
VO1  
VO2  
EN1  
Enable 1  
ON  
OFF  
8
7
3
4
EN2  
NC  
NC  
Enable 2  
OFF  
CBYP  
6
5
NC  
GND  
C1  
C2  
C3  
C4  
C1, C3, C4: 1µF X5R ceramic capacitor  
C2: 0.1µF X5R ceramic capacitor  
FN9219.1  
9
October 13, 2005  
ISL9011  
Block Diagram  
VIN  
IS1  
LDO  
ERROR  
AMPLIFIER  
VREF  
TRIM  
VO1  
VO2  
1V  
VO1  
QEN1  
~1.0V  
LDO-1  
LDO-2  
EN1  
EN2  
CONTROL  
LOGIC  
BANDGAP AND  
TEMPERATURE  
SENSOR  
VOLTAGE  
REFERENCE  
GENERATOR  
1.00V  
UVLO  
GND  
CBYP  
mode. During this condition, all on-chip circuits are off, and  
the device draws minimum current, typically less than 0.1µA.  
When one or both of the enable pins are asserted, the  
device first polls the output of the UVLO detector to ensure  
that VIN voltage is at least about 2.1V. Once verified, the  
device initiates a start-up sequence. During the start-up  
sequence, trim settings are first read and latched. Then,  
sequentially, the bandgap, reference voltage and current  
generation circuitry power up. Once the references are  
stable, a fast-start circuit quickly charges the external  
reference bypass capacitor (connected to the CBYP pin) to  
the proper operating voltage. After the bypass capacitor has  
been charged, the LDO’s power up.  
Functional Description  
The ISL9011 contains all circuitry required to implement two  
high performance LDO’s. High performance is achieved  
through a circuit that delivers fast transient response to  
varying load conditions. In a quiescent condition, the  
ISL9011 adjusts its biasing to achieve the lowest standby  
current consumption.  
The device also integrates current limit protection, smart  
thermal shutdown protection, staged turn-on and soft-start.  
Smart Thermal shutdown protects the device against  
overheating. Staged turn-on and soft-start minimize start-up  
input current surges without causing excessive device turn-  
on time.  
If EN1 is brought high, and EN2 is goes high before the VO1  
output stablizes, the ISL9011 delays the VO2 turn-on until  
the VO1 output reaches its target level. This minimizes input  
current surge due to concurrent turn-on.  
Power Control  
The ISL9011 has two separate enable pins, EN1 and EN2,  
to individually control power to each of the LDO outputs.  
When both EN1 and EN2 are low, the device is in shutdown  
FN9219.1  
10  
October 13, 2005  
ISL9011  
If EN2 is brought high, and EN1 goes high before the VO2  
output stablizes, the ISL9011 delays the VO1 turn-on until  
the VO2 output reaches its target level.  
Overheat Detection  
The bandgap outputs a proportional-to-temperature current  
that is indicative of the temperature of the silicon. This  
current is compared with references to determine if the  
device is in danger of damage due to overheating. When the  
die temperature reaches about 145°C, one or both of the  
LDO’s momentarily shut down until the die cools sufficiently.  
In the overheat condition, only the LDO sourcing more than  
50mA will be shut off. This does not affect the operation of  
the other LDO. If both LDOs source more than 50mA and an  
overheat condition occurs, both LDO outputs are disabled.  
Once the die temperature falls back below about 110°C, the  
disabled LDO(s) are re-enabled and soft-start automatically  
takes place.  
If both EN1 and EN2 are brought high at the same time, the  
VO1 output has priority, and is always powered up first.  
During operation, whenever the VIN voltage drops below  
about 1.8V, the ISL9011 immediately disables both LDO  
outputs. When VIN rises back above 2.1V, the device re-  
initiates its start-up sequence and LDO operation will  
resume automatically.  
Reference Generation  
The reference generation circuitry includes a trimmed  
bandgap, a trimmed voltage reference divider, a trimmed  
current reference generator, and an RC noise filter. The filter  
includes the external capacitor connected to the CBYP pin.  
A 0.01µF capacitor connected CBYP implements a 100Hz  
lowpass filter, and is recommended for most high  
performance applications. For the lowest noise application, a  
0.1µF or greater CBYP capacitor should be used. This filters  
the reference noise to below the 10Hz – 1kHz frequency  
band, which is crucial in many noise-sensitive applications.  
The bandgap generates a zero temperature coefficient (TC)  
voltage for the reference divider. The reference divider  
provides the regulation reference and other voltage  
references required for current generation and over-  
temperature detection.  
The current generator outputs references required for  
adaptive biasing as well as references for LDO output  
current limit and thermal shutdown determination.  
LDO Regulation and Programmable Output Divider  
The LDO Regulator is implemented with a high-gain  
operational amplifier driving a PMOS pass transistor. The  
design of the ISL9011 provides a regulator that has low  
quiescent current, fast transient response, and overall  
stability across all operating and load current conditions.  
LDO stability is guaranteed for a 1µF to 10µF output  
capacitor that has a tolerance better than 20% and ESR less  
than 200m. The design is performance-optimized for a 1µF  
capacitor. Unless limited by the application, use of an output  
capacitor value above 4.7µF is not recommended as LDO  
performance improvement is minimal.  
Soft-start circuitry integrated into each LDO limits the initial  
ramp-up rate to about 30µs/V to minimize current surge. The  
ISL9011 provides short-circuit protection by limiting the  
output current to about 475mA.  
Each LDO uses an independently trimmed 1V reference. An  
internal resistor divider drops the LDO output voltage down  
to 1V. This is compared to the 1V reference for regulation.  
The resistor division ratio is programmed in the factory.  
FN9219.1  
11  
October 13, 2005  
ISL9011  
Dual Flat No-Lead Plastic Package (DFN)  
L10.3x3C  
2X  
10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE  
MILLIMETERS  
0.15 C  
A
A
D
2X  
0.15  
C B  
SYMBOL  
MIN  
0.80  
NOMINAL  
0.90  
MAX  
1.00  
NOTES  
A
A1  
A3  
b
-
-
0.18  
2.23  
1.49  
-
0.05  
-
E
0.20 REF  
0.25  
-
6
0.30  
2.48  
1.74  
5, 8  
INDEX  
AREA  
D
3.00 BSC  
2.38  
-
D2  
E
7, 8  
TOP VIEW  
SIDE VIEW  
B
A
3.00 BSC  
1.64  
-
// 0.10  
0.08  
C
E2  
e
7, 8  
0.50 BSC  
-
-
C
k
0.20  
0.30  
-
-
A3  
C
L
0.40  
0.50  
8
SEATING  
PLANE  
N
10  
2
Nd  
5
3
D2  
D2/2  
2
7
8
(DATUM B)  
Rev. 0 3/05  
NOTES:  
1
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.  
2. N is the number of terminals.  
3. Nd refers to the number of terminals on D.  
6
INDEX  
NX k  
E2  
AREA  
(DATUM A)  
4. All dimensions are in millimeters. Angles are in degrees.  
5. Dimension b applies to the metallized terminal and is measured  
E2/2  
between 0.15mm and 0.30mm from the terminal tip.  
6. The configuration of the pin #1 identifier is optional, but must be  
located within the zone indicated. The pin #1 identifier may be  
either a mold or mark feature.  
NX L  
N
N-1  
NX b  
8
e
5
7. Dimensions D2 and E2 are for the exposed pads which provide  
(Nd-1)Xe  
M
improved electrical and thermal performance.  
0.10  
C A B  
REF.  
8. Nominal dimensions are provided to assist with PCB Land  
Pattern Design efforts, see Intersil Technical Brief TB389.  
BOTTOM VIEW  
(A1)  
9. COMPLIANT TO JEDEC MO-229-WEED-3 except for  
C
L
dimensions E2 & D2.  
NX (b)  
L
9
5
e
SECTION "C-C"  
TERMINAL TIP  
C C  
FOR ODD TERMINAL/SIDE  
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.  
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality  
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without  
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and  
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result  
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see www.intersil.com  
FN9219.1  
12  
October 13, 2005  

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