ISL9104AIRUFZ-T [INTERSIL]
500mA 4.3MHz Low IQ High Efficiency Synchronous Buck Converter; 500毫安4.3MHz低智商高效率同步降压转换器
| 型号： | ISL9104AIRUFZ-T |
| 厂家： | 
Intersil |
| 描述： | 500mA 4.3MHz Low IQ High Efficiency Synchronous Buck Converter |
| 文件： | 总13页 (文件大小：353K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL9104, ISL9104A
®
Data Sheet
July 9, 2009
FN6829.3
500mA 4.3MHz Low I High Efficiency
Q
Features
Synchronous Buck Converter
• High Efficiency Integrated Synchronous Buck Regulator
with up to 93% Efficiency
The ISL9104, ISL9104A is a 500mA, 4.3MHz step-down
regulator, which is ideal for powering low-voltage
• 2.7V to 6.0V Supply Voltage
microprocessors in compact devices such as PDAs and
cellular phones. It is optimized for generating low output
voltages down to 0.8V. The supply voltage range is from
2.7V to 6V allowing the use of a single Li+ cell, three NiMH
cells or a regulated 5V input. It has guaranteed minimum
output current of 500mA. A high switching frequency of
4.3MHz pulse-width modulation (PWM) allows using small
external components. Under light load condition, the device
• 4.3MHz PWM Switching Frequency
• 500mA Guaranteed Output Current
• 3% Output Accuracy Over-Temperature and Line for Fixed
Output Options
• 20µA Quiescent Supply Current in Skip Mode
• Less than 1µA Logic Controlled Shutdown Current
• 100% Maximum Duty Cycle for Lowest Dropout
operates at low I skip mode with typical 20µA quiescent
Q
current for highest light load efficiency to maximize battery
life, and it automatically switches to fixed frequency PWM
mode under heavy load condition.
• Ultrasonic Switching Frequency at Skip Mode to Prevent
Audible Frequency Noise (For ISL9104A Only)
• Discharge Output Capacitor when Disabled
• Internal Digital Soft-Start
The ISL9104, ISL9104A includes a pair of low
ON-resistance P-Channel and N-Channel internal MOSFETs
to maximize system efficiency and minimize the external
component count. 100% duty-cycle operation allows less
than 300mV dropout voltage at 500mA.
• Peak Current Limiting, Short Circuit Protection
• Over-Temperature Protection
The ISL9104, ISL9104A offers internal digital soft-start,
enable for power sequence, overcurrent protection and
thermal shutdown functions. In addition, the ISL9104,
ISL9104A offers a quick bleeding function that discharges
the output capacitor when the IC is disabled.
• Chip Enable
• Small 6 Pin 1.6mmx1.6mm µTDFN Package
• Pb-Free (RoHS Compliant)
Applications
The ISL9104, ISL9104A is offered in a 1.6x1.6mm µTDFN
package. The complete converter occupies less than
• Single Li-ion Battery-Powered Equipment
• Mobile Phones and MP3 Players
• PDAs and Palmtops
2
0.5CM .
Pinout
• WCDMA Handsets
ISL9104, ISL9104A
(6 LD 1.6x1.6 µTDFN)
TOP VIEW
• Portable Instruments
VIN
EN
NC
1
2
3
6
5
4
SW
GND
FB
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008, 2009. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ISL9104, ISL9104A
Ordering Information
OUTPUT
PART NUMBER
(Notes 1, 3)
PART
MARKING
VOLTAGE
(V) (Note 2)
TEMP RANGE
PACKAGE
(Pb-Free)
PKG
DWG. #
ULTRASONIC
FUNCTION
(°C)
ISL9104IRUNZ-T
K6
3.3
2.8
-40 to +85
-40 to +85
6 Ld µTDFN
L6.1.6x1.6
NO
NO
Coming Soon
K7
6 Ld µTDFN
L6.1.6x1.6
ISL9104IRUJZ-T
ISL9104IRUFZ-T
K8
K9
2.5
2.0
-40 to +85
-40 to +85
6 Ld µTDFN
6 Ld µTDFN
L6.1.6x1.6
L6.1.6x1.6
NO
NO
Coming Soon
ISL9104IRUDZ-T
Coming Soon
L0
1.8
-40 to +85
6 Ld µTDFN
L6.1.6x1.6
NO
ISL9104IRUCZ-T
ISL9104IRUBZ-T
ISL9104IRUWZ-T
ISL9104IRUAZ-T
ISL9104AIRUNZ-T
L1
L2
L3
L4
L5
1.5
1.2
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
6 Ld µTDFN
6 Ld µTDFN
6 Ld µTDFN
6 Ld µTDFN
6 Ld µTDFN
L6.1.6x1.6
L6.1.6x1.6
L6.1.6x1.6
L6.1.6x1.6
L6.1.6x1.6
NO
NO
ADJ
3.3
NO
YES
YES
Coming Soon
2.8
ISL9104AIRUJZ-T
ISL9104AIRUFZ-T
L6
L7
2.5
2.0
-40 to +85
-40 to +85
6 Ld µTDFN
6 Ld µTDFN
L6.1.6x1.6
L6.1.6x1.6
YES
YES
Coming Soon
ISL9104AIRUDZ-T
Coming Soon
L8
1.8
-40 to +85
6 Ld µTDFN
L6.1.6x1.6
YES
ISL9104AIRUCZ-T
ISL9104AIRUBZ-T
ISL9104AIRUWZ-T
ISL9104AIRUAZ-T
NOTES:
L9
1.5
1.2
-40 to +85
-40 to +85
-40 to +85
6 Ld µTDFN
6 Ld µTDFN
6 Ld µTDFN
L6.1.6x1.6
L6.1.6x1.6
L6.1.6x1.6
YES
YES
YES
M0
M1
ADJ
1. Please refer to TB347 for details on reel specifications.
2. Other output voltage options may be available upon request, please contact Intersil for more details.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu
plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN6829.3
July 9, 2009
2
ISL9104, ISL9104A
Absolute Maximum Ratings
Thermal Information
VIN, EN to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
SW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.5V to 6.5V
FB to GND (for adjustable version) . . . . . . . . . . . . . . . -0.3V to 2.7V
FB to GND (for fixed output version) . . . . . . . . . . . . . . -0.3V to 3.6V
Thermal Resistance (Typical, Note 4)
θ
(°C/W)
160
JA
1.6x1.6 µTDFN Package . . . . . . . . . . . . . . . . . . . . .
Junction Temperature Range. . . . . . . . . . . . . . . . . .-40°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . 2.7V to 6.0V
Load Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .up to 500mA
Ambient Temperature Range. . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
4. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
Electrical Specifications Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and
the typical specifications are measured at the following conditions: T = +25°C, V = V = 3.6V, L = 1.0µH,
A
IN
EN
C
= 4.7µF, C = 4.7µF, I
= 0A (see “Typical Applications” on page 8). Parameters with MIN and/or MAX
1
2
OUT
limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
SUPPLY
Undervoltage Lockout Threshold (UVLO)
UVLO Hysteresis
V
T
= +25°C, Rising
-
50
-
2.5
150
20
2.7
-
V
UVLO
A
mV
µA
Quiescent Supply Current (for ISL9104
adjustable output voltage only)
I
I
In skip mode, no load at the output, no switch,
= 6.0V
34
VIN1
VIN2
V
IN
In skip mode, no load at the output, no switch,
= 6.0V
Quiescent Supply Current (for ISL9104A
adjustable output only)
-
-
-
32
84
45
-
µA
µA
μA
V
IN
Quiescent Supply Current (for ISL9104A 1.5V
fixed output)
In skip mode, no load at the output,
V
V
= 6.0V
IN
IN
Shut Down Supply Current
I
= 6.0V, EN = LOW
0.05
1
SD
OUTPUT REGULATION
FB Voltage Accuracy (for adjustable output only)
T
= 0°C to +85°C
-2
-
-
+2
%
%
V
A
-2.5
+2.5
FB Voltage
V
0.8
5
FB
FB Bias Current (for adjustable output only)
I
VFB = 0.75V
PWM Mode
-
100
3
nA
%
FB
Output Voltage Accuracy (for fixed output
voltage only)
-3
-
Line Regulation
V
V
= V + 0.5V to 6V (minimal 2.7V)
-
-
0.2
-
-
%/V
IN
IN
O
Load Regulation
=3.6V, I = 150mA to 500mA
0.0009
%/mA
O
SW
P-Channel MOSFET ON-Resistance
V
V
V
V
= 3.6V, I = 200mA
-
-
-
-
-
0.45
0.55
0.4
0.6
0.72
0.52
0.65
-
Ω
Ω
Ω
Ω
Ω
IN
IN
IN
IN
O
= 2.7V, I = 200mA
O
N-Channel MOSFET ON-Resistance
= 3.6V, I = 200mA
O
= 2.7V, I = 200mA
O
0.5
N-Channel Bleeding MOSFET
ON-Resistance
100
P-Channel MOSFET Peak Current Limit
Maximum Duty Cycle
I
V
= 4.2V
0.75
-
1.00
100
1.35
-
A
PK
IN
%
FN6829.3
July 9, 2009
3
ISL9104, ISL9104A
Electrical Specifications Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and
the typical specifications are measured at the following conditions: T = +25°C, V = V = 3.6V, L = 1.0µH,
A
IN
EN
C
= 4.7µF, C = 4.7µF, I
= 0A (see “Typical Applications” on page 8). Parameters with MIN and/or MAX
1
2
OUT
limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested. (Continued)
PARAMETER
SW Leakage Current
SYMBOL
TEST CONDITIONS
SW at Hi-Z state
MIN
TYP
0.01
4.3
MAX
UNITS
µA
-
3.6
-
2
4.9
-
PWM Switching Frequency
SW Minimum On-Time
Soft-Start-Up Time
EN
f
V
= 3.6V, T = -20°C to +85°C
IN A
MHz
ns
S
65
-
1.0
-
ms
Logic Input Low
-
-
-
0.4
V
V
Logic Input High
1.4
-
1
-
Logic Input Leakage Current
Thermal Shutdown
Thermal Shutdown Hysteresis
-
-
-
0.1
130
30
µA
°C
°C
-
Typical Operating Performance
100
100
90
V
= 2.7V
IN
90
80
70
60
50
40
30
20
10
0
80
70
V
= 3.5V
IN
V
= 4.9V
V
= 4.5V
V
= 3.8V
IN
IN
IN
V
= 5.5V
60
50
40
30
20
10
0
IN
0
0.1
0.2
0.3
0.4
0.5
0
0.1
0.2
0.3
0.4
0.5
LOAD CURRENT (A)
LOAD CURRENT (A)
FIGURE 1. EFFICIENCY vs LOAD CURRENT (V
= 1.5V)
FIGURE 2. EFFICIENCY vs LOAD CURRENT (V
= 2.5V)
OUT
OUT
30
1.630
1.625
T = +85°C
25
20
15
10
1.620
1.615
1.610
1.605
1.600
LOAD CURRENT RISING
T = +25°C
LOAD CURRENT FALLING
T = -45°C
2.70
3.25
3.80
4.35
4.90
5.45
6.00
0
100
200
I
300
(mA)
400
500
INPUT VOLTAGE (V)
OUT
FIGURE 3. INPUT QUIESCENT CURRENT vs V (V
IN OUT
= 2.5V)
FIGURE 4. OUTPUT VOLTAGE vs LOAD CURRENT
(V = 3.6V, V = 1.6V)
IN
OUT
FN6829.3
July 9, 2009
4
ISL9104, ISL9104A
Typical Operating Performance (Continued)
2.505
2.500
2.495
2.490
2.485
2.480
2.475
5V/DIV
1V/DIV
V
SW
LOAD CURRENT RISING
V
OUT
200mA/DIV
5V/DIV
I
L
LOAD CURRENT FALLING
EN
0
100
200
I
300
(mA)
400
500
OUT
FIGURE 6. SOFT-START TO PFM MODE (V = 3.6V,
IN
FIGURE 5. OUTPUT VOLTAGE vs LOAD CURRENT
V
= 1.5V, I
= 0.001mA)
(V = 4.0V, V
IN
= 2.5V)
OUT
OUT
OUT
5V/DIV
2V/DIV
5V/DIV
1V/DIV
V
V
V
SW
SW
V
OUT
OUT
200mA/DIV
5V/DIV
500mA/DIV
5V/DIV
I
I
L
L
EN
EN
FIGURE 7. SOFT-START TO PWM MODE (V = 3.6V,
IN
FIGURE 8. SOFT-START TO PFM MODE (V = 3.6V,
IN
V
= 1.5V, I
= 500mA)
V
= 2.5V, I
= 0.001mA)
OUT
OUT
OUT
OUT
5V/DIV
5V/DIV
V
V
SW
SW
20mV/DIV
20mV/DIV
V
(AC COUPLED)
OUT
V
(AC COUPLED)
OUT
20mA/DIV
20mA/DIV
I
o
I
o
FIGURE 9. LOAD TRANSIENT IN PFM MODE (V = 3.6V,
IN
FIGURE 10. LOAD TRANSIENT IN PFM MODE (V = 3.6V,
IN
V
= 1.5V, 5mA TO 30mA)
V
= 1.5V, 30mA TO 5mA)
OUT
OUT
FN6829.3
July 9, 2009
5
ISL9104, ISL9104A
Typical Operating Performance (Continued)
5V/DIV
5V/DIV
V
V
SW
SW
20mV/DIV
20mV/DIV
V
(AC COUPLED)
OUT
V
(AC COUPLED)
OUT
I
20mA/DIV
20mA/DIV
o
I
o
FIGURE 11. LOAD TRANSIENT IN PFM MODE (V = 3.6V,
IN
FIGURE 12. LOAD TRANSIENT IN PFM MODE (V = 3.6V,
IN
V
= 2.5V, 5mA TO 30mA)
V
= 2.5V, 30mA TO 5mA)
OUT
OUT
5V/DIV
5V/DIV
V
V
SW
SW
V
(AC COUPLED)
50mV/DIV
OUT
50mV/DIV
V
(AC COUPLED)
OUT
200mA/DIV
200mA/DIV
I
I
o
o
FIGURE 13. LOAD TRANSIENT FROM PFM TO PWM MODE
(V = 3.6V, V = 1.5V, 5mA TO 300mA)
FIGURE 14. LOAD TRANSIENT FROM PWM TO PFM MODE
(V = 3.6V, V = 1.5V, 300mA TO 5mA)
IN OUT
IN OUT
5V/DIV
5V/DIV
V
V
SW
V
SW
50mV/DIV
50mV/DIV
V
(AC COUPLED)
(AC COUPLED)
OUT
OUT
200mA/DIV
200mA/DIV
I
I
o
o
FIGURE 15. LOAD TRANSIENT FROM PFM TO PWM MODE
(V = 3.6V, V = 2.5V, 5mA TO 300mA)
FIGURE 16. LOAD TRANSIENT FROM PWM TO PFM MODE
(V = 3.6V, V = 2.5V, 300mA TO 5mA)
IN OUT
IN OUT
FN6829.3
July 9, 2009
6
ISL9104, ISL9104A
Typical Operating Performance (Continued)
5V/DIV
5V/DIV
V
SW
V
V
SW
20mV/DIV
20mV/DIV
V
(AC COUPLED)
OUT
OUT
500mA/DIV
500mA/DIV
I
o
I
o
FIGURE 18. LOAD TRANSIENT IN PWM MODE (V = 3.6V,
IN
FIGURE 17. LOAD TRANSIENT IN PWM MODE (V = 3.6V,
IN
V
= 1.5V, 500mA TO 200mA)
V
= 1.5V, 200mA TO 500mA)
O
O
5V/DIV
5V/DIV
V
V
V
SW
SW
20mV/DIV
20mV/DIV
(AC COUPLED)
V
(AC COUPLED)
OUT
OUT
500mA/DIV
500mA/DIV
I
I
o
o
FIGURE 19. LOAD TRANSIENT IN PWM MODE (V = 3.6V,
IN
FIGURE 20. LOAD TRANSIENT IN PWM MODE (V = 3.6V,
IN
V
= 2.5V, 200mA TO 500mA)
V = 2.5V, 500mA TO 200mA)
O
O
GND
Pin Descriptions
Ground connection.
VIN
FB
Input supply voltage. Typically connect a 4.7µF ceramic
capacitor to ground.
Buck converter output feedback pin. For adjustable output
version, its typical value is 0.8V and connect it to the output
through a resistor divider for desired output voltage; for fixed
output version, directly connect this pin to the converter
output.
NC
No connect, leave it floating.
EN
Regulator enable pin. Enable the device when driven to
high. Shut down the chip and discharge output capacitor
when driven to low. Do not leave this pin floating.
SW
Switching node connection. Connect to one terminal of
inductor.
FN6829.3
July 9, 2009
7
ISL9104, ISL9104A
Typical Applications
ISL9104, ISL9104A ADJUSTABLE OUTPUT
L
OUTPUT
UP TO 500mA
1.0µH
INPUT: 2.7V TO 6V
SW
VIN
C2
4.7µF
C1
4.7µF
R1
100k
C3
47pF
R2
100k
ENABLE
EN
FB
DISABLE
GND
ISL9104, ISL9104A FIXED OUTPUT
OUTPUT
UP TO 500mA
L
1.0µH
INPUT: 2.7V TO 6V
VIN
SW
C2
4.7µF
C1
4.7µ F
ENABLE
FB
EN
DISABLE
GND
FIGURE 21. TYPICAL APPLICATIONS DIAGRAM
Note: For adjustable output version, the internal feedback resistor divider is disabled and the FB pin is directly connected to the
error amplifier.
PARTS
DESCRIPTION
Inductor
MANUFACTURERS
KEMET
PART NUMBER
LB3218-T1R0MK
SPECIFICATIONS
1.0µH/1.0A/60mΩ
4.7µF/6.3V, X5R
SIZE
3.2mmx1.8mmx1.8mm
0603
L
C1, C2
Input and output
capacitor
Murata
GRM188R60J475KE19D
C3
Capacitor
Resistor
KEMET
Various
C0402C470J5GACTU
-
47pF/50V
0402
0402
R1, R2
100kΩ, SMD, 1%
FN6829.3
July 9, 2009
8
ISL9104, ISL9104A
Block Diagram
SHUTDOWN
SHUTDOWN
SOFT-
START
OSCILLATOR
VIN
VREF
EN
+
BANDGAP
+
EAMP
PWM/PFM
LOGIC
COMP
CONTROLLER
PROTECTION
DRIVER
SW
SLOPE
COMP
X
GND
*NOTE
FB
BLEEDING
FET
100Ω
+
+
CSA
OCP
SKIP
VREF1
SCP
VREF3
+
+
VREF2
ZERO-CROSS
SENSING
*NOTE: FOR FIXED OUTPUT OPTIONS ONLY
NOTE: For Adjustable output version, the internal feedback resistor divider is disabled and the FB pin is directly connected
to the error amplifier.
FIGURE 22. FUNCTIONAL BLOCK DIAGRAM
PWM Control Scheme
Theory of Operation
The ISL9104, ISL9104A uses the peak-current-mode
pulse-width modulation (PWM) control scheme for fast
transient response and pulse-by-pulse current limiting.
Figure 22 shows the circuit functional block diagram. The
current loop consists of the oscillator, the PWM comparator
COMP, current sensing circuit, and the slope compensation
for the current loop stability. The current sensing circuit
consists of the resistance of the P-Channel MOSFET when it
is turned on and the Current Sense Amplifier (CSA). The
control reference for the current loops comes from the Error
Amplifier (EAMP) of the voltage loop.
The ISL9104, ISL9104A is a step-down switching regulator
optimized for battery-powered handheld applications. The
regulator operates at typical 4.3MHz fixed switching
frequency under heavy load condition to allow small external
inductor and capacitors to be used for minimal printed-circuit
board (PCB) area. At light load, the regulator can
automatically enter the skip mode (PFM mode) to reduce the
switching frequency to minimize the switching loss and to
maximize the battery life. The quiescent current under skip
mode under no load and no switch condition is typically only
20µA. The supply current is typically only 0.05µA when the
regulator is disabled.
FN6829.3
July 9, 2009
9
ISL9104, ISL9104A
The PWM operation is initialized by the clock from the
skip mode operation. A zero-cross sensing circuit (as shown
in Figure 22) monitors the current flowing through SW node
for zero crossing. When it is detected to cross zero for
16-consecutive cycles, the regulator enters the skip mode.
During the 16-consecutive cycles, the inductor current could
be negative. The counter is reset to zero when the sensed
current flowing through SW node does not cross zero during
any cycle within the 16-consecutive cycles. Once ISL9104,
ISL9104A enters the skip mode, the pulse modulation starts
being controlled by the SKIP comparator shown in Figure 22.
Each pulse cycle is still synchronized by the PWM clock. The
P-Channel MOSFET is turned on at the rising edge of clock
and turned off when its current reaches ~20% of the peak
current limit. As the average inductor current in each cycle is
higher than the average current of the load, the output
voltage rises cycle over cycle. When the output voltage is
sensed to reach 1.5% above its nominal voltage, the
oscillator. The P-Channel MOSFET is turned on at the
beginning of a PWM cycle and the current in the P-Channel
MOSFET starts ramping up. When the sum of the CSA
output and the compensation slope reaches the control
reference of the current loop, the PWM comparator COMP
sends a signal to the PWM logic to turn off the P-Channel
MOSFET and to turn on the N-Channel MOSFET. The
N-MOSFET remains on till the end of the PWM cycle. Figure 23
shows the typical operating waveforms during the normal PWM
operation. The dotted lines illustrate the sum of the slope
compensation ramp and the CSA output.
vEAMP
vCSA
d
P-Channel MOSFET is turned off immediately and the
inductor current is fully discharged to zero and stays at zero.
The output voltage reduces gradually due to the load current
discharging the output capacitor. When the output voltage
drops to the nominal voltage, the P-Channel MOSFET will
be turned on again, repeating the previous operations.
iL
vOUT
The regulator resumes normal PWM mode operation when
the output voltage is sensed to drop below 1.5% of its
nominal voltage value.
FIGURE 23. PWM OPERATION WAVEFORMS
The output voltage is regulated by controlling the reference
voltage to the current loop. The bandgap circuit outputs a
0.8V reference voltage to the voltage control loop. The
feedback signal comes from the FB pin. The soft-start block
only affects the operation during the start-up and will be
discussed separately in “Soft-Start” on page 11. The EAMP
is a transconductance amplifier, which converts the voltage
error signal to a current output. The voltage loop is internally
compensated by a RC network. The maximum EAMP
voltage output is precisely clamped to the bandgap voltage.
Enable
The enable (EN) pin allows user to enable or disable the
converter for purposes such as power-up sequencing. With
EN pin pulled to high, the converter is enabled and the
internal reference circuit wakes up first and then the soft
start-up begins. When EN pin is pulled to logic low, the
converter is disabled, both P-Channel MOSFET and
N-Channel MOSFETS are turned off, and the output
capacitor is discharged through internal discharge path.
Skip Mode (PFM Mode)
Under light load condition, ISL9104, ISL9104A automatically
enters a pulse-skipping mode to minimize the switching loss
by reducing the switching frequency. Figure 24 illustrates the
16 CYCLES
CLOCK
20% PEAK CURRENT LIMIT
IL
0
1.015*VOUT_NOMINAL
VOUT
VOUT_NOMINAL
FIGURE 24. SKIP MODE OPERATION WAVEFORMS
FN6829.3
July 9, 2009
10
ISL9104, ISL9104A
In Equation 1, usually the typical values can be used but to
Overcurrent Protection
have a more conservative estimation, the inductance should
consider the value with worst case tolerance; and for
The overcurrent protection is provided on ISL9104, ISL9104A
when overload condition happens. It is realized by monitoring
the CSA output with the OCP comparator, as shown in
Figure 22. When the current at P-Channel MOSFET is sensed
to reach the current limit, the OCP comparator is trigged to
turn off the P-Channel MOSFET immediately.
switching frequency f , the minimum f from the “Electrical
S
S
Specifications” table on page 3 can be used.
To select the inductor, its saturation current rating should be
at least higher than the sum of the maximum output current
and half of the delta calculated from Equation 1. Another
more conservative approach is to select the inductor with the
current rating higher than the P-Channel MOSFET peak
current limit.
Short-Circuit Protection
ISL9104, ISL9104A has a Short-Circuit Protection (SCP)
comparator, which monitors the FB pin voltage for output
short-circuit protection. When the output voltage is sensed to
be lower than a certain threshold, the SCP comparator
reduces the PWM oscillator frequency to a much lower
frequency to protect the IC from being damaged.
Another consideration is the inductor DC resistance since it
directly affects the efficiency of the converter. Ideally, the
inductor with the lower DC resistance should be considered
to achieve higher efficiency.
Undervoltage Lockout (UVLO)
Inductor specifications could be different from different
manufacturers so please check with each manufacturer if
additional information is needed.
When the input voltage is below the Undervoltage Lock Out
(UVLO) threshold, ISL9104, ISL9104A is disabled.
Soft-Start
For the output capacitor, a ceramic capacitor can be used
because of the low ESR values, which helps to minimize the
output voltage ripple. A typical value of 4.7µF/6.3V ceramic
capacitor should be enough for most of the applications and
the capacitor should be X5R or X7R.
The soft-start feature eliminates the inrush current during the
circuit start-up. The soft-start block outputs a ramp reference to
both the voltage loop and the current loop. The two ramps limit
the inductor current rising speed as well as the output voltage
speed so that the output voltage rises in a controlled fashion.
Input Capacitor Selection
Low Dropout Operation
The main function for the input capacitor is to provide
decoupling of the parasitic inductance and to provide filtering
function to prevent the switching current from flowing back to
the battery rail. A 4.7µF/6.3V ceramic capacitor (X5R or X7R)
is a good starting point for the input capacitor selection.
The ISL9104, ISL9104A features low dropout operation to
maximize the battery life. When the input voltage drops to a
level that ISL9104, ISL9104A can no longer operate under
switching regulation to maintain the output voltage, the
P-Channel MOSFET is completely turned on (100% duty
cycle). The dropout voltage under such condition is the product
of the load current and the ON-resistance of the P-Channel
Output Voltage Setting Resistor Selection
For ISL9104, ISL9104A adjustable output option, the voltage
MOSFET. Minimum required input voltage V under this
IN
resistors, R and R , as shown in Figure 21, set the desired
1
2
condition is the sum of output voltage plus the voltage drop
cross the inductor and the P-Channel MOSFET switch.
output voltage values. The output voltage can be calculated
using Equation 2:
Thermal Shut Down
R
⎛
⎞
⎟
⎠
1
(EQ. 2)
------
V
= V • 1 +
⎜
O
FB
R
2
The ISL9104, ISL9104A provides built-in thermal protection
function. The thermal shutdown threshold temperature is
+130°C (typ) with a 30°C (typ) hysteresis. When the internal
temperature is sensed to reach +130°C, the regulator is
completely shut down and as the temperature drops to
+100°C (typ), the ISL9104, ISL9104A resumes operation
starting from the soft-start.
⎝
where V is the feedback voltage (typically it is 0.8V). The
FB
current flowing through the voltage divider resistors can be
calculated as V /(R + R ), so larger resistance is desirable
O
1
2
to minimize this current. On the other hand, the FB pin has
leakage current that will cause error in the output voltage
setting. The leakage current has a typical value of 0.1µA. To
minimize the accuracy impact on the output voltage, select
Applications Information
the R no larger than 200kΩ.
2
Inductor and Output Capacitor Selection
For adjustable output versions, C3 (shown in Figure 21) is
highly recommended for improving stability and achieving
better transient response.
To achieve better steady state and transient response,
ISL9104, ISL9104A typically uses a 1.0µH inductor. The peak-
to-peak inductor current ripple can be expressed in Equation 1:
V
Table 1 provides the recommended component values for
some output voltage options.
⎛
⎞
⎟
⎠
O
---------
V
• 1 –
⎜
O
(EQ. 1)
V
⎝
IN
--------------------------------------
ΔI =
L • f
S
FN6829.3
July 9, 2009
11
ISL9104, ISL9104A
TABLE 1. RECOMMENDED IISL9104, ISL9104A
ADJUSTABLE OUTPUT VERSION CIRCUIT
Layout Recommendation
The PCB layout is a very important converter design step to
make sure the designed converter works well, especially
under the high current high switching frequency condition.
CONFIGURATION vs V
OUT
VOUT (V) L (µH)
C2 (µF)
4.7
R1 (kΩ)
0
C3 (pF)
N/A
100
47
R2 (kΩ)
N/A
0.8
1.0
1.2
1.5
1.8
2.5
2.8
3.3
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
For ISL9104, ISL9104A, the power loop is composed of the
output inductor L, the output capacitor C , the SW pin and
the PGND pin. It is necessary to make the power loop as
small as possible and the connecting traces among them
should be direct, short and wide; the same type of traces
should be used to connect the VIN pin, the input capacitor
4.7
44.2
80.6
84.5
100
178
OUT
4.7
162
4.7
47
97.6
80.6
47.5
40.2
32.4
4.7
47
C
and its ground.
IN
4.7
100
47
The switching node of the converter, the SW pin, and the
traces connected to this node are very noisy, so keep the
voltage feedback trace and other noise sensitive traces
away from these noisy traces.
4.7
100
47
4.7
102
47
The input capacitor should be placed as close as possible to
the VIN pin. The ground of the input and output capacitors
should be connected as close as possible as well. In
addition, a solid ground plane is helpful for EMI performance.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6829.3
July 9, 2009
12
ISL9104, ISL9104A
Package Outline Drawing
L6.1.6x1.6
6 LEAD ULTRA THIN DUAL FLAT NO-LEAD COL PLASTIC PACKAGE (UTDFN COL)
Rev 1, 11/07
2X 1.00
1.60
A
PIN #1 INDEX AREA
6
6
4X 0.50
PIN 1
INDEX AREA
B
1
3
5X 0 . 40 ± 0 . 1
1X 0.5 ±0.1
1.60
(4X)
0.15
4
6
0.10 M C A B
TOP VIEW
4
0.25 +0.05 / -0.07
BOTTOM VIEW
( 6X 0 . 25 )
SEE DETAIL "X"
( 1X 0 .70 )
0 . 55 MAX
C
0.10
BASE PLANE
SEATING PLANE
C
0.08
C
( 1 . 4 )
SIDE VIEW
0 . 2 REF
C
( 5X 0 . 60 )
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
( 4X 0 . 5 )
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN6829.3
July 9, 2009
13
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