ISL95710 [INTERSIL]
Terminal Voltage 3V or 5V, 128 Taps Up/Down Interface; 端电压3V或5V ， 128个抽头上/下接口
| 型号： | ISL95710 |
| 厂家： | 
Intersil |
| 描述： | Terminal Voltage 3V or 5V, 128 Taps Up/Down Interface |
| 文件： | 总8页 (文件大小：238K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL95710
®
Digitally Controlled Potentiometer (XDCP™)
Data Sheet
August 17, 2005
FN8240.2
Terminal Voltage ±3V or ±5V, 128 Taps
Up/Down Interface
The Intersil ISL95710 is a digitally controlled potentiometer
(XDCP). The device consists of a resistor array, wiper
switches, a control section, and nonvolatile memory. The
wiper position is controlled by a Up/Down interface.
Features
• Non-Volatile Solid-State Potentiometer
• Up/Down Interface with Chip Select Enable
• DCP Terminal Voltage, ±3V or ±5V
• 128 Wiper Tap Points
- Wiper position stored in nonvolatile memory and
The potentiometer is implemented by a resistor array
composed of 127 resistive elements and a wiper switching
network. Between each element and at either end are tap
points accessible to the wiper terminal. The position of the
wiper element is controlled by the CS, U/D, and INC inputs.
The position of the wiper can be stored in nonvolatile
memory and then be recalled upon a subsequent power-up
operation.
recalled on power-up
• 127 Resistive Elements
- Typical R
- End to end resistance range ±20%
tempco = ±50ppm/°C
TOTAL
• Low Power CMOS
- Standby current, 1µA
- Active current, 3mA max
The device can be used as a three-terminal potentiometer or
as a two-terminal variable resistor in a wide variety of
applications including:
- V
= 3V to 5.5V
CC
- V- = -3V to -5.5V
• High Reliability
- Endurance, 200,000 data changes per bit
- Register data retention, 50 years
• Industrial and automotive control
• Parameter and bias adjustments
• Amplifier bias and control
• R
Values = 10kΩ, 50kΩ
TOTAL
• Package
- 10 Ld MSOP
- Pb-free plus anneal available (RoHS compliant)
Ordering Information
RES
TEMP
PART NUMBER OPTION RANGE PACKAGE
PKG.
(BRAND)
(Ω)
(°C)
(Pb-Free) DWG. #
Pinout
ISL95710WIU10Z
(AKR) (Notes 1, 2)
10K
-40 to +85
10 Ld
MSOP
M10.118
M10.118
ISL95710
(10 LD MSOP)
TOP VIEW
ISL95710UIU10Z
(AKP) (Notes 1, 2)
50K
-40 to +85
10 Ld
MSOP
NOTES:
INC
U/D
10
9
1
2
3
4
5
1. Add “-T” suffix for tape and reel.
VCC
V-
2. Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and
100% matte tin plate termination finish, which are RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pb-
free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
GND
R
8
L
R
R
CS
NC
7
6
W
H
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil, Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL95710
Block Diagram
U/D
INC
7-BIT
UP/DOWN
COUNTER
R
127
126
H
V
V- (ANALOG VOLTAGE)
CC
CS
125
124
UP/DOWN
(U/D)
R
R
H
7-BIT
NONVOLATILE
MEMORY
INCREMENT
(INC)
CONTROL
AND
MEMORY
W
ONE
OF
128
TRANSFER
GATES
RESISTOR
ARRAY
DEVICE SELECT
(CS)
DECODER
R
L
2
STORE AND
RECALL
CONTROL
CIRCUITRY
GND (GROUND)
GENERAL
1
0
V-
GND
R
R
L
W
DETAILED
Pin Descriptions
PIN NUMBER
SYMBOL
DESCRIPTION
1
2
U/D
V-
Controls the direction of wiper movement and whether the counter is incremented or decremented.
Negative bias voltage for the potentiometer wiper control.
Ground
3
GND
CS
4
Chip select. The device is selected when the CS input is LOW. Also used to initiate a nonvolatile store.
No Connect. Pin is to be left unconnected.
5
NC
6
R
A fixed terminal for one end of the potentiometer resistor.
The wiper terminal which is equivalent to the movable terminal of a potentiometer.
A fixed terminal for one end of the potentiometer resistor.
Positive logic supply voltage.
H
7
R
W
8
R
L
9
VCC
INC
10
Increment input; negative edge triggered.
FN8240.2
August 17, 2005
2
ISL95710
Absolute Maximum Ratings
Thermal Information
Thermal Resistance (Typical, Note 3)
MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature under bias. . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on CS, INC, U/D and VCC
with respect to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +6V
Voltage on V- (referenced to GND) . . . . . . . . . . . . . . . . . . . . . . . -6V
θ
(°C/W)
170
JA
Recommended Operating Conditions
Temperature Range (Industrial). . . . . . . . . . . . . . . . .-40°C to +85°C
∆V = |V
-V
| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V
(RH) (RL)
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Lead temperature (soldering 10 seconds) . . . . . . . . . . . . . . . .300°C
CC
V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.7V to -5.5V
I
(10 seconds). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
W
ESD (Mil-Std 883, Method 3015) . . . . . . . . . . . . . . . . . . . . . . . .>2kV
ESD Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>150V
CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional
operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
NOTE:
3. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Analog Specifications
Over recommended operating conditions unless otherwise stated.
TYP
SYMBOL
PARAMETER
to R resistance
TEST CONDITIONS
MIN
(Note 1)
MAX
UNIT
kΩ
kΩ
%
R
R
R
W option
U option
10
50
TOTAL
H
L
to R resistance tolerance
-20
V-
+20
H
L
V
,V
RH RL
R ,R terminal voltage
V
CC
V
H
L
R
Wiper resistance
V- = -5.5V; V
= +5.5V, wiper current =
CC
70
200
Ω
W
(V -V-)/R
CC TOTAL
C /C /C
W
Potentiometer Capacitance (Note 13)
Leakage on DCP pins
10/10/
25
pF
µA
H
L
I
Voltage at pins; V- to V
-1
0.1
1
LkgDCP
CC
unloaded)
VOLTAGE DIVIDER MODE (V- @ R ; V
@ R ; Voltage at R = V
L
CC
H
W
RW
INL
(Note 6)
Integral non-linearity
-1
1
LSB
(Note 2)
DNL
(Note 5)
Differential non-linearity
W, U options
-0.5
0.5
LSB
(Note 2)
ZSerror
(Note 3)
Zero-scale error
Full-scale error
W option
U option
W option
U option
0
0
1
0.5
-1
4
2
0
0
LSB
(Note 2)
FSerror
(Note 4)
-4
-2
LSB
(Note 2)
-0.5
±4
TC
Ratiometric Temperature Coefficient
DCP Register set between 16 and 120d,
T = -40°C to +85°C
ppm/°C
V
(Notes 7,13)
RESISTOR MODE (Measurements between R and R with R not connected, or between R and R with R not connected)
W
L
H
W
H
L
RINL
Integral non-linearity
Differential non-linearity
Offset
DCP register set between 20 hex and 5F hex.
Monotonic over all tap positions
-1
1
MI
(Note 11)
(Note 8)
RDNL
(Note 10)
W, U options
-0.5
0.5
MI
(Note 8)
Roffset
(Note 9)
DCP Register set to 00 hex, W option
DCP Register set to 00 hex, U option
0
0
2
5
2
MI
(Note 8)
0.5
±50
TC
Resistance Temperature Coefficient
DCP register set between 16 and 127d,
T = -40°C to +85°C
ppm/°C
R
(Note 12,13)
FN8240.2
3
August 17, 2005
ISL95710
Operating Specifications Over the recommended operating conditions unless otherwise specified.
TYP
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 1)
MAX
UNIT
I
V
supply current, volatile write/read CS = V , U/D = V or V and INC = V or V
,
,
500
µA
CC1
CC
IL IL IH IL
IH
IH
R , R , R not connected
L
H
W
I
V- supply current, volatile write/read
CS = V , U/D = V or V and INC = V or V
IL IL IH IL
-100
µA
µA
V-1
R , R , R not connected
L
H
W
I
V
supply current, nonvolatile write U/D = V or V and INC = V , CS = transitions
CC IL IH IH
500
CC2
from V to V . R , R , R not connected
IL IH
L
H
W
I
V- supply current, nonvolatile write
current (standby)
U/D = V or V and INC = V , CS = transitions
IL IH IH
-3
mA
V-2
from V to V . R , R , R not connected
IL IH
L
H
W
2
I
V
V
V
= +5.5V, I C Interface in Standby State
1
1
µA
µA
µA
µA
µA
CCSB
CC
CC
CC
2
= +3.6V, I C Interface in Standby State
I
V- current (standby)
V- = -5.5V, CS = V
V- = -3.6V, CS = V
-5
-2
V-SB
IH
IH
I
Leakage current, at pins INC, CS, and
U/D
V
or V applied at pin
IH
-10
10
LkgDig
IL
I
Leakage at CS, input low
V
= 0V
-300
-2.5
µA
V
IL_CS
Vpor
IL
Power-on recall for both V- and V
V-
CC
V
2.5
V
CC
V- Ramp
EEPROM SPECS
EEPROM Endurance
EEPROM Retention
3-WIRE INTERFACE SPECS
V- ramp rate
-0.2
V/ms
200,000
50
Cycles
Years
Temperature ≤ 75°C
V
INC, CS, and U/D input buffer LOW
voltage
-0.3
0.3*V
V
V
IL
CC
V
INC, CS, and U/D input buffer HIGH
voltage
0.7*V
CC
V
+
IH
CC
0.3
Hysteresis INC, CS, and U/D input buffer
0.15*
CC
V
(Note 13)
hysteresis
V
Cpin
INC, CS, and U/D pin capacitance
10
pF
AC Electrical Specifications
V
= 5V ±10%, T = Full Operating Temperature Range unless otherwise stated
A
CC
SYMBOL
PARAMETER
MIN
100
100
1
TYP (Note 1)
MAX
UNIT
t
CS to INC setup
ns
ns
µs
µs
µs
µs
ms
Cl
lD
DI
t
INC HIGH to U/D change
U/D to INC setup
t
t
INC LOW period
1
lL
lH
lC
t
t
INC HIGH period
1
INC inactive to CS inactive
CS deselect time (STORE)
1
t
20
CPHS
(Note 14)
t
CS deselect time (NO STORE)
1
µs
CPHNS
FN8240.2
August 17, 2005
4
ISL95710
AC Electrical Specifications
V
= 5V ±10%, T = Full Operating Temperature Range unless otherwise stated (Continued)
CC
A
SYMBOL
PARAMETER
MIN
TYP (Note 1)
MAX
UNIT
µs
t
INC to R change
W
100
500
IW
t
INC cycle time
2
µs
CYC
t
t
INC input rise and fall time
500
µs
R, F
NOTES:
1. Typical values are for T = 25°C and 3.3V supply voltage.
A
2. LSB: [V(R
)
– V(R ) ]/127. V(R
)
and V(R ) are V(R ) for the DCP register set to 7F hex and 00 hex respectively. LSB is the
W 0
W 127
W 0 W 127
W
incremental voltage when changing from one tap to an adjacent tap.
3. ZS error = (V(R ) – V-)/LSB.
W 0
4. FS error = [V(R
)
– V+]/LSB.
]/LSB-1, for i = 1 to 127. i is the DCP register setting.
W 127
5. DNL = [V(R ) – V(R
)
W i W i-1
6. INL = V(R ) – (i • LSB – V(R ) ) for i = 1 to 127.
W i W 0
Max(V(RW) ) – Min(V(RW) )
6
i
i
10
7. TC = ---------------------------------------------------------------------------------------------- x ----------------
V
[Max(V(RW) ) + Min(V(RW) )] ⁄ 2
125°C
i
i
for i = 16 to 120 decimal. Max ( ) is the maximum value of the wiper voltage and Min ( ) is the minimum value of the wiper voltage over the
temperature range.
8. MI = |R
– R | /127. R
and R are the measured resistances for the DCP register set to 7F hex and 00 hex respectively.
127 0
9. Roffset = R /MI, when measuring between RW and RL.
127
0
0
Roffset = R
/MI, when measuring between RW and RH.
127
10. RDNL = (R – R )/MI, for i = 16 to 127.
i
i-1
11. RINL = [R – (MI • i) – R ]/MI, for i = 16 to 127.
i
0
6
[Max(Ri) – Min(Ri)] 10
×
--------------------------------------------------------------- ----------------
12.
TC
=
R
[Max(Ri) + Min(Ri)] ⁄ 2
125°C
for i = 16 to 127, T = -40°C to 85°C. Max ( ) is the maximum value of the resistance and Min ( ) is the minimum value of the resistance over the
temperature range.
13. This parameter is not 100% tested.
14. t
is the minimum cycle time to be allowed for any non-volatile Write by the user. It is the time from a valid STORE condition to the end of
CPHS
the self-timed internal non-volatile write cycle. No CS or INC changes should be allowed.
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be steady
Will be steady
May change from Low to High
May change from High to Low
Will change from Low to High
Will change from High to Low
Don’t Care: Changes Allowed
N/A
Changing: State Not Known
Center Line is High Impedance
FN8240.2
5
August 17, 2005
ISL95710
A.C. Timing
CS
t
CYC
t
CPHNS
t
t
t
t
t
CPHS
CI
IL
IH
IC
90%
10%
90%
INC
U/D
t
t
t
t
R
ID
DI
F
t
IW
(1)
MI
R
W
Note (1): MI in the timing diagram refers to the minimum incremental change in the wiper position.
Chip Select (CS)
Power Up and Down Requirements
The device is selected when the CS input is LOW. The
current wiper counter value is stored in nonvolatile memory
when CS is returned HIGH while the INC input is also HIGH.
After the store operation is complete the ISL95710 will be
placed in the low power standby mode until the device is
selected once again.
In order to prevent unwanted tap position changes, or an
inadvertent store, bring the CS and INC high before or
concurrently with the V
pin on power-up. The
CC
potentiometer voltages must be applied after this sequence
is completed. During power-up, the data sheet parameters
for the DCP do not fully apply until 1ms after V
reaches its
CC
ramp spec is always in effect.
final value. The V
CC
Principles of Operation
Pin Descriptions
There are three sections of the ISL95710: the input control,
wiper counter and decode section; the nonvolatile memory;
and the resistor array. The input control section operates as
an up/down counter. The output of this wiper counter is
decoded to turn on a electronic switch connecting a point on
the resistor array to the wiper output. The contents of the
wiper counter can be stored in nonvolatile memory and
retained for future use. The resistor array is comprised of
individual resistors connected in series. At either end of the
array and between each resistor is an electronic switch that
transfers the potential at that point to the wiper.
R and R
H
L
The high (R ) and low (R ) terminals of the ISL95710 are
H
L
equivalent to the fixed terminals of a mechanical
potentiometer. The terminology of R and R references the
L
H
relative position of the terminal in relation to wiper movement
direction selected by the U/D input and not the voltage
potential on the terminal.
RW
w
R
is the wiper terminal and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the wiper counter.
The wiper, when at either fixed terminal, acts like its
mechanical equivalent and does not move beyond the last
position. The wiper counter does not wrap around when
clocked to either extreme.
Up/Down (U/D)
The U/D input controls the direction of the wiper movement
and whether the wiper counter is incriminated or
decremented.
The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions. If
the wiper is moved several positions, multiple taps are
Increment (INC)
connected to the wiper for t (INC to R change). The
IW
W
The INC input is negative-edge triggered. Toggling INC will
move the wiper and either increment or decrement the wiper
counter in the direction indicated by the logic level on the
U/D input.
R
value for the device can temporarily be reduced by
TOTAL
a significant amount if the wiper is moved several positions.
When the device is powered-down, the last wiper position
stored will be maintained in the nonvolatile memory. When
FN8240.2
6
August 17, 2005
ISL95710
power is restored, the contents of the memory are recalled
and the wiper is set to the value last stored.
This procedure allows the system to always power-up to a
preset value stored in nonvolatile memory; then during
system operation minor adjustments could be made. The
adjustments might be based on user preference, system
parameter changes due to temperature drift, etc.
Instructions and Programming
The INC, U/D and CS inputs control the movement of the
wiper along the resistor array. With CS set LOW the device
is selected and enabled to respond to the U/D and INC
inputs. HIGH to LOW transitions on INC will increment or
decrement (depending on the state of the U/D input) a seven
bit wiper counter. The output of this wiper counter is decoded
to select one of 128 wiper positions along the resistive array.
The state of U/D may be changed while CS remains LOW.
This allows the host system to enable the device and then
move the wiper up and down until the proper trim is attained.
During initial power-up CS must go high along with or before
V
to avoid an accidental store generation.
CC
TABLE 1. MODE SELECTION
The value of the wiper counter is stored in nonvolatile
memory whenever CS transitions HIGH while the INC input
is also HIGH.
CS
INC
U/D
H
MODE
L
L
Wiper up
L
Wiper down
The system may select the ISL95710, move the wiper and
deselect the device without having to store the latest wiper
position in nonvolatile memory. After the wiper movement is
performed as described above and once the new position is
reached, the system must keep INC LOW while taking CS
HIGH. The new wiper position will be maintained until
changed by the system or until a power-up/down cycle
recalls the previously stored data.
H
X
L
X
Store wiper position
Standby current
H
H
X
X
No store, return to standby
Standby
H
L
X
H
Wiper up one position
(not recommended)
L
L
Wiper down one position
(not recommended)
FN8240.2
August 17, 2005
7
ISL95710
Mini Small Outline Plas tic Packages (MSOP)
N
M10.118 (JEDEC MO-187BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
INCHES
MILLIMETERS
E1
E
SYMBOL
MIN
MAX
MIN
0.94
0.05
0.75
0.18
0.09
2.95
2.95
MAX
1.10
0.15
0.95
0.27
0.20
3.05
3.05
NOTES
A
A1
A2
b
0.037
0.002
0.030
0.007
0.004
0.116
0.116
0.043
0.006
0.037
0.011
0.008
0.120
0.120
-
-B-
0.20 (0.008)
INDEX
AREA
1 2
A
B
C
-
-
TOP VIEW
4X θ
9
0.25
(0.010)
R1
c
-
R
GAUGE
PLANE
D
3
E1
e
4
SEATING
PLANE
L
0.020 BSC
0.50 BSC
-
-C-
4X θ
L1
A
A2
E
0.187
0.016
0.199
0.028
4.75
0.40
5.05
0.70
-
L
6
SEATING
PLANE
L1
N
0.037 REF
10
0.95 REF
10
-
0.10 (0.004)
-A-
C
C
b
7
-H-
A1
e
R
0.003
0.003
-
-
0.07
0.07
-
-
-
D
0.20 (0.008)
C
R1
θ
-
o
o
o
o
a
SIDE VIEW
5
15
5
15
-
C
L
o
o
o
o
0
6
0
6
-
α
E
1
-B-
Rev. 0 12/02
0.20 (0.008)
C
D
END VIEW
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
- H -
and are measured at Datum Plane.
Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
- B -
-A -
10. Datums
and
to be determined at Datum plane
.
- H -
11. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8240.2
8
August 17, 2005
相关型号：
©2020 ICPDF网 联系我们和版权申明