ISL95820CRTZ [INTERSIL]
Green Hybrid Digital Four Phase PWM Controller for Intel VR12.5 CPUs; 绿色混合数字四相PWM控制器，用于Intel VR12.5处理器
| 型号： | ISL95820CRTZ |
| 厂家： | 
Intersil |
| 描述： | Green Hybrid Digital Four Phase PWM Controller for Intel VR12.5 CPUs |
| 文件： | 总47页 (文件大小：1884K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Green Hybrid Digital Four Phase PWM Controller for
Intel VR12.5™ CPUs
ISL95820
Features
The ISL95820 Pulse Width Modulation (PWM) controller IC
provides a complete low-cost solution for Intel VR12.5™
compliant microprocessor core power supplies. It provides the
control and protection for a Voltage Regulator (VR). The VR
incorporates 3 integrated drivers and can operate in 4-, 3-, 2-
or 1-phase configurations. The VR uses a serial control bus to
communicate with the CPU and achieve lower cost and smaller
board area.
• Serial data bus
2
• SMBus/PMBus/I C interface with SVID conflict free
• Configurable 4-, 3-, 2- or 1-phase for the output using three
integrated gate drivers
• Green Hybrid Digital R3™ modulator
- Excellent transient response
- Phase shedding with power state selection
- Diode emulation in single-phase for high light-load
efficiency
The VR utilizes Intersil’s Robust Ripple Regulator R3
Technology™. The R3™ modulator has many advantages
compared to traditional modulators, including faster transient
response, variable switching frequency in response to load
transients, and improved light load efficiency due to diode
emulation mode with load-dependent low switching frequency.
• 0.5% system accuracy over-temperature
• Supports multiple current sensing methods
- Lossless inductor DCR current sensing
- Precision resistor current sensing
The ISL95820 has several other key features. It supports
either DCR current sensing with a single NTC thermistor for
DCR temperature compensation, or more precise resistor
current sensing if desired. The output comes with remote
• Differential remote voltage sensing
• Programmable V
BOOT
voltage at start-up
, load line, diode emulation,
• Resistor programmable I
MAX
voltage sense, programmable V
voltage, I
voltage
slope compensation, and switching frequency
BOOT
MAX,
transition slew rate and switching frequency, adjustable
overcurrent protection and Power-Good signal.
• Adaptive body diode conduction time reduction
Applications
• Intel VR12.5 desktop computers
VIN
PHASE4
INTERSIL
DRIVER
VIN
VCORE
PHASE3
ISL95820
VIN
PHASE2
VIN
PHASE1
FIGURE 1. SIMPLIFIED APPLICATION CIRCUIT
February 4, 2013
FN8318.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas LLC 2013. All Rights Reserved
Intersil (and design) and R3 Technology are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
ISL95820
Table of Contents
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Multiphase Power Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Interleaving. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Multiphase R3™ Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Diode Emulation and Period Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Adaptive Body Diode Conduction Time Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Programming Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
General Design Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Integrated Driver Operation and Adaptive Shoot-through Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Output Filter Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Inductor Current Sensing and Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Current Sense Circuit Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Voltage Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Fault Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
VR_HOT#/ALERT# Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Serial Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Serial VID (SVID) Supported Data and Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Serial PMBus (I2C/SMBus/PMBus) Supported Data and Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Typical Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
FN8318.0
February 4, 2013
2
ISL95820
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
TEMP. RANGE
PACKAGE
(Pb-Free)
PKG.
DWG. #
PART MARKING
(°C)
ISL95820CRTZ
ISL9582 0CRTZ
ISL9582 0IRTZ
Evaluation Board
0 to +70
-40 to +85
40 Ld 5x5 TQFN
40 Ld 5x5 TQFN
L40.5x5
L40.5x5
ISL95820IRTZ
ISL95820EVAL1Z
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL95820. For more information on MSL please see techbrief TB363.
Pin Configuration
ISL95820
(40 LD TQFN)
TOP VIEW
40 39 38 37 36 35 34 33 32 31
VR_ON
PGOOD
IMON
VR_HOT#
NTC
1
2
3
4
5
6
7
8
9
30 BOOT3
29 UGATE3
28 PHASE3
27 LGATE3
26 LGATE2
25 VCCP
GND PAD
(BOTTOM)
COMP
FB
24 UGATE2
23 PHASE2
22 BOOT2
21 LGATE1
FB2
FB3
ISEN4 10
11 12 13 14 15 16 17 18 19 20
FN8318.0
February 4, 2013
3
ISL95820
Pin Descriptions
PIN #
SYMBOL
DESCRIPTION
BOTTOM
PAD
GND
Signal common of the IC. Unless otherwise stated, signals are referenced to the GND pad. It should also be used as the
thermal pad for heat removal.
1
2
VR_ON
PGOOD
Controller enable input. A high level logic signal on this pin enables the controller.
Power-Good open-drain output indicating when VR is able to supply regulated voltage. Pull-up externally to VDD or to a
lower supply, such as 3.3V.
3
IMON
VR output current monitor. IMON sources a current proportional to the regulator output current. A resistor to ground
determines the scaling of the IMON voltage to output current.
4
5
6
7
VR_HOT#
NTC
Open drain thermal overload output indicator. Part of the communication bus with the CPU.
The thermistor input to VR_HOT# circuit. Use it to monitor VR temperature.
COMP
FB
This pin is the output of the VR error amplifier. It provides error amplifier feedback to the compensation network.
This pin is the inverting input of the VR error amplifier. A DAC-derived voltage equal to the VID reference voltage is
connected internally to the non-inverting error amplifier input.
8
9
FB2
FB3
There is an internal switch between FB pin and FB2 pin. The switch is off (open) when VR is in 1-phase mode and is on
(closed) otherwise. The components connecting to FB2 are used to adjust the compensation in 1-phase mode to achieve
optimum performance for VR.
There is an internal switch between pins FB and FB3. The switch will be on (closed) in droop mode (whenever
programmable output DC loadline operation is enabled), and off (open) when no-droop mode is selected. The purpose is
to include a resistor in parallel with the fixed droop resistor when droop is active, and to isolate that resistor when droop
is inactive. This parallel resistor increases the open-loop gain of the compensator while droop is active. The effective
droop (output DC loadline) programming resistance is the parallel combination of these two resistors.
10
11
ISEN4
ISEN3
Individual current sensing for Phase4. When ISEN4 is pulled to VDD (5V), the controller will disable VR Phase 4. This
signal is used to monitor for and to correct phase current imbalance.
Individual current sensing for Phase3. When ISEN4 and ISEN3 is pulled to VDD (5V), the controller will disable VR Phases
4 and 3. Do not disable Phase 3 without also disabling Phase 4. This signal is used to monitor for and to correct phase
current imbalance.
12
ISEN2
Individual current sensing for Phase 2. When ISEN4, ISEN3 and ISEN2 are pulled to VDD (5V), the controller will disable
VR Phases 4, 3 and 2. Do not disable Phase 2 without also disabling Phases 3 and 4. This signal is used to monitor for
and to correct phase current imbalance.
13
14
ISEN1
RTN
Individual current sensing for Phase 1. This signal is used to monitor for and to correct phase current imbalance.
Remote ground (return) voltage sensing. Part of the differential remote VR voltage sense network.
15, 16
ISUMN and VR droop current sensing inputs.
ISUMP
17
18
VDD
+5V bias power.
BOOT1
Phase 1 internal gate driver high-side MOSFET bootstrap capacitor connection. Connect an MLCC capacitor between the
BOOT1 and the PHASE1 pins. The boot capacitor is charged through an internal boot diode connected from the VCCP pin
to the BOOT1 pin each time the PHASE1 pin drops below VCCP minus the voltage dropped across the internal boot diode.
19
PHASE1
Current return path for Phase 1 high-side MOSFET gate driver. Connect the PHASE1 pin to the node consisting of the
high-side MOSFET source, the low-side MOSFET drain, and the output inductor of Phase1.
20
21
22
UGATE1
LGATE1
BOOT2
Output of Phase 1 high-side MOSFET gate driver. Connect the UGATE1 pin to the gate of Phase 1 high-side MOSFET.
Output of Phase 1 low-side MOSFET gate driver. Connect the LGATE1 pin to the gate of Phase 1 low-side MOSFET.
Phase 2 internal gate driver high-side MOSFET bootstrap capacitor connection. Connect an MLCC capacitor between the
BOOT2 and the PHASE2 pins. The boot capacitor is charged through an internal boot diode connected from the VCCP pin
to the BOOT2 pin, each time the PHASE2 pin drops below VCCP minus the voltage dropped across the internal boot diode.
23
PHASE2
Current return path for Phase 2 high-side MOSFET gate driver. Connect the PHASE2 pin to the node consisting of the
high-side MOSFET source, the low-side MOSFET drain, and the output inductor of Phase 2.
24
25
UGATE2
VCCP
Output of Phase 2 high-side MOSFET gate driver. Connect the UGATE2 pin to the gate of Phase 2 high-side MOSFET.
Input voltage bias for the internal gate drivers. Connect +5V or +12V to the VCCP pin. Decouple with at least 1µF of an
MLCC capacitor. Diode Emulation Mode must be disabled (using PROG2 pin resistor) for +5V driver operation.
FN8318.0
February 4, 2013
4
ISL95820
Pin Descriptions(Continued)
PIN #
SYMBOL
LGATE2
LGATE3
PHASE3
DESCRIPTION
26
Output of Phase 2 low-side MOSFET gate driver. Connect the LGATE2 pin to the gate of Phase 2 low-side MOSFET.
Output of Phase 3 low-side MOSFET gate driver. Connect the LGATE3 pin to the gate of Phase 3 low-side MOSFET.
27
28
Current return path for Phase 3 high-side MOSFET gate driver. Connect the PHASE3 pin to the node consisting of the
high-side MOSFET source, the low-side MOSFET drain, and the output inductor of Phase 3.
29
30
UGATE3
BOOT3
Output of Phase 3 high-side MOSFET gate driver. Connect the UGATE3 pin to the gate of Phase 3 high-side MOSFET.
Phase 3 internal gate driver high-side MOSFET bootstrap capacitor connection. Connect an MLCC capacitor between the
BOOT3 and the PHASE3 pins. The boot capacitor is charged through an internal boot diode connected from the VCCP pin
to the BOOT3 pin, each time the PHASE3 pin drops below VCCP minus the voltage dropped across the internal boot diode.
31
32
33
34
PWM4
VIN
PWM output for Phase 4. Phase 4 requires an external gate driver device. The Intersil ISL6625A driver is recommended.
Input supply voltage, used for feed-forward. Connect this pin to the input voltage of the output drive stages.
A resistor from the PROG3 pin to GND programs the internal modulator slope compensation and switching frequency.
PROG3
PROG2
A resistor from the PROG2 pin to GND programs the initial power-up voltage (V
), enables/disables the DC loadline
BOOT
(droop) function, and enables/disables diode emulation mode (DEM) in Power States 2 and 3 (PS2 and PS3).
35
PROG1
A resistor from PROG1 pin to GND programs I , the designed nominal maximum load current of the VR. The value of
MAX
establishes the scaling of the reported VR output current, which can be read via the SVID or PMBus interfaces. The
I
MAX
PROG1 resistor is chosen such that the reported I
current is FFh when the output current is equal to the maximum
MAX
load current.
2
36, 37
I2DATA, I2CLK Interface of SMBus/PMBus/I C. Tie to VCC with 4.7kΩ pull-up resistor when not used.
38, 39, 40
SDA,
SVID communication bus between the CPU and the VR.
ALERT#, SCLK,
FN8318.0
February 4, 2013
5
ISL95820
Block Diagram
VDD
NTC
TEMP MONITOR
T_MONITOR
VIN
VR_HOT#
PWM4
IMAX
VBOOT
DROOP
FREQUENCY
SLOPE COMP
PROG
PROG1
PROG2
BOOT3
PROG3
DRIVER
UGATE3
PHASE3
IDROOP
DAC
VR_ON
SDA
A/D
D/A
DIGITAL
INTERFACE
ALERT#
SCLK
LGATE3
DRIVER
MODE
I2DATA
I2CLK
BOOT2
DRIVER
UGATE2
PHASE2
R3TM
MODULATOR
/DRIVER
COMP
+
CONTROL
+
RTN
FB
+
_
Σ
E/A
LGATE2
DRIVER
FB2/FB3
CIRCUIT
FB2
FB3
IDROOP
BOOT1
ISUMP
ISUMN
+
_
CURRENT
SENSE
DRIVER
UGATE1
PHASE1
IMON
ISEN1
ISEN2
ISEN3
ISEN4
LGATE1
VCCP
DRIVER
CURRENT
BALANCING
OC FAULT
IBAL FAULT
OV FAULT
PGOOD
GND
FN8318.0
February 4, 2013
6
ISL95820
Typical Application Circuit
12V
VDD
VCCP
VIN
+5V
SDA
ALERT#
SCLK
SDA
ALERT#
SCLK
12V
VCCP
VCC
L4
UGATE
LVCC
PHASE
ISL6625A
BOOT
PWM
PWM4
LGATE
GND
SMBUS/PMBUS/I²C CLOCK
SMBUS/PMBUS/I²C DATA
I2CLK
I2DATA
10Ω
BOOT3
UGATE3
PHASE3
L3
LGATE3
10Ω
PROG1
PROG2
RROG3
BOOT2
UGATE2
PHASE2
L2
VCORE
RNTC
°C
NTC
LGATE2
VR_HOT#
VR_HOT#
10Ω
BOOT1
PGOOD
VR_ON
PGOOD
VR_ON
L1
UGATE1
PHASE1
IMON
LGATE1
10Ω
ISL95820
RSUM4
RSUM3
RSUM2
RSUM1
ISUMP
FB3
FB2
CN
RN
COMP
FB
RI
VSUMN
CVSUMN
ISUMN
ISEN4
CISEN2 CISEN3 CISEN4
CISEN1
RDROOP
RISEN4
RISEN3
RISEN2
RISEN1
ISEN3
ISEN2
VCCSENSE
VSSSENSE
RTN
ISEN1
GND
FIGURE 2. TYPICAL ISL95820 APPLICATION CIRCUIT USING INDUCTOR DCR SENSING
FN8318.0
February 4, 2013
7
ISL95820
Absolute Maximum Ratings
Thermal Information
VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +28V
VCCP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15V
BOOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +36V
Thermal Resistance (Typical)
40 Ld TQFN Package (Notes 4, 5) . . . . . . .
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . -65°C to +150°C
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . +150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
θ
JA (°C/W)
31
θ
JC (°C/W)
3
UGATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
- 0.3V to V
+ 0.3V
+ 0.3V
+ 0.3V
+ 0.3V
PHASE
- 3.5V (<100ns Pulse Width, 2µJ) to V
DC
BOOT
BOOT
VCCP
VCCP
V
PHASE
LGATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to V
DC
GND - 5V (<100ns Pulse Width, 2µJ) to V
Recommended Operating Conditions
PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 25V
DC DC
- GND < 36V)
GND - 8V (<400ns, 20µJ) to 30V (<200ns, V
Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5%
Input Voltage, VIN (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . .+4.5V to 20.0V
Driver Supply Voltage, VCCP (Note 6). . . . . . . . . . . . . . . . . +4.5V to +13.2V
Ambient Temperature
BOOT
Open Drain Outputs, PGOOD, VR_HOT#, ALERT#. . . . . . . . . . -0.3V to +7V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V
CRTZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
IRTZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Junction Temperature
CRTZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +125°C
IRTZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
5. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
6. It is recommended that VIN+VCCP not exceed 24V nominally. For VCCP < 7V, Diode Emulation Mode (DEM) must be disabled using the PROG2 pin
programming resistor.
Electrical Specifications Operating Conditions: V = 5V, T = 0°C to +70°C (ISL95820CRTZ), T = -40°C to +85°C
DD
A
A
(ISL95820IRTZ), f
= 300kHz, unless otherwise noted. Boldface limits apply over the operating temperature ranges.
SW
MIN
MAX
PARAMETER
INPUT POWER SUPPLIES
VDD Supply Current
SYMBOL
TEST CONDITIONS
(Note 7)
TYP
6.4
(Note 7)
UNITS
I
V
V
V
V
V
= 5V; VR_ON = 1V
8.0
mA
µA
kΩ
µA
mA
VDD
VDD
VDD
= 5V; VR_ON = 0V
125
VIN Supply Current
R
= 25V; VR_ON = 1V
= 25V; VR_ON = 0V
600
VIN
VIN
I
1
VIN
VIN
VCCP No Load Switching Supply
Current
I
= 12V; f = f _300k; Phases 1-3
8
VCCP
VCCP
sw
sw
= 0.1µF
active; C
BOOT1,2,3
V
= 12V; Phases inactive
0.72
1.5
mA
VCCP
POWER-ON-RESET THRESHOLDS
VDD Power-On-Reset Threshold
VDD_POR
V
V
V
V
V
V
rising
4.3
4.0
4.35
4.15
4.00
3.50
4.30
3.90
4.5
4.3
4.5
3.7
4.5
4.1
V
V
V
V
V
V
r
VDD
VDD
VDD_POR
falling
f
VIN Power-On-Reset Threshold
VCCP Power-On-Reset Threshold
VIN_POR
VIN_POR
rising
3.75
3.05
4.0
r
VIN
falling
f
VIN
VCCP_POR
rising
r
f
VCCP
VCCP
VCCP_POR
falling
3.45
SYSTEM AND REFERENCES
Maximum Output Voltage
V
VID = [10110101]
VID = [00000001]
2.3
0.5
12
3
V
OUT(MAX)
Minimum Output Voltage
V
V
OUT(MIN)
Fast Slew Rate (for VID changes)
Slow Slew Rate (for VID changes)
10
mV/µs
mV/µs
2.5
FN8318.0
February 4, 2013
8
ISL95820
Electrical Specifications Operating Conditions: V = 5V, T = 0°C to +70°C (ISL95820CRTZ), T = -40°C to +85°C
DD
A
A
(ISL95820IRTZ), f
= 300kHz, unless otherwise noted. Boldface limits apply over the operating temperature ranges. (Continued)
SW
MIN
MAX
PARAMETER
System Accuracy
SYMBOL
CRTZ
TEST CONDITIONS
(Note 7)
TYP
(Note 7)
UNITS
%
No load; closed loop, active mode range,
VID = 1.00V to 2.3V,
-0.5
+0.5
Error (V
OUT)
VID = 0.80V to 0.99V
VID = 0.5V to 0.79V
-5
-8
+5
+8
mV
mV
%
IRTZ
Error (V
No load; closed loop, active mode range,
VID = 1.00V to 2.3V
-0.8
+0.8
)
OUT
VID = 0.8V to 0.99V
VID = 0.5V to 0.79V
-8
+8
mV
mV
-10
+10
Internal V
BOOT
CRTZ
1.64
1.69
1.65
1.70
1.75
1.65
1.70
1.75
1.66
1.71
V
V
V
V
V
V
1.74
1.76
IRTZ
1.635
1.685
1.735
1.665
1.715
1.765
CHANNEL FREQUENCY
200kHz Configuration
300kHz Configuration
450kHz Configuration
AMPLIFIERS
f
f
f
_200k
_300k
_450k
180
275
410
200
300
450
220
325
490
kHz
kHz
kHz
sw
sw
sw
Current-Sense Amplifier Input Offset
CRTZ
IRTZ
I
I
= 0A
= 0A
-0.2
-0.3
+0.2
+0.3
mV
mV
dB
FB
FB
Error Amp DC Gain
Error Amp Gain-Bandwidth Product
ISEN
A
119
17
V0
GBW
C = 20pF
L
MHz
ISEN Offset Voltage
ISEN Input Bias Current
Maximum of I
- Minimum of I
1
mV
nA
SEN
SEN
20
GATE DRIVER BOOTSTRAP SWITCHES (Phases 1-3)
On-resistance
R
40
Ω
F
Reverse Leakage
I
V
= 12V, V = 0, BOOT and PHASE
VR_ON
0.2
µA
R
VDDP
connected and total current measured
GATE DRIVER OUTPUTS (Phases 1-3)
UGATE Pull-Up Resistance
UGATE Source Current
R
250mA Source Current
UGATE - PHASE = 2.5V
250mA Sink Current
UGATE - PHASE = 2.5V
250mA Source Current
LGATE - VSSP = 2.5V
250mA Sink Current
LGATE - VSSP = 2.5V
3.70
1.30
1.41
1.27
2.75
1.75
0.60
2.14
Ω
A
Ω
A
Ω
A
Ω
A
UGPU
I
UGSRC
UGATE Pull-Down Resistance
UGATE Sink Current
R
UGPD
I
UGSNK
LGATE Pull-Up Resistance
LGATE Source Current
R
LGPU
I
LGSRC
LGATE Pull-Down Resistance
LGATE Sink Current
R
LGPD
I
LGSNK
FN8318.0
February 4, 2013
9
ISL95820
Electrical Specifications Operating Conditions: V = 5V, T = 0°C to +70°C (ISL95820CRTZ), T = -40°C to +85°C
DD
A
A
(ISL95820IRTZ), f
= 300kHz, unless otherwise noted. Boldface limits apply over the operating temperature ranges. (Continued)
SW
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 7)
TYP
59
(Note 7)
UNITS
ns
t
UGATE falling to LGATE rising, no load,
UGFLGR
UGATE to LGATE Deadtime
V
= 7V
VDDP
LGATE falling to UGATE rising, no load,
= 7V
t
LGFUGR
LGATE to UGATE Deadtime
37
ns
V
VDDP
PWM4 (Phase 4)
PWM4 Output Low
PWM4 Output High
PWM4 Tri-State Leakage
PROTECTION
V
Sinking 5mA
Sourcing 5mA
PWM = 2.5V
1.0
V
V
0L
V
4.5
1
0H
µA
Overvoltage Threshold
OV
V
V
> setpoint for >1µs, SET_OV = 00h
> setpoint for >1µs, SET_OV = 01h
VID +
300mV
V
H
SEN
3.3
19
60
V
SEN
Current Imbalance Threshold
One I
SEN
above another ISEN for >3.2ms
mV
µA
Overcurrent Threshold
(See Table 1 for configuration and PSn
dependencies.)
OCP_TH
PS0 in 4-, 3-, 2-, 1-Phase configuration,
or any PSx in 1-Phase configuration
54
66
PS1 in 3-Phase configuration
36
27
40
30
44
33
µA
µA
PS1 in 4-Phase configuration
PS1/2/3 in 2-Phase configuration
PS2/3 in 4-, 3-Phase configuration
NTC = 1.3V
18
54
20
60
22
66
µA
µA
V
NTC Source Current
NTC VR_HOT# Trip Voltage, TZ 7Fh to
TZ FFh Threshold
NTC voltage forced, voltage falling threshold
0.881
0.893
0.905
NTC Thermal Alert# Trip Voltage, TZ
3Fh to TZ 7Fh Threshold
NTC voltage forced, voltage falling threshold
NTC voltage forced, voltage rising threshold
NTC voltage forced, voltage rising threshold
0.92
0.923
0.96
0.932
0.936
0.974
0.944
0.948
0.986
V
V
V
NTC VR_HOT# Reset Voltage, TZ 7Fh
to TZ 3Fh Threshold
NTC Thermal Alert# Reset Voltage, TZ
3Fh to TZ 1Fh Threshold
POWER-GOOD AND PROTECTION MONITORS
PGOOD Low Voltage
PGOOD Leakage Current
PGOOD Delay
V
I
= 4mA
0.15
0.4
1
V
OL
PGOOD
I
PGOOD = 3.3V
µA
ms
OH
tpgd
Time from VR_ON high to PGOOD high;
V
3
7
= 1.7V
BOOT
VR_HOT# Low Resistance
VR_HOT# Leakage Current
ALERT# Low Resistance
ALERT# Leakage Current
LOGICAL AND SERIAL INTERFACE
VR_ON Input Low
I
= 10mA
= 5V
12
1
Ω
µA
Ω
VR_HOT#
V
VR_HOT#
I
= 10mA
7
12
1
ALERT#
V
= 5V
µA
ALERT
V
0.3
V
V
V
IL
VR_ON Input High
V
V
CRTZ
IRTZ
0.7
IH
IH
0.75
FN8318.0
February 4, 2013
10
ISL95820
Electrical Specifications Operating Conditions: V = 5V, T = 0°C to +70°C (ISL95820CRTZ), T = -40°C to +85°C
DD
A
A
(ISL95820IRTZ), f
= 300kHz, unless otherwise noted. Boldface limits apply over the operating temperature ranges. (Continued)
SW
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 7)
TYP
0
(Note 7)
UNITS
µA
VR_ON Leakage Current
I
VR_ON = 0V
VR_ON = 1V
-1
VR_ON
3.5
42
13
6
µA
SCLK Maximum Speed
SCLK Minimum Speed
SCLK, SDA Leakage
MHz
MHz
µA
VR_ON = 0V, SCLK and SDA = 0V and 1V
VR_ON = 1V, SCLK and SDA = 1V
VR_ON = 1V, SDA = 0V
-1
-2
1
1
µA
-26
-52
−21
−42
7
−16
−32
12
µA
VR_ON = 1V, SCLK= 0V
µA
SDA Low Resistance
I
= 10mA
Ω
SDA
2
I CLK Maximum Speed
400
25
kHz
kHz
ms
Ω
2
I CLK Minimum Speed
50
35
40
1
2
I C Timeout
30
28
2
I DATA Low Resistance
I
= 4mA
I2DATA
2
2
2
2
I CLK, I DATA Leakage
VR_ON = 0V, I CLK and I DATA = 0V and 1V
-1
-2
-1
-1
µA
2
2
VR_ON = 1V, I CLK and I DATA = 1V
1
µA
2
VR_ON = 1V, I DATA = 0V
1
µA
2
VR_ON = 1V, I CLK= 0V
1
µA
NOTE:
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
FN8318.0
February 4, 2013
11
ISL95820
Theory of Operation
The ISL95820 is a 1-, 2-, 3-, or 4-phase PWM controller for the Intel
microprocessor VR12.5 core voltage regulator. The ISL95820 is
designed to be compliant to Intel VR12.5 specifications with
IL1 + IL2 + IL3, 7A/DIV
2
IL1, 7A/DIV
PWM1, 5V/DIV
SerialVID Features. The SMBus/PMBus/I C can be programmed
with the Embedded Controller. The system parameters and SVID
required registers are programmable with two dedicated pins. This
greatly simplifies the system design for various platforms and
lowers inventory complexity and cost by using a single device.
IL2, 7A/DIV
PWM2, 5V/DIV
Multiphase Power Conversion
IL3, 7A/DIV
PWM3, 5V/DIV
Microprocessor load current profiles have changed to the point
that the advantages of multiphase power conversion are
impossible to ignore. Multiphase converters overcome the
daunting technical challenges in producing a cost-effective and
thermally viable single-phase converter. The ISL95820 controller
reduces the complexity of multiphase implementation by
integrating vital functions, including integrated drivers for three
phases, direct interface for a fourth external driver device, and
requiring minimal output components. The “Typical Application
Circuit” on page 7 provides the top level views of multiphase
power conversion using the ISL95820 controller.
1µs/DIV
FIGURE 3. PWM AND INDUCTOR-CURRENT WAVEFORMS FOR
3-PHASE CONVERTER
In a multiphase converter, the output capacitor current is the
superposition of the ripple currents from each of the individual
phases. Compare Equation 1 to the expression for the peak-to-peak
current after the summation of N (symmetrically phase-shifted
inductor currents) in Equation 2, the peak-to-peak overall ripple
current (I
) decreases with the increase in the number of
C(P-P)
channels, as shown in Figure 4, which introduces the concept of the
Ripple Current Multiplier (K ). At the (steady state) duty cycles for
Interleaving
RCM
which the ripple current, and thus the K
The switching of each channel in a multiphase converter is timed
to be symmetrically out-of-phase with the other channels. For the
example of a 3-phase converter, each channel switches 1/3 cycle
after the previous channel and 1/3 cycle before the following
channel. As a result, the 3-phase converter has a combined
ripple frequency three times that of the ripple frequency of any
one phase, as illustrated in Figure 3. The three channel currents
(IL1, IL2, and IL3) combine to form the AC ripple current and to
supply the DC load current.
, is zero, the turn-off of
RCM
one phase corresponds exactly with the turn-on of another phase,
resulting in the sum of all phase currents being always the
(constant) load current, and therefore there is no ripple current in
this case.
The ripple current of a multiphase converter is less than that of a
single-phase converter supplying the same load. To understand
why, examine Equation 1, which represents an individual
channel’s peak-to-peak inductor current.
N=1
2
(V – V
) ⋅ V
OUT
IN
OUT
(EQ. 1)
I
= ---------------------------------------------------------
3
P-P
L ⋅ F
⋅ V
SW
IN
4
5
In Equation 1, V and V
IN OUT
are the input and output voltages
respectively, L is the single-channel inductor value, and F
the switching frequency.
is
SW
6
DUTY CYCLE (V )
/V
OUT IN
FIGURE 4. RIPPLE CURRENT MULTIPLIER vs DUTY CYCLE
Output voltage ripple is a function of capacitance, capacitor
equivalent series resistance (ESR), and the summed inductor
ripple current. Increased ripple frequency and lower ripple
amplitude mean that the designer can use lower
saturation-current inductors and fewer or less costly output
capacitors for any performance specification.
FN8318.0
February 4, 2013
12
ISL95820
phases. C voltage V
is a sawtooth waveform traversing
between the VW and COMP voltages. It resets (charges quickly) to
rm crm
V
OUT
(EQ. 2)
-------------------
K
RCM
I
=
=
C(P-P)
L ⋅ F
SW
VW when it discharges (with discharge current g V ) to COMP and
m o
generates a one-shot master clock signal. A phase sequencer
distributes the master clock signal to the active slave circuits. If VR is
in 4-phase mode, the master clock signal will be distributed to the
four phases 90° out-of-phase, in 3-phase mode distributed to the
three phases 120° out-of-phase, and in 2-phase mode distributed to
Phases 1 and 2 180° out-of-phase. If VR is in 1-phase mode, the
master clock signal will be distributed to Phase 1 only and will be
the Clock1 signal.
(N ⋅ D – m + 1) ⋅ (m – (N ⋅ D))
----------------------------------------------------------------------------
K
RCM
N ⋅ D
for
m – 1 ≤ N ⋅ D ≤ m
m = ROUNDUP(N ⋅ D, 0)
Another benefit of interleaving is to reduce the input ripple
current. Input capacitance is determined in part by the maximum
input ripple current. Multiphase topologies can improve overall
system cost and size by lowering input ripple current and
allowing the designer to reduce the cost of input capacitors.
Figure 5 example illustrates input currents from a three-phase
converter combining to reduce the total input ripple current.
Each slave circuit has its own ripple capacitor C , whose
rsn
voltage mimics the inductor ripple current. A g amplifier
converts the inductor voltage (or alternatively, series sense
resistor voltage, indicative of that phase’s inductor current) into a
m
current source to charge and discharge C . The slave circuit
INPUT-CAPACITOR CURRENT, 10A/DIV
rsn
turns on its PWM pulse upon receiving its respective clock signal
Clockn, and the current source charges C with a current
rsn
proportional to its respective positive inductor voltage. When C
rsn
voltage V
rises to VW, the slave circuit turns off the PWM
Crsn
pulse, and the current source then discharges C , with a current
CHANNEL 1
INPUT CURRENT
10A/DIV
rsn
proportional to its respective now-negative inductor voltage. C
rsn
discharges until the next Clockn pulse, and the cycle repeats.
CHANNEL 2
INPUT CURRENT
10A/DIV
Since the modulator works with the V
, which are
crsn
large-amplitude and noise-free synthesized signals, it achieves
lower phase jitter than conventional hysteretic mode and fixed
PWM mode controllers. Unlike conventional hysteretic mode
converters, the ISL95820 uses an error amplifier that allows the
controller to maintain a 0.5% output voltage accuracy.
CHANNEL 3
INPUT CURRENT
10A/DIV
1µs/DIV
MASTER CLOCK CIRCUIT
VW
FIGURE 5. CHANNEL INPUT CURRENTS AND INPUT-CAPACITOR
RMS CURRENT FOR 3-PHASE CONVERTER
MASTER
CLOCK
CLOCK1
CLOCK2
CLOCK3
COMP
Vcrm
MASTER
CLOCK
PHASE
SEQUENCER
The converter depicted in Figure 5 delivers 36A to a 1.5V load from
a 12V input. The RMS input capacitor current is 5.9A. Compare this
to a single-phase converter also stepping down 12V to 1.5V at 36A.
gmVo
Crm
SLAVE CIRCUIT 1
The single-phase converter has 11.9A
input capacitor current.
RMS
PHASE1 L1
CLOCK1
PWM1
Vo
S
R
The single-phase converter must use an input capacitor bank with
twice the RMS current capacity as the equivalent three-phase
converter.
VW
Q
IL1
Co
Vcrs1
gm
A more detailed exposition of input capacitor design is provided
in “Input Capacitor Selection” on page 20.
Crs1
Crs2
Crs3
SLAVE CIRCUIT 2
Multiphase R3™ Modulator
PHASE2 L2
CLOCK2
PWM2
S
R
VW
Q
The Intersil ISL95820 multiphase regulator uses the patented
R3™ (Robust Ripple Regulator™) modulator. The R3™ modulator
combines the best features of fixed frequency PWM and hysteretic
PWM while eliminating many of their shortcomings. Figure 6
shows the conceptual multiphase R3™ modulator circuit, and
Figure 7 illustrates the operational principles.
IL2
Vcrs2
gm
SLAVE CIRCUIT 3
PHASE3 L3
CLOCK3
PWM3
S
R
VW
The internal modulator uses a master clock circuit to generate the
clocks for the slave circuits, one per phase. The R3™ modulator
master oscillator slews between two voltage signals, the COMP
voltage (the output of the voltage sense error amplifier) and VW
(Voltage Window), a voltage positively offset from COMP by an offset
voltage that is dependent on the nominal switching frequency. The
Q
IL3
Vcrs3
gm
modulator discharges the master clock ripple capacitor C with a
rm
FIGURE 6. R3™ MODULATOR CIRCUIT AT 3-PHASE MODE
current source equal to g V , where g is a gain factor, dependent
m o
m
on nominal switching frequency, and also on number of active
FN8318.0
February 4, 2013
13
ISL95820
voltage, making the PWM on-time pulses wider. During load
VW
release response, the COMP voltage falls. It takes the master
clock circuit longer to generate the next master clock signal so
the PWM pulse is held off until needed. The VW voltage falls with
the COMP voltage, reducing the current PWM pulse width. The
inherent pulse frequency and width increases due to an
increasing load transient, and likewise the pulse frequency and
width reductions due to a decreasing load transient, produce the
excellent load transient response of the R3™ modulator.
HYSTERETIC
WINDOW
Vcrm
COMP
MASTER
CLOCK
CLOCK1
PWM1
Since all phases share the same VW window (master clock
frequency generator) and threshold (slave pulse width generator)
voltage, dynamic current balance among phases is ensured,
inherently, for the duration of any load transient event.
CLOCK2
PWM2
The R3™ modulator intrinsically has input voltage feed-forward
control, due to the proportional dependence of the clock generator
slave transconductance gains on the input voltage. This dependence
decreases the on-time pulse-width of each phase in proportion to an
increase in input voltage, making the output voltage insensitive to a
fast slew rate input voltage change.
CLOCK3
PWM3
VW
Diode Emulation and Period Stretching
Vcrs2 Vcrs3 Vcrs1
FIGURE 7. R3™ MODULATOR OPERATION PRINCIPLES IN
STEADY STATE AT 3-PHASE MODE
P H A S E
VW
U G A TE
LG A TE
COMP
Vcrm
MASTER
CLOCK
IL
CLOCK1
PWM1
FIGURE 9. DIODE EMULATION
The ISL95820 can operate in diode emulation mode (DEM) to
improve light load efficiency. Diode emulation can be optionally
enabled in PS2 and PS3, in Phase-1 only operation, by selection of
PROG2 pin resistance to ground. In DEM, the low-side MOSFET
conducts while the current is flowing from source to drain and
blocks reverse current, emulating a diode. As illustrated in Figure
9, when LGATE is on, the low-side MOSFET carries current, creating
negative voltage on the phase node due to the voltage drop across
the ON-resistance. The controller monitors the inductor current by
monitoring the phase node voltage. It turns off LGATE when the
phase node voltage reaches zero to prevent the inductor current
from reversing the direction and creating unnecessary power loss.
CLOCK2
PWM2
CLOCK3
PWM3
VW
Vcrs1
Vcrs3
Vcrs2
If the load current is light enough, as Figure 9 illustrates, the
inductor current will reach and stay at zero before the next phase
node pulse and the regulator is in discontinuous conduction
mode (DCM). If the load current is heavy enough, the inductor
current will never reach 0A, and the regulator will appear to
operate in continuous conduction mode (CCM), although the
controller is nevertheless configured for DEM.
FIGURE 8. R3™ MODULATOR OPERATION PRINCIPLES IN LOAD
INSERTION RESPONSE AT 3-PHASE MODE
Figure 8 illustrates the operational principles during load
insertion response. The COMP voltage rises during load insertion
(due to the sudden discharge of the output capacitor driving the
inverting input of the error amplifier), generating the master
clock signal more quickly, so the PWM pulses turn on earlier,
increasing the effective switching frequency. This phenomenon
allows for higher control loop bandwidth than conventional fixed
frequency PWM controllers. The VW voltage rises with the COMP
Figure 10 shows the operation principle in diode emulation mode
at light load. The load gets incrementally lighter in the three cases
from top to bottom. The PWM on-time is determined by the VW
window size, making the inductor current triangle the same in the
FN8318.0
February 4, 2013
14
ISL95820
three cases (only the time between inductor current triangles
Modes of Operation
changes). The controller clamps the ripple capacitor voltage V in
crs
TABLE 1. VR MODES OF OPERATION
DEM to make it mimic the inductor current. It takes the COMP
voltage longer to hit V , which produces master clock pulses,
crm
OCP
THRESHOLD
(µA)
naturally stretching the switching period. The inductor current
triangles move further apart from each other, such that the
inductor current average value is equal to the load current. The
reduced switching frequency improves light load efficiency.
ISEN4
ISEN3
ISEN2
CONFIG.
4-phase
PS
0
MODE
To Power To Power To
Stage
4-phase
CCM
60
30
20
Stage
Power CPU VR
Stage
Config.
1
2-phase
CCM
Because the next clock pulse occurs when V
COMP
(which tracks
output voltage error) rises above V
, DEM switching pulse
CRM
frequency is responsive to load transient events in a manner
similar to that of multiphase CCM operation.
2
3
1-phase
opt: DEM
or CCM
Tied to
5V
3-phase
CPU VR
Config.
0
1
3-phase
CCM
60
40
20
CCM/DCM BOUNDARY
VW
Vcrs
IL
2-phase
CCM
2
3
1-phase
opt: DEM
or CCM
LIGHT DCM
VW
Tied to
5V
2-phase
CPU VR
Config.
0
1
2-phase
CCM
60
30
Vcrs
IL
1-phase
CCM
2
3
1-phase
opt: DEM
or CCM
DEEP DCM
VW
Vcrs
Tied to 1-phase
0
1
2
3
1-phase
CCM
60
5V
CPU VR
Config.
1-phase
opt: DEM
or CCM
IL
FIGURE 10. PERIOD STRETCHING
VR can be configured for 4-, 3-, 2-, or 1-phase operation. Table 1
shows VR configurations and operational modes, programmed
by the ISEN4, ISEN3 and ISEN2 pin status, and the Set PS
command. For the 3-phase configuration, tie the ISEN4 pin to 5V.
In this configuration, phases 1, 2, and 3 are active. For the
2-phase configuration, tie the ISEN3 and ISEN4 pin to 5V. In this
configuration, phases 1 and 2 are active. For the 1-phase
configuration, tie the ISEN4, ISEN3, and ISEN2 pin to 5V. In this
configuration, only Phase 1 is active.
Adaptive Body Diode Conduction Time
Reduction
When in DCM, the controller ideally turns off the low-side
MOSFET when the inductor current approaches zero. During
on-time of the low-side MOSFET, phase voltage is negative by the
product of the (negative) inductor current and the low-side
MOSFET r
, producing a voltage drop that is proportional to
DS(ON)
the inductor current. A phase comparator inside the controller
monitors the phase voltage during on-time of the low-side
MOSFET and compares it with a threshold to determine the
zero-crossing point of the inductor current. If the inductor current
has not reached zero when the low-side MOSFET turns off, it will
flow through the low-side MOSFET body diode, causing the phase
node to have a larger voltage drop until it decays to zero. If the
inductor current has crossed zero and reversed the direction
when the low-side MOSFET turns off, it will flow through the
high-side MOSFET body diode, causing the phase node to have a
In the 4-phase configuration, VR operates in 4-phase CCM in PS0.
It enters 2-phase CCM mode in PS1 by dropping phases 4 and 3
and reducing the overcurrent protection level to 1/2 of the initial
value. It enters 1-phase DEM (optionally CCM) in PS2 and PS3 by
dropping phases 4, 3, and 2, and reducing the overcurrent
protection levels to 1/4 of the initial value.
In the 3-phase configuration, VR operates in 3-phase CCM in PS0.
(Phase 4 is disabled). It enters 2-phase CCM mode in PS1 by
dropping phase 3 and reducing the overcurrent protection level to
2/3 of the initial value. It enters 1-phase DEM (optionally CCM) in
PS2 and PS3 by dropping phases 3 and 2, and reducing the
overcurrent and the protection level to 1/3 of the initial value.
positive voltage spike (to V plus a PN diode voltage drop) until
IN
the current decays to zero. The controller continues monitoring
the phase voltage after turning off the low-side MOSFET and
adjusts the phase comparator threshold voltage accordingly in
iterative steps, such that the low-side MOSFET body diode
conducts for approximately 40ns (turning off 40ns before the
inductor current zero-crossing) to minimize the body
diode-related loss.
In the 2-phase configuration, VR operates in 2-phase CCM in PS0.
(Phases 4 and 3 are disabled.) It enters 1-phase mode in PS1,
PS2, and PS3 by dropping phase 2 and reducing the overcurrent
FN8318.0
February 4, 2013
15
ISL95820
protection level to 1/2 of the initial value. PS1 operates in CCM,
the VR alone, select R
PROG2
for V
of 1.65V, 1.7V or 1.75V.
BOOT
and PS2 and PS3 operate in DEM (optionally CCM).
Table 3 shows how to select R
to enable droop, select V
,
BOOT
PROG2
and select operational mode in PS2 and PS3 (CCM vs DEM). Note
In the 1-phase configuration, VR operates in 1-phase CCM in PS0
and PS1, and enters 1-phase DEM (optionally CCM) in PS2 and
PS3. the overcurrent protection level is the same for all power
states.
that the effective resistance value of the DC loadline, i.e., the output
voltage droop due to load current, is determined by components of
the output current sense, voltage feedback, and modulator
compensation networks.
This information is summarized in Table 1.
TABLE 3. PROG2 PROGRAMMING TABLE
Programming Resistors
There are three programming resistors: R and
R
(kΩ)
OPERATIONAL
MODE IN PS2
AND PS3
PROG2
EIA E96 1%
DROOP
ENABLED
V
, R
based on VR
BOOT
(V)
PROG1 PROG2
VALUE
R
. Table 2 shows how to select R
PROG1
PROG3
I
register settings. Determine the maximum current VR
CC(MAX)
3.24
5.76
9.53
13.3
16.9
21.0
24.9
28.7
34.0
42.2
49.9
57.6
64.9
73.2
80.6
88.7
YES
YES
YES
YES
YES
YES
YES
YES
NO
DEM
DEM
DEM
DEM
CCM
CCM
CCM
CCM
DEM
DEM
DEM
DEM
CCM
CCM
CCM
CCM
0
can support and set the VR I
register value accordingly,
value. The CPU will read the
CC(MAX)
by selecting the appropriate R
1.65
1.7
1.75
1.75
1.7
1.65
0
PROG1
VR I register value and ensure that the CPU CORE current
doesn’t exceed the value specified by VR I
CC(MAX)
.
CC(MAX)
TABLE 2. PROG1 PROGRAMMING TABLE
R
(kΩ)
VR I
PROG1
CC(MAX)
(A)
EIA E96 1% VALUE
3.24
5.76
9.53
13.3
16.9
21.0
24.9
28.7
34.0
42.2
49.9
57.6
15
20
0
25
NO
1.65
1.7
1.75
1.75
1.7
1.65
0
30
NO
35
NO
40
NO
45
NO
50
NO
55
60
NO
65
SWITCHING FREQUENCY SELECTION
70
There are a number of variables to consider when choosing the
switching frequency, as there are considerable effects on the
upper-MOSFET loss calculation. These effects are outlined in
“MOSFETs” on page 17, and they establish the upper limit for the
switching frequency. The lower limit is established by the
requirement for fast transient response and small output-voltage
ripple as outlined in “Output Filter Design” on page 20. Choose the
lowest switching frequency that allows the regulator to meet the
transient-response and output-voltage ripple requirements.
64.9
73.2
80.6
88.7
100
75
80
90
100
115
130
145
160
180
200
225
225
113
The resistor from PROG3 to GND selects one of three available
switching frequencies, 200kHz, 300kHz, and 450kHz, and sets
the modulator slope compensation value. Note that when the
ISL95820 is in continuous conduction mode (CCM), the switching
frequency is not strictly constant due to the nature of the R3™
modulator. As explained in “Multiphase R3™ Modulator” on
page 13, the effective switching frequency will increase during
load insertion and will decrease during load release to achieve
fast response. However, the switching frequency is nearly
constant at constant load. Variation is expected when the power
stage condition, such as input voltage, output voltage, load, etc.
changes. The variation is usually less than 15% and doesn’t have
any significant effect on output voltage ripple magnitude. Table 4
124
137
154
169
187
221
R
sets the start-up (V
) voltage, and selects whether the
PROG2
BOOT
Droop (programmable DC loadline) function is enabled on power-up,
and whether Diode Emulation is enabled in PS2 and PS3. When the
controller works in the targeted application with a CPU, select
R
, such that VR powers up to V
= 0V, as required by
shows how to select R
to obtain the desired modulator slope
PROG2
BOOT
PROG3
the SVID command. In the absence of a CPU, such as testing of
FN8318.0
February 4, 2013
16
ISL95820
compensation and switching frequency. There are many choices of
slope compensation for each switching frequency.
end of this current range. If through-hole MOSFETs and inductors
can be used, higher per-phase currents are possible. In cases
where board space is the limiting constraint, current can be
pushed as high as 40A per phase, but these designs require heat
sinks and forced air to cool the MOSFETs, inductors and
heat-dissipating surfaces.
TABLE 4. PROG3 PROGRAMMING TABLE
R
(kΩ)
SLOPE
SWITCHING
PROG3
EIA E96 1% VALUE
3.24
5.76
9.53
13.3
16.9
21.0
24.9
34.0
42.2
49.9
57.6
COMPENSATION
FREQUENCY (kHz)
0.25x
0.5x
0.75x
1x
200
200
200
200
200
200
200
300
300
300
300
300
300
300
300
450
450
450
450
450
450
450
450
MOSFETs
The choice of MOSFETs depends on the current each MOSFET will
be required to conduct; the switching frequency; the capability of
the MOSFETs to dissipate heat; and the availability and nature of
heat sinking and air flow.
1.25x
1.5x
1.75x
0.25x
0.5x
0.75x
1x
Lower MOSFET Power Calculation
The calculation for heat dissipated in the lower (alternatively
called low-side) MOSFET of each phase is simple, since virtually
all of the heat loss in the lower MOSFET is due to current
conducted through the channel resistance (r
). In
DS(ON)
Equation 3, I is the maximum continuous output current; I
is
M
P-P
the peak-to-peak inductor current per phase (see Equation 1 on
page 12); d is the duty cycle (V /V ); and L is the per-channel
OUT IN
inductance. Equation 3 shows the approximation.
64.9
73.2
80.6
88.7
100
1.25x
1.5x
1.75x
2x
2
2
I
I
P-P
12
(EQ. 3)
M
P
= r
+ ---------- ⋅ (1 – d)
-----
LOW, 1
DS(ON)
N
A term can be added to the lower-MOSFET loss equation to
account for the loss during the dead time when inductor current
is flowing through the lower-MOSFET body diode. This term is
0.25x
0.5x
0.75x
1x
113
dependent on the diode forward voltage at I , V ; the
M
D(ON)
switching frequency, F ; and the length of dead times (t and
sw
d1
124
t
at the beginning and the end of the lower-MOSFET
d2)
137
conduction interval respectively.
154
1.25x
1.5x
1.75x
2x
⎛
⎜
⎞
⎟
⎠
⎛
⎜
⎞
⎟
⎠
I
I
M
⎝ N
I
I
M
P-P
2
P-P
2
(EQ. 4)
P
= V
F
D(ON) SW
t
t
d2
+
----------
----------
----- –
----- –
LOW, 2
169
d1
⎝ N
187
Finally, the power loss of output capacitance of the lower
MOSFET is approximated in Equation 5:
221
General Design Guide
2
3
1.5
(EQ. 5)
--
P
≈
⋅ V
⋅ C
⋅
V
⋅ F
DS_LOW SW
LOW,3
IN
OSS_LOW
This design guide is intended to provide a high-level explanation of
the steps necessary to create a multiphase power converter. It is
assumed that the reader is familiar with many of the basic skills
and techniques referenced in the following. In addition to this
guide, Intersil provides complete reference designs, which include
schematics, bill of materials, and example board layouts for
common microprocessor applications.
where C
is the output capacitance of lower MOSFET at
OSS_LOW
the test voltage of V
ringing, the actual power dissipation will be slightly higher than
this.
. Depending on the amount of
DS_LOW
Thus the total maximum power dissipated in each lower MOSFET
is approximated by the summation of P
, P and
LOW,1 LOW,2
Power Stages
P
.
LOW,3
Upper MOSFET Power Calculation
In addition to r losses, a large portion of the upper-MOSFET
The first step in designing a multiphase converter is to determine
the number of phases. This determination depends heavily upon
the cost analysis, which in turn depends on system constraints
that differ from one design to the next. Principally, the designer
will be concerned with whether components can be mounted on
both sides of the circuit board; whether through-hole components
are permitted; and the total board space available for power
supply circuitry. Generally speaking, the most economical
solutions are those in which each phase handles between 15A
and 25A. All surface-mount designs will tend toward the lower
DS(ON)
losses are due to currents conducted across the input voltage (V
during switching. Since a substantially higher portion of the
upper-MOSFET losses are dependent on switching frequency, the
power calculation is more complex. Upper MOSFET losses can be
divided into separate components involving the upper-MOSFET
switching times; the lower-MOSFET body-diode reverse-recovery
)
IN
charge, Q ; and the upper MOSFET r
conduction loss.
rr DS(ON)
FN8318.0
February 4, 2013
17
ISL95820
When the upper MOSFET turns off, the lower MOSFET does not
Integrated Driver Operation and Adaptive
Shoot-through Protection
The ISL95820 provides three integrated MOSFET drivers, for
phases 1 through 3, and a PWM signal to operate a single external
driver device, required if a fourth phase is required. Designed for
high-speed switching, the internal MOSFET drivers control both
high-side and low-side N-Channel FETs from the internal PWM
signal
conduct any portion of the inductor current until the voltage at
the phase node falls below ground. Once the lower MOSFET
begins conducting, the current in the upper MOSFET falls to zero
as the current in the lower MOSFET ramps up to assume the full
inductor current. In Equation 6, the required time for this
commutation is t and the approximated associated power loss
1
is P
.
UP(1)
t
⎞
1
I
I
⎛
M
P-P
2
⎛
⎝
⎞
(EQ. 6)
P
≈ V
F
SW
⎜ ---- ⎟
----- + ----------
UP(1)
IN
⎠
A rising transition on the internal PWM signal (phases 1 through 3)
initiates the turn-off of the lower MOSFET. After a short
2
N
⎝
⎠
At turn on, the upper MOSFET begins to conduct and this
transition occurs over a time (t ). In Equation 7, the approximate
propagation delay [t
25ns blanking period, adaptive shoot-through circuitry monitors
the LGATE voltage and turns on the upper gate following a short
], the lower gate begins to fall. Following a
PDLL
2
power loss is P
.
UP(2)
delay time [t
] after the LGATE voltage drops below ~1.75V.
PDHU
I
t
⎞
2
2
⎠
⎛I
⎞ ⎛
The upper gate drive then begins to rise [t ] and the upper
MOSFET turns on.
P-P
2
(EQ. 7)
RU
M
P
≈ V
F
⎜
⎝
----------⎟ ⎜ ---- ⎟
----- –
UP(2)
IN
SW
N
⎠ ⎝
A falling transition on the internal PWM signal indicates the turn-
off of the upper MOSFET and the turn-on of the lower MOSFET. A
A third component involves the lower MOSFET’s reverse-recovery
short propagation delay [t
] is encountered before the upper
charge, Q . Since the inductor current has fully commutated to the
PDLU
rr
gate begins to fall [t ]. The adaptive shoot-through circuitry
upper MOSFET before the lower-MOSFET’s body diode can draw all
FU
monitors the UGATE-PHASE voltage and turns on the lower
of Q , it is conducted through the upper MOSFET across V . The
rr
IN
MOSFET a short delay time [t
] after the upper MOSFET’s
power dissipated as a result is P
and is approximated in
PDHL
UP(3)
PHASE voltage drops below +0.8V or 40ns after the upper
MOSFET’s gate voltage [UGATE-PHASE] drops below ~1.75V. The
Equation 8:
(EQ. 8)
P
= V
Q F
lower gate then rises [t ], turning on the lower MOSFET. These
UP(3)
IN rr SW
RL
methods prevent both the lower and upper MOSFETs from
conducting simultaneously (shoot-through), while adapting the
dead time to the gate charge characteristics of the MOSFETs being
used.
The resistive part of the upper MOSFET is given in Equation 9 as
P
.
UP(4)
2
2
⎛
⎜
⎝
⎞
⎟
⎠
I
P-P
I
(EQ. 9)
M
P
≈ r
+
⋅ d
----------
12
-----
UP(4)
DS(ON)
The internal drivers are optimized for voltage regulators with large
step down ratio. The lower MOSFET is usually sized larger
compared to the upper MOSFET because the lower MOSFET
conducts for a longer time during a switching period. The lower
gate driver is therefore sized much larger to meet this application
requirement. The 0.8Ω ON-resistance and 3A sink current
capability enable the lower gate driver to absorb the current
injected into the lower gate through the drain-to-gate capacitor of
the lower MOSFET and help prevent shoot-through caused by the
self turn-on of the lower MOSFET due to high dV/dt of the switching
node.
N
Equation 10 accounts for some power loss due to the
drain-source parasitic inductance (L , including PCB parasitic
DS
inductance) of the upper MOSFET, although it is not exact:
2
⎛
⎜
⎝
I
⎞
⎟
⎠
I
P-P
2
M
(EQ. 10)
P
≈ L
+
----------
-----
UP(5)
DS
N
Finally, the power loss of output capacitance of the upper
MOSFET is approximated in Equation 11:
For VCCP < 7V, Diode Emulation Mode (DEM) must be disabled
using the PROG2 pin programming resistor.
2
3
1.5
(EQ. 11)
--
P
≈
⋅ V
⋅ C
⋅
V
⋅ F
DS_UP SW
UP(6)
IN
OSS_UP
INTERNAL BOOTSTRAP DEVICE
where C
is the output capacitance of the lower MOSFET at
OSS_UP
test voltage of V
. Depending on the amount of ringing, the
The integrated drivers feature an internal bootstrap Schottky
diode equivalent circuit implemented by switchers with a typical
ON-resistance of 40Ω and without the typical diode forward
voltage drop. Simply adding an external capacitor across the
BOOT and PHASE pins completes the bootstrap circuit. The
bootstrap function is also designed to prevent the bootstrap
capacitor from overcharging due to the large negative swing at
the trailing-edge of the PHASE node. This reduces the voltage
stress on the BOOT to PHASE pins.
DS_UP
actual power dissipation will be slightly higher than this.
The total power dissipated by the upper MOSFET at full load can
now be approximated as the summation of the results from
Equations 6 through 11. Since the power equations depend on
MOSFET parameters, choosing the correct MOSFET can be an
iterative process involving repetitive solutions to the loss
equations for different MOSFETs and different switching
frequencies.
The bootstrap capacitor must have a maximum voltage rating
well above the maximum voltage intended for UVCC. Its
minimum capacitance value can be estimated using
Equation 12:
FN8318.0
February 4, 2013
18
ISL95820
MOSFET datasheet; I is the driver’s total quiescent current with
Q
Q
UGATE
no load at both drive outputs; N and N are the number of,
-------------------------------------
≥
C
Q
Q1
Q2
BOOT_CAP
ΔV
BOOT_CAP
and UVCC and LVCC are the drive voltages for, the upper and
lower MOSFETs, respectively. The I product is the
(EQ. 12)
V
Q* CCP
Q
• UVCC
quiescent power of the driver without a load.
G1
V
-----------------------------------
=
• N
Q1
UGATE
GS1
The total gate drive power losses are dissipated among the
resistive components along the transition path, as outlined in
Equation 15. The drive resistance dissipates a portion of the total
gate drive power losses; the rest will be dissipated by the external
where Q is the amount of gate charge per upper MOSFET at
G1
V
gate-source voltage and N is the number of control
GS1
MOSFETs. The ΔV
Q1
term is defined as the allowable
BOOT_CAP
gate resistors (R and R ) and the internal gate resistors (R
G1 G2 GI1
droop in the rail of the upper gate drive. Select results are
exemplified in Figure 11.
and R ) of MOSFETs. Figures 12 and 13 show the typical upper
GI2
and lower gate drives turn-on current paths.
.
1.6
P
P
= P
+ P
+ I • VCC
(EQ. 15)
DR
DR_UP
DR_LOW
Q
1.4
1.2
1.0
0.8
0.6
R
R
P
Qg_Q1
⎛
⎞
HI1
LO1
-------------------------------------- --------------------------------------- ---------------------
=
+
•
⎜
⎝
⎟
DR_UP
R
+ R
R
+ R
EXT1
2
⎠
HI1
EXT1
LO1
R
R
P
Qg_Q2
⎛
⎜
⎝
⎞
HI2
LO2
-------------------------------------- --------------------------------------- ---------------------
P
R
=
+
•
⎟
DR_LOW
R
+ R
R
+ R
EXT2
2
⎠
HI2
EXT2
LO2
R
R
GI1
GI2
-------------
-------------
= R
+
R
= R +
G2
EXT1
G1
EXT2
N
N
Q1
Q2
Q
= 100nC
UGATE
0.4
.
VCCP
50nC
BOOT
0.2
0.0
D
20nC
C
GD
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
R
HI1
G
ΔV (V)
BOOT_CAP
C
DS
FIGURE 11. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE VOLTAGE
R
R
G1
LO1
R
L1
C
GS
Q1
POWER DISSIPATION IN THE INTEGRATED DRIVERS
S
Internal driver power dissipation is mainly a function of the
PHASE
switching frequency (F ), the output drive impedance, the layout
SW
resistance, and the selected MOSFET’s internal gate resistance
FIGURE 12. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
and total gate charge (Q ). Calculating the power dissipation in the
G
driver for a desired application is critical to ensure safe operation.
Exceeding the maximum allowable power dissipation level may
push the IC beyond the maximum recommended operating
junction temperature. The DFN package is more suitable for high
frequency applications. The total gate drive power losses due to
the gate charge of MOSFETs and the driver’s internal circuitry and
their corresponding average driver current, per driver, can be
estimated using Equations 13 and 14, respectively:
VCCP
D
C
GD
R
HI2
G
C
DS
R
R
LO2
R
G2
C
L2
GS
Q2
P
= P
+ P
+ I • VCCP
Q
Qg_TOT
Qg_Q1
Qg_Q2
2
S
Q
• UVCC
G1
---------------------------------------
P
=
=
• F
• F
• N
• N
Qg_Q1
SW
Q1
V
FIGURE 13. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
GS1
2
Q
• LVCC
G2
UPPER MOSFET SELF TURN-ON EFFECT AT START-UP
--------------------------------------
P
Qg_Q2
SW
Q2
V
GS2
(EQ. 13)
Should a driver have insufficient bias voltage applied (at pin
VCCP), its outputs are floating. If the input bus is energized at a
high dV/dt rate while the driver outputs are floating, due to
Q
• UVCC • N
Q
• LVCC • N
G2 Q2
⎛
⎜
⎝
⎞
⎟
⎠
G1
Q1
----------------------------------------------------- ----------------------------------------------------
I
=
+
• F
+ I
SW
DR
Q
V
V
GS2
self-coupling via the internal C of the MOSFET, the gate of the
GD
GS1
upper MOSFET could momentarily rise up to a level greater than
the threshold voltage of the device, potentially turning on the
upper switch. Therefore, if such a situation could conceivably be
(EQ. 14)
where the gate charge (Q and Q ) is defined at a particular
G1
GS1
G2
and V
gate-to-source voltage (V
) in the corresponding
GS2
encountered, it is a common practice to place a resistor (R
)
UGPH
FN8318.0
February 4, 2013
19
ISL95820
across the gate and source of the upper MOSFET to suppress the
Miller coupling effect. The value of the resistor depends mainly
di
ΔV ≈ (ESL) ---- + (ESR) ΔI
(EQ. 17)
dt
on the input voltage’s rate of rise, the C /C ratio, as well as
GD GS
The filter capacitor must have sufficiently low ESL and ESR so
that ΔV < ΔV
the gate-source threshold of the upper MOSFET. A higher dV/dt, a
.
MAX
lower C /C ratio, and a lower gate-source threshold upper
DS GS
FET will require a smaller resistor to diminish the effect of the
internal capacitive coupling. For most applications, the
integrated 20kΩ resistor is sufficient, not affecting normal
performance and efficiency.
Most capacitor solutions rely on a mixture of high-frequency
capacitors with relatively low capacitance in combination with
bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors, allows them to support the output
voltage as the current increases. Minimizing the ESR of the bulk
capacitors, allows them to supply the increased current with less
output voltage deviation.
–V
DS
⎛
⎜
⎜
⎜
⎜
⎝
⎞
⎟
---------------------------------
dV
-------
⋅ R ⋅ C
dV
dt
iss
⎟
⎟
⎟
⎠
dt
-------
V
=
⋅ R ⋅ C
1 – e
= C
(EQ. 16)
GS_MILLER
rss
rss
The ESR of the bulk capacitors also creates the majority of the
output-voltage ripple. As the bulk capacitors sink and source the
inductor AC ripple current (see “Interleaving” on page 12 and
Equation 2), a voltage develops across the bulk-capacitor ESR
C
= C
+ C
GD GS
C
R = R
+ R
GI
iss
GD
UGPH
The coupling effect can be roughly estimated with Equation 16,
which assumes a fixed linear input ramp and neglects the
clamping effect of the body diode of the upper drive and the
bootstrap capacitor. Other parasitic components such as lead
inductances and PCB capacitances are also not taken into
account. Figure 6 provides a visual reference for this
phenomenon and its potential solution.
equal to I
(ESR). Thus, once the output capacitors are
C(P-P)
selected, the maximum allowable ripple voltage, V
,
P-P(MAX)
determines a lower limit on the inductance, as shown in
Equation 18.
V
⋅ K
OUT
RCM
(EQ. 18)
L
------------------------------------------------------------
≥ ESR ⋅
F
⋅ V ⋅ V
IN
SW
P-P(MAX)
EXTERNAL (PHASE 4) DRIVER SELECTION
Since the capacitors are supplying a decreasing portion of the
load current while the regulator recovers from the transient, the
capacitor voltage becomes slightly depleted. The output
inductors must be capable of assuming the entire load current
When a fourth phase is to be used, it is recommended that the
Intersil ISL6625A driver be selected as the external Phase 4
driver device.
before the output voltage decreases more than ΔV
places an upper limit on inductance.
. This
MAX
Output Filter Design
The output inductors and the output capacitor bank together to
form a low-pass filter responsible for smoothing the pulsating
voltage at the phase nodes. The output filter also must provide
the transient energy until the regulator can respond. Because it
has a low bandwidth compared to the switching frequency, the
output filter necessarily limits the system transient response. The
output capacitor must supply or sink load current while the
current in the output inductors increases or decreases to meet
the demand.
Equation 19 gives the upper limit on L for the cases when the
trailing edge of the current transient causes a greater
output-voltage deviation than the leading edge. Equation 20
addresses the leading edge. Normally, the trailing edge dictates
the selection of L because duty cycles are usually less than 50%.
Nevertheless, both inequalities should be evaluated, and L
should be selected based on the lower of the two results. In each
equation, L is the per-channel inductance, C is the total output
capacitance, and N is the number of active channels.
In high-speed converters, the output capacitor bank is usually the
most costly (and often the largest) part of the circuit. Output filter
design begins with minimizing the cost of this part of the circuit.
The critical load parameters in choosing the output capacitors are
the maximum size of the load step, ΔI; the load-current slew rate,
di/dt; and the maximum allowable output-voltage deviation under
2 ⋅ N ⋅ C ⋅ V
OUT
(EQ. 19)
(EQ. 20)
L ≤ ----------------------------------------- ΔV
– ΔI ⋅ ESR
MAX
2
(
)
ΔI
⋅ N ⋅ C
1.25
⎛
⎝
⎞
L ≤ ---------------------------- ΔV
– ΔI ⋅ ESR
V
– V
IN OUT
MAX
2
⎠
(
)
ΔI
transient loading, ΔV
. Capacitors are characterized according
MAX
to their capacitance, equivalent series resistance (ESR), and
equivalent series inductance (ESL).
Input Capacitor Selection
The input capacitors are responsible for sourcing the AC
component of the input current flowing into the upper MOSFETs.
Their RMS current capacity must be sufficient to handle the AC
component of the current drawn by the upper MOSFETs, which is
related to duty cycle and the number of active phases. The input
RMS current can be calculated with Equation 21..
At the beginning of the load transient, the output capacitors supply
all of the transient current. The output voltage will initially deviate by
an amount approximated by the voltage drop across the ESL. As the
load current increases, the voltage drop across the ESR increases
linearly until the load current reaches its final value. The capacitors
selected must have sufficiently low ESL and ESR so that the total
output-voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates by an amount, as
shown in Equation 17:
(EQ. 21)
2
2
2
2
I
=
K
• Io + K
• I
Lo(P-P)
IN(RMS)
IN(CM)
RAMP(CM)
FN8318.0
February 4, 2013
20
ISL95820
0.3
0.2
0.1
0
I
I
= 0
= 0.25 I
I
I
= 0.5 I
O
L(P-P)
L(P-P)
L(P-P)
L(P-P)
(N • D – m + 1) • (m – N • D)
(EQ. 22)
K
K
=
---------------------------------------------------------------------------
= 0.75 I
IN(CM)
O
O
2
N
2
3
2
3
m (N • D – m + 1) + (m – 1) (m – N • D)
=
------------------------------------------------------------------------------------------------------------------
RAMP(CM)
2
2
12N D
(EQ. 23)
0.3
0.2
0.1
0
0.2
0.4
DUTY CYCLE (V
0.6
/V
OUT IN
0.8
1.0
)
FIGURE 16. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs
DUTY CYCLE FOR 4-PHASE CONVERTER
I
I
I
= 0
L(P-P)
L(P-P)
L(P-P)
= 0.5 I
O
Figures 15 and 16 provide the same input RMS current
information for 3- and 4-phase designs, respectively. Use the
same approach to selecting the bulk capacitor type and number,
as previously described.
= 0.75 I
0.2
O
0
0
0.4
0.6
0.8
1.0
DUTY CYCLE (V
/V
)
OUT IN
FIGURE 14. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs
DUTY CYCLE FOR 2-PHASE CONVERTER
Low capacitance, high-frequency ceramic capacitors are needed
in addition to the bulk capacitors to suppress leading and falling
edge voltage spikes. The result from the high current slew rates
produced by the upper MOSFETs turn on and off. Select low ESL
ceramic capacitors and place one as close as possible to each
upper MOSFET drain to minimize board parasitic impedances
and maximize noise suppression.
For a 2-phase design, use Figure 14 to determine the input capacitor
RMS current requirement given the duty cycle, maximum sustained
output current (I ), and the ratio of the per-phase peak-to-peak
O
inductor current (I
) to I . Select a bulk capacitor with a ripple
L(P-P)
O
current rating, which will minimize the total number of input
capacitors required to support the RMS current calculated. The
voltage rating of the capacitors should also be at least 1.25x greater
than the maximum input voltage.
0.6
0.4
0.2
0.3
I
I
= 0
I
I
= 0.5 I
O
L(P-P)
L(P-P)
= 0.25 I
= 0.75 I
O
L(P-P)
O
L(P-P)
0.2
0.1
0
I
I
I
= 0
= 0.5 I
= 0.75 I
L(P-P)
L(P-P)
L(P-P)
O
O
0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (V
/V )
OUT IN
FIGURE 17. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs
DUTY CYCLE FOR SINGLE-PHASE CONVERTER
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (V
/V
)
OUT IN
MULTIPHASE RMS IMPROVEMENT
FIGURE 15. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs
DUTY CYCLE FOR 3-PHASE CONVERTER
Figure 17 is provided as a reference to demonstrate the dramatic
reductions in input-capacitor RMS current upon the
implementation of the multiphase topology. For example,
compare the input RMS current requirements of a 2-phase
converter versus that of a single-phase. Assume both converters
have a duty cycle of 0.25, maximum sustained output current of
40A, and a ratio of I
would require 17.3A
to I of 0.5. The single-phase converter
L(P-P)
current capacity, while the 2-phase
O
RMS
converter would only require 10.9A
. The advantages become
RMS
even more pronounced when output current is increased and
additional phases are added to keep the component cost down
relative to the single-phase approach.
FN8318.0
February 4, 2013
21
ISL95820
Inductor Current Sensing and Balancing
DCR
-------------
=
ω
ω
(EQ. 27)
(EQ. 28)
INDUCTOR DCR CURRENT-SENSING NETWORK
L
L
PHASE1 PHASE2 PHASE3
Rsum
Rsum
1
--------------------------------------------------------
=
sns
R
--------------
sum
N
R
×
ntcnet
ISUMP
Rsum
------------------------------------------
× C
n
R
--------------
sum
N
R
+
ntcnet
Rntcs
L
L
L
where N is the number of phases.
Cn Vcn
Ri
Rp
The inductor DCR value increases as the inductor temperature
increases, due to the positive temperature coefficient of the
copper windings. If uncompensated, this will cause the estimate
of inductor current to increase with temperature. The resistance
of the co-located NTC thermistor, R , decreases as its
temperature increases, compensating for the increase in DCR.
Rntc
Ro
DCR
DCR
DCR
ISUMN
Ro
Ro
ntc
Proper selections of R
, R
, R and R parameters ensure
sum ntcs
p
ntc
that V represents the inductor total DC current over the
temperature range of interest.
Cn
Io
FIGURE 18. DCR CURRENT-SENSING NETWORK
There are many sets of parameters that can properly
temperature-compensate the DCR change. Since the NTC network
Figure 18 shows the inductor DCR current-sensing network for the
example of a 3-phase voltage regulator. An inductor’s current flows
through the inductor’s DCR and creates a voltage drop. Each
and the R
resistors form a voltage divider, V is always a
sum
cn
fraction of the inductor DCR voltage. It is recommended to have a
high ratio of V to the inductor DCR voltage, so the current sense
cn
inductor has two resistors, R
and R , connected to the pads to
sum
o
circuit has a higher signal level to work with.
accurately sense the inductor current by sensing the DCR voltage
drop. The R and R resistors are connected in a summing
sum
network as shown, and feed the total current information to the
NTC network (consisting of R , R and R ) and capacitor C .
o
A typical set of parameters that provide good temperature
compensation are: R
= 3.65kΩ, R = 11kΩ, R = 2.61kΩ
sum
p
ntcs
ntcs ntc
p
n
and R = 10kΩ (ERT-J1VR103J). The NTC network parameters
ntc
R
is a negative temperature coefficient (NTC) thermistor, used
ntc
may need to be fine tuned on actual boards. One can apply full
load DC current and record the output voltage reading
immediately; then record the output voltage reading again when
the board has reached the thermal steady state. A good NTC
network can limit the output voltage drift to within 2mV. It is
recommended to follow the Intersil evaluation board layout and
current-sensing network parameters to minimize engineering
time.
to compensate for the change in inductor DCR due to temperature
changes.
The inductor output side pads are electrically shorted in the
schematic, but have some parasitic impedance in actual board
layout, which is why one cannot simply short them together for the
current-sensing summing network. It is recommended to use
1Ω~10Ω R to create quality signals. Since the R value is much
o
o
smaller than the rest of the current sensing circuit, the following
analysis will ignore it for simplicity.
V
(s) response must track I (s) over a broad range of frequency
Cn
o
for the controller to achieve good transient response. Transfer
function A (s) (Equation 29) has unity gain at DC, a pole ω
cs
sns,
L
The summed inductor current information is presented to the
and a zero ω . To obtain unity gain at all frequencies, set ω
L
sns
capacitor C . Equations 24 thru 28 describe the
n
equal to ω
and solve for Cn.
frequency-domain relationship between inductor total current
I (s) and C voltage V (s):
L
o
n
Cn
--------------------------------------------------------------
C
=
(EQ. 29)
n
R
sum
N
--------------
R
×
ntcnet
⎛
⎞
⎟
⎟
⎟
⎠
R
------------------------------------------
× DCR
⎜
⎜
⎜
⎝
DCR
N
ntcnet
R
------------------------------------------ -------------
V
(s) =
×
× I (s) × A (s)
(EQ. 24)
sum
Cn
o
cs
R
--------------
R
+
sum
ntcnet
N
--------------
+
R
ntcnet
N
For example, given N = 3, R
= 3.65kΩ, R = 11kΩ,
p
sum
= 2.61kΩ, R = 10kΩ, DCR = 0.9mΩ and L = 0.36µH,
R
(R
+ R ) × R
ntc p
ntcs
ntc
ntcs
----------------------------------------------------
R
A
=
(EQ. 25)
(EQ. 26)
Equation 29 gives C = 0.397µF.
ntcnet
n
R
+ R
+ R
ntc p
ntcs
Assuming the loop compensator design is correct, Figure 26
shows the expected load transient response waveforms for the
s
------
1 +
ω
correctly chosen value of C . When the load current I
has a
also has a step change,
L
n
core
----------------------
1 +
(s) =
cs
step change, the output voltage V
s
core
------------
sns
ω
determined by the DC loadline resistance (the output voltage
droop value of the regulator, (see “Current Sense Circuit
FN8318.0
February 4, 2013
22
ISL95820
Adjustments” on page 28).
If the C value is too large or too small, V (s) will not accurately
n
Cn
represent real-time I (s) and will worsen the transient response.
o
Figure 28 shows the load transient response when C is too
n
1
---------------------------
1 +
A
(s) =
(EQ. 3
Rsen
s
small. V
will droop excessively, briefly, upon abrupt load
core
-----------------
ω
insertion, before recovering to the intended DC value, which may
create a system failure. There will be excessive overshoot during
load decreases, which may potentially hurt the CPU reliability.
Rsen
With the proper selection of C , assume that A (s) = 1. With this
cs
n
assumption, Equation 29 can be recast as Equation 30:
⎛
⎜
⎜
⎜
⎝
⎞
⎟
⎟
⎟
⎠
V
R
ntcnet
DCR
------------------------------------------ -------------
Cn
----------
=
×
(EQ. 30)
1
I
R
N
----------------------------
ω
=
o
sum
(EQ. 3
Rsen
--------------
+
R
R
ntcnet
sum
N
--------------
× C
n
N
With a properly designed inductor temperature compensation
network, we may also assume the room temperature inductor DCR
value together with the room temperature value of R
in
ntcnet
subsequent calculations, since any temperature variation in one
value will be, ideally, exactly compensated by a variation in the other
value. Equation 31 can be evaluated, using room temperature
RESISTOR CURRENT-SENSING NETWORK
PHASE1 PHASE2 PHASE3
resistance values, to obtain a constant value of the ratio V /I ,
Cn
o
in units of resistance, for a given DCR current sense network
L
L
L
design. This constant value, designated ρ , will be required to
ο
complete the regulator design.
DCR
DCR
DCR
⎛
⎜
⎜
⎜
⎝
⎞
⎟
⎟
⎟
⎠
Rsum
Rsum
Rsum
R
DCR
------------------------------------------ -------------
ntcnet
ρ
=
×
(EQ. 31)
o
R
N
sum
--------------
+
R
ntcnet
ISUMP
N
RoomTemp
Rsen
Rsen
Rsen
Vcn
Cn
Ri
This expression applies to the DCR current sense circuit of
Figure 18.
ISUMN
Ro
Ro
Ro
Figure 19 shows the resistor current-sensing network for the
example of a 3-phase regulator. Each inductor has a series
current-sensing resistor R . R
and R are connected to the
sen sum
o
R
pads to accurately capture the inductor current information.
sen
The R
and R resistors are connected to capacitor C . R
sum
o
n
sum
Io
and C form a filter for noise attenuation. Equations 32 thru 34
n
FIGURE 19. RESISTOR CURRENT-SENSING NETWORK
give V (s) expression:
Cn
Transfer function A
(s) always has unity gain at DC.
Rsen
Current-sensing resistor R
value will not have significant
sen
variation over-temperature, so there is no need for the NTC
network.
R
sen
N
(EQ. 3
-------------
V
(s) =
× I (s) × A
(s)
Rsen
Cn
o
The recommended values are R
sum
= 1kΩ and C = 5600pF.
n
As with the DCR current sense network, Equation 34 can be recast
as Equation 35:
V
R
sen
N
Cn
----------
-------------
=
(EQ. 35)
I
o
This equation can be evaluated to obtain a constant value of the
ratio V /I , in Ω units, for a given sense-resistor current sense
Cn
o
network design. This constant value will be designated ρ in
ο
FN8318.0
February 4, 2013
23
ISL95820
Equation 36.
always 60µA in PS0, so Ri must be chosen to obtain the desired
I
using Equation 37:
OCP
R
sen
N
-------------
ρ
=
I
(EQ. 36)
o
OCP
--------------
Ri = ρ
×
(EQ. 37)
o
60μA
As with the DCR-sense design, this constant value will be
required to complete the regulator design. This expression
applies to the resistor current sense circuit of Figure 19.
where ρ is the constant value determined in Equations 31 or 36.
o
For a given value of output current, I , I
o
will have the value:
(EQ. 38)
droop
ρ
o
-----
I
=
× I
droop
o
Ri
PROGRAMMING OF OUTPUT OVERCURRENT
PROTECTION, I
, AND IMON
DROOP
I
is also used to program the slope of the output DC
droop
The final step in designing the current sense network is the
selection of resistor Ri of Figures 18 or 19. This resistor
determines the ratio of the controller’s internal representation of
loadline. The DC loadline slope is the programmable regulator
output resistance.
The IOUT register will contain an 8-bit unsigned number
indicative of the IMON pin voltage, scaled such that its value is
00h when V
determined, R
IMON
regulator load current is equal to I
value programmed by R
output current (I
, also called the “droop current”) to the
droop
actual output current, that is, to the sum of all the measured
inductor currents. This internal representation is itself a current
that will be used (a) to compare to the overcurrent protection
threshold, (b) to drive the IMON pin external resistor to produce a
voltage to represent the output current, which is measured and
written to the IOUT register, and (c) to source the I
the FB pin to provide the programmable load-dependent output
voltage “droop”, or output DC loadline.
= 0V, and FFh when V
is chosen, such that V
= 1.2V. With Ri
= 1.2V when the
IMON
IMON
IMON
, the maximum current
CC(MAX)
. Select R
using Equation 39:
(EQ. 39)
PROG1
IMON
–1
current to
I
droop
CC(MAX)
⎛
⎞
⎠
--------------------------
R
= 1.2V × ρ
×
IMON
o
⎝
Ri × 4
where again ρ is the constant value determined in
Equations 31 or 36.
o
Begin by selecting the maximum current that the regulator is
designed to provide. This will be the value of VR I
programmed with the PROG1 pin resistance to ground, as per
Table 2 on page 16. Select R to program the lowest
available value of I
load. The Overcurrent Protection (OCP) threshold I
exceed this value. I
OCP
CC(MAX)
PROGRAMMING THE DC LOADLINE
PROG1
that exceeds the expected maximum
The DC loadline is the effective DC series resistance of the
voltage regulator output. The output series resistance causes the
output voltage to “droop” below the selected regulation voltage
by a voltage equal to the load current multiplied by the output
resistance. The linear relationship of output voltage drop to load
current is called the loadline, and is expressed in units of
resistance. It will be designated R . Figure 21 shows the
equivalent circuit of a voltage regulator (VR) with the droop
function. An ideal VR is equivalent to a voltage source (V = VID)
CC(MAX)
must
is typically chosen to be 20% to 25%
. I will determine the value of Ri.
OCP
greater than I
CC(MAX) OCP
Refer to Table 1 on page 15. The value of OCP THRESHOLD for
any phase configuration (1- through 4-phase regulator) and any
powerstate (PS0-PS3) is the value of I
output overcurrent protection. Notice that the OCP THRESHOLD
value of the PS0 row of any phase configuration is 60µA. Ri
LL
that will trigger
droop
and output impedance Z (s). If Z (s) is equal to the load line
slope R , i.e., constant output impedance independent of
LL
frequency, V will have step response when I has a step change.
out out
should be chosen, such that I
will be 60µA when the
droop
regulator output current is equal to the chosen value of output
o
o
I
.
OCP
i
Zout(s) = RLL
o
The mechanism by which Ri determines I
Figure 20.
is illustrated in
droop
VR
V
VID
LOAD
o
...
1
1
/
4
1
ISUMP
VCn
...
Cn
gm
ISUMN
Idroop
Ri
FIGURE 21. VOLTAGE REGULATOR EQUIVALENT CIRCUIT
IMON
The ISL95820 provides programmable DC loadline resistance.
This feature can be disabled by choice of the programming
resistor on pin PROG2, or disabled via the serial bus. A typical
desired value of the DC loadline for Intel VR12.5 applications is
ADC
IOUT
RIMON
REGISTER
R
= 1.5mΩ.
LL
The programmable DC loadline mechanism is integral to the
regulator’s output voltage feedback compensator. This is
illustrated in the feedback circuit and recommended
FIGURE 20.
The ISUM transconductance amplifier produces the current that
drops the voltage V across Ri, to make V = V . This
Cn ISUMN
ISUMP
current is mirrored 1:1 to produce I , and 4:1 to produce
droop
I
. I
is compared directly to the OCP THRESHOLD,
IMON droop
FN8318.0
February 4, 2013
24
ISL95820
compensation network shown in Figure 22.
Rdroop
ρ
VCCSENSE = VOUT
o
-----
× I × R
o droop
V
= I
× R
=
(EQ. 4
Vdroop
droop
droop
droop
Ri
FB
VR LOCAL
VOUT
“CATCH”
Idroop
RESISTOR
E/A
VIDs
COMP
VID
DAC
X 1
Σ
VDAC
PHASE DUTY CYCLE BALANCING
RTN
VSS
To equally distribute power dissipation between the phases, the
ISL95820 provides a means to reduce the deviation of the duty
cycle of each phase from the average of all phases. The
VSSSENSE
INTERNAL TO IC
controller achieves duty cycle balance by matching the ISENn pin
voltages. The connection of these pins to their respective phase
nodes is depicted in Figure 23 for the inductor DCR current sense
method. The current balancing methods described in this section
apply also to current sensing using discrete sense resistors.
“CATCH”
RESISTOR
FIGURE 22. DIFFERENTIAL VOLTAGE SENSING AND LOAD LINE
IMPLEMENTATION
The ISL95820 implements the DC loadline by injecting a current,
L3
L2
L1
Rdcr3
Rdcr2
Rdcr1
Rpcb3
Rpcb2
Rpcb1
V3p
I
, which is proportional to the regulator output current I
,
PHASE3
Risen
droop
into the voltage feedback node (the FB pin). The scaling of I
OUT
droop
IL3
IL2
IL1
ISEN3
with respect to I
was selected in the previous section to
OUT
Cisen
obtain the desired output I
threshold. The droop voltage is the
V2p
OCP
voltage drop across the resistance, called R
V
INTERNAL
TO IC
o
PHASE2
Risen
, between the FB
will be selected
droop
droop droop
pin and the output voltage due to I
. R
ISEN2
to implement the desired DC loadline resistance R . The FB pin
Cisen
LL
V1p
voltage is thus raised above V
OUT
by the droop voltage, requiring
PHASE1
Risen
the regulator to reduce V
to make V equal to the voltage
OUT
FB
regulator reference voltage applied to the Error Amplifier
non-inverting input.
ISEN1
Cisen
R
is a component of the voltage regulator stability
droop
compensation network. Regulator stability and dynamic
response are somewhat insensitive to the value of R
FIGURE 23. CURRENT BALANCING CIRCUIT
, since
droop
a parallel series-RC will dominate the compensator response at,
The phase nodes have high amplitude square-wave voltage
waveforms, for which the comparative duty cycle is indicative of
each phase’s relative contribution to the output. R and C
form lowpass filters to remove the switching ripple of the phase
node voltages, such that the average voltages at the ISENn pins
approximately indicate each phase’s duty cycle, and thus the
relative contribution of each phase. The controller gradually, and
continually, trims the R3™ modulator slave circuits, such that the
and well below, the open loop crossover frequency. But R
droop
plays a singular role in determining the DC loadline, and so will
be chosen solely for that purpose.
isen
isen
For a desired R , the output voltage reduction, V
LL droop
, due to an
output load current, I , is as shown by Equation 40.
o
relative duty cycle of each phase, as indicated by each V
, is
ISENn
equal to the others. This adjustment occurs slowly compared to
the dynamic response of the multi-phase modulator to output
voltage commands, load transients, and other system
V
= R × I
LL
(EQ. 4
droop
o
perturbations. It is recommended to use a large R time
C
isen isen
constant, such that the ISEN voltages have small ripple and are
n
representative of the average or steady-state contribution of
each phase to the output. Recommended values are
The value of V
droop current, I
obtained from the ISL95820 controller is the
droop
R
= 10kΩ and C = 0.22µF.
isen
isen
, multiplied by the droop resistor, R .
droop
droop
Using Equation 41, this value is as shown by Equation 41.
Ideally, balancing the phase duty cycles will also balance the
output current provided by each phase, and thus the power
dissipated in each phase’s components. This will be the case if
the current sense elements of each phase are identical (DCR of
the inductors, or discrete current sense resistors, and the
associated current sense networks), and if parasitic resistances
of the circuit board traces from the sense connections to the
common output voltage node are identical. Figure 23 includes
Equate these two expressions for V
obtain the value in Equation 42.
and solve for R to
droop
droop
Ri × R
LL
----------------------
R
=
(EQ. 42)
droop
ρ
o
FN8318.0
February 4, 2013
25
ISL95820
the printed circuit trace resistances from each phase to the
L3
L2
Rdcr3
Rpcb3
Rpcb2
Rpcb1
V3p
Risen
common output node. If these trace resistances are all equal,
then the ideal of phase current balance will be achieved. This
balance assumes the inductors and other current sense
components are identical, comparing each phase to the others, a
true assumption within the published tolerance of component
parameters.
PHASE3
IL3
ISEN3
Cisen
V3n
Risen
Risen
INTERNAL
TO IC
Rdcr2
V
o
V2p
PHASE2
Risen
Risen
Risen
Figure 23 includes the trace-resistance from each inductor to a
IL2
ISEN2
V2n
Cisen
single common output node. Note that each R
connection
isen
(V1p, V2p, and V3p) should be routed to its respective inductor
phase-node-side pad in order to eliminate the effect of phase node
parasitic PCB resistance from the switching elements to the
inductor. Equations 43 thru 45 give the ISEN pin voltages:
L1 Rdcr1
IL1
V1p
PHASE1
Risen
Risen
Risen
ISEN1
Cisen
V1n
(EQ. 43)
V
= (R
+ R
) × I + Vo
ISEN1
dcr1
pcb1
L1
FIGURE 24. DIFFERENTIAL-SENSING CURRENT BALANCING CIRCUIT
(EQ. 44)
(EQ. 45)
V
V
= (R
= (R
+ R
+ R
) × I + Vo
ISEN2
ISEN3
dcr2
pcb2
L2
Each ISEN pin sees the average voltage of three sources: its own
phase inductor phase-node pad, and the other two phases
inductor output-side pads. Equations 46 thru 48 give the ISEN pin
voltages:
) × I + Vo
dcr3
pcb3
L3
where R
, R
and R
are the respective inductor DCRs;
dcr1 dcr2
dcr3
are the respective parasitic PCB
pcb3
(V + V + V )
3n
1p
2n
R
, R and R
------------------------------------------------
V
V
=
=
pcb1 pcb2
resistances between the inductor output-side pad and the output
voltage rail; and I , I and I are inductor average currents.
(EQ. 46)
(EQ. 47)
ISEN1
ISEN2
3
L1 L2 L3
(V + V + V )
3n
1n
2p
3
------------------------------------------------
The controller will adjust the phase pulse-width relative to the
other phases to make V = V = V , thus to achieve
ISEN1
ISEN2
= R
ISEN3
= R
I
= I = I , when there are R
and
L1 L2 L3
dcr1
dcr2
dcr3
(V + V + V )
3p
1n
2n
3
R
= R
pcb2
= R
.
pcb3
pcb1
------------------------------------------------
V
=
(EQ. 48)
ISEN3
Since using the same components for L1, L2 and L3 will typically
provide a good match of R , R and R , board layout will
dcr1 dcr2 dcr3
The controller will make V
ISEN1
the equalities shown in Equations 49 and 50:
= V
ISEN2
= V , resulting in
ISEN3
determine R
, R
and R , and thus the matching of
pcb1 pcb2
pcb3
current per phase. It is recommended to have symmetrical layout
for the power delivery path between each inductor and the output
V
+ V + V
= V + V + V
1n 2p
(EQ. 49)
(EQ. 50)
1p
2n
3n
3n
voltage rail, such that R
= R
= R .
pcb1
pcb2
pcb3
While careful symmetrical layout of the circuit board can achieve
very good matching of these trace resistances, such layout is
often difficult to achieve in practice. If trace resistances differ,
then exact matching the duty cycles of the phases will result in
the imbalance of the phase currents. A modification of this
circuit (to couple the signals of all the phases in the ISENn
networks), can correct the current imbalance due to unequal
trace resistances to the output.
V
+ V + V
= V + V + V
1n 2n
1n
2p
3n
3p
For the example case of a 3-phase configuration, Figure 24
shows the current balancing circuit with the recommended
trace-resistance imbalance correction. As before, V1p, V2p, and
V3p should be routed to their respective inductor phase-node-side
pads in order to eliminate the effect of phase node parasitic PCB
resistance from the switching elements to each inductor. The
sensing traces for V1n, V2n, and V3n should be routed to the
V
output-side inductor pads so they indicate the voltage due
OUT
only to the voltage drop across the inductor DCR, and not due to
the PCB trace resistance.
FN8318.0
February 4, 2013
26
ISL95820
Simplifying Equation 49 gives Equation 51:
REP RATE = 10kHz
V
– V
= V – V
1n 2p 2n
(EQ. 51)
1p
and simplifying Equation 50 gives Equation 52:
V
– V
= V – V
2n 3p 3n
(EQ. 52)
(EQ. 53)
(EQ. 54)
2p
Combining Equations 51 and 52 gives Equation 53:
V
– V
= V – V
= V – V
2n 3p 3n
1p
1n
2p
Which produces the desired result in Equation 54:
REP RATE = 25kHz
R
× I
= R
× I
= R
× I
dcr3 L3
dcr1
L1
dcr2
L2
Current balancing (I = I = I ) will be achieved independently
L1 L2 L3
of any mismatch of R , R
, and R , to within the
pcb1 pcb2 pcb3
tolerance of the resistance of the current sense elements. Note
that with the crosscoupling of Figure 25, the phase balancing
circuit no longer seeks to equalize the duty cycles of the phases,
but rather to equalize the DC components of the voltage drops
across the current sense elements.
REP RATE = 50kHz
Small absolute differences in PCB trace resistance from the
inductors to the common output node, can result in significant
phase current imbalance. It is strongly recommended that the
resistor pads and connections for the current balancing method
be included in any PCB layout. The decision to include the
additional Nx(N-1) trace-resistance-correcting resistors can then
be deferred until the extent of the current imbalance can be
measured on a functioning circuit. Considerations for making
this decision are described in “Current Sense OFFSET Error” on
page 28.
With the ISENn phase balancing mechanism (with cross coupling
resistors if needed, or without if not needed), the R3™ modulator
achieves excellent current balancing during both steady state
and transient operation. Figure 25 shows current balancing
performance of an evaluation board with load transient of
12A/51A at different rep rates. The inductor currents follow the
load current dynamic change with the output capacitors
supplying the difference. The inductor currents can track the load
current well at low rep rate, but cannot track the load when the
rep rate gets into the hundred-kHz range, which is outside of the
control loop bandwidth. Regardless, the controller achieves
excellent current balancing in all cases.
REP RATE = 100kHz
REP RATE = 200kHz
FIGURE 25. CURRENT BALANCING DURING DYNAMIC OPERATION.
CH1: IL1, CH2: I
, CH3: IL2, CH4: IL3
LOAD
FN8318.0
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ISL95820
CURRENT SENSE SENSITIVITY ERROR
Current Sense Circuit Adjustments
The current sense, IMON, and DC Loadline (droop) network
component values should be designed according to the
instructions in “Current Sense Circuit Adjustments” on page 28.
Once the voltage regulator is designed and a functional prototype
has been assembled, adjustments may be necessary to correct
for non-ideal components, or assembly and printed circuit board
parasitic effects. These are effects that are usually not known
until the design has been realized. The following adjustments
should be considered when refining a product design.
This will ensure the correct ratio of V
to I
(which
IMON
droop
determines R ) for the chosen system design parameters, for
LL
which no adjustment should be required. However, testing of the
resulting circuit may reveal a measurement sensitivity error
VERIFICATION OF INDUCTOR-DCR CURRENT-SENSE
POLE-ZERO MATCHING
factor, which should effect V
may be seen as a too-large R value (droop voltage per load
LL
current), and as a too-large IMON voltage for a given load current.
A single component modification will correct both errors.
and I equally. This error
IMON
droop
Recall that if the inductor DCR is used as the phase current
sense-element, it is necessary to select the capacitor C such
n
that the current sense transfer function pole at ω
matches
The current sense resistance value per phase (either a discrete
sense resistor, or the inductor DCR) is typically very small, on the
order of 1mΩ. The solder connections used in the assembly of
such sense elements may contribute significant resistance to
these sense elements, resulting in a larger load-dependent
voltage drop than due to the sense element alone. Thus, the
sensed output current value will be greater than intended for a
given load current. If this is the case, then the value of Ri (the
ISUMN pin resistor) should be increased by the factor of the
sensitivity error. For example, if the current sense value is 3%
larger than intended, then Ri should be increased by 3%.
sns,
the zero at ω . The ideal response to a load step, with DC
L
Loadline (i.e., “droop”) enabled, is shown in Figure 26.
i
o
V
o
Changing Ri will change the sensitivity, with respect to I
, of
OUT
FIGURE 26. DESIRED LOAD TRANSIENT RESPONSE WAVEFORMS
V
and I by the same factor, thus simultaneously
IMON
droop
correcting the IMON voltage error and the loadline resistance,
while preserving the intended ratio between the two parameters.
Figure 27 shows the load step transient response when C is too
n
large. V
droop response (rising or falling) lags in settling to its
core
final value.
Note that the assembly procedure for installing the current sense
elements (sense resistors or inductors) can have a significant
impact on the effective total resistance of each sense element. It
is important that any adjustments to Ri be performed on circuits
that have been assembled with the same procedures that will be
used in mass production. The current measurement sensitivity
error should be determined on a sufficient number of samples to
avoid adjusting sensitivity to correct what may be a
i
o
component-tolerance outlier.
V
o
CURRENT SENSE OFFSET ERROR
Nonlinearity of the R
resistors can induce a small positive
SUM
FIGURE 27. LOAD TRANSIENT RESPONSE WHEN C IS TOO LARGE
n
offset in the ISUMP voltage, and thus in the IMON pin current
(viewed as a positive offset in the ICC register value), and also in
the droop current (viewed as an output voltage negative offset).
The offset error occurs as follows: for each inductor, the
Figure 28 shows the load step response when Cn is too small.
V
response is underdamped, and overshoots before settling
core
to its final voltage.
instantaneous voltage across its R
resistor is approximately
SUM
. During that phase’s on time,
V
V
= V
– V
RSUM
PHASE
VIN
VOUT
= V , giving V
= V
– V
. During the off
. For the example
i
PHASE
RSUM-ON
VIN
= –V
VOUT
o
time, V
= 0V, and so V
PHASE
RSUM-OFF
VOUT
of V
= 1.8V and V
VIN
= 12V, V
= 10.2V and
VOUT
RSUM-ON
= –1.8V, a sign-dependent magnitude difference
V
RSUM-OFF
exceeding 8V. Inexpensive thick film resistors can have a voltage
nonlinearity of 25ppm/volt or more, with the device resistance
V
o
decreasing with increasing voltage. Because of this R
resistor
SUM
nonlinearity, each R
’s (positive) current into the common
SUM
ISUMP node (during its on-time) will be biased slightly greater
than the nominal V/R value expected. Each R ’s (negative)
FIGURE 28. LOAD TRANSIENT RESPONSE WHEN C IS TOO SMALL
n
SUM
current (during its off-time) will also be biased negatively due to
the resistor nonlinearity, but less so because the R voltage
Once the regulator design is complete, the measured load step
SUM
response can be compared to Figures 26 through 28. C should be
n
magnitude is always much less during the off-time than during
the on-time. This nonlinearity-bias-current polarity mismatch
adjusted if necessary to obtain the behavior of Figure 26.
causes a small positive offset error in V
.
ISUMP
FN8318.0
February 4, 2013
28
ISL95820
The exact magnitude of this offset error is difficult to predict. It
of the sense element resistance, independently of the PCB trace
resistance differences.
depends on an attribute of the sense resistors that is typically not
specified or controlled, and so not reliably quantified. It also
varies with the input voltage and the output voltage. If battery
powered, the input voltage can vary significantly. The output
voltage is subject to the VID setting, and to a lesser extent on the
droop voltage. A further complication is that the nonlinearity
offset changes with the number of active phases. For a 4-phase
The decision to populate the cross-coupling phase sense
resistors will depend upon the magnitude of, and system
tolerance of, the uncorrected imbalance current.
LOAD STEP RING BACK
Figure 29 shows the output voltage ring back problem during
load transient response with DC Loadline (i.e., “droop”) enabled.
configuration in PS0, four R
resistors are subjected to the
SUM
high difference in on-time compared to off-time voltage
magnitudes. But in PS1, two phases are disabled with the
respective PHASE nodes approximately following the output. So
The load current i has a fast step change, but the inductor
o
current i cannot accurately follow. Instead, i responds in first
L
L
order system fashion due to the nature of current loop. The ESR
and ESL effect of the output capacitors makes the output voltage
V
for the disabled phases is approximately zero for the
RSUM
entire switching cycle, reducing the offset error by half. In PS2,
three phases are disabled, leaving only a fourth of the PS0 offset
error.
V dip quickly upon load current change. However, the controller
o
regulates V according to the droop current i
, which is a
real-time representation of i ; therefore it pulls V back to the
o
droop
L
o
The most direct solution to the phenomenon of current sense
offset due to resistor nonlinearity is to use highly linear summing
resistors, such as thin film resistors. But the magnitude of the
offset error typically does not warrant the considerably greater
expense of doing so. Instead, a correcting fixed offset can be
introduced to the current sense network.
level dictated by i , causing the ring back problem. This
L
phenomenon is not observed when the output capacitor bank
has very low ESR and ESL, such as if using only ceramic
capacitors.
i
For the example case described, with each thick film
o
i
L
R
= 3.65kΩ, and an I setting of 100A, the current
SUM
CC(MAX)
sense offset error in PS0 typically represents less than 1% of full
scale, and is always positive. It has been found empirically that a
10MΩ pulldown resistor, from the ISUMP node to ground,
provides a good correcting offset compromise, slightly
V
o
under-correcting in PS0, and slightly over-correcting in PS2, but
meeting processor vendor specification tolerances with adequate
margin in all cases. For other applications, a suitable
RING
BACK
compromise pull-down resistor can be determined empirically by
testing over the full range of expected operating conditions and
power states. It is recommended that this resistor be included in
any VR design layout to allow population of the pull-down resistor
if required. Because of the high value of resistance, two smaller
valued resistors in series may be preferred, to reduce the
environmental sensitivity of high resistance value devices.
FIGURE 29. OUTPUT VOLTAGE RING BACK PROBLEM
ISUMP
Rntcs
Cn.1
PHASE CURRENT BALANCING
Vcn
Cn.2
Rp
Phase current imbalance should be measured on a functioning
circuit. First determine the correct assembly of the current
balancing mechanism by measuring, on a stable operating
regulator, the voltage difference between the ISEN1 pin and the
remaining ISENn pins (of all the operational phases) with various
static loads applied. Whether using the simplest circuit of
Figure 1 on page 1, or the PCB trace resistance compensating
circuit of Figure 2 on page 7, the voltage difference between any
pair of the ISENn pins should be very small, usually less than
1mV. If not, there may be an assembly error.
Rn
Rntc
ISUMN
Ri
OPTIONAL
Cip
Rip
OPTIONAL
FIGURE 30. OPTIONAL CIRCUITS FOR RING BACK REDUCTION
Then, again with various static loads applied, measure the
voltage directly across each active sense element (sense resistor
or inductor). Any discrepancy in the phase sense element
voltages beyond what can be attributed to the sense element
resistance tolerance must be due to PCB trace resistance
deviations. Install the cross-coupling resistors of Figure 29, and
again compare the sense element voltages. Now the sense
element voltages should be the same among the phases in all
cases (to within the tolerance of the cross-coupling resistors), and
the phase current balance will be within the parametric tolerance
Figure 30 shows two optional circuits for reduction of the ring
back.
C is the capacitor used to match the inductor time constant. It
n
often takes the paralleling of multiple capacitors to get the
desired value. Figure 30 shows that two capacitors C and C
n.1 n.2
are in parallel. Resistor R is an optional component to reduce
n
the V ring back. At steady state, C + C provides the desired
o
n.1 n.2
C capacitance. At the beginning of i change, the effective
n
o
FN8318.0
February 4, 2013
29
ISL95820
capacitance is less because R increases the impedance of the
n
C
branch. As Figure 28 shows, V tends to dip when C is too
V
L
n.1
o
n
o
small, and this effect will reduce the V ring back. This effect is
o
Q1
more pronounced when C is much larger than C . It is also
n.1 n.2
i
Q2
V
GATE
DRIVER
more pronounced when R is bigger. However, the presence of
COUT
o
n
in
R increases the ripple of the V signal if C is too small. It is
n
n
n.2
recommended to keep C greater than 2200pF. R value
n.2
n
usually is a few ohms. C , C and R values should be
determined through tuning the load transient response
waveforms directly on the target system circuit board.
n.1 n.2
n
LOAD LINE SLOPE
Ω
20
EA
MOD.
R
and C form an R-C branch in parallel with R , providing a
ip
ip
i
COMP
VID
lower impedance path than R at the beginning of I
change.
i
OUT
ISOLATION
R
and C do not have any effect at steady state. Through
TRANSFORMER
ip
ip
CHANNEL B
CHANNEL A
LOOP GAIN =
proper selection of R and C values, I
rather than i , and V will not ring back. The recommended value
for R is 100Ω. C should be determined by observing the load
transient response waveforms in a physical circuit. The
can resemble I
OUT
ip ip
droop
L
o
CHANNEL A
NETWORK
ANALYZER
CHANNEL B
ip ip
EXCITATION OUTPUT
recommended range for C is 100pF~2000pF. However, it
ip
should be noted that the R -C branch may distort the I
FIGURE 31. LOOP GAIN T1(s) MEASUREMENT SET-UP
ip ip
waveform. Instead of being triangular as the real inductor
current, I may have sharp spikes, which may adversely
droop
droop
average value detection and therefore may affect
affect I
droop
V
L
O
OCP accuracy.
Q1
Voltage Regulation
COMPENSATOR
I
V
GATE Q2
DRIVER
COUT
IN
O
Intersil provides a Microsoft Excel-based spreadsheet to help
design the compensator and the current sensing network, so the
VR achieves constant output impedance as a stable system.
Please go to www.intersil.com/design/ to request spreadsheet.
LOAD LINE SLOPE
EA
20Ω
MOD.
COMP
VID
A VR with active droop function is a dual-loop system consisting of
a voltage loop and a droop loop, which is a current loop. However,
neither loop alone is sufficient to describe the entire system. The
spreadsheet shows two loop gain transfer functions, T1(s) and
T2(s), that describe the entire system. Figure 31 conceptually
shows T1(s) measurement set-up and Figure 32 conceptually
shows T2(s) measurement set-up. The VR senses the inductor
current, multiplies it by a gain of the load line slope, then adds it
on top of the sensed output voltage and feeds it to the
compensator. T(1) is measured after the summing node, and T2(s)
is measured in the voltage loop before the summing node. The
spreadsheet gives both T1(s) and T2(s) plots. However, only T2(s)
can be actually measured on an ISL95820 regulator.
ISOLATION
TRANSFORMER
CHANNEL B
LOOP GAIN=
CHANNEL A
CHANNEL A
CHANNEL B
NETWORK
ANALYZER
EXCITATION OUTPUT
FIGURE 32. LOOP GAIN T2(s) MEASUREMENT SET-UP
FB2 Function
The FB2 function allows modification of the compensator when
operating in 1-phase. Figure 33 shows the FB2 function.
C1
C1
R2
C3.1
C3.2
R2
C3.1
C3.2
CONTROLLER IN
4/3/2-PHASE
MODE
CONTROLLER IN
1-PHASE MODE
T1(s) is the total loop gain of the voltage loop and the droop loop.
It always has a higher crossover frequency than T2(s) and has
more meaning of system stability.
C2
R3
C2
R3
FB2
FB2
T2(s) is the voltage loop gain with closed droop loop. It has more
meaning of output voltage response.
R1
R1
VSEN
VSEN
COMP
E/A
E/A
FB
FB
COMP
Design the compensator to get stable T1(s) and T2(s) with
sufficient phase margin, and output impedance equal or smaller
than the load line slope.
VREF
VREF
FIGURE 33. FB2 FUNCTION
A switch (called FB2 switch) turns on (closes) to short, internally,
the FB and the FB2 pins when the controller is in 4-phase, 3-phase
or 2-phase mode. When FB2 is closed, capacitors C3.1 and C3.2
are in parallel, serving as part of the compensator. When the
controller enters 1-phase mode, the FB2 switch opens, removing
FN8318.0
February 4, 2013
30
ISL95820
C3.2 and leaving only C3.1 in the compensator. The compensator
VDD
gain will increase with the removal of C3.2. By properly sizing C3.1
and C3.2, the compensator can be optimized separately for 4-, 3-,
2-phase modes and for 1-phase mode.
SLEW RATE
VID
VR_ON
2.5mV/µs
VID
COMMAND
VOLTAGE
While the FB2 switch is open and C3.2 is disconnected from the
FB pin, the controller actively drives the FB2 pin voltage to track
the FB pin voltage, such that the C3.2 voltage remains equal to
the C3.1 voltage. When the controller closes the FB2 switch, C3.2
will be reconnected to the compensator smoothly with no
capacitor voltage discontinuities.
2.3ms
DAC
PGOOD
ALERT#
…...
The FB2 function ensures excellent transient response in 4-, 3-,
2-phase modes and in 1-phase mode. If one decides not to use
the FB2 function, simply populate C3.1 only.
FIGURE 35. VR SOFT-START WAVEFORMS
VOLTAGE REGULATION
FB3 Function
After the start sequence, the controller regulates the output
voltage to the value set by the VID information per Table 5. The
controller will control the no-load output voltage to an accuracy of
±0.5% over the VID range. A differential amplifier allows voltage
sensing for precise voltage regulation at the microprocessor die.
The FB3 function allows for changing the compensator loop gain
depending on whether the V
Figure 34 shows the FB3 pin function.
droop function is enabled.
OUT
C1
R2
C1
R2
CONTROLLER
WITH DROOP
ENABLED
This mechanism is illustrated in Figure 22. VCC
VSS
SENSE
and
are the remote voltage sensing signals from the
CONTROLLER
SENSE
WITH DROOP
DISABLED
processor die. A unity gain differential amplifier senses the
VSS voltage and adds it to the DAC output. Note how the
C2
R3
C2
R3
C3.1
C3.1
SENSE
illustrated DC Loadline mechanism (the “droop” mechanism,
described in “Programming the DC Loadline” on page 24),
introduces a load-dependent reduction in the output voltage,
FB
FB
R1
R1
VSEN
VSEN
E/A
E/A
VREF
VREF
R1'
R1'
FB3
COMP
COMP
FB3
(denoted VCC
), below the VID value output by the DAC. The
SENSE
error amplifier regulates the inverting and the non-inverting input
voltages to be equal, as shown in Equation 55:
FIGURE 34. FB3 FUNCTION
A switch (called the FB3 switch) turns on to short ( internally) the
FB and the FB3 pins, whenever the droop function is enabled.
Resistors R1 and R1’ are in parallel when droop is enabled,
together setting the droop loadline resistance, and serving as part
of the compensator. When droop is disabled, the FB3 switch turns
off (opens), removing R1’ and leaving only R1 in the compensator.
The compensator gain will decrease with the removal of R1’. By
properly sizing R1 and R1’, the compensator can be optimized
separately for both droop enabled and disabled.
(EQ. 55)
VCC
+ V
= V
+ VSS
DAC SENSE
SENSE
droop
Rewriting Equation 55 and substitution of Equation 5 gives
Equation 56:
VCC
– VSS
= V
– R
× I
droop droop
(EQ. 56)
SENSE
SENSE
DAC
Equation 56 is the exact equation required for load line
implementation.
To use the FB3 function, the droop resistor (R
in
droop
The VCC
SENSE
and VSS signals come from the processor die.
SENSE
Equation 56) is the parallel combination of R1 and R1’. The
compensator will use R1 only while droop is disabled, and R1 in
parallel with R1’ when droop is enabled. If one decides not to use
the FB3 function, simply populate R1 only.
The feedback will be open circuit in the absence of the processor. As
Figure 22 shows, it is recommended to add a “catch” resistor to feed
the VR local output voltage back to the compensator, and add
another “catch” resistor to connect the VR local output ground to the
RTN pin. These resistors, typically 10Ω~100Ω, will provide voltage
feedback if the system is powered up without a processor installed.
START-UP TIMING
With the controller's V voltage above the POR threshold, the
DD
start-up sequence begins when VR_ON exceeds the logic high
threshold. Figure 35 shows the typical start-up timing. The
controller uses digital soft-start to ramp-up DAC to the voltage
programmed by the SetVID command. PGOOD is asserted high
and ALERT# is asserted low at the end of the ramp up. Similar
The maximum VID (output voltage command) value supported is
2.3V. Any VID command (or sum of VID command and VID offset)
above 2.3V will be ignored.
TABLE 5. VID TABLE
behavior occurs if VR_ON is tied to V , with the soft-start
sequence starting 2.3ms after V crosses the POR threshold.
DD
DD
VID
V (V)
O
7
0
0
0
0
6
0
0
0
0
5
0
0
0
0
4
0
0
0
0
3
0
0
0
0
2
0
0
0
0
1
0
0
1
1
0
0
1
0
1
HEX
VR12.5
0.00000
0.50000
0.51000
0.52000
0
0
0
0
0
1
2
3
FN8318.0
February 4, 2013
31
ISL95820
TABLE 5. VID TABLE (Continued)
VID
TABLE 5. VID TABLE (Continued)
VID
V
(V)
V (V)
O
O
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
HEX
VR12.5
0.53000
0.54000
0.55000
0.56000
0.57000
0.58000
0.59000
0.60000
0.61000
0.62000
0.63000
0.64000
0.65000
0.66000
0.67000
0.68000
0.69000
0.70000
0.71000
0.72000
0.73000
0.74000
0.75000
0.76000
0.77000
0.78000
0.79000
0.80000
0.81000
0.82000
0.83000
0.84000
0.85000
0.86000
0.87000
0.88000
0.89000
0.90000
0.91000
0.92000
0.93000
0.94000
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
3
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
2
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
HEX
VR12.5
0.95000
0.96000
0.97000
0.98000
0.99000
1.00000
1.01000
1.02000
1.03000
1.04000
1.05000
1.06000
1.07000
1.08000
1.09000
1.10000
1.11000
1.12000
1.13000
1.14000
1.15000
1.16000
1.17000
1.18000
1.19000
1.20000
1.21000
1.22000
1.23000
1.24000
1.25000
1.26000
1.27000
1.28000
1.29000
1.30000
1.31000
1.32000
1.33000
1.34000
1.35000
1.36000
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
4
5
6
7
8
9
A
B
C
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
0
1
2
3
4
5
6
7
FN8318.0
February 4, 2013
32
ISL95820
TABLE 5. VID TABLE (Continued)
VID
TABLE 5. VID TABLE (Continued)
VID
V
(V)
V (V)
O
O
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
6
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
5
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
4
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
HEX
VR12.5
1.37000
1.38000
1.39000
1.40000
1.41000
1.42000
1.43000
1.44000
1.45000
1.46000
1.47000
1.48000
1.49000
1.50000
1.51000
1.52000
1.53000
1.54000
1.55000
1.56000
1.57000
1.58000
1.59000
1.60000
1.61000
1.62000
1.63000
1.64000
1.65000
1.66000
1.67000
1.68000
1.69000
1.70000
1.71000
1.72000
1.73000
1.74000
1.75000
1.76000
1.77000
1.78000
7
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
3
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
2
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
HEX
VR12.5
1.79000
1.80000
1.81000
1.82000
1.83000
1.84000
1.85000
1.86000
1.87000
1.88000
1.89000
1.90000
1.91000
1.92000
1.93000
1.94000
1.95000
1.96000
1.97000
1.98000
1.99000
2.00000
2.01000
2.02000
2.03000
2.04000
2.05000
2.06000
2.07000
2.08000
2.09000
2.10000
2.11000
2.12000
2.13000
2.14000
2.15000
2.16000
2.17000
2.18000
2.19000
2.20000
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
8
8
8
9
A
B
C
8
8
8
8
8
8
8
8
8
8
8
8
8
8
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
A
A
A
A
A
A
A
A
A
A
A
A
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
0
1
FN8318.0
February 4, 2013
33
ISL95820
TABLE 5. VID TABLE (Continued)
VID
In the example scenario of Figure 36, the controller receives a
SetVID_decay command at t1. The VR enters DEM and the
output voltage Vo decays down slowly. At t2, before Vo reaches
the intended VID target of the SetVID_decay command, the
controller receives a SetVID_fast (or SetVID_slow) command to
go to a voltage higher than the actual Vo. The controller will
preempt the decay to the lower voltage and slew Vo to the new
target voltage at the slew rate specified by the SetVID command.
At t3, Vo reaches the new target voltage and the controller
asserts the ALERT# signal.
V
(V)
O
7
1
1
1
1
1
1
1
1
1
1
6
0
0
0
0
0
0
0
0
0
0
5
1
1
1
1
1
1
1
1
1
1
4
0
0
0
0
1
1
1
1
1
1
3
1
1
1
1
0
0
0
0
0
0
2
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
HEX
VR12.5
2.21000
2.22000
2.23000
2.24000
2.25000
2.26000
2.27000
2.28000
2.29000
2.30000
A
A
A
A
B
B
B
B
B
B
C
D
E
F
0
1
2
3
4
5
SLEW RATE COMPENSATION CIRCUIT FOR VID
TRANSITION
During a large VID transition, the DAC steps through the VID table
at proscribed step rate. For example, the DAC may change 1 tick
+
(10mV) per 1 µs, controlling output voltage V
slew rate at
core
+
less than 10mV/µs, or 1 tick per 4 µs, controlling output voltage
slew rate at less than 2.5mV/µs.
V
core
Figure 37 shows the waveforms of VID transition.
DYNAMIC VID OPERATION
The controller receives VID commands via either the Serial VID
(SVID) port or the serial I C/SMBus/PMBus port. It responds to
Rdroop
2
Vcore
VID changes by slewing to the new voltage at a slew rate
indicated in the SetVID command. There are three SetVID slew
rates: SetVID_fast, SetVID_slow, and SetVID_decay.
Cvid
Rvid
OPTIONAL
FB
Ivid
Idroop_vid
SetVID_fast command prompts the controller to enter CCM and
to actively drive the output voltage to the new VID value at a slew
rate up to but not to exceed 10mV/µs.
E/A
VIDs
COMP
VID
DAC
SetVID_slow command prompts the controller to enter CCM and
to actively drive the output voltage to the new VID value at a slew
rate up to but not to exceed 2.5mV/µs.
Σ VDAC
RTN
VSS
VSSSENSE
X 1
INTERNAL TO
IC
SetVID_decay command prompts the controller to enter DEM. The
output voltage will decay down to the new VID value at a slew rate
determined by the load. If the voltage decay rate is too fast, the
controller will limit the voltage slew rate to the fast slew rate of
10mV/µs. If DEM is disabled by the PROG2 programming resistor,
the SVID command "SetVID_decay" executes as single-phase
(Phase 1 only) “SetVID_slow” except that ALERT# signaling mimics
that of the “SetVID_decay” command.
VID
Vfb
Ivid
ALERT# is asserted (low) upon completion of all non-zero VID
transitions.
Figure 36 shows SetVID Decay Pre-Emptive response, which
occurs whenever a new VID command is received before
completion of a previous SetVID Decay command.
Vcore
S e tV ID _ d e c a y
S e tV ID _ fa s t/s lo w
Idroop_vid
V o
FIGURE 37. SLEW RATE COMPENSATION CIRCUIT FOR VID
TRANSITION
V ID
During VID transition, the output capacitor is being charged and
t3
discharged, causing C x dV
/dt current on the inductor. The
out core
t1
T _ a le rt
controller senses the inductor current increase during the up
transition (as the I waveform shows) and will droop the
t2
A L E R T #
droop_vid
accordingly, making V
output voltage V
slew rate slow.
core
core
Similar behavior occurs during the down transition. To get the
correct V slew rate during VID transition, one can add the
FIGURE 36. SETVID DECAY PRE-EMPTIVE BEHAVIOR
core
R
-C branch, whose current I compensates for I
.
vid vid vid droop_vid
FN8318.0
February 4, 2013
34
ISL95820
Choose the R, C values from the reference design as a starting
point, then tweak the actual values on the board to get the best
performance.
Because the higher output voltage requires a higher switching
duty cycle, a higher slope compensation value may be required
for stability.
During normal transient response, the FB pin voltage is held
constant, therefore is virtual ground in small signal sense. The
The abrupt inclusion of Rg to the feedback network will create a
step in the selected output voltage, which may result in high
overshoot or ringing in the output. The RC network on the gate of
the 2N7002 may slow the transition from normal range to
extended range.
R
- C network is between the virtual ground and the real
vid vid
ground, and hence has no effect on transient response.
EXTENDED V RANGE
OUT
Note that with extended range enabled, the VID step size will
increase by the inverse divider ratio. Consequently, the DVID slew
rates will also increase by the same ratio.
If a higher (than max supported VID) output voltage is required,
such as for overclocking applications, the feedback voltage can
be divided down to the FB pin such that V = VID for V
>
FB
VOUT
VID. Figure 38 shows the addition of resistor Rg (and optional
2N7002 switch), which adds the feedback voltage division to the
schematic of Figure 22 on page 25.
Fault Protection
The ISL95820 provides overcurrent, current-balance and
overvoltage fault protections. The controller also provides
over-temperature protection.
With the 2N7002 off, V
VOUT
= VID – Vdroop = VID – Rdroop*Idroop,
the same as in the normal configuration. But with the 2N7002
switch closed, V = VID -(Idroop - VID/Rg)*Rdroop = VID
The controller determines overcurrent protection (OCP) by
OUT
(1 + Rdroop/Rg) – Idroop*Rdroop.
comparing the average value of the droop current I
with an
droop
internal current source threshold as Table 4 shows. It declares OCP
when I is above the threshold for 120µs.
droop
The controller monitors the ISEN pin voltages to determine
current-balance protection. If the difference of one ISEN pin
voltage and the average ISENs pin voltage is greater than 9mV (for
at most 4ms), the controller will declare a fault and latch off.
Rdroop
Vdroop
VCCSENSE = VOUT
2N7002
FB
Rg
EN_EXT_VOUT
The controller takes the same actions for all of the above fault
protections: de-assertion of PGOOD and turn-off of all the
high-side and low-side power MOSFETs. Any residual inductor
current will decay through the MOSFET body diodes.
Idroop
E/A
COMP
DAC
X 1
VID
RTN
VSS
Σ
VDAC
COMP
The controller will declare an overvoltage protection (OVP) fault and
de-assert PGOOD if the voltage of the ISUMN pin (approximately the
output voltage) exceeds the VID set value by +300mV. Optionally,
the overvoltage threshold can be set, via the PMBus interface, to
3.3V fixed. The controller will immediately declare an OV fault,
de-assert PGOOD, and turn on the low-side power MOSFETs. The
low-side power MOSFETs remain on until the output voltage is
pulled down below the VID set value when all power MOSFETs are
turned off. If the output voltage rises above the VID set value again,
the protection process is repeated. This behavior provides the
maximum amount of protection against shorted high-side power
MOSFETs while preventing output ringing below ground.
VSSSENSE
INTERNAL TO IC
FIGURE 38. EXTENDING THE RANGE OF VOUT WITH A FEEDBACK
RESISTOR DIVIDER
The unloaded output voltage is then V
VOUT (unloaded)
= VID
(1 + Rdroop/Rg), and the droop voltage Vdroop = Idroop*Rdroop.
Notice that the droop voltage is determined by the droop resistor,
and is independent of whether the feedback voltage is divided or
not. Then Rg is selected to obtain the desired divider ratio. The
programmed loadline resistance is not affected by the addition
of Rg.
The default overvoltage fault threshold is 2.6V when output
voltage ramps up from 0V. The overvoltage fault threshold
reverts to VID + 300mV after the output voltage settles.
Optionally, via the PMBus interface, the overvoltage threshold
can be fixed at 3.3V prior to increasing VID from 0V.
To avoid false OVP faults, the OVP threshold may have to be
changed to 3.3V fixed, rather than at the relative value of 300mV
above VID, via the PMBus interface (see “Fault Protection” on
page 35 for details). The OVP threshold must be changed prior to
turning on the EN_EXT_VOUT switch. Because of OVP, a practical
All the above fault conditions can be reset by bringing VR_ON low
or by bringing V below the POR threshold. When VR_ON and
DD
upper limit for V
is 3.04V, which is also the maximum defined
VOUT
V
return to their high operating levels, a soft-start will occur.
DD
VID value. The maximum supported VID value in the ISL95820 is
2.3V, so the inverse divider ratio (1 + Rdroop/Rg) should not
exceed 1.32.
FN8318.0
February 4, 2013
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ISL95820
TABLE 7. TZONE TABLE
Table 6 summarizes the fault protections.
VNTC (V)
1.04
1.08
1.12
1.16
1.2
TMAX (%)
88
TZONE
0Fh
TABLE 6. FAULT PROTECTION SUMMARY
FAULT DURATION
85
07h
BEFORE
PROTECTION
PROTECTION
ACTION
FAULT
RESET
FAULT TYPE
Overcurrent
82
03h
01h
01h
00h
79
120µs
PWM4/Phase tri- VR_ON
state, PGOOD
latched low
toggle or
VDD
toggle
76
>1.2
<76
Phase Current
Imbalance
4ms
Figure 39 shows how the NTC network should be designed to get
correct VR_HOT#/ALERT# behavior when the system temperature
rises and falls, manifested as the NTC pin voltage falls and rises. The
series of events are:
Overvoltage: V
VID + 300mV
>
>
Immediate
PGOOD latched
low. Actively pulls
the output voltage
to below VID
value, then
tri-states the
OUT
(optionally 3.3V
fixed)
1. The temperature rises so the NTC pin voltage drops. Tzone
value changes accordingly.
Overvoltage: V
OUT
2. The temperature crosses the threshold where Tzone register
Bit 6 changes from 0 to 1.
phase switches
(Phases 1, 2, 3)
and PWM4.
2.6V = VIDmax +
300mV (optionally
3.3V fixed) during
3. The controller changes Status_1 register bit 1 from 0 to 1.
4. The controller asserts ALERT#.
output voltage ramp
up from 0V
5. The CPU reads Status_1 register value to know that the alert
assertion is due to Tzone register Bit 6 flipping.
VR_HOT#/ALERT# Behavior
6. The controller clears ALERT#.
7. The temperature continues rising.
VR Temperature
Temp Zone
3% Hysteresis
1111 1111
0111 1111
0011 1111
0001 1111
7
Bit 7 =1
Bit 6 =1
Bit 5 =1
8. The temperature crosses the threshold where Tzone register
Bit 7 changes from 0 to 1.
1
10
9. The controller asserts VR_HOT# signal. The CPU reduces
power consumption, and the system temperature eventually
drops.
12
Temp Zone
Register
10. The temperature crosses the threshold where Tzone register
Bit 6 changes from 1 to 0. This threshold is 1 ADC step lower
than the one when VR_HOT# gets asserted, to provide 3%
hysteresis.
2
8
0001 1111 0011 1111 0111 1111 1111 1111 0111 1111 0011 1111 0001 1111
Status 1
Register
= “011” 3
= “001”
= “001”
GerReg 15
Status1
13
14
5
GerReg
Status1
11. The controllers de-asserts VR_HOT# signal.
SVID
12. The temperature crosses the threshold where Tzone register
Bit 5 changes from 1 to 0. This threshold is 1 ADC step lower
than the one when ALERT# gets asserted during the
temperature rise to provide 3% hysteresis.
ALERT#
6
4
16
VR_HOT#
9
11
13. The controller changes Status_1 register bit 1 from 1 to 0.
14. The controller asserts ALERT#.
FIGURE 39. VR_HOT#/ALERT# BEHAVIOR
The controller drives 60µA current source out of the NTC pin. The
current source flows through the respective NTC resistor
networks on the pins and creates voltages that are monitored by
the controller through an A/D converter (ADC) to generate the
Tzone value. Table 7 shows the programming table for Tzone. The
user needs to scale the NTC network resistance, such that it
generates the NTC pin voltage that corresponds to the left-most
column. Do not use any capacitor to filter the voltage.
15. The CPU reads Status_1 register value to know that the alert
assertion is due to Tzone register Bit 5 flipping.
16. The controller clears ALERT#.
To disable the NTC function, connect the NTC pin to VDD using a
pullup resistor.
Serial Interfaces
TABLE 7. TZONE TABLE
Serial VID (SVID) Supported Data and
Configuration Registers
The controller supports the following data and configuration
registers, accessible via the SVID interface.
VNTC (V)
0.84
TMAX (%)
>100
100
TZONE
FFh
0.88
FFh
0.92
97
7Fh
The device is compliant with Intel VR12.5/VR12/IMVP7 SVID
protocol. To ensure proper CPU operation, refer to this document
for SVID bus design and layout guidelines; each platform requires
0.96
94
3Fh
1.00
91
1Fh
FN8318.0
February 4, 2013
36
ISL95820
TABLE 8. SUPPORTED DATA AND CONFIGURATION
REGISTERS (Continued)
different pull-up impedance on the SVID bus, while impedance
matching and spacing among DATA, CLK, and ALERT# signals
must be followed. Common mistakes are insufficient spacing
among signals and improper pull-up impedance.
REGISTER
NAME
DEFAULT
VALUE
INDEX
31h
DESCRIPTION
VID Setting Data register containing currently
programmed VID voltage. See Table 5
beginning on page 31.
TABLE 8. SUPPORTED DATA AND CONFIGURATION
REGISTERS
REGISTER
NAME
DEFAULT
VALUE
32h
33h
Power State Register containing the current
programmed power state.
00h
INDEX
00h
DESCRIPTION
Vendor ID
Uniquely identifies the VR vendor.
Assigned by Intel.
12h
Voltage
Offset
Sets offset in VID steps added to the 00h
VID setting for voltage margining,
expressed as an 8-bit 2's-complement
offset value. For example:
...
01h
02h
05h
06h
Product ID
Uniquely identifies the VR product.
Intersil assigns this number.
10h
Product
Revision
Uniquely identifies the revision of the
VR control IC. Intersil assigns this data.
FEh = -2 VID steps
FFh = -1 VID step
00h = zero offset, no margin
01h = +1 VID step
02h = +2 VID steps
...
Protocol ID Identifies what revision of SVID
protocol the controller supports.
03h
00h
Capability
Identifies the SVID VR capabilities and 81h
which of the optional telemetry
registers are supported.
34h
Multi VR
Config
Data register that configures multiple 00h
VRs behavior on the same SVID bus.
10h
Status_1
Data register read after ALERT#
signal. Indicating if a VR rail has
settled, has reached VRHOT condition
or has reached ICC max.
The SVID alertB is asserted for the following conditions:
1. When VRsettled is asserted for non-zero volt
commandedVID. If the commandedVID is changed, the
alertB will de-assert while the DAC is moving to the new
target.
11h
12h
Status_2
Data register showing status_2
communication.
00h
00h
Temperature Data register showing temperature
Zone
zones that have been entered.
2. Therm alert changing from 0 to 1 or from 1 to 0. (Read
Status1 required to clear this alert flag.)
15h
1Ch
ICC
Read output current, range 00h to FFh
Status_2_
LastRead
This register contains a copy of the
Status_2 data that was last read with
the GetReg (Status_2) command.
00h
3. I
alert changing from 0 to 1 or from 1 to 0. (Read
CC(MAX)
Status1 required to clear this alert flag.)
2
21h
I
Data register containing the ICC max Refer to
the platform supports, set at start-up Table 2
by resistors Rprog1 and Rprog2. The
platform design engineer programs
this value during the design process.
Binary format in amps, i.e., 100A =
64h
CC(MAX)
Serial PMBus (I C/SMBus/PMBus) Supported
Data and Configuration Registers
The ISL95820 features SMBus, PMBus, and I C with fixed write
address 80h and fixed read address 81h. (The least significant
bit of the 8-bit address is for write (0h) and read (1h).)
SMBus/PMBus includes an Alert# line and Packet Error Check
(PEC) to ensure data properly transmitted. In addition, the output
voltage and offset, droop enable, overvoltage setpoint, and the
priority of SVID and SMBus/PMBus/I C can be written and read
via this bus, as summarized in Table 9. Output current and
voltage setting can be read as summarized in Table 10. For
2
22h
24h
Temp max
SR-fast
Not supported
00h
0Ah
Slew Rate Normal. The fastest slew
rate the platform VR can sustain.
Binary format in mV/µs. i.e.,
0Ah = 10mV/µs.
2
2
25h
26h
SR-slow
Is 4x slower than normal. Binary
02h
proper operation, users should follow the SMBus, PMBus, and I C
format in mV/µs. i.e., 02h = 2.5mV/µs
protocol, as shown in Figure 42. Note that STOP (P) bit is NOT
allowed before the repeated START condition when “reading”
contents of register, as shown in Figure 42.
V
If programmed by the platform, the VR 00h
supports V voltage during
BOOT
BOOT
start-up ramp. The VR will ramp to
and hold at V until it
V
BOOT
BOOT
receives a new SetVID command to
move to a different voltage.
30h
V
max
This register is programmed by the
master and sets the maximum VID the
VR will support. If a higher VID code is
received, the VR will respond with “not
supported” acknowledge.
B5h
OUT
FN8318.0
February 4, 2013
37
ISL95820
2
SMBus/PMBus/I C allows programming the registers of Table 9,
11ms after VCC above POR, and after VR_ON input is high.
5V
User Can Change
Resistor Divider
To Reset 0C- 0F
VCC POR
TIME OUT
READER
DONE
VCC
SVID 0C-0F CONFIGURATION
LOADED WITH New DC-DF
READER
RE-LOADED
READER
RE-LOADED
2 ms
9 ms
INDEFINITELY
ENABLE
4.6 ms
4.6 ms
D0 to F3
D0 to F3
COMMAND
COMMAND
NO SUCCESFUL BUS SEND COMMAND
V
OUT
2
FIGURE 40. SIMPLIFIED SMBus/PMBus/I C INITIALIZATION TIMING DIAGRAM WHEN NO BUS WRITE COMMAND RECEIVED
5V
VCC POR
TIME OUT
READER
DONE
VCC
SVID 0C-0F CONFIGURATION
LOADED WITH DC-DF
SVID 0C-0F CONFIGURATION
LOADED WITH NEW DC-DF
USE PREVIOUS
SVID 0C-0F
2 ms
9 ms
INDEFINITELY
ENABLE
DC to DF
D0 to F3
D0 to F3
DC to DF
D0 to F3
D1 to F3
COMMAND
COMMAND
COMMAND
COMMAND
COMMAND
COMMAND
V
OUT
2
FIGURE 41. SIMPLIFIED SMBus/PMBus/I C INITIALIZATION TIMING DIAGRAM WHEN BUS WRITE COMMAND SUCESSFULLY RECEIVED
Not Used for One Byte Word
Write Byte/Word Protocol
1
7 + 1
1
8
1
8
1
1
8
8
1
1
S
A
Command Code
Slave Address_0
A
Low Data Byte
A
High Data Byte
A
PEC
A
P
Optional 9 Bits for SMBus/PMBus
2
NOT used in I C
Example command: DAh SET_VID (one word, High Data Byte and ACK are not used)
S: Start Condition
A: Acknowledge (“0”)
N: Not Acknowledge (“1”)
W: Write (“0”)
RS: Repeated Start Condition
R: Read (“1”)
PEC: Packet Error Checking
P: Stop Condition
Acknowledge or DATA from Slave,
ISL95820 Controller
2
FIGURE 42. SMBus/PMBus/I C PROTOCOL
FN8318.0
February 4, 2013
38
ISL95820
2
TABLE 9. SMBus, PMBus, AND I C WRITE AND READ REGISTERS
COMMAND
CODE
ACCESS
R/W
DEFAULT
COMMAND NAME
DESCRIPTION
D4h[0]
DROOP_EN
0h=Droop Disabled; 1h = Droop Enabled; default determined by PROG2
pin resistance to ground. See Table 3. When the controller is reset by the
VR_ON pin transitioning from low to high, the PROG2 resistance is
measured and this register is stored accordingly.
2
D6h[1:0]
D8h[0]
R/W
R/W
R/W
00h
00h
LOCK_SVID
SET_OV
set SVID and SMBus/PMBus/I C Priority (See Table 11 for details)
0h = VID+300mV, 1h = 3.3V fixed.
DAh[7:0]
SET_VID
SVID Bus VID Code. See Table 5 beginning on page 31. Default to V
value on start-up, determined by PROG2 pin resistance to ground.
BOOT
DBh[7:0]
R/W
00h
SET_OFFSET
SVID Bus VID offset code, expressed as an 8-bit 2's-complement offset
value. For example:
...
FEh = -2 VID steps
FFh = -1 VID step
00h = zero offset, no margin
01h = +1 VID step
02h = +2 VID steps
...
2
TABLE 10. SMBus, PMBus, AND I C TELEMETRIES
WORD LENGTH
(BYTE)
CODE
8Bh
COMMAND NAME
DESCRIPTION
TYPICAL RESOLUTION
8-BIT, 10mV
TWO
READ_VOUT
Output Voltage
(VID+OFFSET, see Table 5
8Ch
TWO
READ_IOUT
Output Current (FF = I
8-BIT, I
/255
CC(MAX)
CC(MAX)
FN8318.0
February 4, 2013
39
ISL95820
TABLE 11. LOCK_SVID
2
SVID
SMBus, PMBus or I C
SETPS (1/2/3)
D6h
00h
01h
02h
03h
SETVID
Yes
AND SETDECAY SET OFFSET
SETVID
Not
SET OFFSET
FINAL DAC
TARGETED APPLICATIONS
Not Overclocking
Not Overclocking
Overclocking
Yes
Yes
Not
Yes
Yes
Yes
SV_VID + SV_OFFSET
SV_VID + PM_OFFSET
SV_VID + PM_OFFSET
PM_VID + PM_OFFSET
Yes
Yes
Yes
Not
Yes
ACK ONLY
ACK ONLY
ACK ONLY
ACK ONLY
Not
ACK ONLY
Yes
Overclocking
NOTE:
2
8. The ISL95820 controller is designed such that all SVID commands are acknowledged as if the SMBus, PMBus or I C does not exist. To avoid conflict
2
between SMBus/PMBus/I C and SVID bus during operation, execute this command prior to writing the VID setting or offset commands. With 01h
option, SMBus/PMBus/I C’s OFFSET should only adjust slightly higher or lower (say ±20mV) than SVID OFFSET for margining purpose or PCB loss
2
compensation so that CPU will not draw significantly more power in PSI1/2/3/Decay mode. To program full range of PM_OFFSET for overclocking
2
applications, select 02h or 03h options. 03h option gives full control of the output voltage (VID+OFFSET) via SMBus/PMBus/I C, commonly used in
overclocking applications. Prior to a successful written PMBus VID or OFFSET, the controller will continue executing SVID VID or OFFSET command.
FN8318.0
February 4, 2013
40
ISL95820
Layout Guidelines
ISL95820
PIN NUMBER
SYMBOL
GND
LAYOUT GUIDELINES
BOTTOM PAD
Connect this ground pad to the ground plane through low impedance path. Recommend use of at least 5 vias to connect
to ground planes in PCB internal layers. This is also the primary conduction path for heat removal.
1
2
3
4
5
VR_ON
PGOOD
IMON
No special consideration.
No special consideration.
No special consideration.
No special consideration.
VR_HOT#
NTC
The NTC thermistor needs to be placed close to the thermal source that is monitored to determine CPU V
core
thermal
throttling. Recommend placing it at the hottest spot of the CPU V
VR.
core
Place the compensator components in general proximity of the controller.
6
7
COMP
FB
8
FB2
9
FB3
10
11
12
13
ISEN4
ISEN3
ISEN2
ISEN1
Each ISEN pin has a capacitor (Cisen) decoupling it to VSUMN, then through another capacitor (Cvsumn) to GND. Place
Cisen capacitors as close as possible to the controller and keep the following loops small:
1. Any ISEN pin to another ISEN pin
2. Any ISEN pin to GND
The red traces in the following drawing show the loops that need to minimized.
Phase1
L3
Risen
Ro
Ro
Ro
ISEN3
ISEN2
Cisen
Cisen
Cisen
V
o
Phase2
Risen
L2
L1
Phase3
Risen
ISEN1
GND
Vsumn
Cvsumn
14
RTN
Place the RTN filter in close proximity of the controller for good decoupling.
FN8318.0
February 4, 2013
41
ISL95820
Layout Guidelines(Continued)
ISL95820
PIN NUMBER
SYMBOL
ISUMN
ISUMP
LAYOUT GUIDELINES
Place the current sensing circuit in general proximity of the controller.
15
16
Place capacitor C very close to the controller.
n
Place the inductor temperature sensing NTC thermistor next to phase-1 inductor (L1) so it senses the inductor
temperature correctly.
Each phase of the power stage sends a pair of VSUMP and VSUMN signals to the controller. Run these two signals traces
in parallel fashion with decent width (>20mil).
IMPORTANT: Sense the inductor current by routing the sensing circuit to the inductor pads. Route the ISUMPn and ISENn
resistor traces to the phase-side pad of each inductor. The ISUMNn network Ro resistor traces should be routed to the
VOUT-side pad of each inductor. If possible, route the traces on a different layer from the inductor pad layer and use vias
to connect the traces to the center of the pads. If no via is allowed on the pad, consider routing the traces into the pads
from the inside of the inductor. The following drawings show the two preferred ways of routing current sensing traces.
INDUCTOR
INDUCTOR
VIAS
CURRENT-SENSING TRACES
CURRENT-SENSING TRACES
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
VDD
A capacitor decouples it to GND. Place it in close proximity of the controller.
Place the Phase1 bootstrap capacitor between BOOT1 and PHASE1, near the controller.
No special consideration.
BOOT1
PHASE1
UGATE1
LGATE1
BOOT2
PHASE2
UGATE2
VCCP
No special consideration.
No special consideration.
Place the Phase2 bootstrap capacitor between BOOT2 and PHASE2, near the controller.
No special consideration.
No special consideration.
A capacitor decouples it to GND. Place it in close proximity of the controller.
No special consideration.
LGATE2
LGATE3
PHASE3
UGATE3
BOOT3
PWM4
VIN
No special consideration.
No special consideration.
No special consideration.
Place the Phase3 bootstrap capacitor between BOOT3 and PHASE3, near the controller.
No special consideration.
A capacitor decouples it to GND. Place it in close proximity of the controller.
No special consideration.
PROG3
PROG2
PROG1
No special consideration.
No special consideration.
36, 37, 38, 39,
40
I2DATA,
I2CLK, SDA,
ALERT#,
SCLK
Follow Intel recommendation.
FN8318.0
February 4, 2013
42
ISL95820
Typical Performance
FIGURE 44. SHUT DOWN, V = 12V, I = 5A, VID = 1.7V,
IN
FIGURE 43. SOFT-START, V = 12V, I = 5A, VID = 1.7V,
O
IN
O
Ch1: PHASE1, Ch2: VR_ON, Ch3: PGOOD, Ch4: V
Ch1: PHASE1, Ch2: VR_ON, Ch3: PGOOD, Ch4: V
OUT
OUT
FIGURE 45. STEADY STATE, PS0, V = 12V, I = 5A, VID = 1.8V
IN
FIGURE 46. STEADY STATE, PS1, V = 12V, I = 5A, VID = 1.8V
IN
O
O
Ch1: PHASE1, Ch2: PHASE2, Ch3: PHASE3,
Ch1: PHASE1, Ch2: PHASE2, Ch3: PHASE3,
Ch4: V , PHASE4 NOT SHOWN
Ch4: V , PHASE4 NOT SHOWN
OUT
OUT
FIGURE 47. STEADY STATE, PS2, V = 12V, I = 5A, VID = 1.8V Ch1: PHASE1, Ch2: PHASE2, Ch3: PHASE3, Ch4: V
IN
, PHASE4 NOT SHOWN
OUT
O
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ISL95820
Typical Performance(Continued)
FIGURE 48. VR1 LOAD RELEASE RESPONSE, V = 12V,
IN
FIGURE 49. VR1 LOAD INSERTION RESPONSE, V = 12V,
IN
VID = 1.8V, I = 61A/1A, SLEW TIME = 50ns,
VID = 1.8V, I = 1A/61A, SLEW TIME = 50ns,
O
O
LL = 1.5mΩ, Ch1: PHASE1, Ch2: PHASE2
LL = 1.5mΩ, Ch1: PHASE1, Ch2: PHASE2
,
,
Ch3: PHASE3, Ch4: V
, PHASE4 NOT SHOWN
Ch3: PHASE3, Ch4: V
, PHASE4 NOT SHOWN
OUT
OUT
FIGURE 50. SETVID-FAST RESPONSE, I = 5A, VID = 1.6V - 1.8V,
FIGURE 51. SETVID-FAST RESPONSE, I = 5A, VID = 1.8V - 1.6V,
O
O
Ch1: PHASE1, Ch3: ALERT#, Ch4: V
Ch1: PHASE1, Ch3: ALERT#, Ch4: V
OUT
OUT
FIGURE 52. SETVID-SLOW RESPONSE, I = 5A, VID = 1.6V - 1.8V,
O
FIGURE 53. SETVID-SLOW RESPONSE, I = 5A, VID = 1.8V - 1.6V,
O
Ch1: PHASE1, Ch3: ALERT#, Ch4: V
Ch1: PHASE1, Ch3: ALERT#, Ch4: V
OUT
OUT
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Typical Performance(Continued)
FIGURE 54. SETVID DECAY RESPONSE, I = 5A, VID = 1.8V - 1.6V,
O
FIGURE 55. SETVID SLOW RESPONSE FOLLOWING SETVID DECAY,
= 5A, VID = 1.6V - 1.8V, Ch1: PHASE1,
Ch1: PHASE1, Ch3: ALERT#, Ch4: V
I
OUT
O
Ch3: ALERT#, Ch4: V
OUT
FIGURE 56. SETVID FAST RESPONSE FOLLOWING SETVID DECAY, I = 5A, VID = 1.6V - 1.8V, Ch1: PHASE1, Ch3: ALERT#, Ch4: V
O
OUT
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Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web for the latest Rev.
DATE
REVISION
FN8318.0
CHANGE
February 4, 2013
Initial Release.
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the fastest growing markets within the industrial and infrastructure,
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
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FN8318.0
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ISL95820
Package Outline Drawing
L40.5x5
40 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 9/10
4X 3.60
36X 0.40
A
B
5.00
6
6
PIN #1 INDEX AREA
PIN 1
INDEX AREA
0.15
(4X)
40X 0.4± 0 .1
0.20
b
BOTTOM VIEW
TOP VIEW
0.10 M
C A B
4
PACKAGE OUTLINE
0.40
0.750
SEE DETAIL “X”
0.10 C
//
BASE PLANE
SEATING PLANE
0.08 C
C
0.050
SIDE VIEW
(36X 0.40
(40X 0.20)
0.2 REF
5
C
(40X 0.60)
0.00 MIN
0.05 MAX
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.27mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
JEDEC reference drawing: MO-220WHHE-1
7.
FN8318.0
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