ISL97632_08 [INTERSIL]
White LED Driver with Digital Dimming; 白光LED驱动器，数字调光
| 型号： | ISL97632_08 |
| 厂家： | 
Intersil |
| 描述： | White LED Driver with Digital Dimming |
| 文件： | 总9页 (文件大小：176K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL97632
®
Data Sheet
February 22, 2008
FN9239.3
White LED Driver with Digital Dimming
Features
The ISL97632 represents an efficient and highly integrated
PWM boost LED driver that is suitable for 1.8” to 3.5” LCDs
that employ 2 to 6 white LEDs for backlighting. With
integrated Schottky diode, OVP, and dynamic digital
dimming capability, the ISL97632 provides a simple, reliable,
and flexible solution to the backlight designers.
• 5-Bit Digital Dimming Control
• Drives up to 6 LEDs in Series
• OVP (14V, 18V and 26V for 3, 4, and 6 LEDs applications)
• Integrated Schottky Diode
• 2.4V to 5.5V input
The ISL97632 features a simple single-wire digital interface
that provides a 5-bit dimming control. The dimming signal
adjusts the FB voltage and therefore the LED brightness in a
DC manner in 32 linear steps. An EN pin can be used to
provide a zero brightness setting or shutdown power saving
function.
• 86% Efficiency
• 1.4MHz Switching Frequency Allows Small LC
• Enable for Shutdown Function or Zero Brightness Setting
• 1µA Shutdown Current
• Internally Compensated
The ISL97632 is available in the 8 Ld TDFN (2mmx3mm)
package. There are 14V, 18V, and 26V OVP options that are
suitable for 3, 4, and 6 LEDs backlight applications
respectively. The ISL97632 is specified for operation over
the -40°C to +85°C ambient temperature at input voltage
from 2.4V to 5.5V.
• 8 Ld TDFN (2mmx3mm)
• Pb-Free (RoHS Compliant)
Applications
• LED backlighting for
- Cell phones
Pinout
ISL97632
(8 LD 2x3 TDFN)
TOP VIEW
- Smartphones
- MP3
- PMP
- Automotive Navigation Panel
- Portable GPS
GND
LX
1
2
3
4
8
7
6
5
VIN
EN
VOUT
FBSW
FB
Ordering Information
PACKAGE
SDIN
PART NUMBER
(Note)
PART
MARKING
TAPE AND REEL
(Pb-Free)
PKG.
DWG.#
ISL97632IRT14Z-T* ELB
ISL97632IRT14Z-TK* ELB
ISL97632IRT18Z-T* ELC
ISL97632IRT18Z-TK* ELC
ISL97632IRT26Z-T* ELD
ISL97632IRT26Z-TK* ELD
8 Ld 2x3 TDFN
8 Ld 2x3 TDFN
8 Ld 2x3 TDFN
8 Ld 2x3 TDFN
8 Ld 2x3 TDFN
8 Ld 2x3 TDFN
L8.2x3A
L8.2x3A
L8.2x3A
L8.2x3A
L8.2x3A
L8.2x3A
Typical Application Circuit
10µH or 22µH
VIN
LX
VIN
EN
VOUT
SDIN
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach
materials and 100% matte tin plate PLUS ANNEAL - e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
FBSW
FB
GND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006-2008. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ISL97632
Absolute Maximum Ratings (T = +25°C)
Thermal Information
A
Input Voltage (V
)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
Thermal Resistance (Typical, Note 1)
TDFN Package (Notes 1, 2). . . . . . . . .
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300°C
θ
(°C/W)
70
θ
(°C/W)
IN
JA
JC
10.5
LX Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 28V
FBSW Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 28V
All Other Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed over temperature of -40°C to +85°C unless otherwise stated. Typical values are for
information purposes only at TJ = TC = TA = +25°C.
NOTE:
1. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
2. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications
V
= V
= 3V
EN
IN
DESCRIPTION
Supply Voltage
PARAMETER
CONDITION
MIN
TYP
MAX
5.5
UNIT
V
V
2.4
IN
I
Supply Current
EN = 3V, enabled, not switching
EN = 0V, disabled
0.8
1.5
mA
μA
IN
1
Fsw
Switching Frequency
Maximum Duty Cycle
LX Current
1,300
90
1,450
95
1,600
kHz
%
DMAX
I
400
470
900
mA
mΩ
μA
LIM
R
LX Switch ON-Resistance
LX Switch Leakage Current
Feedback Voltage
ILX = 100mA
SW(LX)
ILEAK
VFB
VLX = 28V
1
Serial interface setting = 15 (center)
Serial interface setting = S (S = 0,1..31)
90
95
9.8 + 5.68 x S
9.8
100
mV
mV
mV
Serial interface setting = 0
VFB = 95mV
IFB
FB Pin Bias Current
1
μA
Ω
R
FBSW Switch ON-Resistance
10
SW(FBSW)
V
Schottky Diode Forward
Voltage
IDIODE = 100mA, T = +25°C
A
600
850
mV
DIODE
OVP
Overvoltage Protection
ISL97632IRT14Z
ISL97632IRT18Z
ISL97632IRT26Z
14
18
26
V
V
28
V
VIL
Logic Low Voltage
0.6
V
VIH
Logic High Voltage
1.5
15
90
215
3
V
t
t
1
0
Timing Range for Logic 1
Timing Range for Logic 0
Timing Range for Load
SDIN = low
SDIN = low
SDIN = low
SDIN = high
45
μs
μs
μs
μs
LOGIC
LOGIC
120
t
LOGIC-LOAD
t
Minimum Valid SDIN High
Time
LOGIC-HIGH
FN9239.3
February 22, 2008
2
ISL97632
Block Diagram
VIN (2.4V to 5.5V)
CIN
L
VIN
EN
LX
1.4MHZ OSCILLATOR AND RAMP
GENERATOR
ISL97632
V
OUT
C
OUT
PWM
PWM LOGIC
FET
COMPARATOR
CONTROLLER
DRIVER
2 to 6 LEDs
CURRENT
SENSE
GND
FBSW
EN
GM
FB
AMPLIFIER
10 - 186mV
GM AMP
COMPENSATION
RSET
BANDGAP
REFERENCE
GENERATOR
SERIAL
INTERFACE
SDIN
Pin Descriptions
PIN
PIN
NUMBER
NAME
DESCRIPTION
1
2
GND
VIN
Ground Pin. Connect to local ground.
Input Supply Pin. Connect to the input supply voltage, the inductor and the input supply decoupling
capacitor.
3
4
5
6
7
8
EN
SDIN
FB
Enable Pin. Connect to enable signal to turn-on or off the device. Active High.
Single-Wire XSD Digital Interface.
Feedback Pin. Connect to the cathode of bottom LED and the sense resistor.
Optional FB Disconnect Switch.
FBSW
VOUT
LX
Output Pin. Connect to the anode of the top LED and the output filter capacitor.
Switching Pin. Connect to inductor.
FN9239.3
February 22, 2008
3
ISL97632
Single-Wire Serial Interface
30µs
100µs
220µs
'1'
'0'
'1'
'0'
'0'
'LOAD'
0
200
400
600
800
1000
1200
µs
FIGURE 1. SINGLE-WIRE XSD INTERFACE
The ISL97632 uses a simple single-wire serial interface for
programming the output brightness of the LEDs. A 5-bit
interface is used to give a total of 32 levels of output
brightness. The interface uses a normally high connection
for use with open-drain driving schemes and Intersil’s
proprietary XSD bus. When held low for between 15µs and
45µs, the interface registers a logic 1. When held low for
between 90µs and 120µs the interface registers a logic 0.
When held low for greater that 215µs, the interface loads the
last 5 bits into the brightness control register and updates
the brightness level. The required minimum high time is 3µs.
This simple single-wire programming is summarized as
follow:
• Logic 0 = Negative pulse >90µs and <120µs
• Logic 1 = Negative pulse >15µs and <45µs
• Load = Negative pulse >215µs
Figure 1 shows an example of programming a binary code of
10100 and load it in to the device serial register.
The serial interface is automatically reset to 0 when the
device is disabled, or enters UVLO. Therefore, when the part
is enabled, the output brightness is automatically set to the
minimum level.
FN9239.3
February 22, 2008
4
ISL97632
Typical Performace Curves
90
1.0
0.8
0.6
0.4
0.2
0
4.2V IN 4 LEDs OUT (15µH)
85
80
3.6V IN 4 LEDs OUT (10µH)
75
70
65
60
55
50
3.6V IN 4 LEDs OUT (15µH)
4.2V IN 4 LEDs OUT (10µH)
4.2V IN 4 LEDs OUT (22µH)
3.6V IN 4 LEDs OUT (22µH)
- 0.2
0
5
10
15
20
25
30
35
40
45
0
1
2
3
4
5
I
(mA)
OUT
V
(V)
IN
FIGURE 2. EFFICIENCY vs LED CURRENT
FIGURE 3. QUIESCENT CURRENT vs V (ENAB = HI)
IN
20.08
20.04
20.00
19.96
19.92
19.76
19.74
19.72
19.70
19.68
19.66
19.64
19.62
0
5
10
15
(V)
20
25
30
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
V
OUT
V
IN
FIGURE 4. LOAD REGULATION (V = 4V)
IN
FIGURE 5. LINE REGULATION
40
R
= 4.7Ω
35
30
25
20
15
10
5
SET
0
0
5
10
15
20
25
30
35
CODE = DECIMAL
FIGURE 6. ILED vs PROGRAMMING CODES
FN9239.3
February 22, 2008
5
ISL97632
resume previous setting, the device needs to be
reprogrammed.
Detailed Description
The ISL97632 uses a constant frequency, current mode
control scheme to provide excellent line and load regulation.
There are three OVP models for driving 3, 4, and 6 LEDs and
their OVP thresholds are set at 14V, 18V, and 26V
respectively. The ISL97632 operates from an input voltage of
2.4V to 5.5V and ambient temperature from -40°C to +85°C.
The switching frequency is around 1.45MHz and allows the
driver circuit to employ small LC components. The forward
Output Disconnect
The ISL97632 features a FBSW feedback disconnect switch
that can be used in between the LED and Rset for an
optional short-circuit protection. For example, the user may
build an external short circuit detection to monitor the V
.
OUT
goes low due to one or more LEDs which are
If the V
OUT
shorted, the circuit can release the EN and FBSW switch to
disconnect the LEDs.
current of the LED is set using the R resistor. In the steady
state mode, the LED current is given by Equation 1:
SET
Components Selection
V
(S)
9.8mV + 5.68mV × S
FB
The input capacitance is typically 0.22µF to 4.7µF. The
output capacitor should be in the range of 0.22µF to 1µF.
X5R or X7R type of ceramic capacitors of the appropriate
voltage rating are recommended.
--------------------
-------------------------------------------------------
I
(S) =
=
LED
(EQ. 1)
R
R
SET
SET
where S is the 5-bit Serial Interface Setting or Digital code
from 0 to 31 programmed in the XSD single-wire interface.
The default setting is 0 and the VFB is at minimum.
When choosing an inductor, make sure the average and
peak current ratings are adequate by using the following
equations (80% efficiency assumed):
Dimming Control
The ISL97632 powers up to provide minimium current. By
programming the digital code with the Intersil’s XSD single-
wire interface as shown in Figure 1, the current can be
changed linearly with the digital code from 0 to 31. Figure 6
shows LED current versus the programming codes.
I
⋅ V
OUT
LED
--------------------------------
=
I
(EQ. 2)
(EQ. 3)
(EQ. 4)
LAVG
0.8 ⋅ V
IN
1
2
--
I
= I
+
⋅ ΔI
L
LPK
LAVG
Overvoltage Protection
V
⋅ (V
– V
)
IN
IN
OUT
The ISL97632 comes with overvoltage protection. The
OVP trip points are at 14V, 18V, and 26V for
--------------------------------------------------
ΔI
=
L
L ⋅ V
⋅ f
OUT OSC
Where:
ISL97632IRT14Z, ISL97632IRT18Z, and
ISL97632IRT26Z respectively. The maximum numbers of
LEDs and OVP threshold are shown in Table 1. When the
device reaches the OVP, the LX stops switching, disabling
• ΔI is the peak-to-peak inductor current ripple in Amps
L
• L is the inductance in H.
the boost circuit until V
threshold. At this point, LX will be allowed to switch again.
The OVP event will not cause the device to shutdown
falls about 7% below the OVP
OUT
• f
is the switching frequency, typically 1.45MHz
OSC
The ISL97632 supports a wide range of inductance values
(10µH~82µH). For lower inductor values or lighter loads, the
boost inductor current may become discontinuous. For high
boost inductor values, the boost inductor current will be in
continuous mode.
TABLE 1.
MAX NO. OF
PART NO.
OVP
14V
18V
26V
LEDS
MAX ILED
70mA
ISL97632IRT14Z
ISL97632IRT18Z
ISL97632IRT26Z
3
4
6
In addition to the inductor value and switching frequency, the
input voltage, the number of LEDs and the LED current also
affect whether the converter operates in continuous
50mA
30mA
conduction or discontinuous conduction mode. Both operating
modes are allowed and normal. The discontinuos conduction
mode yields lower efficiency due to higher peak current.
There are three OVP options so that the 3 LEDs
application should use the 14V OVP device and the 6 LEDs
application should use the 26V OVP device. An output
capacitor that is only rated for the required voltage range can
therefore be used which will optimize the component costs in
some cases.
Compensation
The product of the output capacitor and the load create a
pole while the inductor creates a right half plane zero. Both
attributes degrade the phase margin but the ISL97632 has
an internal compensation network that ensures the device
operates reliabily under the specified conditions. The
internal compensation and the highly integrated functions of
the ISL97632 make it a design friendly device to be used in
high volume high reliability applications.
Shut-Down
An active high EN pin is normally on but this pin can be used
as a shutdown power saving function or zero brightness
setting. When taken low the EN pin places the ISL97632 into
power down mode down where the supply current is
reduced to less than 1µA. The EN pin cannot be used as
PWM input as the part resets to 0 whenever EN is low. To
FN9239.3
February 22, 2008
6
ISL97632
MOSFET connected in cascode fashion to achieve higher
output voltage. A conceptual 8 LEDs driver circuit is shown
in Figure 9. A 60V logic level N-Channel MOSFET is
Applications
Efficiency Improvement
Figure 2 shows the efficiency measurements. The choice of
the inductor has a significant impact on the power efficiency.
As shown in Equation 4, the higher the inductance, the lower
the peak current therefore the lower the conduction and
switching losses. On the other hand, it has also a higher
series resistance. Nevertheless, the efficiency improvement
from lowering the peak current is greater than the impact of
the resistance increase with larger value of inductor.
Efficiency can also be improved for systems that have high
supply voltages. Since the ISL97632 can only supply from
2.4V to 5.5V, VIN must be seperated from the high supply
voltage for the boost circuit as shown in Figure 7 and the
efficiency improvement is shown in Figure 8.
configured such that its drain ties between the inductor and
the anode of schottky diode, its gate ties to the input, and its
source ties to the ISL97632 LX node connecting to the drain
of the internal switch. When the internal switch turns on, it
pulls the source of M1 down to ground, and LX conducts as
normal. When the internal switch turns off, the source of M1
will be pulled up by the follower action of M1, limiting the
maximum voltage on the ISL97632 LX pin to below Vin, but
allowing the output voltage to go much higher than the
breakdown limit on the LX pin. The switch current limit and
maximum duty cycle will not be changed by this setup, so
input voltage will need to be carefully considered to make
sure that the required output voltage and current levels are
achievable. Because the source of M1 is effectively floating
when the internal LX switch is off, the drain-to-source
capacitance of M1 may be sufficient to capacitively pull the
node high enough to breaks down the gate oxide of M1. To
prevent this, VOUT should be connected to VIN, allowing the
internal schottky to limit the peak voltage. This will also hold
the VOUT pin at a known low voltage, preventing the built in
OVP function from causing problems. This OVP function is
effectively useless in this mode as the real output voltage is
outside its intended range. If the user wants to implement
their own OVP protection (to prevent damage to the output
capacitor, they should insert a zener from vout to the FB pin.
In this setup, it would be wise not to use the FBSW to FB
switch as otherwise the zener will have to be a high power
one capable of dissipating the entire LED load power. Then
the LED stack can then be connected directly to the sense
resistor and via a 10k resistor to FB. A zener can be placed
from Vout to the FB pin allowing an over voltage event to pull
up on FB with a low breakdown current (and thus low power
zener) as a result of the 10k resistor.
C3
0.22µ
D1
D2
D3
D4
D5
D6
L1
Vs = 12V
C1
1
2
22µ
1µ
V
= 2.7V TO 5.5V
25mA
IN
VIN
LX
VOUT
ISL97632
FBSW
0.1µ
C2
EN
FB
SDIN
GND
R1
4Ω
FIGURE 7. SEPERATE HIGH INPUT VOLTAGE FOR HIGHER
EFFICIENCY OPERATION
90
L1
D0
V
= 2.7V TO 5.5V
V
= 12V
IN
S
1
2
C3
C1
1µ
2.2µ
10BQ100
FQT13N06L
D1
D2
D3
D4
D5
D6
D7
D8
4.7µ
M1
85
80
V
= 9V
S
SK011C226KAR
VIN
VOUT
LX
ISL97632
C2
0.1µ
FBSW
EN
V
= 4V
75
70
IN
FB
6 LEDs
L1 = 22µH
R1 = 4Ω
SDIN
GND
6.3Ω
R1
5
10
15
ILED (mA)
20
25
30
0
FIGURE 8. EFFICIENCY IMPROVEMENT WITH 9V AND 12V
INPUTS
8 LEDs Operation
FIGURE 9. CONCEPTUAL 8 LEDS HIGH VOLTAGE DRIVER
For medium size LCDs that need more than 6 low power
LEDs for backlighting, such as a Portable Media Player or
Automotive Navigation Panel displays, the voltage range of
the ISL97632 is not sufficient. However, the ISL97632 can
be used as an LED controller with an external protection
SEPIC Operation
For applications where the output voltage is not always
above the input voltage, a buck or boost regulation is
needed. A SEPIC (Single Ended Primary Inductance
FN9239.3
February 22, 2008
7
ISL97632
Converter) topology, (shown in Figure ), can be considered
boost regulator operation, except the lowest reference point
for such an application. A single cell Li-Ion battery
operating a cellphone backlight or flashlight is one
example. The battery voltage is between 2.5V and 4.2V
depending on the state of charge. On the other hand, the
output may require only one 3V to 4V medium power LED
for illumination because the light guard of the backlight
assembly is optimized or it is a cost efficiency trade off
reason.
is at -V . The output is approximated as:
IN
D
-----------------
V
= V
IN
(EQ. 5)
OUT
(1 – D)
where D is the on-time of the PWM duty cycle.
The convenience of SEPIC comes with some trade off in
addition to the additional L and C costs. The efficiency is
usually lowered because of the relatively large efficiency
loss through the Schottky diode if the output voltage is low.
The L2 series resistance also contributes additional loss.
Figure 11 shows the efficiency measurement of a single LED
application as the input varies between 2.7V and 4.2V.
In fact, a SEPIC configured LED driver is flexible enough to
allow the output to be well above or below the input voltage,
unlike the previous example. Another example is when the
number of LEDs and input requirements are different from
platform to platform, a common circuit and PCB that fit all the
platforms, in some cases, may be beneficial enough that it
outweights the disadvantage of adding additional component
cost. L1 and L2 can be a coupled inductor in one package.
Note, V is considered the level-shifted LX node of a
B
standard boost regulator. The higher the input voltage, the
lower the V voltage will be during PWM on period. The
B
C3
L1
V
V
B
VIN = 2.7V to 5.5V
A
1
2
result is that the efficiency will be lower at higher input
voltages because the SEPIC has to work harder to boost up
to the required level. This behavior is the opposite to the
standard boost regulator’s and the comparison is shown in
Figure 11.
22µ
1µ
C1
1µ
C4 0.22µ
L2
22µ
D1
LX
VOUT
VIN
EN
C2
0.1µ
76
FBSW
FB
V
= 2.7V
IN
SDIN
GND
72
1Ω
R1
V
= 4.2V
IN
68
64
FIGURE 10. SEPIC LED DRIVER
1 LED
L1 = L2 = 22µH
C3 = 1µF
The simplest way to understand SEPIC topology is to think
about it as a boost regulator in which the input voltge is level
shifted downward at the same magnitude and the lowest
R1 = 4.7Ω
60
0
5
10
ILED (mA)
15
20
reference level starts at -V rather than 0V.
IN
FIGURE 11. EFFICIENCY MEASUREMENT OF A SINGLE LED
SEPIC DRIVER
The SEPIC works as follows; assume the circuit in Figure 10
operates normally when the ISL97632 internal switch opens
and it is in the PWM off state after a short duration where few
LC time constants elapsed, the circuit is considered in the
steady-state within the PWM off period that L1 and L2 are
PCB Layout Considerations
The layout is very important for the converter to function
shorted. V is therefore shorted to the ground and C3 is
B
properly. R
must be located as close as possible to the FB
SET
charged to V with V = V . When the ISL97632 internal
IN IN
A
and GND pins. Longer traces to the LEDs are acceptable.
Similarly, the supply decoupling cap and the output filter cap
should be as close as possible to the VIN and VOUT pins.
switch closes and the circuit is in the PWM on state, V is
A
now pulled to ground. Since the voltage in C3 cannot be
changed instantenously, V is shifted downward and
B
becomes -V . The next cycle when the ISL97632 switch
IN
The heat of the IC is mainly dissipated through the thermal
pad of the package. Maximize the copper area connected to
this pad if possible. In addition, a solid ground plane is always
helpful for the EMI performance.
opens, V boosts up to the targetted output like the standard
B
FN9239.3
February 22, 2008
8
ISL97632
Thin Dual Flat No-Lead Plastic Package (TDFN)
2X
L8.2x3A
0.15
C A
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
A
D
2X
MILLIMETERS
0.15
C B
SYMBOL
MIN
0.70
NOMINAL
MAX
0.80
NOTES
A
A1
A3
b
0.75
-
-
0.20
1.50
1.65
-
0.20 REF
0.25
0.05
-
E
-
6
INDEX
AREA
0.32
1.75
1.90
5,8
D
2.00 BSC
1.65
-
B
A
D2
E
7,8
TOP VIEW
3.00 BSC
1.80
-
// 0.10
0.08
C
E2
e
7,8
0.50 BSC
-
-
C
k
0.20
0.30
-
-
SIDE VIEW
A3
C
SEATING
PLANE
L
0.40
0.50
8
N
8
2
D2
D2/2
2
7
8
Nd
4
3
(DATUM B)
Rev. 0 6/04
NOTES:
1
NX k
6
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
INDEX
AREA
3. Nd refers to the number of terminals on D.
(DATUM A)
E2
4. All dimensions are in millimeters. Angles are in degrees.
E2/2
5. Dimension b applies to the metallized terminal and is measured
between 0.25mm and 0.30mm from the terminal tip.
NX L
8
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
N
N-1
e
NX b
5
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
0.10
M
C A B
(Nd-1)Xe
REF.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
BOTTOM VIEW
C
L
(A1)
NX (b)
5
L
SECTION "C-C"
C C
TERMINAL TIP
e
FOR EVEN TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9239.3
February 22, 2008
9
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