ISL97645IRZ-TK [INTERSIL]
Boost + VON Slice + VCOM; 提升+ VON片+ VCOM
| 型号： | ISL97645IRZ-TK |
| 厂家： | 
Intersil |
| 描述： | Boost + VON Slice + VCOM |
| 文件： | 总14页 (文件大小：531K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL97645
®
Data Sheet
April 11, 2006
FN9263.0
Boost + V Slice + V
The ISL97645 represents an integrated DC/DC regulator for
monitor and notebook applications with screen sizes up to
20”. The device integrates a boost converter for generating
Features
• 2.7V to 5.5V Input
ON
COM
• 2.6A Integrated Boost for Up to 20V AVDD
• Integrated VON Slice
A
VDD, a VON slice circuit, and a high performance VCOM
amplifier.
• 600kHz/1.2MHz fS
The boost converter features a 2.6A FET and has user
programmable soft-start and compensation. With efficiencies
up to 92%, the AVDD is user selectable from 7V to 20V.
• VCOM Amplifier
- 30MHz BW
- 50V/µs SR
The VON slice circuit can control gate voltages up to 30V.
High and low levels are programmable, as well as discharge
rate and timing.
- 400mA Peak Output Current
• UV and OT Protection
• 24 Ld 4x4 QFN
The integrated VCOM features high speed and drive
capability. With 30MHz bandwidth and 50V/µs slew rate, the
• Pb-Free Plus Anneal Available (RoHS Compliant)
V
COM amplifier is capable of driving 400mA peaks, and
Applications
100mA continuous output current.
• LCD Monitors (15”+)
Pinout
• Notebook Display (up to 16”)
ISL97645
(24 LD 4x4 QFN)
TOP VIEW
Ordering Information
TEMP.
PART NUMBER
(Note)
PART
RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
MARKING
DWG. #
ISL97645IRZ
97645IRZ -40 to 85 24 Ld 4x4 QFN
L24.4x4D
L24.4x4D
24 23 22 21 20 19
ISL97645IRZ-T 97645IRZ -40 to 85 24 Ld 4x4 QFN
6k pc Tape & Reel
GND
1
LX
18
17
16
15
14
13
VGH_M
2
VIN
ISL97645IRZ-TK 97645IRZ -40 to 85 24 Ld 4x4 QFN
1k pc Tape & Reel
L24.4x4D
VFLK
3
FREQ
COMP
SS
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
VDPM
4
VDD_1
VDD_2
5
6
NC
7
8
9
10 11 12
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ISL97645
Pin Descriptions
PIN NUMBER
PIN NAME
GND
FUNCTION
1
2
Ground
VGH_M
VFLK
VDPM
VDD_1
VDD_2
OUT
Gate Pulse Modulation Output
Gate Pulse Modulation Control Input
Gate Pulse Modulation Enable
3
4
5
Gate Pulse Modulation Lower Voltage Input
6
V
V
V
COM Amplifier Supply
7
COM Amplifier Output
8
NEG
COM Amplifier Inverting Input
9
POS
VCOM Amplifier Noninverting Input
VCOM Amplifier Ground
10
11
12
13
14
AGND
NC
NC
NC
SS
Boost Converter Soft-start. Connect a capacitor between this pin and GND to set the soft-start
time.
15
COMP
Boost Converter Compensation Pin. Connect a series resistor and capacitor between this pin and
GND to optimize transient response.
16
17
18
19
20
21
22
FREQ
VIN
Boost Converter Frequency Select.
Boost Converter Power Supply
LX
Boost Converter Switching Node
ENABLE
FB
Chip Enable Pin. Connect to Vin for normal operation, GND for shutdown.
Boost Converter Feedback
PGND
CE
Boost Converter Power Ground
Gate Pulse Modulator Delay Control. Connect a capacitor between this pin and GND to set the
delay time.
23
24
RE
Gate Pulse Modulator Slew Control. Connect a resistor between this pin and GND to set the falling
slew rate.
VGH
Gate Pulse Modulator High Voltage Input
FN9263.0
2
April 11, 2006
ISL97645
Absolute Maximum Ratings
Thermal Information
Thermal Resistance
4x4 QFN Package (Notes 1, 2) . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Maximum Continuous Junction Temperature . . . . . . . . . . . . 125°C
Power Dissipation
Lx to GND, AGND and PGND . . . . . . . . . . . . . . . . . . . . -0.5 to +25V
θJA (°C/W) θJC (°C/W)
39 2.5
VDD2, OUT, NEG and POS
to GND, AGND and PGND. . . . . . . . . . . . . . . . . . . . . -0.5 to +25V
VDD1, VGH and VGH_M
to GND, AGND and PGND. . . . . . . . . . . . . . . . . . . . . -0.5 to +32V
Differential Voltage Between POS and NEG . . . . . . . . . . . . . . . ±6V
Voltage Between GND, AGND and PGND . . . . . . . . . . . . . . . ±0.5V
All Other Pins to GND, AGND and PGND . . . . . . . . . . -0.5 to +6.5V
Input, Output, or I/O Voltage . . . . . . . . . . .GND -0.3V to VIN + 0.3V
T
A ≤ 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.44W
TA = 70°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.34W
TA = 85°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.98W
TA = 100°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.61W
Recommended Operating Conditions
Input Voltage Range, VS . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Boost Output Voltage Range, AVDD . . . . . . . . . . . . . . . . . 8V to 20V
Input Capacitance, CIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22µF
Boost Inductor, L1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3µH to 10µH
Output Capacitance, COUT. . . . . . . . . . . . . . . . . . . . . . . . . .2x22µF
Operating Ambient Temperature Range . . . . . . . . . .-40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications VIN = ENABLE = 5V, VDD1 = VDD2 = 14V, VGH = 25V, AVDD = 10V, TA = -40°C to 85°C
Unless Otherwise Noted.
SYMBOL
GENERAL
VS
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
VINInput Voltage Range
2.7
3.3
0.2
5.5
2
V
µA
mA
V
IS_DIS
VIN Supply Currents when Disabled ENABLE = 0V
IS
VIN Supply Currents
ENABLE = 5V, LX not switching
1
UVLO
Undervoltage Lockout Threshold
VIN2 Rising
2.3
2.2
2.45
2.35
140
100
2.6
2.5
VIN2 Falling
V
OTR
OTF
Thermal Shutdown Temperature
Temperature Rising
Temperature Falling
°C
°C
LOGIC INPUT CHARACTERISTICS - ENABLE, VFLK, FREQ, VDPM
VIL
VIH
RIL
Low Voltage Threshold
High Voltage Threshold
Pull-Down Resistor
0.8
400
20
V
V
2.2
Enabled, Input at Vin
150
250
kΩ
STEP-UP SWITCHING REGULATOR
AVDD
Output Voltage Range
Load Regulation
VIN*1.25
V
%
∆AVDD/∆IOUT
∆AVDD/∆VIN
ACCAVDD
50mA < ILOAD < 250mA
0.2
Line Regulation
ILOAD = 150mA, 3.0 < VIN < 5.5V
0.15
0.25
3
%/V
%
Overall Accuracy (Line, Load,
Temperature)
10mA < ILOAD < 300mA,
3.0 < Vin < 5.5V, 0°C < TA < 85°C
-3
VFB
Feedback Voltage (VFB
)
ILOAD = 100mA, TA = 25°C
1.20
1.19
1.21
1.21
1.22
1.23
V
V
ILOAD = 100mA, TA = -40°C to +85°C
FN9263.0
April 11, 2006
3
ISL97645
Electrical Specifications VIN = ENABLE = 5V, VDD1 = VDD2 = 14V, VGH = 25V, AVDD = 10V, TA = -40°C to 85°C
Unless Otherwise Noted. (Continued)
SYMBOL
PARAMETER
FB Input Bias Current
Switch On Resistance
Peak Efficiency
TEST CONDITION
MIN
TYP
250
150
92
MAX
500
UNIT
nA
IFB
RDS(ON)
EFF
300
mΩ
%
ILIM
Switch Current Limit
Max Duty Cycle
2.1
85
2.6
3.1
A
DMAX
FOSC
90
%
Oscillator Frequency
FREQ = 0V
550
1.0
650
1.2
800
1.4
kHz
MHz
µA
FREQ = VIN2
ISS
Soft-Start Slew Current
SS < 1V, TA = 25°C
2.75
VCOM AMPLIFIER RLOAD = 10k, CLOAD = 10pF, Unless Otherwise Stated
VSAMP
ISAMP
VOS
Supply Voltage
4.5
20
V
mA
mV
nA
V
Supply Current
3
3
0
Offset Voltage
20
100
IB
Noninverting Input Bias Current
CMIR
Common Mode Input Voltage
Range
0
VDD2
CMRR
PSRR
VOH
VOH
VOL
VOL
ISC
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Output Voltage Swing High
Output Voltage Swing High
Output Voltage Swing Low
Output Voltage Swing Low
Output Short Circuit Current
Slew Rate
50
70
70
85
dB
dB
Iout(source) = 5mA
Iout(source) = 50mA
Iout(sink) = 5mA
VDD2-50
VDD2-450
50
mV
mV
mV
mV
mA
V/µs
MHz
Iout(sink) = 50mA
450
250
400
SR
50
BW
Gain Bandwidth
-3dB gain point
30
GATE PULSE MODULATOR
VGH
IVGH
VGH Voltage
7
30
V
µA
µA
V
VGH Input Current
VFLK = 0
260
40
RE = 33kΩ, VFLK = VDD1
VDD1
VDD1 Voltage
3
VGH - 2
2
IVDD1
VDD1 Input Current
VGH to VGH_M On Resistance
-2
0.1
70
8
µA
Ω
RONVGH
IDIS_VGH
TDEL
VGH_M Discharge Current (Note 1) RE = 33kΩ
DELAY Time (Note 2) CE = 470pF, RE = 33kΩ
mA
µs
1.9
NOTES:
1. Nominal discharge current = 300/(RE+5kΩ).
2. Nominal delay time = 4000*CE.
FN9263.0
April 11, 2006
4
ISL97645
I
Typical Performance Curves
100
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
F
= 650kHz
OSC
90
80
70
60
50
40
30
20
10
0
F
= 1.2MHz
OSC
F
= 650kHz
= 1.2MHz
OSC
F
OSC
0
200
400
600
(mA)
800
1000
1200
0
200
400
600
IA (mA)
VDD
800
1000
1200
IA
VDD
FIGURE 1. AVDD EFFICIENCY vs IAVDD
FIGURE 2. AVDD LOAD REGULATION vs IAVDD
10.5
10.45
10.4
L = 10µH, C
= 40µF, C
= 2.2nF, R
= 10k
COMP
OUT
COMP
A
150mA
VDD
IA
VDD
A
500mA
VDD
10.35
10.3
10.25
10.2
A
(AC COUPLED)
VDD
10.15
3
3.5
4.0
4.5
(V)
5.0
5.5
6.0
V
IN
FIGURE 3. LINE REGULATION AVDD vs VIN
FIGURE 4. BOOST CONVERTER TRANSIENT RESPONSE
CE = 1pF, RE = 100k
CE = 1000pF, RE = 100k
VGH_M
VGH_M
VFLK
VFLK
FIGURE 5. GPM CIRCUIT WAVEFORM
FIGURE 6. GPM CIRCUIT WAVEFORM
FN9263.0
April 11, 2006
5
ISL97645
Typical Performance Curves (Continued)
CE = 10pF, RE = 100k
CE = 10pF, RE = 150k
VGH_M
VGH_M
VFLK
VFLK
FIGURE 7. GPM CIRCUIT WAVEFORM
FIGURE 8. GPM CIRCUIT WAVEFORM
INPUT
SIGNAL
INPUT SIGNAL
OUTPUT SIGNAL
OUTPUT
SIGNAL
(-3dB ATTENTUATION
FROM INPUT SIGNAL)
FIGURE 9. VCOM RISING SLEW RATE
FIGURE 10. VCOM BANDWIDTH MEASUREMENT
FN9263.0
April 11, 2006
6
ISL97645
Block Diagram
FREQ
LX
OSCILLATION
GENERATOR
SLOPE
COMPENSATION
COMP
SUMMING
AMPLIFIER
FB
-
PWM
LOGIC
+
2.5µA
-
+
PGND
SS
VIN
REFERENCE
GENERATOR
START-UP AND
FAULT CONTROL
VDPM
ENABLE
NC
NC
VDD2
POS
NEG
GND
+
-
OUT
GPM
VDD1
CIRCUIT
VFLK VGH VGH_M CE
RE
FIGURE 11. ISL97645 BLOCK DIAGRAM
FN9263.0
April 11, 2006
7
ISL97645
Typical Application Diagram
L1
D1
10µH
V
A
IN
VDD
LX
C2
47µF
C1
22µF
R1
10K
C3
2.2nF
COMP
BOOST
FB
C4
R2
1.3K
10nF
PGND
SS
S1
S2
S3
ENABLE
FREQ-
VDPM
V
VGH
ON
VDD_1
VFLK
C5
GPM
CIRCUIT
470P
VGH_M
VDD2
CE
TO ROW DRIVER
RE
R6
130k
0.47µF
R3
2K
POS
A
VDD
C11
1µF
NEG-
OUT
VIN
R7
80k
V
COM
+4.0V
NC
C6
0.1µF
AGND
GND
NC
FIGURE 12. TYPICAL APPLICATION DIAGRAM
switching frequency can save power dissipation, while
higher switching frequency can allow smaller external
components like inductor and output capacitors, etc.
Connecting FREQ pin to ground sets the PWM switching
frequency to 650MHz, or connecting FREQ pin to VIN for
1.2MHz.
Applications Information
The ISL97645 provides a complete power solution for TFT
LCD applications. The system consists of one boost
converter to generate AVDD voltage for column drivers, one
integrated VCOM buffer which can provide up to 400mA peak
current. This part also integrates Gate Pulse Modulator
circuit that can help to optimize the picture quality.
Soft-Start
The soft-start is provided by an internal 2.5µA current source
to charge the external soft start capacitor. The ISL97645
ramps up current limit from 0A up to full value, as the voltage
at SS pin ramps from 0 to 1.2V. Hence the soft-start time is
4.8ms when the soft-start capacitor is 10nF, 22.6ms for 47nF
and 48ms for 100nF.
Enable Control
When enable pin is pulling down, the ISL97645 is shut down
reducing the supply current to <10µA. When the voltage at
enable pin reaches 2.2V, the ISL97645 is on.
Boost Converter
Frequency Selection
The ISL97645 switching frequency can be user selected to
operate at either constant 650kHz or 1.2MHz. Lower
Operation
The boost converter is a current mode PWM converter
operating at either a 650kHz or 1.2MHz. It can operate in
both discontinuous conduction mode (DCM) at light load and
FN9263.0
8
April 11, 2006
ISL97645
continuous mode (CCM). In continuous current mode,
current flows continuously in the inductor during the entire
switching cycle in steady state operation. The voltage
conversion ratio in continuous current mode is given by:
This restricts the maximum output current (average) based
on the following equation:
V
V
∆I
2
IN
L
---------
I
=
I
– -------- ×
OMAX
LMT
O
V
1
Boost
------------------ = -------------
V
1 – D
Where ∆IL is peak to peak inductor ripple current, and is set
by:
IN
Where D is the duty cycle of the switching MOSFET.
V
L
D
IN
×
--------- ---
∆I
=
Figure 11 shows the block diagram of the boost regulator. It
uses a summing amplifier architecture consisting of gm
stages for voltage feedback, current feedback and slope
compensation. A comparator looks at the peak inductor
current cycle by cycle and terminates the PWM cycle if the
current limit is reached.
L
f
s
where fS is the switching frequency (650kHz or 1.2MHz).
The Table 2 gives typical values (margins are considered
10%, 3%, 20%, 10% and 15% on VIN, VO, L, fS and IOMAX).
Capacitor
An external resistor divider is required to divide the output
voltage down to the nominal reference voltage. Current
drawn by the resistor network should be limited to maintain
the overall converter efficiency. The maximum value of the
resistor network is limited by the feedback input bias current
and the potential for noise being coupled into the feedback
pin. A resistor network in the order of 60kΩ is recommended.
The boost converter output voltage is determined by the
following equation:
An input capacitor is used to suppress the voltage ripple
injected into the boost converter. The ceramic capacitor with
capacitance larger than 10µF is recommended. The voltage
rating of input capacitor should be larger than the maximum
input voltage. Some capacitors are recommended in Table 1
for input capacitor.
TABLE 1. BOOST CONVERTER INPUT CAPACITOR
RECOMMENDATION
R
+ R
2
1
CAPACITOR
10µF/16V
SIZE
1206
0805
1210
MFG
TDK
PART NUMBER
--------------------
V
=
× V
Boost
FB
R
2
C3216X7R1C106M
10µF/10V
22µF/10V
Murata GRM21BR61A106K
Murata GRB32ER61A226K
The current through the MOSFET is limited to 2.6APEAK
.
TABLE 2. MAXIMUM OUTPUT CURRENT CALCULATION
VIN (V)
VO (V)
9
L (µH)
10
Fs (MHz)
0.65
0.65
0.65
0.65
0.65
0.65
0.65
1.2
IOMAX (mA)
636
3
3
3
5
5
5
5
3
3
3
5
5
5
5
12
15
9
10
419
10
289
10
1060
699
12
15
18
9
10
10
482
10
338
10
742
12
15
9
10
1.2
525
10
1.2
395
10
1.2
1236
875
12
15
18
10
1.2
10
1.2
658
10
1.2
514
FN9263.0
April 11, 2006
9
ISL97645
For low ESR ceramic capacitors, the output ripple is
Inductor
dominated by the charging and discharging of the output
capacitor. The voltage rating of the output capacitor should
be greater than the maximum output voltage.
The boost inductor is a critical part which influences the
output voltage ripple, transient response, and efficiency.
Values of 3.3µH to 10µH are used to match the internal
slope compensation. The inductor must be able to handle
the following average and peak current:
Note: Capacitors have a voltage coefficient that makes their
effective capacitance drop as the voltage across then
increases. COUT in the equation above assumes the
effective value of the capacitor at a particular voltage and not
the manufacturer’s stated value, measured at zero volts.
I
O
I
= -------------
LAVG
LPK
1 – D
∆I
2
L
I
= I
+ --------
LAVG
The following table shows some selections of output
capacitors.
Some inductors are recommended in Table 3.
TABLE 5. BOOST OUTPUT CAPACITOR RECOMMENDATION
TABLE 3. BOOST INDUCTOR RECOMMENDATION
DIMENSIONS
CAPACITOR SIZE
MFG
TDK
Murata
PART NUMBER
C3225X7R1E106M
GRM32DR61E106K
INDUCTOR
6.8µH/3APEAK
10µH/4APEAK
(mm)
MFG
PART NUMBER
RLF7030T-6R8N3R0
CDR8D43-100NC
CD1-5R2
10µF/25V
10µF/25V
1210
1210
7.3x6.8x3.2 TDK
8.3x8.3x4.5 Sumida
5.2µH/4.55APEAK 10x10.1x3.8 Cooper
Bussmann
Compensation
The boost converter of ISL97645 can be compensated by a
RC network connected from CM1 pin to ground. 4.7nF and
10k RC network is used in the demo board. The larger value
resistor and lower value capacitor can lower the transient
overshoot, however, at the expense of stability of the loop.
Rectifier Diode
A high-speed diode is necessary due to the high switching
frequency. Schottky diodes are recommended because of
their fast recovery time and low forward voltage. The reverse
voltage rating of this diode should be higher than the
maximum output voltage. The rectifier diode must meet the
output current and peak inductor current requirements. The
following table is some recommendations for boost converter
diode.
Cascaded MOSFET Application
An 20V N-channel MOSFET is integrated in the boost
regulator. For the applications where the output voltage is
greater than 20V, an external cascaded MOSFET is needed
as shown in Figure 13. The voltage rating of the external
MOSFET should be greater than AVDD
.
TABLE 4. BOOST CONVERTER RECTIFIER DIODE
RECOMMENDATION
A
V
VDD
IN
DIODE
SS23
VR/IAVG RATING PACKAGE
MFG
30V/2A
40V/3A
30V/2A
SMB
SMC
SMB
Fairchild
Semiconductor
MBRS340
SL23
International
Rectifier
LX
FB
Vishay
Semiconductor
Intersil
ISL97645
Output Capacitor
The output capacitor supplies the load directly and reduces
the ripple voltage at the output. Output ripple voltage
consists of two components: the voltage drop due to the
inductor ripple current flowing through the ESR of output
capacitor, and the charging and discharging of the output
capacitor.
FIGURE 13. CASCADED MOSFET TOPOLOGY FOR HIGH
OUTPUT VOLTAGE APPLICATIONS
V
– V
I
1
×
O
IN
O
----------------------- --------------- ---
V
= I
× ESR +
LPK
×
RIPPLE
V
C
f
s
O
OUT
FN9263.0
April 11, 2006
10
ISL97645
Gate Pulse Modulator Circuit
The gate pulse modulator circuit functions as a three way
multiplexer, switching VGHM between ground, VDD1 and
VGH. Voltage selection is provided by digital inputs VDPM
(enable) and VFLK (control). High to low delay and slew
control is provided by external components on pins CE and
RE, respectively. A block diagram of the gate pulse
modulator circuit is shown in Figure 14.
When VDPM is LOW, the block is disabled and VGHM is
grounded. When VDPM is HIGH, the output is determined
by VFLK. When VFLK goes high, VGHM is pulled to VGH by
a 70Ω switch. When VFLK goes low, there is a delay
controlled by capacitor CE, following which VGHM is driven
to VDD1, with a slew rate controlled by resistor RE. Note
that VDD1 is used only as a reference voltage for an
amplifier, thus does not have to source or sink a significant
DC current.
VGH_M
FIGURE 14. GATE PULSE MODULATOR CIRCUIT BLOCK DIAGRAM
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ISL97645
Low to high transition is determined primarily by the switch
resistance and the external capacitive load. High to low
transition is more complex. Take the case where the block is
already enabled (VDPM is H). When VFLK is H, pin CE is
grounded. On the falling edge of VFLK, a current is passed
into pin CE, to charge an external capacitor to 1.2V. This
creates a delay, equal to CE * 4200. At this point, the output
begins to pull down from VGH to VDD1. The slew current is
equal to 300/(RE+5000)*Load Capacitance.
the following circuit can be inserted between input and
inductor to disconnect the DC path when the part is disabled.
INPUT
TO INDUCTOR
ENABLE
VDPM
0
FIGURE 17. CIRCUIT TO DISCONNECT THE DC PATH OF
BOOST CONVERTER
VFLK
SLOPE CONTROLLED
0
V
Amplifier
BY RE AND LOAD
COM
CAPACITANCE
The VCOM amplifier is designed to control the voltage on the
back plate of an LCD display. This plate is capacitively
coupled to the pixel drive voltage which alternately cycles
positive and negative at the line rate for the display. Thus the
amplifier must be capable of sourcing and sinking capacitive
pulses of current, which can occasionally be quite large (a
few 100mA for typical applications).
VGH
VGH_M
VDD_1
0
DELAY TIME
CONTROLLED BY CE
The ISL97645 VCOM amplifier's output current is limited to
400mA. This limit level, which is roughly the same for
sourcing and sinking, is included to maintain reliable
operation of the part. It does not necessarily prevent a large
temperature rise if the current is maintained. (In this case the
whole chip may be shut down by the thermal trip to protect
functionality.) If the display occasionally demands current
pulses higher than this limit, the reservoir capacitor will
provide the excess and the amplifier will top the reservoir
capacitor back up once the pulse has stopped. This will
happen on the µs time scale in practical systems and for
pulses 2 or 3 times the current limit, the VCOM voltage will
have settled again before the next line is processed.
FIGURE 15. GATE PULSE MODULATOR TIMING DIAGRAM
Start-Up Sequence
Figure 16 shows a detailed start-up sequence waveform.
V
IN
0
ENABLE
0
VIN THRESHOLD
VDPM
0
Fault Protection
ISL97645 provides the overall fault protections including
over current protection and over-temperature protection.
AVDD
VGH_M
An internal temperature sensor continuously monitors the
die temperature. In the event that die temperature exceeds
the thermal trip point, the device will shut down and disable
itself. The upper and lower trip points are typically set to
140°C and 100°C respectively.
0
FIGURE 16. START-UP SEQUENCE
When VIN exceeds 2.5V and ENABLE reaches the VIH
threshold value, Boost converter starts up, and gate pulse
modulator circuit output holds until VDPM goes to high. Note
that there is a DC path in the boost converter from the input
to the output through the inductor and diode, hence the input
voltage will be seen at output with a forward voltage drop of
diode before the part is enabled. If this voltage is not desired,
FN9263.0
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April 11, 2006
ISL97645
Layout Recommendation
The device’s performance including efficiency, output noise,
transient response and control loop stability is dramatically
affected by the PCB layout. PCB layout is critical, especially
at high switching frequency.
There are some general guidelines for layout:
1. Place the external power components (the input
capacitors, output capacitors, boost inductor and output
diodes, etc.) in close proximity to the device. Traces to
these components should be kept as short and wide as
possible to minimize parasitic inductance and resistance.
2. Place VIN and VDD bypass capacitors close to the pins.
3. Reduce the loop area with large AC amplitudes and fast
slew rate.
4. The feedback network should sense the output voltage
directly from the point of load, and be as far away from LX
node as possible.
5. The power ground (PGND) and signal ground (SGND)
pins should be connected at only one point.
6. The exposed die plate, on the underneath of the
package, should be soldered to an equivalent area of
metal on the PCB. This contact area should have multiple
via connections to the back of the PCB as well as
connections to intermediate PCB layers, if available, to
maximize thermal dissipation away from the IC.
7. To minimize the thermal resistance of the package when
soldered to a multi-layer PCB, the amount of copper track
and ground plane area connected to the exposed die
plate should be maximized and spread out as far as
possible from the IC. The bottom and top PCB areas
especially should be maximized to allow thermal
dissipation to the surrounding air.
8. A signal ground plane, separate from the power ground
plane and connected to the power ground pins only at the
exposed die plate, should be used for ground return
connections for control circuit.
9. Minimize feedback input track lengths to avoid switching
noise pick-up.
A demo board is available to illustrate the proper layout
implementation.
FN9263.0
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ISL97645
Quad Flat No-Lead Plastic Package (QFN)
L24.4x4D
24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
2X
0.15
C A
A
D
SYMBOL
MIN
0.80
-
NOMINAL
MAX
1.00
0.05
0.30
NOTES
D/2
A
A1
b
0.90
-
2X
-
-
N
0.15
C B
6
0.18
0.23
5, 8
INDEX
1
2
3
AREA
D
4.00 BSC
-
E/2
D2
E
2.30
2.30
2.50
2.65
2.65
7, 8
E
4.00 BSC
-
E2
e
2.50
7, 8
0.50 BSC
-
0.15
0.15
C B
B
2X
2X
k
0.25
0.30
-
0.40
24
6
-
-
TOP VIEW
C
A
L
0.50
8
N
2
Nd
Ne
3
A
// 0.10
0.08
C
C
6
3
Rev. 0 2/06
NOTES:
C
A1
SEATING
PLANE
SIDE VIEW
5
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
NX b
M
0.10
C A B
NX k
5. Dimension b applies to the metallized terminal and is measured
D2
7
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
(DATUM B)
D2
2
7. Dimensions D2 and E2 are for the exposed pad which provides
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
(DATUM A)
(Ne-1) X e
REF.
E2/2
E2
7
3
2
1
6
INDEX
AREA
NX L
N
e
C
C
(Nd-1)Xe
REF.
BOTTOM VIEW
(A1)
NX (b)
5
SECTION "C-C"
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9263.0
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April 11, 2006
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