首页 |元器件品牌

ISL98001CQZ-240 [INTERSIL]

Triple Video Digitizer with Digital PLL; 三路视频数字化仪，数字锁相环
ISL98001CQZ-240
型号： ISL98001CQZ-240
厂家： Intersil    Intersil
描述：

Triple Video Digitizer with Digital PLL
三路视频数字化仪，数字锁相环
文件： 总29页 (文件大小：467K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
ISL98001  
Key Features  
®
Data Sheet  
October 25, 2005  
FN6148.0  
Triple Video Digitizer with Digital PLL  
Features  
The ISL98001 3-channel, 8-bit Analog Front End (AFE)  
contains all the functions necessary to digitize analog YPbPr  
video signals and RGB graphics signals from DVD players,  
digital VCRs, video set-top boxes, and personal computers.  
This product family’s conversion rates support HDTV  
resolutions up to 1080p and PC monitor resolutions up to  
UXGA and QXGA, while the front end's programmable input  
bandwidth ensures sharp, clear images at all resolutions.  
• 140MSPS, 170MSPS, 210MSPS, 240MSPS, and  
275MSPS maximum conversion rates  
• Glitchless Macrovision®-compliant sync separator  
• Extremely fast recovery from VCR head switching  
• Low PLL clock jitter (250ps p-p @ 170MSPS)  
• 64 interpixel sampling positions  
• 0.35V  
to 1.4V  
video input range  
p-p  
p-p  
To maximize performance with the widest variety of video  
sources, the ISL98001 features a fast-responding digital PLL  
(DPLL), providing extremely low jitter with PC graphics signals  
and quick recovery from VCR head switching with video  
signals. Integrated HSYNC and SOG processing eliminate the  
need for external slicers, sync separators, Schmitt triggers,  
and filters.  
• Programmable bandwidth (100MHz to 780MHz)  
• 2 channel input multiplexer  
• RGB 4:4:4 and YUV 4:2:2 output formats  
• 5 embedded voltage regulators allow operation from  
single 3.3V supply and enhance performance, isolation  
Glitchless, automatic Macrovision®-compliance is obtained  
by a digital Macrovision® detection function that detects and  
automatically removes Macrovision® from the HSYNC  
signal.  
• Completely independent 8-bit gain/10-bit offset control  
• Pb-free plus anneal available (RoHS compliant)  
Applications  
• Digital TVs  
Ease-of-use is also emphasized with features such as the  
elimination of PLL charge pump current/VCO range  
programming and single-bit switching between RGB and  
YPbPr signals. Automatic Black Level Compensation  
(ABLC™) eliminates part-to-part offset variation, ensuring  
perfect black level performance in every application.  
• Projectors  
• Multifunction monitors  
• Digital KVM  
• RGB graphics processing  
The ISL98001 is fully backwards compatible (hardware and  
software) with the X980xx family of AFEs.  
Simplified Block Diagram  
Offset  
DAC  
ABLC™  
Voltage  
Clamp  
3
RGB/YPbPrIN1  
8 or 16  
x3  
RGB/YUVOUT  
8 bit ADC  
PGA  
3
+
RGB/YPbPrIN2  
HSYNCOUT  
VSYNCOUT  
SOGIN1/2  
Sync  
HSOUT  
HSYNCIN1/2  
VSYNCIN1/2  
Digital PLL  
PIXELCLKOUT  
Processing  
AFE Configuration and Control  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
Copyright Intersil Americas Inc. 2005. All Rights Reserved  
1
All other trademarks mentioned are the property of their respective owners.  
ISL98001  
Ordering Information  
MAXIMUM  
TEMPERATURE  
RANGE (°C)  
PACKAGE  
(Pb-free)  
PART NUMBER (Note)  
PART MARKING  
PIXEL RATE (MHz)  
PKG. DWG. #  
MDP0055  
MDP0055  
MDP0055  
MDP0055  
MDP0055  
ISL98001CQZ-140  
ISL98001CQZ-170  
ISL98001CQZ-210  
ISL98001CQZ-240  
ISL98001CQZ-275  
ISL98001CQ-140 Z  
ISL98001CQ-170 Z  
ISL98001CQ-210 Z  
ISL98001CQ-240 Z  
ISL98001CQ-275 Z  
140  
170  
210  
240  
275  
0 to 70  
0 to 70  
0 to 70  
0 to 70  
0 to 70  
128 MQFP  
128 MQFP  
128 MQFP  
128 MQFP  
128 MQFP  
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100%  
matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil  
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC  
J STD-020.  
Block Diagram  
VCLAMP  
Offset  
DAC  
10  
ABLC™  
RIN1  
RIN2  
VIN+  
VIN-  
8
8
RP[7:0]  
RS[7:0]  
8
8
8
8 bit ADC  
PGA  
PGA  
PGA  
+
+
+
VCLAMP  
Offset  
DAC  
10  
ABLC™  
GIN1  
RGBGND1  
VIN+  
VIN-  
8
8
GP[7:0]  
GS[7:0]  
8 bit ADC  
GIN2  
RGBGND2  
VCLAMP  
Offset  
DAC  
10  
ABLC™  
BIN1  
BIN2  
VIN+  
VIN-  
8
8
BP[7:0]  
BS[7:0]  
8 bit ADC  
DATACLK  
DATACLK  
SOGIN1  
SOGIN2  
HSYNCIN1  
Sync  
AFE Configuration  
and Control  
HSOUT  
VSOUT  
HSYNCIN2  
VSYNCIN1  
Processing  
VSYNCIN2  
HSYNCOUT  
VSYNCOUT  
CLOCKINV  
Digital PLL  
XTALIN  
XTALOUT  
XCLKOUT  
SCL  
SDA  
Serial  
Interface  
SADDR  
FN6148.0  
2
October 25, 2005  
ISL98001  
Absolute Maximum Ratings  
Thermal Information  
Thermal Resistance  
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Maximum Biased Junction Temperature . . . . . . . . . . . . . . . . . . 125°C  
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C  
Voltage on V , V , or V  
θ
(°C/W)  
30  
A
D
X
JA  
(referenced to GND = GND = GND ). . . . . . . . . . . . . . . . . 4.0V  
A
D
X
Voltage on any Analog Input Pin  
(referenced to GND ). . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V  
A
A
Voltage on any Digital Input Pin  
(referenced to GND ). . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V  
D
Recommended Operating Conditions  
Current into any Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA  
ESD Classification  
Temperature (Commercial) . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C  
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . V = V = V = 3.3V  
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000V  
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V  
A
D
X
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the  
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
Electrical Specifications Specifications apply for V = V = V = 3.3V, pixel rate = 140MHz for ISL98001-140, 170MHz for  
A
D
X
ISL98001-170, 210MHz for ISL98001-210, 240MHz for ISL98001-240, 275MHz for ISL98001-275,  
f
= 25MHz, T = 25°C, unless otherwise noted  
A
XTAL  
SYMBOL  
PARAMETER  
COMMENT  
MIN  
TYP  
MAX  
UNIT  
FULL CHANNEL CHARACTERISTICS  
Conversion Rate  
ISL98001-140  
Per Channel  
10  
10  
10  
10  
10  
8
140  
170  
210  
240  
275  
MHz  
MHz  
MHz  
MHz  
MHz  
Bits  
ISL98001-170  
ISL98001-210  
ISL98001-240  
ISL98001-275  
ADC Resolution  
Missing Codes  
Guaranteed monotonic  
None  
DNL  
(Full-  
Channel)  
Differential Non-Linearity  
ISL98001-140  
±0.5  
±0.5  
±0.6  
±0.6  
±0.7  
+1.0/-0.9  
+1.0/-0.9  
+1.0/-0.9  
+1.1/-0.9  
+1.2/-0.9  
LSB  
LSB  
LSB  
LSB  
LSB  
ISL98001-170  
ISL98001-210  
ISL98001-240  
ISL98001-275  
INL  
(Full-  
Channel)  
Integral Non-Linearity  
ISL98001-140  
±1.1  
±1.1  
±1.25  
±1.5  
±1.6  
±6  
±2.75  
±3.25  
±3.25  
±3.5  
LSB  
LSB  
LSB  
LSB  
LSB  
dB  
ISL98001-170  
ISL98001-210  
ISL98001-240  
ISL98001-275  
±3.75  
Gain Adjustment Range  
Gain Adjustment Resolution  
Gain Matching Between Channels  
8
Bits  
%
Percent of full scale  
±1  
Full Channel Offset Error,  
ABLC™ enabled  
ADC LSBs,  
±0.125  
±0.5  
1.4  
LSB  
over time and temperature  
Offset Adjustment Range  
(ABLC™ enabled or disabled)  
ADC LSBs (See ABLC™  
applications information section)  
±127  
LSB  
ANALOG VIDEO INPUT CHARACTERISTICS (R 1, G 1, B 1, R 2, G 2, B 2)  
IN  
IN  
IN  
IN  
IN  
IN  
Input Range  
0.35  
0.7  
V
P-P  
FN6148.0  
3
October 25, 2005  
ISL98001  
Electrical Specifications Specifications apply for V = V = V = 3.3V, pixel rate = 140MHz for ISL98001-140, 170MHz for  
A
D
X
ISL98001-170, 210MHz for ISL98001-210, 240MHz for ISL98001-240, 275MHz for ISL98001-275,  
f
= 25MHz, T = 25°C, unless otherwise noted (Continued)  
A
XTAL  
SYMBOL  
PARAMETER  
Input Bias Current  
COMMENT  
MIN  
TYP  
±0.01  
5
MAX  
UNIT  
µA  
DC restore clamp off  
±1  
Input Capacitance  
pF  
Full Power Bandwidth  
Programmable  
780  
MHz  
INPUT CHARACTERISTICS (SOG 1, SOG 2)  
IN  
IN  
V
/V  
Input Threshold Voltage  
Programmable - see register  
listing for details  
0 to  
-0.3  
V
IH IL  
Hysteresis  
Centered around threshold  
40  
5
mV  
pF  
Input Capacitance  
INPUT CHARACTERISTICS (HSYNC 1, HSYNC 2)  
IN  
IN  
V
/V  
Input Threshold Voltage  
Programmable - see register  
listing for details  
0.4 to  
3.2  
V
IH IL  
Hysteresis  
Centered around threshold  
voltage  
240  
mV  
R
C
Input Impedance  
Input Capacitance  
1.2  
5
kΩ  
IN  
pF  
IN  
DIGITAL INPUT CHARACTERISTICS (SDA, SADDR, CLOCKINV , RESET)  
IN  
V
Input HIGH Voltage  
Input LOW Voltage  
Input Leakage Current  
Input Capacitance  
2.0  
1.45  
2.4  
V
V
IH  
V
0.8  
IL  
I
RESET has a 70kΩ pullup to V  
±10  
5
nA  
pF  
D
SCHMITT DIGITAL INPUT CHARACTERISTICS (SCL, VSYNC 1, VSYNC 2)  
IN  
IN  
V +  
Low to High Threshold Voltage  
High to Low Threshold Voltage  
Input Leakage Current  
V
V
T
V -  
T
0.95  
I
±10  
5
nA  
pF  
Input Capacitance  
DIGITAL OUTPUT CHARACTERISTICS (DATACLK, DATACLK)  
Output HIGH Voltage, I = 16mA  
V
V
V
OH  
O
V
Output LOW Voltage, I = -16mA  
0.4  
0.4  
OL  
O
DIGITAL OUTPUT CHARACTERISTICS (R , G , B , R , G , B , HS  
, VS  
, HSYNC  
, VSYNC  
)
P
P
P
S
S
S
OUT  
OUT  
OUT  
OUT  
V
Output HIGH Voltage, I = 8mA  
2.4  
V
V
OH  
O
V
Output LOW Voltage, I = -8mA  
O
OL  
R
Pulldown to GND when Three-state  
R , G , B , R , G , B only  
56  
kΩ  
TRI  
D
P
P
P
S
S
S
DIGITAL OUTPUT CHARACTERISTICS (SDA, XCLK  
)
OUT  
V
Output HIGH Voltage, I = 4mA  
XCLK only; SDA is open-drain  
OUT  
2.4  
V
V
OH  
O
V
Output LOW Voltage, I = -4mA  
0.4  
OL  
O
POWER SUPPLY REQUIREMENTS  
V
Analog Supply Voltage  
3
3
3
3.3  
3.3  
3.3  
3.6  
3.6  
3.6  
200  
V
V
A
V
V
Digital Supply Voltage  
D
X
Crystal Oscillator Supply Voltage  
Analog Supply Current  
V
I
mA  
A
FN6148.0  
4
October 25, 2005  
ISL98001  
Electrical Specifications Specifications apply for V = V = V = 3.3V, pixel rate = 140MHz for ISL98001-140, 170MHz for  
A
D
X
ISL98001-170, 210MHz for ISL98001-210, 240MHz for ISL98001-240, 275MHz for ISL98001-275,  
f
= 25MHz, T = 25°C, unless otherwise noted (Continued)  
A
XTAL  
SYMBOL  
PARAMETER  
Digital Supply Current  
COMMENT  
MIN  
TYP  
MAX  
200  
2
UNIT  
mA  
I
With grayscale ramp input  
D
I
Crystal Oscillator Supply Current  
1.4  
mA  
X
P
Total Power Dissipation  
ISL98001-140  
D
With grayscale ramp input  
With grayscale ramp input  
With grayscale ramp input  
With grayscale ramp input  
With grayscale ramp input  
ADCs, PLL powered down  
0.95  
1.05  
1.10  
1.15  
1.20  
50  
1.10  
1.15  
1.20  
1.25  
1.30  
80  
W
W
ISL98001-170  
ISL98001-210  
ISL98001-240  
ISL98001-275  
Standby Mode  
W
W
W
mW  
AC TIMING CHARACTERISTICS  
PLL Jitter  
250  
450  
ps p-p  
Sampling Phase Steps  
Sampling Phase Tempco  
5.6° per step  
64  
±1  
±3  
ps/°C  
°
Sampling Phase  
Differential Nonlinearity  
Degrees out of 360°  
HSYNC Frequency Range  
10  
23  
23  
150  
27  
kHz  
MHz  
MHz  
f
Crystal Frequency Range  
25  
25  
XTAL  
f
Frequency Range with External 3.3V Clock  
33.5  
XTALIN  
Signal Driving XTAL  
IN  
t
DATA Valid Before Rising Edge of  
DATACLK  
15pF DATACLK load, 15pF DATA  
load (Note 1)  
1.3  
2.0  
ns  
ns  
SETUP  
t
DATA Valid After Rising Edge of DATACLK 15pF DATACLK load, 15pF DATA  
load (Note 1)  
HOLD  
AC TIMING CHARACTERISTICS (2-WIRE INTERFACE)  
f
SCL Clock Frequency  
0
400  
kHz  
ns  
SCL  
Maximum Width of a Glitch on SCL that Will 2 XTAL periods min  
be Suppressed  
80  
t
SCL LOW to SDA Data Out Valid  
5 XTAL periods plus SDA’s RC  
time constant  
See  
comment  
µs  
µs  
AA  
t
Time the Bus Must be Free Before a New  
Transmission Can Start  
1.3  
BUF  
t
Clock LOW Time  
1.3  
0.6  
0.6  
0.6  
100  
0
µs  
µs  
µs  
µs  
ns  
ns  
µs  
ns  
LOW  
t
Clock HIGH Time  
HIGH  
t
Start Condition Setup Time  
Start Condition Hold Time  
Data In Setup Time  
SU:STA  
HD:STA  
SU:DAT  
HD:DAT  
SU:STO  
t
t
t
Data In Hold Time  
t
Stop Condition Setup Time  
Data Output Hold Time  
0.6  
160  
t
4 XTAL periods min  
DH  
NOTE:  
1. Setup and hold times are specified for a 170MHz DATACLK rate.  
FN6148.0  
5
October 25, 2005  
ISL98001  
t
t
t
t
R
F
HIGH  
LOW  
SCL  
SDA IN  
t
SU:DAT  
t
t
t
SU:STO  
SU:STA  
HD:DAT  
t
HD:STA  
t
t
t
BUF  
AA  
DH  
SDA OUT  
FIGURE 1. 2-WIRE INTERFACE TIMING  
DATACLK  
DATACLK  
Pixel Data  
tHOLD  
tSETUP  
FIGURE 2. DATA OUTPUT SETUP AND HOLD TIMING  
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.  
HSYNCIN  
The sampling phase setting determines its relative position to the rest of the AFE’s output signals  
tHSYNCin-to-HSout = 7.5ns + (PHASE/64 +8.5)*tPIXEL  
Analog  
P0  
P1  
P2  
P3  
P4  
P5  
P6  
P7  
P8  
P9  
P10  
P11  
P12  
Video In  
DATACLK  
RP/GP/BP[7:0]  
RS/GS/BS[7:0]  
HSOUT  
8 DATACLK Pipeline Latency  
D0  
D1  
D2  
D3  
Programmable  
Width and Polarity  
FIGURE 3. 24-BIT OUTPUT MODE  
FN6148.0  
October 25, 2005  
6
ISL98001  
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.  
The sampling phase setting determines its relative position to the rest of the AFE’s output signals  
HSYNCIN  
tHSYNCin-to-HSout = 7.5ns + (PHASE/64 +8.5)*tPIXEL  
Analog  
P0  
P1  
P2  
P3  
P4  
P5  
P6  
P7  
P8  
P9  
P10  
P11  
P12  
Video In  
DATACLK  
GP[7:0]  
RP[7:0]  
BP[7:0]  
HSOUT  
8.5 DATACLK Pipeline Latency  
G0 (Yo) G1 (Y1) G2 (Y2)  
B0 (Uo) R1 (V1) B2 (U2)  
Programmable  
Width and Polarity  
FIGURE 4. 24-BIT 4:2:2 OUTPUT MODE (FOR YUV SIGNALS)  
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.  
HSYNCIN  
The sampling phase setting determines its relative position to the rest of the AFE’s output signals  
tHSYNCin-to-HSout = 7.5ns + (PHASE/64 +10.5)*tPIXEL  
Analog  
Video In  
P0  
P1  
P2  
P3  
P4  
P5  
P6  
P7  
P8  
P9  
P10  
P11  
P12  
DATACLK  
RP/GP/BP[7:0]  
RS/GS/BS[7:0]  
HSOUT  
D0  
D2  
D3  
D1  
Programmable  
Width and Polarity  
FIGURE 5. 48-BIT OUTPUT MODE  
FN6148.0  
7
October 25, 2005  
ISL98001  
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.  
HSYNCIN  
The sampling phase setting determines its relative position to the rest of the AFE’s output signals  
tHSYNCin-to-HSout = 7.5ns + (PHASE/64 +8.5)*tPIXEL  
Analog  
Video In  
P1  
P2  
P3  
P4  
P5  
P6  
P7  
P8  
P9  
P10  
P11  
P0  
DATACLK  
RP/GP/BP[7:0]  
RS/GS/BS[7:0]  
HSOUT  
D0  
D2  
D1  
Programmable  
Width and Polarity  
FIGURE 6. 48-BIT OUTPUT MODE, INTERLEAVED TIMING  
FN6148.0  
October 25, 2005  
8
ISL98001  
Pin Configuration (MQFP, ISL98001CQZ-xxx)  
NC  
NC  
1
2
3
4
5
6
7
8
9
102 RS5  
101 RS6  
100 RS7  
99 VD  
GNDA  
VBYPASS  
GNDA  
VA  
GNDD  
98  
97 GP0  
96 GP1  
RIN1  
GP2  
GNDA  
95  
VBYPASS  
94 GP3  
93 GP4  
92 GP5  
91 GP6  
90 GP7  
89 VD  
GNDA 10  
VA 11  
GIN  
RGBGND  
SOGIN  
1
1
1
12  
13  
14  
GNDA 15  
VBYPASS 16  
GNDA 17  
VA 18  
88 GNDD  
GS0  
87  
86 GS1  
85 GS2  
GS3  
BIN1  
19  
84  
VA 20  
83 GS4  
82 GS5  
81 GS6  
80 GS7  
79 VCORE  
78 GNDD  
77 VD  
GNDA 21  
RIN2  
22  
GNDA 23  
GIN  
RGBGND  
SOGIN  
2
2
2
24  
25  
26  
GNDD  
GNDA 27  
BIN 28  
76  
2
75 BP0  
74 BP1  
VA 29  
GNDA 30  
BP2  
73  
VCOREADC 31  
GNDD 32  
72 BP3  
71 BP4  
70 BP5  
69 BP6  
HSYNCIN  
1
33  
HSYNCIN2 34  
VA 35  
BP7  
68  
GNDA 36  
GNDX 37  
VX 38  
67 VD  
66 GNDD  
VREGIN  
65  
FN6148.0  
October 25, 2005  
9
ISL98001  
Pin Descriptions  
SYMBOL  
MQFP PIN #(s)  
DESCRIPTION  
R
G
1
1
7
Analog input. Red channel 1. DC couple or AC couple through 0.047µF.  
Analog input. Green channel 1. DC couple or AC couple through 0.047µF.  
Analog input. Blue channel 1. DC couple or AC couple through 0.047µF.  
IN  
12  
19  
13  
IN  
B
1
IN  
RGB  
1
Analog input. Ground reference for the R, G, and B inputs of channel 1 in the DC coupled configuration.  
Connect to the same ground as channel 1's R, G, and B termination resistors. This signal is not used in the  
GND  
AC-coupled configuration, but the pin should still be tied to GND .  
A
SOG  
1
14  
33  
Analog input. Sync on Green. Connect to G 1 through a 0.01µF capacitor in series with a 500Ω resistor.  
IN  
IN  
HSYNC  
1
1
Digital input, 5V tolerant, 240mV hysteresis, 1.2kΩ impedance to GND . Connect to channel 1's HSYNC  
IN  
A
signal through a 680Ω series resistor.  
VSYNC  
44  
22  
24  
28  
25  
Digital input, 5V tolerant, 500mV hysteresis. Connect to channel 1's VSYNC signal.  
Analog input. Red channel 2. DC couple or AC couple through 0.047µF.  
Analog input. Green channel 2. DC couple or AC couple through 0.047µF.  
Analog input. Blue channel 2. DC couple or AC couple through 0.047µF.  
IN  
R
G
2
IN  
2
IN  
B
2
IN  
RGB  
2
Analog input. Ground reference for the R, G, and B inputs of channel 2 in the DC coupled configuration.  
Connect to the same ground as channel 1's R, G, and B termination resistors. This signal is not used in the  
GND  
AC-coupled configuration, but the pin should still be tied to GND .  
A
SOG  
2
26  
34  
Analog input. Sync on Green. Connect to G 1 through a 0.01µF capacitor in series with a 500Ω resistor.  
IN  
IN  
HSYNC  
2
2
Digital input, 5V tolerant, 240mV hysteresis, 1.2kΩ impedance to GND . Connect to channel 2's HSYNC  
IN  
A
signal through a 680Ω series resistor.  
VSYNC  
45  
41  
Digital input, 5V tolerant, 500mV hysteresis. Connect to channel 2's VSYNC signal.  
Digital input, 5V tolerant. When high, changes the pixel sampling phase by 180 degrees. Toggle at frame rate  
IN  
CLOCKINV  
IN  
during VSYNC to allow 2x undersampling to sample odd and even pixels on sequential frames. Tie to D  
if unused.  
GND  
RESET  
46  
39  
40  
47  
Digital input, 5V tolerant, active low, 70kΩ pullup to V . Take low for at least 1µs and then high again to reset  
D
the ISL98001. This pin is not necessary for normal use and may be tied directly to the V supply.  
D
XTAL  
Analog input. Connect to external 24.5MHz to 27MHz crystal and load capacitor (See crystal spec for  
IN  
recommended loading). Typical oscillation amplitude is 1.0V  
centered around 0.5V.  
P-P  
XTAL  
XCLK  
Analog output. Connect to external 24.5MHz to 27MHz crystal and load capacitor (See crystal spec for  
OUT  
recommended loading). Typical oscillation amplitude is 1.0V  
centered around 0.5V.  
P-P  
3.3V digital output. Buffered crystal clock output at f  
system components.  
or f  
/2. May be used as system clock for other  
XTAL  
OUT  
XTAL  
SADDR  
SCL  
48  
50  
Digital input, 5V tolerant. Address = 0x4C when tied low. Address = 0x4D when tied high.  
Digital input, 5V tolerant, 500mV hysteresis. Serial data clock for 2-wire interface.  
Bidirectional Digital I/O, open drain, 5V tolerant. Serial data I/O for 2-wire interface.  
3.3V digital output. Red channel, primary pixel data. 56K pulldown when three-stated.  
3.3V digital output. Red channel, secondary pixel data. 56K pulldown when three-stated.  
3.3V digital output. Green channel, primary pixel data. 56K pulldown when three-stated.  
3.3V digital output. Green channel, secondary pixel data. 56K pulldown when three-stated.  
3.3V digital output. Blue channel, primary pixel data. 56K pulldown when three-stated.  
3.3V digital output. Blue channel, secondary pixel data. 56K pulldown when three-stated.  
SDA  
49  
R [7:0]  
112-119  
100-107  
90-97  
80-87  
68-75  
55-62  
121  
P
R [7:0]  
S
G [7:0]  
P
G [7:0]  
S
B [7:0]  
P
B [7:0]  
S
DATACLK  
3.3V digital output. Data clock output. Equal to pixel clock rate in 24-bit mode, one half of pixel clock rate in  
48-bit mode.  
DATACLK  
122  
125  
3.3V digital output. Inverse of DATACLK.  
HS  
3.3V digital output. HSYNC output aligned with pixel data. Use this output to frame the digital output data.  
This output is always purely horizontal sync (without any composite sync signals).  
OUT  
FN6148.0  
10  
October 25, 2005  
ISL98001  
Pin Descriptions (Continued)  
SYMBOL  
MQFP PIN #(s)  
DESCRIPTION  
VS  
126  
3.3V digital output. Artificial VSYNC output aligned with pixel data. VS  
is generated 8 pixel clocks after  
OUT  
OUT  
the trailing edge of HS  
. This signal is usually not needed.  
OUT  
HSYNC  
127  
128  
3.3V digital output. Buffered HSYNC (or SOG or CSYNC) output. This is typically used for measuring HSYNC  
period. This output will pass composite sync signals and Macrovision signals if present on HSYNC or  
OUT  
OUT  
IN  
SOG  
.
IN  
VSYNC  
3.3V digital output. Buffered VSYNC output. For composite sync signals, this output will be asserted for the  
duration of the disruption of the normal HSYNC pattern. This is typically used for measuring VSYNC period.  
V
6, 11, 18, 20, 29, Power supply for the analog section. Connect to a 3.3V supply and bypass each pin to GND with 0.1µF.  
A
A
35  
GND  
3, 5, 8, 10, 15, Ground return for V and V  
A
.
BYPASS  
A
D
X
17, 21, 23, 27,  
30, 36  
V
54, 67, 77, 89, Power supply for all digital I/Os. Connect to a 3.3V supply and bypass each pin to GND with 0.1µF.  
D
99, 111, 124  
D
GND  
32, 43, 51, 53, Ground return for V , V  
D
, V  
, and V  
.
PLL  
CORE COREADC  
66, 76, 78, 88,  
98, 108, 110,  
120, 123  
V
38  
37  
Power supply for crystal oscillator. Connect to a 3.3V supply and bypass to GND with 0.1µF.  
X
X
GND  
Ground return for V .  
X
V
4, 9, 16  
65  
Bypass these pins to GND with 0.1µF. Do not connect these pins to each other or anything else.  
A
BYPASS  
VREG  
3.3V input voltage for V  
voltage regulator. Connect to a 3.3V source and bypass to GND with 0.1µF.  
CORE D  
IN  
VREG  
64  
Regulated output voltage for V  
, V  
and V  
; typically 1.9V. Connect only to V , V  
PLL COREADC  
OUT  
PLL COREADC  
CORE  
and V  
and bypass at input pins as instructed below. Do not connect to anything else - this output can  
CORE  
only supply power to V  
, V  
and V  
.
PLL COREADC  
CORE  
V
31  
42  
Internal power for the ADC’s digital logic. Connect to VREG  
with 0.1µF.  
through a 10Ω resistor and bypass to GND  
through a 10Ω resistor and bypass to GND  
COREADC  
OUT  
OUT  
D
D
V
Internal power for the PLL’s digital logic. Connect to VREG  
with 0.1µF.  
PLL  
V
52, 79, 109  
1, 2, 63  
Internal power for core logic. Connect to VREG  
and bypass each pin to GND with 0.1µF.  
OUT D  
CORE  
NC  
Reserved. Do not connect anything to these pins.  
FN6148.0  
11  
October 25, 2005  
ISL98001  
Register Listing  
ADDRESS  
REGISTER (DEFAULT VALUE)  
BIT(S) FUNCTION NAME  
DESCRIPTION  
1 = initial silicon, 2 = second revision, etc.  
1 = ISL98001  
0x00  
Device ID  
(read only)  
3:0  
7:4  
0
Device Revision  
Device ID  
0x01  
SYNC Status  
(read only)  
HSYNC1 Active  
0: HSYNC1 is Inactive  
1: HSYNC1 is Active  
1
2
3
4
5
6
7
0
1
2
3
4
5
HSYNC2 Active  
VSYNC1 Active  
VSYNC2 Active  
SOG1 Active  
SOG2 Active  
PLL Locked  
0: HSYNC2 is Inactive  
1: HSYNC2 is Active  
0: VSYNC1 is Inactive  
1: VSYNC1 is Active  
0: VSYNC2 is Inactive  
1: VSYNC2 is Active  
0: SOG1 is Inactive  
1: SOG1 is Active  
0: SOG2 is Inactive  
1: SOG2 is Active  
0: PLL is unlocked  
1: PLL is locked to incoming HSYNC  
CSYNC Detect at  
Sync Splitter  
0: Composite Sync signal not detected  
1: Composite Sync signal is detected  
0x02  
SYNC Polarity  
(read only)  
HSYNC1  
Polarity  
0: HSYNC1 is Active High  
1: HSYNC1 is Active Low  
HSYNC2  
Polarity  
0: HSYNC2 is Active High  
1: HSYNC2 is Active Low  
VSYNC1  
Polarity  
0: VSYNC1 is Active High  
1: VSYNC1 is Active Low  
VSYNC2  
Polarity  
0: VSYNC2 is Active High  
1: VSYNC2 is Active Low  
HSYNC1  
Trilevel  
0: HSYNC1 is Standard Sync  
1: HSYNC1 is Trilevel Sync  
HSYNC2  
Trilevel  
0: HSYNC2 is Standard Sync  
1: HSYNC2 is Trilevel Sync  
7:6  
2:0  
N/A  
Returns 0  
0x03  
0x04  
HSYNC Slicer (0x33)  
HSYNC1 Threshold 000 = lowest (0.4V) All values referred to  
011 = default (1.6V) voltage at HSYNC input  
111 = highest (3.2V) pin, 240mV hysteresis  
3
6:4  
7
Reserved  
Set to 00  
HSYNC2 Threshold See HSYNC1  
Disable Glitch Filter 0: HSYNC/VSYNC Glitch Filter Enabled (default)  
1: HSYNC/VSYNC Glitch Filter Disabled  
SOG Slicer (0x16)  
3:0  
4
SOG1 and SOG2  
Threshold  
0x0 = lowest (0mV)  
0x6 = default (120mV) 20mV step size  
0xF = highest (300mV)  
SOG Filter  
Enable  
0: SOG low pass filter disabled  
1: SOG low pass filter enabled, 14MHz corner  
(default)  
5
SOG Hysteresis  
Disable  
0: 40mV SOG hysteresis enabled  
1: 40mV SOG hysteresis disabled (default)  
7:6  
Reserved  
Set to 00.  
FN6148.0  
October 25, 2005  
12  
ISL98001  
Register Listing (Continued)  
ADDRESS  
REGISTER (DEFAULT VALUE)  
BIT(S) FUNCTION NAME  
DESCRIPTION  
0x05  
Input configuration (0x00)  
0
Channel Select  
0: VGA1  
1: VGA2  
1
Input Coupling  
0: AC coupled (positive input connected to clamp  
DAC during clamp time, negative input disconnected  
from outside pad and always internally tied to  
appropriate clamp DAC).  
1: DC coupled (+ and - inputs are brought to pads and  
never connected to clamp DACs). Analog clamp  
signal is turned off in this mode.  
2
RGB/YPbPr  
Sync Type  
0: RGB inputs  
Base ABLC target code = 0x00 for R, G, and B)  
1: YPbPr inputs  
Base ABLC target code = 0x00 for G (Y)  
Base ABLC target code = 0x80 for R (Pr) and B (Pb)  
3
4
0: Separate HSYNC/VSYNC  
1: Composite (from SOG or CSYNC on HSYNC)  
Composite Sync  
Source  
0: SOG  
IN  
1: HSYNC  
IN  
Note: If Sync Type = 0, the multiplexer will pass  
HSYNC regardless of the state of this bit.  
IN  
5
6
COAST CLAMP  
enable  
0: DC restore clamping and ABLC™ suspended  
during COAST.  
1: DC restore clamping and ABLC™ continue during  
COAST.  
Sync Mask Disable 0: Interval between HSYNC pulses masked  
(preventing PLL from seeing Macrovision and any  
spurious glitches).  
1: Interval between HSYNC pulses not masked  
(Macrovision will cause PLL to lose lock).  
7
HSYNC  
Disable  
Mask  
0: HSYNC  
signal is masked (any Macrovision,  
OUT  
OUT  
sync glitches on incoming SYNC are stripped from  
HSYNC  
).  
OUT  
OUT  
1: HSYNC  
signal is not masked (any  
Macrovision, sync glitches on incoming SYNC  
appear on HSYNC  
).  
OUT  
If Sync Mask Disable = 1, HSYNC  
is not masked.  
OUT  
0x06  
0x07  
7:0  
7:0  
Red Gain  
Channel gain, where:  
Red Gain (0x55)  
gain (V/V) = 0.5 + [7:0]/170  
0x00: gain = 0.5V/V  
(1.4V  
input = full range of ADC)  
P-P  
Green Gain  
0x55: gain = 1.0V/V  
(0.7V input = full range of ADC)  
Green Gain (0x55)  
Blue Gain (0x55)  
P-P  
0xFF: gain = 2.0V/V  
(0.35V input = full range of ADC)  
0x08  
7:0  
Blue Gain  
P-P  
FN6148.0  
13  
October 25, 2005  
ISL98001  
Register Listing (Continued)  
ADDRESS  
REGISTER (DEFAULT VALUE)  
BIT(S) FUNCTION NAME  
DESCRIPTION  
0x09  
7:0  
7:0  
7:0  
0
Red Offset  
Green Offset  
Blue Offset  
ABLC™ enabled: digital offset control. A 1LSB change  
in this register will shift the ADC output by 1 LSB.  
ABLC™ disabled: analog offset control. These bits go  
to the upper 8-bits of the 10-bit offset DAC. A 1LSB  
change in this register will shift the ADC output  
approximately 1 LSB (Offset DAC range = 0) or  
0.5LSBs (Offset DAC range = 1).  
Red Offset (0x80)  
0x0A  
0x0B  
0x0C  
Green Offset (0x80)  
0x00 = min DAC value or -0x80 digital offset,  
0x80 = mid DAC value or 0x00 digital offset,  
0xFF = max DAC value or +0x7F digital offset  
Blue Offset (0x80)  
Offset DAC Configuration (0x00)  
Offset DAC Range  
Reserved  
0: ±½ ADC fullscale (1 DAC LSB ~ 1 ADC LSB)  
1: ±¼ ADC fullscale (1 DAC LSB ~ ½ ADC LSB)  
1
Set to 0.  
3:2  
Red Offset DAC  
LSBs  
These bits are the LSBs necessary for 10-bit manual  
offset DAC control.  
Combine with their respective MSBs in registers  
0x09, 0x0A, and 0x0B to achieve 10-bit offset DAC  
control.  
5:4  
7:6  
Green Offset DAC  
LSBs  
Blue Offset DAC  
LSBs  
0x0D  
AFE Bandwidth (0x2E)  
0
Unused  
Value doesn’t matter  
3:1  
AFE BW  
3dB point for AFE lowpass filter  
000b: 100MHz  
111b: 780MHz (default)  
7:4  
Peaking  
0x0: Peaking off  
0x1: Moderate peaking  
0x2: Maximum recommended peaking (default)  
Values above 2 are not recommended.  
0x0E  
0x0F  
PLL Htotal MSB (0x03)  
PLL Htotal LSB (0x20)  
5:0  
7:0  
PLL Htotal MSB  
PLL Htotal LSB  
14-bit HTOTAL (number of active pixels) value  
The minimum HTOTAL value supported is 0x200.  
HTOTAL to PLL is updated on LSB write only.  
0x10  
PLL Sampling Phase (0x00)  
5:0  
PLL Sampling Phase Used to control the phase of the ADC’s sample point  
relative to the period of a pixel. Adjust to obtain  
optimum image quality. One step = 5.625° (1.56% of  
pixel period).  
0x11  
0x12  
PLL Pre-coast (0x04)  
PLL Post-coast (0x04)  
7:0  
7:0  
Pre-coast  
Number of lines the PLL will coast prior to the start of  
VSYNC.  
Post-coast  
Number of lines the PLL will coast after the end of  
VSYNC.  
FN6148.0  
14  
October 25, 2005  
ISL98001  
Register Listing (Continued)  
ADDRESS  
REGISTER (DEFAULT VALUE)  
BIT(S) FUNCTION NAME  
DESCRIPTION  
0x13  
PLL Misc (0x04)  
0
PLL Lock Edge  
HSYNC1  
0: Lock on trailing edge of HSYNC1 (default)  
1: Lock on leading edge of HSYNC1  
1
PLL Lock Edge  
HSYNC2  
0: Lock on trailing edge of HSYNC2 (default)  
1: Lock on leading edge of HSYNC2  
2
3
Reserved  
Set to 0  
CLKINV Pin  
IN  
Disable  
0: CLKINV pin enabled (default)  
IN  
1: CLKINV pin disabled (internally forced low)  
IN  
5:4  
CLKINV Pin  
IN  
Function  
00: CLKINV (default)  
01: External CLAMP (See Note)  
10: External COAST  
11: External PIXCLK  
Note: the CLAMP pulse is used to  
- perform a DC restore (if enabled)  
- start the ABLC™ function (if enabled), and  
- update the data to the Offset DACs (always).  
In the default internal CLAMP mode, the ISL98001  
automatically generates the CLAMP pulse. If External  
CLAMP is selected, the Offset DAC values only  
change on the leading edge of CLAMP. If there is no  
internal clamp signal, there will be up to a 100ms  
delay between when the PGA gain or offset DAC  
register is written to, and when the PGA or offset DAC  
is actually updated.  
6
7
XCLK  
0: XCLK  
1: XCLK  
= f  
= f  
(default)  
OUT  
OUT  
OUT  
CRYSTAL  
CRYSTAL  
Frequency  
/2  
Disable XCLK  
0 = XCLK  
1 = XCLK  
enabled  
OUT  
OUT  
OUT  
is logic low  
0x14  
0x15  
0x16  
DC Restore and ABLC™ starting pixel  
MSB (0x00)  
4:0  
DC Restore and  
ABLC™ starting  
pixel (MSB)  
Pixel after HSYNC trailing edge to begin  
IN  
DC restore and ABLC™ functions. 13-bits.  
Set this register to the first stable black pixel following  
the trailing edge of HSYNC  
.
IN  
DC Restore and ABLC™ starting pixel LSB  
(0x03)  
7:0  
7:0  
DC Restore and  
ABLC™ starting  
pixel (LSB)  
DC Restore Clamp Width  
(0x10)  
DC Restore clamp  
width (pixels)  
Width of DC restore clamp used in AC-coupled  
configurations. Has no effect on ABLC™. Minimum  
value is 0x02 (a setting of 0x01 or 0x00 will not  
generate a clamp pulse).  
0x17  
ABLC™ Configuration (0x40)  
0
ABLC™ disable  
Reserved  
0: ABLC™ enabled (default)  
1: ABLC™ disabled  
1
Set to 0.  
3:2  
ABLC™ pixel width Number of black pixels averaged every line for  
ABLC™ function  
00: 16 pixels [default]  
01: 32 pixels  
10: 64 pixels  
11: 128 pixels  
6:4  
7
ABLC™ bandwidth  
Reserved  
ABLC™ Time constant (lines) = 2(5+[6:4])  
000 = 32 lines  
100 = 256 lines (default)  
111 = 4096 lines  
Set to 0.  
FN6148.0  
15  
October 25, 2005  
ISL98001  
Register Listing (Continued)  
ADDRESS  
REGISTER (DEFAULT VALUE)  
BIT(S) FUNCTION NAME  
DESCRIPTION  
0: 24-bits: Data output on R , G , B only; R , G , B  
S
0x18  
Output Format (0x00)  
0
Bus Width  
P
P
P
S
S
are all driven low (default).  
1: 48-bits: Data output on R , R , G , G , B , B  
S.  
P
P
P
S
S
1
Interleaving  
(48-bit mode only)  
0: No interleaving: data changes on same edge of  
DATACLK (default).  
1: Interleaved: Secondary databus data changes on  
opposite edge of DATACLK from primary databus.  
2
Bus Swap  
(48-bit mode only)  
0: First data byte after trailing edge of HSOUT  
appears on R , G , B (default).  
P P P  
1: First data byte after trailing edge of HSOUT  
appears on R , G , B (primary and secondary  
S
S
S
busses are reversed).  
3
4
UV order  
0: U0 V0 U2 V2 U4 V4 U6 V6… (default)  
1: U0 V1 U2 V3 U4 V5 U6 V7… (X980xx)  
(422 mode only)  
422 mode  
0: Data is formatted as 4:4:4 (RGB, default).  
1: Data is decimated to 4:2:2 (YUV), blue channel is  
driven low.  
5
DATACLK  
Polarity  
0: HS  
, VS  
, and Pixel Data changes on falling  
OUT  
OUT  
edge of DATACLK (default).  
1: HS  
edge of DATACLK.  
, VS  
, and Pixel Data changes on rising  
OUT  
OUT  
6
7
VS  
HS  
HS  
Polarity  
Polarity  
Width  
0: Active High (default)  
1: Active Low  
OUT  
OUT  
OUT  
0: Active High (default)  
1: Active Low  
0x19  
0x1A  
HS  
Width (0x10)  
7:0  
HS  
width, in pixels. Minimum value is 0x01 for 24-  
OUT  
OUT  
bit modes, 0x02 for 48-bit modes.  
Output Signal Disable (0x00)  
0
1
2
3
4
5
6
Three-state R [7:0] 0 = Output byte enabled  
P
1 = Output byte three-stated  
Three-state R 7:0]  
S
These bits override all other I/O settings  
Output data pins have 56kΩ pulldown resistors to  
Three-state G [7:0]  
P
GND .  
D
Three-state G 7:0]  
S
Three-state B [7:0]  
P
Three-state B [7:0]  
S
Three-state  
DATACLK  
0 = DATACLK enabled  
1 = DATACLK three-stated  
7
0
1
2
3
Three-state  
DATACLK  
0 = DATACLK enabled  
1 = DATACLK three-stated  
0x1B  
Power Control (0x00)  
Red  
Power-down  
0 = Red ADC operational (default)  
1 = Red ADC powered down  
Green  
Power-down  
0 = Green ADC operational (default)  
1 = Green ADC powered down  
Blue  
Power-down  
0 = Blue ADC operational (default)  
1 = Blue ADC powered down  
PLL  
Power-down  
0 = PLL operational (default)  
1 = PLL powered down  
7:4  
7:0  
Reserved  
Reserved  
Set to 0.  
0x1C  
PLL Tuning (0x49)  
Use default setting of 0x49 for all PC and video  
modes except signals coming from an analog VCR.  
Set to 0x4C for analog videotape compatibility.  
FN6148.0  
16  
October 25, 2005  
ISL98001  
Register Listing (Continued)  
ADDRESS  
REGISTER (DEFAULT VALUE)  
BIT(S) FUNCTION NAME  
DESCRIPTION  
0x1D  
Red ABLC Target (0x00)  
7:0  
Reserved  
This is a 2's complement number controlling the  
target code of the Red ADC output when ABLC is  
enabled.  
In RGB mode, the Red ADC output will be servoed to  
0x00 + the number in this register (-0x00 to +0x7F).  
In YPbPr mode, the Red ADC output will be servoed  
to 0x80 + the number in this register (-0x80 to +0x7F).  
Note: This register does NOT disable the digital offset  
adder. Both functions can be used simultaneously.  
0x1E  
0x1F  
Green ABLC Target (0x00)  
Blue ABLC Target (0x00)  
7:0  
7:0  
Reserved  
Reserved  
This is a 2's complement number controlling the  
target code of the Green ADC output when ABLC is  
enabled.  
In RGB and YPbPr modes, the Green ADC output will  
be servoed to 0x00 + the number in this register  
(-0x00 to +0x7F).  
Note: This register does NOT disable the digital offset  
adder. Both functions can be used simultaneously.  
This is a 2's complement number controlling the  
target code of the Blue ADC output when ABLC is  
enabled.  
In RGB mode, the Blue ADC output will be servoed to  
0x00 + the number in this register (-0x00 to +0x7F).  
In YPbPr mode, the Blue ADC output will be servoed  
to 0x80 + the number in this register (-0x80 to +0x7F).  
Note: This register does NOT disable the digital offset  
adder. Both functions can be used simultaneously.  
0x23  
DC Restore Clamp (0x18)  
3:0  
6:4  
Reserved  
Set to 1000  
DC Restore Clamp  
Impedance  
DC Restore clamp's ON resistance.  
Shared for all three channels  
0: Infinite (clamp disconnected) (default)  
1: 1600Ω  
2: 800Ω  
3: 533Ω  
4: 400Ω  
5: 320Ω  
6: 267Ω  
7: 228Ω  
7
Reserved  
Set to 0.  
FN6148.0  
17  
October 25, 2005  
ISL98001  
Register Listing (Continued)  
ADDRESS  
REGISTER (DEFAULT VALUE)  
BIT(S) FUNCTION NAME  
DESCRIPTION  
, HSYNC , VS  
0x25  
Sync Separator Control (0x00)  
0
Three-state Sync  
Outputs  
0: VSYNC  
, HS  
are  
OUT  
OUT  
OUT  
OUT  
OUT  
active (default).  
1: VSYNC , HSYNC  
, VS , HS  
OUT  
are in  
OUT  
OUT  
three-state.  
1
COAST Polarity  
0: Coast active high (default)  
1: Coast active low  
Set to 0 for internal VSYNC extracted from CSYNC.  
Set to 0 or 1 as appropriate to match external VSYNC  
or external COAST.  
2
HS  
Lock Edge  
0: HS  
's trailing edge is locked to selected  
OUT  
OUT  
HSYNC 's lock edge. Leading edge moves  
IN  
backward in time as HS  
(X980xx default).  
width is increased  
OUT  
1: HS  
's leading edge is locked to selected  
OUT  
HSYNC 's lock edge. Trailing edge moves forward  
IN  
in time as HS  
width is increased.  
OUT  
3
4
Reserved  
VSYNC  
Set to 0  
Mode  
0: VSYNC  
is aligned to HSYNC  
edge,  
OUT  
OUT  
OUT  
providing “perfect” VSYNC signal (default).  
1: VSYNC  
is “raw” integrator output.  
OUT  
5
6
7
Reserved  
Reserved  
Set to 0  
Set to 0  
VS  
Mode  
0: VS  
is output on VS  
pin (default).  
OUT  
OUT  
OUT  
1: COAST (including pre- and post-coast COAST) is  
output on VS pin.  
OUT  
The ISL98001's DPLL has less than 250ps of jitter, peak to  
peak, and independent of the pixel rate. The DPLL generates  
64 phase steps per pixel (vs. the industry standard 32), for  
fine, accurate positioning of the sampling point. The crystal-  
locked NCO inside the DPLL completely eliminates drift due to  
charge pump leakage, so there is inherently no frequency or  
phase change across a line. An intelligent all-digital loop filter/  
controller eliminates the need for the user to have to program  
or change anything (except for the number of pixels) to lock  
over a range from interlaced video (10MHz or higher) to  
UXGA 60Hz (170MHz, with the ISL98001-170).  
Technical Highlights  
The ISL98001 provides all the features of traditional triple  
channel video AFEs, but adds several next-generation  
enhancements, bringing performance and ease of use to  
new levels.  
DPLL  
All video AFEs must phase lock to an HSYNC signal,  
supplied either directly or embedded in the video stream  
(Sync On Green). Historically this has been implemented as  
a traditional analog PLL. At SXGA and lower resolutions, an  
analog PLL solution has proven adequate, if somewhat  
troublesome (due to the need to adjust charge pump  
currents, VCO ranges and other parameters to find the  
optimum trade-off for a wide range of pixel rates).  
The DPLL eliminates much of the performance limitations and  
complexity associated with noise-free digitization of high  
speed signals.  
Automatic Black Level Compensation (ABLC™)  
and Gain Control  
As display resolutions and refresh rates have increased,  
however, the pixel period has shrunk. An XGA pixel at a  
60Hz refresh rate has 15.4ns to change and settle to its new  
value. But at UXGA 75Hz, the pixel period is 4.9ns. Most  
consumer graphics cards (even the ones with “350MHz”  
DACs) spend most of that time slewing to the new pixel  
value. The pixel may settle to its final value with 1ns or less  
before it begins slewing to the next pixel. In many cases it  
rings and never settles at all. So precision, low-jitter  
sampling is a fundamental requirement at these speeds, and  
a difficult one for an analog PLL to meet.  
Traditional video AFEs have an offset DAC prior to the ADC,  
to both correct for offsets on the incoming video signals and  
add/subtract an offset for user “brightness control” without  
sacrificing the 8-bit dynamic range of the ADC. This solution  
is adequate, but it places significant requirements on the  
system's firmware, which must execute a loop that detects  
the black portion of the signal and then servos the offset  
DACs until that offset is nulled (or produces the desired ADC  
output code). Once this has been accomplished, the offset  
(both the offset in the AFE and the offset of the video card  
FN6148.0  
18  
October 25, 2005  
ISL98001  
generating the signal) is subject to drift - the temperature  
inside a monitor or projector can easily change 50°C  
between power-on/offset calibration on a cold morning and  
the temperature reached once the monitor and the monitor's  
environment have reached steady state. Offset can drift  
significantly over 50°C, reducing image quality and requiring  
that the user do a manual calibration once the monitor has  
warmed up.  
Functional Description  
Inputs  
The ISL98001 digitizes analog video inputs in both RGB  
and Component (YPbPr) formats, with or without  
embedded sync (SOG).  
RGB Inputs  
For RGB inputs, the black/blank levels are identical and equal  
to 0V. The range for each color is typically 0V to 0.7V from  
black to white. HSYNC and VSYNC are separate signals.  
In addition to drift, many AFEs exhibit interaction between  
the offset and gain controls. When the gain is changed, the  
magnitude of the offset is changed as well. This again  
increases the complexity of the firmware as it tries to  
optimize gain and offset settings for a given video input  
signal. Instead of adjusting just the offset, then the gain, both  
have to be adjusted interactively until the desired ADC  
output is reached.  
Component YPbPr Inputs  
In addition to RGB and RGB with SOG, the ISL98001 has an  
option that is compatible with the component YPbPr video  
inputs typically generated by DVD players. While the  
ISL98001 digitizes signals in these color spaces, it does not  
perform color space conversion; if it digitizes an RGB signal,  
it outputs digital RGB, while if it digitizes a YPbPr signal, it  
outputs digital YCbCr, also called YUV.  
The ISL98001 simplifies offset and gain adjustment and  
completely eliminates offset drift using its Automatic Black  
Level Compensation (ABLC™) function. ABLC™ monitors the  
black level and continuously adjusts the ISL98001's 10-bit  
offset DACs to null out the offset. Any offset, whether due to  
the video source or the ISL98001's analog amplifiers, is  
eliminated with 10-bit (1/4 of an ADC LSB) accuracy. Any drift  
is compensated for well before it can have a visible effect.  
Manual offset adjustment control is still available - an 8-bit  
register allows the firmware to adjust the offset ±64 codes in  
exactly 1 ADC LSB increments. And gain is now completely  
independent of offset - adjusting the gain no longer affects the  
offset, so there is no longer a need to program the firmware to  
cope with interactive offset and gain controls.  
The Luminance (Y) signal is applied to the Green Channel  
and is processed in a manner identical to the Green input  
with SOG described previously. The color difference signals  
Pb and Pr are bipolar and swing both above and below the  
black level. When the YPbPr mode is enabled, the black  
level output for the color difference channels shifts to a mid  
scale value of 0x80. Setting configuration register  
0x05[2] = 1 enables the YPbPr signal processing mode of  
operation.  
TABLE 1. YUV MAPPING (4:4:4)  
ISL98001  
INPUT  
ISL98001  
OUTPUT  
INPUT  
OUTPUT  
SIGNAL  
Finally, there should be no concerns over ABLC™ itself  
introducing visible artifacts; it doesn't. ABLC™ functions at a  
very low frequency, changing the offset in 1/4 LSB  
increments, so it can't cause visible brightness fluctuations.  
And once ABLC™ is locked, if the offset doesn't drift, the  
DACs won't change. If desired, ABLC™ can be disabled,  
allowing the firmware to work in the traditional way, with  
10-bit offset DACs under the firmware's control.  
SIGNAL  
CHANNEL  
ASSIGNMENT  
Y
Green  
Blue  
Green  
Blue  
Y Y Y Y  
1 2 3  
0
Pb  
Pr  
U U U U  
0
1
2
3
3
Red  
Red  
V V V V  
0 1 2  
The ISL98001 can optionally decimate the incoming data to  
provide a 4:2:2 output stream (configuration register  
0x18[4] = 1) as shown in Table 2.  
Gain and Offset Control  
To simplify image optimization algorithms, the ISL98001  
features fully-independent gain and offset adjustment.  
Changing the gain does not affect the DC offset, and the  
weight of an Offset DAC LSB does not vary depending on  
the gain setting.  
TABLE 2. YUV MAPPING (4:2:2)  
ISL98001  
INPUT  
ISL98001  
OUTPUT  
INPUT  
OUTPUT  
SIGNAL  
SIGNAL  
CHANNEL  
ASSIGNMENT  
Y
Green  
Blue  
Green  
Blue  
Y Y Y Y  
0 1 2 3  
The full-scale gain is set in the three 8-bit registers  
Pb  
Pr  
driven low  
U V U V  
0 0 2 2  
(0x06-0x08). The ISL98001 can accept input signals with  
amplitudes ranging from 0.35V  
to 1.4V  
.
Red  
Red  
P-P  
P-P  
The offset controls shift the entire RGB input range, changing  
the input image brightness. Three separate registers provide  
independent control of the R, G, and B channels. Their  
nominal setting is 0x80, which forces the ADC to output code  
0x00 (or 0x80 for the R (Pr) and B (Pb) channels in YPbPr  
mode) during the back porch period when ABLC™ is enabled.  
There is also a “compatibility mode”, enabled by setting bit 3  
of register 0x18 to a 1, that outputs the U and V data with the  
format used by the previous generation (“X980xx”) series of  
AFEs, shown in Table 3.  
FN6148.0  
19  
October 25, 2005  
ISL98001  
Automatic Black Level  
Compensation (ABLC™) Loop  
DC Restoration  
Offset  
10  
Fixed  
Offset  
Control  
To  
CLAMP  
Offset  
DAC  
Registers  
10  
ABLC  
Block  
GENERATION  
0x00  
8
VCLAMP  
8
DC Restore  
Clamp DAC  
10  
ABLC™  
ABLC™  
Fixed  
Offset  
ABLC™  
R(GB)IN  
1
8
VIN  
+
VGA1  
VGA2  
R(GB)GND1  
Input  
8
8
To Output  
Formatter  
PGA  
8 bit ADC  
Bandwidth  
VIN  
-
R(GB)IN  
2
Bandwidth  
Control  
R(GB)GND2  
FIGURE 7. VIDEO FLOW (INCLUDING ABLC™)  
SOG  
TABLE 3. YUV MAPPING (4:2:2)  
For component YPbPr signals, the sync signal is embedded  
on the Y channel’s video, which is connected to the green  
input, hence the name SOG (Sync on Green). The horizontal  
sync information is encoded onto the video input by adding  
the sync tip during the blanking interval. The sync tip level is  
typically 0.3V below the video black level.  
ISL98001  
INPUT  
ISL98001  
OUTPUT  
INPUT  
OUTPUT  
SIGNAL  
SIGNAL  
CHANNEL  
ASSIGNMENT  
Y
Green  
Blue  
Green  
Blue  
Y Y Y Y  
1 2 3  
0
Pb  
Pr  
driven low  
U V U V  
1 2 3  
To minimize the loading on the green channel, the SOG input  
for each of the green channels should be AC-coupled to the  
ISL98001 through a series combination of a 10nF capacitor  
and a 500Ω resistor. Inside the ISL98001, a window  
Red  
Red  
0
Input Coupling  
Inputs can be either AC-coupled (default) or DC-coupled (See  
register 0x05[1]). AC coupling is usually preferred since it  
allows video signals with substantial DC offsets to be accurately  
digitized. The ISL98001 provides a complete internal  
DC-restore function, including the DC restore clamp (See  
Figure 7) and programmable clamp timing (registers 0x14,  
0x15, 0x16, and 0x23).  
comparator compares the SOG signal with an internal 4-bit  
programmable threshold level reference ranging from 0mV to  
300mV below the minimum sync level. The SOG threshold  
level, hysteresis, and low-pass filter is programmed via  
register 0x04. If the Sync-On-Green function is not needed,  
the SOG pin(s) may be left unconnected.  
IN  
SYNC Processing  
When AC-coupled, the DC restore clamp is applied every line,  
a programmable number of pixels after the trailing edge of  
HSYNC. If register 0x05[5] = 0 (the default), the clamp will not  
be applied while the DPLL is coasting, preventing any clamp  
voltage errors from composite sync edges, equalization pulses,  
or Macrovision signals.  
The ISL98001 can process sync signals from 3 different  
sources: discrete HSYNC and VSYNC, composite sync on  
the HSYNC input, or composite sync from a Sync-On-Green  
(SOG) signal embedded on the Green video input. The  
ISL98001 has SYNC activity detect functions to help the  
firmware determine which sync source is available.  
After the trailing edge of HSYNC, the DC restore clamp is  
turned on after the number of pixels specified in the DC Restore  
and ABLC™ Starting Pixel registers (0x14 and 0x15) has been  
reached. The clamp is applied for the number of pixels  
specified by the DC Restore Clamp Width Register (0x16). The  
clamp can be applied to the back porch of the video, or to the  
front porch (by increasing the DC Restore and ABLC™ Starting  
Pixel registers so all the active video pixels are skipped).  
Macrovision  
The ISL98001 automatically detects the presence of  
Macrovision-encoded video. When Macrovision is detected,  
it generates a mask signal that is ANDed with the incoming  
SOG CSYNC signal to remove the Macrovision before the  
HSYNC goes to the PLL. No additional programming is  
required to support Macrovision.  
If DC-coupled operation is desired, the input to the ADC will be  
If desired (it is never necessary in normal operation), this  
function can be disabled by setting the Sync Mask Disable  
(register 0x05 bit 6) to a 1.  
the difference between the input signal (R 1, for example) and  
IN  
that channel’s ground reference (RGB  
1 in that example).  
GND  
FN6148.0  
20  
October 25, 2005  
ISL98001  
The mask signal is also applied to the HSYNC  
signal.  
to the correct value before the next headswitch, rendering  
OUT  
When Sync Mask Disable = 0, any Macrovision present on  
the incoming sync will not be visible on HSYNC . If the  
the image completely unintelligible.  
OUT  
Intersil’s DPLL has the capability to correct large phase  
changes almost instantly by maximizing the phase error gain  
while keeping the frequency gain relatively low. This is done  
by changing the contents of register 0x1C to 0x4C. This  
increases the phase error gain to 100%. Because a phase  
setting this high will slightly increase jitter, the default setting  
(0x49) for register 0x1C is recommended for all other sync  
sources.  
application requires the Macrovision pulses to be visible on  
HSYNC , set the HSYNC Mask Disable bit (register  
OUT  
OUT  
0x05 bit 7).  
Headswitching from Analog Videotape Signals  
Occasionally this AFE may be used to digitize signals  
coming from analog videotape sources. The most common  
example of this is a Digital VCR (which for best signal quality  
would be connected to this AFE with a component YPbPr  
connection). If the digital VCR is playing an older analog  
VHS tape, the sync signals from the VCR may contain the  
worst of the traditional analog tape artifacts: headswitching.  
Headswitching is traditionally the enemy of PLLs with large  
capture ranges, because a headswitch can cause the  
HSYNC period to change by as much as ±90%. To the PLL,  
this can look like a frequency change of -50% to greater than  
+900%, causing errors in the output frequency (and  
PGA  
The ISL98001’s Programmable Gain Amplifier (PGA) has a  
nominal gain range from 0.5V/V (-6dB) to 2.0V/V (+6dB).  
The transfer function is:  
V
   
---  
GainCode  
Gain  
= 0.5 + ----------------------------  
   
V
170  
where GainCode is the value in the Gain register for that  
particular color. Note that for a gain of 1V/V, the GainCode  
should be 85 (0x55). This is a different center value than the  
128 (0x80) value used by some other AFEs, so the firmware  
should take this into account when adjusting gains.  
obviously the phase) to change. Subsequent HSYNCs have  
the correct, original period, but most analog PLLs will take  
dozens of lines to settle back to the correct frequency and  
phase after a headswitch disturbance. This causes the top of  
the image to “tear” during normal playback. In “trick modes”  
(fast forward and rewind), the HSYNC signal has multiple  
headswitch-like discontinuities, and many PLLs never settle  
The PGAs are updated by the internal clamp signal once per  
line. In normal operation this means that there is a maximum  
ACTIVITY 0x01[6:0]  
&
POLARITY 0x02[5:0]  
DETECT  
HSYNC1  
HSYNCOUT  
CSYNC  
HSYNCIN  
1
1
SLICER  
SOURCE  
0x03[2:0]  
0:  
00, 10,  
11:  
SYNC  
TYPE  
VSYNCIN  
HSYNCIN  
VGA1  
HSYNCIN  
SOG  
SLICER  
0x1C  
VSYNC  
SYNC  
SOGIN1  
1:  
0x05[4:3]  
SPLITTER  
SYNC  
SPLTR  
SOGIN  
0x05[0]  
HSYNC2  
SLICER  
0x03[6:4]  
01:  
HSYNCIN  
2
VSYNCOUT  
SOGIN  
0x05[3]  
VSYNCIN  
1:  
0:  
VSYNCIN2  
SOGIN  
VGA2  
VSYNCIN  
SOG  
SLICER  
0x1C  
2
COAST  
RP[7:0]  
RS[7:0]  
GP[7:0]  
GENERATION  
0x11, 0x12, 0x13[2]  
Pixel Data  
from AFE  
24  
CLOCKINVIN  
GS[7:0]  
BP[7:0]  
Output  
HS  
Formatter  
PLL  
BS[7:0]  
XTALIN  
0x18,  
0x19,  
0x1A  
0x0E through 0x13  
DATACLK  
DATACLK  
PIXCLK  
0: ÷1  
XTALOUT  
0x13  
[6]  
HSOUT  
VSOUT  
1: ÷2  
÷2  
XTALCLOCKOUT  
FIGURE 8. SYNC FLOW  
FN6148.0  
October 25, 2005  
21  
ISL98001  
delay of one HSYNC period between a write to a Gain  
When the ABLC function is enabled (0x17[0] = 0), the ABLC  
function is executed every line after the trailing edge of  
HSYNC. If register 0x05[5] = 0 (the default), the ABLC  
function will be not be triggered while the DPLL is coasting,  
preventing any composite sync edges, equalization pulses,  
or Macrovision signals from corrupting the black data and  
potentially adding a small error in the ABLC accumulator.  
register for a particular color and the corresponding change  
in that channel’s actual PGA gain. If there is no regular  
HSYNC/SOG source, or if the external clamp option is  
enabled (register 0x13[5:4]) but there is no external clamp  
signal being generated, it may take up to 100ms for a write  
to the Gain register to update the PGA. This is not an issue  
in normal operation with RGB and YPbPr signals.  
After the trailing edge of HSYNC, the start of ABLC is  
delayed by the number of pixels specified in registers 0x14  
and 0x15. After that delay, the number of pixels specified  
by register 0x17[3:2] are averaged together and added to  
the ABLC’s accumulator. The accumulator stores the  
average black levels for the number of lines specified by  
register 0x17[6:4], which is then used to generate a 10-bit  
DAC value.  
Offset DAC  
The ISL98001 features a 10-bit Digital-to-Analog Converter  
(DAC) to provide extremely fine control over the full channel  
offset. The DAC is placed after the PGA to eliminate  
interaction between the PGA (controlling “contrast”) and the  
Offset DAC (controlling “brightness”).  
In normal operation, the Offset DAC is controlled by the  
ABLC™ circuit, ensuring that the offset is always reduced  
to sub-LSB levels (See the following ABLC™ section for  
more information). When ABLC™ is enabled, the Offset  
registers (0x09, 0x0A, 0x0B) control a digital offset added  
to or subtracted from the output of the ADC. This mode  
provides the best image quality and eliminates the need for  
any offset calibration.  
The default values provide excellent results with offset  
stability and absolute accuracy better than 1 ADC LSB for  
most input signals.  
ADC  
The ISL98001 features 3 fully differential, high-speed 8-bit  
ADCs.  
Clock Generation  
If desired, ABLC™ can be disabled (0x17[0] = 1) and the  
Offset DAC programmed manually, with the 8 most  
significant bits in registers 0x09, 0x0A, 0x0B, and the 2 least  
significant bits in register 0x0C[7:2].  
A Digital Phase Lock Loop (DPLL) is employed to generate  
the pixel clock frequency. The HSYNC input and the external  
XTAL provide a reference frequency to the PLL. The PLL  
then generates the pixel clock frequency that equal to the  
incoming HSYNC frequency times the HTOTAL value  
programmed into registers 0x0E and 0x0F.  
The default Offset DAC range is ±127 ADC LSBs. Setting  
0x0C[0] = 1 reduces the swing of the Offset DAC by 50%,  
making 1 Offset DAC LSB the weight of 1/8th of an ADC  
LSB. This provides the finest offset control and applies to  
both ABLC™ and manual modes.  
The stability of the clock is very important and correlates  
directly with the quality of the image. During each pixel time  
transition, there is a small window where the signal is  
slewing from the old pixel amplitude and settling to the new  
pixel value. At higher frequencies, the pixel time transitions  
at a faster rate, which makes the stable pixel time even  
smaller. Any jitter in the pixel clock reduces the effective  
stable pixel time and thus the sample window in which pixel  
sampling can be made accurately.  
Automatic Black Level Compensation (ABLC™)  
ABLC is a function that continuously removes all offset  
errors from the incoming video signal by monitoring the  
offset at the output of the ADC and servoing the 10-bit  
analog DAC to force those errors to zero. When ABLC is  
enabled, the user offset control is a digital adder, with 8-bit  
resolution (See Table 4).  
TABLE 4. OFFSET DAC RANGE AND OFFSET DAC ADJUSTMENT  
OFFSET  
DAC RANGE  
0X0C[0]  
10-BIT  
USER OFFSET CONTROL RESOLUTION  
USING REGISTERS 0x09 - 0X0B ONLY  
(8-BIT OFFSET CONTROL)  
USER OFFSET CONTROL RESOLUTION  
USING REGISTERS 0X09 - 0x0B AND  
0X0C[7:2](10-BIT OFFSET CONTROL)  
OFFSET DAC  
RESOLUTION  
ABLC™  
0x17[0]  
0
1
0
1
0.25 ADC LSBs  
(0.68mV)  
0
1 ADC LSB  
N/A  
(ABLC on)  
(digital offset control)  
0.125 ADC LSBs  
(0.34mV)  
0
1 ADC LSB  
(digital offset control)  
N/A  
(ABLC on)  
0.25 ADC LSBs  
(0.68mV)  
1
1.0 ADC LSB  
(analog offset control)  
0.25 ADC LSB  
(analog offset control)  
(ABLC off)  
0.125 ADC LSBs  
(0.34mV)  
1
0.5 ADC LSB  
(analog offset control)  
0.125 ADC LSB  
(analog offset control)  
(ABLC off)  
FN6148.0  
October 25, 2005  
22  
ISL98001  
The accuracy of the Trilevel Sync detect bit can be increased  
Sampling Phase  
The ISL98001 provides 64 low-jitter phase choices per pixel  
period, allowing the firmware to precisely select the optimum  
sampling point. The sampling phase register is 0x10.  
by multiple reads of the Trilevel Sync detect bit. See the  
Trilevel Sync Detect section for more details.  
For best SOG operation, the SOG low pass filter (register  
0x04[4] should always be enabled to reject the high  
frequency peaking often seen on video signals.  
HSYNC Slicer  
To further minimize jitter, the HSYNC inputs are treated as  
analog signals, and brought into a precision slicer block with  
thresholds programmable in 400mV steps with 240mV of  
hysteresis, and a subsequent digital glitch filter that ignores  
any HSYNC transitions within 100ns of the initial transition.  
This processing greatly increases the AFE’s rejection of  
ringing and reflections on the HSYNC line and allows the  
AFE to perform well even with pathological HSYNC signals.  
HSYNC and VSYNC Activity Detect  
Activity on these bits always indicates valid sync pulses, so  
they should have the highest priority and be used even if the  
SOG activity bit is also set.  
SOG Activity Detect  
The SOG activity detect bit monitors the output of the SOG  
slicer, looking for 64 consecutive pulses with the same period  
and duty cycle. If there is no signal on the Green (or Y)  
channel, the SOG slicer will clamp the video to a DC level and  
will reject any sporadic noise. There should be no false  
positive SOG detects if there is no video on Green (or Y).  
Voltages given above and in the HSYNC Slicer register  
description are with respect to a 3.3V sync signal at the  
HSYNC input pin. To achieve 5V compatibility, a 680Ω  
IN  
series resistor should be placed between the HSYNC source  
and the HSYNC input pin. Relative to a 5V input, the  
IN  
hysteresis will be 240mV*5V/3.3V = 360mV, and the slicer  
step size will be 400mV*5V/3.3V = 600mV per step.  
If there is video on Green (or Y) with no valid SOG signal,  
the SOG activity detect bit may sometimes report false  
positives (it will detect SOG when no SOG is actually  
present). This is due to the presence of video with a  
repetitive pattern that creates a waveform similar to SOG.  
For example, the desktop of a PC operating system is black  
during the front porch, horizontal sync, and back porch, then  
increases to a larger value for the video portion of the  
screen. This creates a repetitive video waveform very similar  
to SOG that may falsely trigger the SOG Activity detect bit.  
However, in these cases where there is active video without  
SOG, the SYNC information will be provided either as  
SOG Slicer  
The SOG input has programmable threshold, 40mV of  
hysteresis, and an optional low pass filter that can be used to  
remove high frequency video spikes (generated by overzealous  
video peaking in a DVD player, for example) that can cause  
false SOG triggers. The SOG threshold sets the comparator  
threshold relative to the sync tip (the bottom of the SOG pulse).  
SYNC Status and Polarity Detection  
The SYNC Status register (0x01) and the SYNC Polarity  
register (0x02) continuously monitor all 6 sync inputs  
separate H and V sync on HSYNC and VSYNC , or  
IN  
IN  
composite sync on HSYNC . HSYNC and VSYNC  
IN  
IN  
IN  
(VSYNC , HSYNC , and SOG for each of 2 channels)  
IN  
IN  
IN  
should therefore be used to qualify SOG. The SOG Active bit  
should only be considered valid if HSYNC Activity  
Detect = 0. Note: Some pattern generators can output  
HSYNC and SOG simultaneously, in which case both the  
HSYNC and the SOG activity bits will be set, and valid. Even  
in this case, however, the monitor should still choose  
HSYNC over SOG.  
and report their status. However, accurate sync activity  
detection is always a challenge. Noise and repetitive video  
patterns on the Green channel may look like SOG activity  
when there actually is no SOG signal, while non-standard  
SOG signals and trilevel sync signals may have amplitudes  
below the default SOG slicer levels and not be easily  
detected. As a consequence, not all of the activity detect bits  
in the ISL98001 are correct under all conditions.  
TriLevel Sync Detect  
Unlike SOG detect, the TriLevel Sync detect function does  
not check for 64 consecutive trilevel pulses in a row, and is  
therefore less robust than the SOG detect function. It will  
report false positives for SOG-less video for the same  
reasons the SOG activity detect does, and should therefore  
be qualified with both HSYNC and SOG. TriLevel Sync  
Detect should only be considered valid if HSYNC Activity  
Detect = 0 and SOG Activity Detect = 1.  
Table 5 shows how to use the SYNC Status register (0x01)  
to identify the presence of and type of a sync source. The  
firmware should go through the table in the order shown,  
stopping at the first entry that matches the activity indicators  
in the SYNC Status register.  
Final validation of composite sync sources (SOG or  
Composite sync on HSYNC) should be done by setting the  
Input Configuration register (0x05) to the composite sync  
source determined by this table, and confirming that the  
CSYNC detect bit is set.  
FN6148.0  
23  
October 25, 2005  
ISL98001  
TABLE 5. SYNC SOURCE DETECTION TABLE  
HSYNC  
VSYNC  
SOG  
TRILEVEL  
DETECT  
DETECT  
DETECT  
DETECT  
RESULT  
1
1
1
0
X
X
X
X
Sync is on HSYNC and VSYNC  
Sync is composite sync on HSYNC. Set Input configuration register to CSYNC on  
HSYNC and confirm that CSYNC detect bit is set.  
0
0
1
0
Sync is composite sync on SOG. It is possible that trilevel sync is present but amplitude  
is too low to set trilevel detect bit. Use video mode table to determine if this video mode  
is likely to have trilevel sync, and set clamp start, width values appropriately if it is.  
0
0
0
0
1
0
1
Sync is composite sync on SOG. Sync is likely to be trilevel.  
No valid sync sources on any input.  
X
If there is a SOG signal, the TriLevel Detect bit will operate  
detection. HSYNC  
sync signal: either horizontal or composite sync. If a SOG input  
is selected, HSYNC will output the entire SOG signal,  
including the VSYNC portion, pre-/post-equalization pulses if  
present, and Macrovision pulses if present. HSYNC  
will be the same format as the incoming  
OUT  
correctly for standard trilevel sync levels (600mV ). In  
P-P  
some real-world situations, the peak-to-peak sync amplitude  
OUT  
may be significantly smaller, sometimes 300mV  
or less.  
P-P  
In these cases the sync slicer will continue to operate  
correctly, but the TriLevel Detect bit may not be set. Trilevel  
detection accuracy can be enhanced by polling the trilevel  
bit multiple times. If HSYNC is inactive, SOG is present, and  
the TriLevel Sync Detect bit is read as a 1, there is a high  
likelihood there is trilevel sync.  
OUT  
remains active when the ISL98001 is in power-down mode.  
HSYNC is generally used for mode detection.  
OUT  
VSYNC  
OUT  
VSYNC  
is an unmodified, buffered version of the  
OUT  
incoming VSYNC signal of the selected channel, with the  
IN  
CSYNC Present  
original VSYNC period, polarity, and width to aid in mode  
detection. If a SOG input is selected, this signal will output  
the VSYNC signal extracted by the ISL98001’s sync slicer.  
Extracted VSYNC will be the width of the embedded VSYNC  
pulse plus pre- and post-equalization pulses (if present).  
Macrovision pulses from an NTSC DVD source will lengthen  
the width of the VSYNC pulse. Macrovision pulses from  
other sources (PAL DVD or videotape) may appear as a  
second VSYNC pulse encompassing the width of the  
Macrovision. See the Macrovision section for more  
information. VSYNC  
function) remains active in power-down mode. VSYNC  
is generally used for mode detection, start of field detection,  
and even/odd field detection.  
If a composite sync source (either CSYNC on HSYNC or  
SOG) is selected through bits 3 and 4 of register 0x05, the  
CSYNC Present bit in register 0x01 should be set. CSYNC  
Present detects the presence of a low frequency, repetitive  
signal inside HSYNC, which indicates a VSYNC signal. The  
CSYNC Present bit should be used to confirm that the signal  
being received is a reliable composite sync source.  
SYNC Output Signals  
The ISL98001 has 2 pairs of HSYNC and VSYNC output  
(including the sync separator  
OUT  
signals, HSYNC  
and VSYNC  
, and HS  
and  
OUT  
OUT  
OUT  
OUT  
VS  
.
OUT  
HSYNC  
and VSYNC  
are buffered versions of the  
OUT  
OUT  
incoming sync signals; no synchronization is done. These  
signals are used for mode detection  
HS  
OUT  
HS  
is generated by the ISL98001’s control logic and is  
OUT  
HS  
and VS  
are generated by the ISL98001’s logic  
OUT  
synchronized to the output DATACLK and the digital pixel  
data on the output databus. Its trailing edge is aligned with  
pixel 0. Its width, in units of pixels, is determined by register  
0x19, and its polarity is determined by register 0x18[7]. As  
the width is increased, the trailing edge stays aligned with  
pixel 0, while the leading edge is moved backwards in time  
OUT  
and are synchronized to the output DATACLK and the digital  
pixel data on the output databus. HS is used to signal  
OUT  
the start of a new line of digital data. VS  
most applications.  
is not needed in  
OUT  
Both HSYNC  
and VSYNC  
(including the sync  
OUT  
OUT  
relative to pixel 0. HS  
start of a new line of pixels.  
is used by the scaler to signal the  
OUT  
separator function) remain active in power-down mode. This  
allows them to be used in conjunction with the Sync Status  
registers to detect valid video without powering up the  
ISL98001.  
The HS Width register (0x19) controls the width of the  
OUT  
HS  
pulse. The pulse width is nominally 1 pixel clock  
OUT  
period times the value in this register. In the 48 bit output  
mode (register 0x18[0] = 1), or the YPbPr input mode  
(register 0x05[2] = 1), the HS  
pixel clock (1 DATACLK) increments (See Table 6).  
HSYNC  
OUT  
is an unmodified, buffered version of the incoming  
HSYNC  
OUT  
width is incremented in 2  
OUT  
HSYNC or SOG signal of the selected channel, with the  
IN  
IN  
incoming signal’s period, polarity, and width to aid in mode  
FN6148.0  
October 25, 2005  
24  
ISL98001  
22Ω. If the databus is heavily loaded (long traces, many other  
part on the same bus), this value may need to be reduced. If  
the databus is lightly loaded, it may be increased.  
TABLE 6. HS  
WIDTH  
OUT  
HS  
WIDTH (PIXEL CLOCKS)  
OUT  
REGISTER  
24-BIT MODE, 24-BIT MODE,  
ALL 48-BIT  
MODES  
Intersil’s recommendations to minimize EMI are:  
• Minimize the databus trace length  
0x19 VALUE  
RGB  
YPbPr  
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
1
1
3
3
5
5
7
7
0
0
2
2
4
4
6
6
• Minimize the databus capacitive loading.  
If EMI is a problem in the final design, increase the value of the  
digital output series resistors to reduce slew rates on the bus.  
This can only be done as long as the scaler’s setup and hold  
timing requirements continue to be met.  
Reducing Power Dissipation  
It is possible to reduce the total power consumption of the  
ISL98001 in applications where power is a concern. There are  
several techniques that can be used to reduce power  
consumption:  
VS  
OUT  
VS  
is generated by the ISL98001’s control logic and is  
OUT  
• Internal Digital Voltage Regulator. The ISL98001 features  
synchronized to the output DATACLK and the digital pixel  
data on the output databus. Its leading and trailing edges are  
aligned with pixel 7 (8 pixels after HSYNC trailing edge). Its  
width, in units of lines, is equal to the width of the incoming  
a 3.3V to 1.9V voltage regulator (pins VREG and  
IN  
VREG  
) for the low voltage digital supply. This regulator  
OUT  
typically sources 100mA at 1.9V, dissipating up to 140mW in  
heat. Providing an external, clean 1.8V supply to the V  
,
CORE  
VSYNC (See the VSYNC  
description). Its polarity is  
OUT  
V
, and V  
will substantially reduce power  
PLL  
COREADC  
determined by register 0x18[6]. This output is not needed in  
dissipation. The external 1.8V supply should ramp up after  
most applications. Intersil strongly discourages using this  
(or at the same time as) the digital 3.3V (V ) supply.  
D
signal - use VSYNC  
instead.  
OUT  
• Internal Analog Voltage Regulator. The ISL98001 also  
features a 3.3V to 1.9V voltage regulator for the low voltage  
Crystal Oscillator  
analog supply. This voltage appears on the V  
pins.  
BYPASS  
An external 22MHz to 27MHz crystal supplies the low-jitter  
reference clock to the DPLL. The absolute frequency of this  
crystal within this range is unimportant, as is the crystal’s  
temperature coefficient, allowing use of less expensive,  
lower-grade crystals.  
Unlike the digital low voltage supply, there are no “in” and  
“out” connections for this regulator. However, this internal  
regulator can only source voltage, and can be effectively  
bypassed by driving the V  
pins with an external, clean  
BYPASS  
2.0V supply. The external 2.0V supply should ramp up after  
(or at the same time as) the analog 3.3V (V ) supply.  
A
As an alternative to a crystal, the XTAL pin can be driven  
IN  
• Buffering Digital Outputs. Switching 24 or 48 data output  
pins into a capacitive bus can consume significant current.  
The higher the capacitance on the external databus, the  
higher the switching current. To minimize current  
consumption inside the ISL98001, minimize bus capacitance  
and/or insert data buffers such as the SN64AVC16827  
between the ISL98001’s data outputs and the external  
databus.  
with a 3.3V CMOS-level external clock source at any  
frequency between 22MHz and 33.5MHz. The ISL98001’s  
jitter specification assumes a low-jitter crystal source. If the  
external clock source has increased jitter, the sample clock  
generated by the DPLL may exhibit increased jitter as well.  
EMI Considerations  
There are two possible sources of EMI on the ISL98001:  
• Internal Reference Frequency. The crystal frequency is  
multiplied by the value in register 0x2B to generate an  
internal high frequency reference clock. This internal  
frequency should be set to 400MHz ±10% for minimum  
power consumption. For example, for a 33MHz frequency at  
Crystal oscillator. The EMI from the crystal oscillator is  
negligible. This is due to an amplitude-regulated, low voltage  
sine wave oscillator circuit, instead of the typical high-gain  
square wave inverter-type oscillator, so there are no harmonics.  
The crystal oscillator is not a significant source of EMI.  
XTAL , register 0x2B should be set to a value of 0x0C to  
IN  
minimize power.  
Digital output switching. This is the largest potential source of  
EMI. However, the EMI is determined by the PCB layout and  
the loading on the databus. The way to control this is to put  
series resistors on the output of all the digital pins (as our demo  
board and reference circuits show). These resistors should be  
as large as possible, while still meeting the setup and hold  
timing requirements of the scaler. We recommend starting with  
Standby Mode  
The ISL98001 can be placed into a low power standby mode  
by writing a 0x0F to register 0x1B, powering down the triple  
ADCs, the DPLL, and most of the internal clocks.  
FN6148.0  
25  
October 25, 2005  
ISL98001  
To allow input monitoring and mode detection during power-  
The ISL98001 has a 7-bit address on the serial bus. The  
upper 6-bits are permanently set to 100110, with the lower  
bit determined by the state of pin 48. This allows two  
ISL98001s to be independently controlled while sharing the  
same bus.  
down, the following blocks remain active:  
• Serial interface (including the crystal oscillator) to enable  
register read/write activity  
• Activity and polarity detect functions (registers 0x01 and  
0x02)  
The bus is nominally inactive, with SDA and SCL high.  
Communication begins when the host issues a START  
command by taking SDA low while SCL is high (Figure 9).  
The ISL98001 continuously monitors the SDA and SCL lines  
for the start condition and will not respond to any command  
until this condition has been met. The host then transmits the  
7-bit serial address plus a R/W bit, indicating if the next  
transaction will be a Read (R/W = 1) or a Write (R/W = 0). If  
the address transmitted matches that of any device on the  
bus, that device must respond with an ACKNOWLEDGE  
(Figure 10).  
• The HSYNC  
detection)  
and VSYNC  
pins (for mode  
OUT  
OUT  
Initialization  
The ISL98001 initializes with default register settings for an  
AC-coupled, RGB input on the VGA1 channel, with a 24-bit  
output.  
Reset  
The ISL98001 has a Power On Reset (POR) function that  
resets the chip to its default state when power is initially  
applied, including resetting all the registers to their default  
settings as described in the Register Listing. The external  
RESET pin duplicates the reset function of the POR without  
having to cycle the power supplies. The RESET pin does not  
need to be used in normal operation and can be tied high.  
Once the serial address has been transmitted and  
acknowledged, one or more bytes of information can be  
written to or read from the slave. Communication with the  
selected device in the selected direction (read or write) is  
ended by a STOP command, where SDA rises while SCL is  
high (Figure 9), or a second START command, which is  
commonly used to reverse data direction without  
relinquishing the bus.  
ISL98001 Serial Communication  
Overview  
The ISL98001 uses a 2-wire serial bus for communication  
with its host. SCL is the Serial Clock line, driven by the host,  
and SDA is the Serial Data line, which can be driven by all  
devices on the bus. SDA is open drain to allow multiple  
devices to share the same bus simultaneously.  
Data on the serial bus must be valid for the entire time SCL  
is high (Figure 11). To achieve this, data being written to the  
ISL98001 is latched on a delayed version of the rising edge  
of SCL. SCL is delayed and deglitched inside the ISL98001  
for three crystal clock periods (120ns for a 25MHz crystal) to  
eliminate spurious clock pulses that could disrupt serial  
communication.  
Communication is accomplished in three steps:  
When the contents of the ISL98001 are being read, the SDA  
line is updated after the falling edge of SCL, delayed and  
deglitched in the same manner.  
1) The Host selects the ISL98001 it wishes to communicate  
with.  
2) The Host writes the initial ISL98001 Configuration  
Register address it wishes to write to or read from.  
Configuration Register Write  
Figure 12 shows two views of the steps necessary to write  
one or more words to the Configuration Register.  
3) The Host writes to or reads from the ISL98001’s  
Configuration Register. The ISL98001’s internal address  
pointer auto increments, so to read registers 0x00 through  
0x1B, for example, one would write 0x00 in step 2, then  
repeat step three 28 times, with each read returning the  
next register value.  
Configuration Register Read  
Figure 13 shows two views of the steps necessary to read  
one or more words from the Configuration Register.  
SCL  
SDA  
Start  
Stop  
FIGURE 9. VALID START AND STOP CONDITIONS  
FN6148.0  
26  
October 25, 2005  
ISL98001  
SCL from  
Host  
1
8
9
Data Output  
from Transmitter  
Data Output  
from Receiver  
Start  
Acknowledge  
FIGURE 10. ACKNOWLEDGE RESPONSE FROM RECEIVER  
SCL  
SDA  
Data Change  
FIGURE 11. VALID DATA CHANGES ON THE SDA BUS  
Data Stable  
Data Stable  
Signals the beginning of serial I/O  
ISL98001 Serial Bus Address Write  
START Command  
ISL98001 Serial Bus  
R/W  
This is the 7-bit address of the ISL98001 on the 2-wire bus. The  
address is 0x4C if pin 48 is low, 0x4D if pin 48 is high. Shift this  
value left to when adding the R/W bit.  
A
0
0
1
1
0
0
1
(pin 48)  
ISL98001 Register Address Write  
This is the address of the ISL98001’s configuration register that  
the following byte will be written to.  
A7  
D7  
A6  
D6  
A5  
D5  
A4  
D4  
A3  
D3  
A2  
D2  
A1  
D1  
A0  
D0  
ISL98001 Register Data Write(s)  
This is the data to be written to the ISL98001’s configuration register.  
Note: The ISL98001’s Configuration Register’s address pointer auto  
increments after each data write: repeat this step to write multiple  
sequential bytes of data to the Configuration Register.  
(Repeat if desired)  
Signals the ending of serial I/O  
STOP Command  
S
T
A
R
T
S
T
Serial Bus  
Address  
Register  
Address  
Data  
Write*  
* The data write step may be repeated to write to the  
ISL98001’s Configuration Register sequentially, beginning at  
the Register Address written in the previous step.  
Signals from  
the Host  
O
P
1 0 0 1 1 0A0 a a a a a a a a d d d d d d d d  
SDA Bus  
Signals from  
the ISL98001  
A
C
K
A
C
K
A
C
K
FIGURE 12. CONFIGURATION REGISTER WRITE  
FN6148.0  
27  
October 25, 2005  
ISL98001  
Signals the beginning of serial I/O  
ISL98001 Serial Bus Address Write  
START Command  
ISL98001 Serial Bus  
R/W  
This is the 7-bit address of the ISL98001 on the 2-wire bus. The  
address is 0x4C if pin 48 is low, 0x4D if pin 48 is high. R/W = 0,  
indicating next transaction will be a write.  
A
0
1
1
0
0
0
1
(pin 48)  
ISL98001 Register Address Write  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
This sets the initial address of the ISL98001’s configuration  
register for subsequent reading.  
Ends the previous transaction and starts a new one  
START Command  
ISL98001 Serial Bus  
R/W  
ISL98001 Serial Bus Address Write  
This is the 7-bit address of the ISL98001 on the 2-wire bus. The  
address is 0x4C if pin 48 is low, 0x4D if pin 48 is high. R/W = 1,  
indicating next transaction(s) will be a read.  
A
1
1
1
0
0
0
1
(pin 48)  
ISL98001 Register Data Read(s)  
This is the data read from the ISL98001’s configuration register.  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
Note: The ISL98001’s Configuration Register’s address pointer  
auto increments after each data read: repeat this step to read  
multiple sequential bytes of data from the Configuration Register.  
(Repeat if desired)  
Signals the ending of serial I/O  
STOP Command  
R
E
S
S
T
A
R
T
S
T
A
R
T
Serial Bus  
Address  
Serial Bus  
Register  
Address  
Data  
Signals from  
the Host  
* The data read step may be repeated to read  
from the ISL98001’s Configuration Register  
sequentially, beginning at the Register  
Address written in the two steps previous.  
T
O
P
Address  
Read*  
A
C
K
1 0 0 1 1 0A0 a a a a a a a a  
1 0 0 1 1 0A1  
SDA Bus  
Signals from  
the ISL98001  
A
C
K
A
C
K
A
C
K
d d d d d d d d  
FIGURE 13. CONFIGURATION REGISTER READ  
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.  
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality  
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without  
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and  
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result  
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see www.intersil.com  
FN6148.0  
28  
October 25, 2005  
128-Lead Metric Quad Flat Pack (MQFP) Package  
All dimensions in mm.  

相关型号：

ISL98001CQZ-275

 Triple Video Digitizer with Digital PLL
INTERSIL

ISL98001IQZ-140

 Triple Video Digitizer with Digital PLL
INTERSIL

ISL98001_06

 Triple Video Digitizer with Digital PLL
INTERSIL

ISL98001_07

 Triple Video Digitizer with Digital PLL
INTERSIL

ISL98002

 Triple Video Digitizer with Digital PLL
INTERSIL

ISL98002CRZ-140

 Triple Video Digitizer with Digital PLL
INTERSIL

ISL98002CRZ-170

 Triple Video Digitizer with Digital PLL
INTERSIL

ISL98003

 8-Bit Video Analog Front End (AFE) with Measurement and Auto-Adjust Features
INTERSIL

ISL98003CNZ-110

 8-Bit Video Analog Front End (AFE) with Measurement and Auto-Adjust Features
INTERSIL

ISL98003CNZ-150

 8-Bit Video Analog Front End (AFE) with Measurement and Auto-Adjust Features
INTERSIL

ISL98003CNZ-165

 8-Bit Video Analog Front End (AFE) with Measurement and Auto-Adjust Features
INTERSIL

ISL98003CNZ-EVALZ

 8-Bit Video Analog Front End (AFE) with Measurement and Auto-Adjust Features
INTERSIL
©2020 ICPDF网 联系我们和版权申明