ISLA214P12 [INTERSIL]
High Performance 14-Bit, 125MSPS ADC; 高性能14位， 125MSPS ADC
| 型号： | ISLA214P12 |
| 厂家： | 
Intersil |
| 描述： | High Performance 14-Bit, 125MSPS ADC |
| 文件： | 总34页 (文件大小：963K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Performance 14-Bit, 125MSPS ADC
ISLA214P12
Features
The ISLA214P12 is a high performance 14-bit 125MSPS
analog-to-digital converter offering very high dynamic range
and low power consumption. It carries the export control
classification number 3A991.c.3 and can be exported
without a license to most countries, including China and
Russia. It is part of a pin-compatible family of 12- to 16-bit
A/Ds with maximum sample rates ranging from 125 to
500MSPS. This allows a design using the ISLA214P12 to
accommodate any of the other pin-compatible A/Ds with
minimal changes.
• License-free Import for most countries including China and
Russia (ECCN 3A991.c.3).
• Multi-ADC Support
- SPI Programmable Fine Gain and Offset Control
- Multiple ADC Synchronization
- Optimized Output Timing
• Clock Duty Cycle Stabilizer
• Nap and Sleep Modes
• Programmable Built-in Test Patterns
• SDR/DDR LVDS-Compatible or LVCMOS Outputs
• Data Output Clock
The ISLA214P12 is very flexible and can be designed into a wide
variety of systems. A serial peripheral interface (SPI) port allows
access to its extensive configurability as well as provides digital
control over various analog parameters such as input gain and
offset. Digital output data is presented in selectable LVDS or
CMOS formats and can be configured as full-width, single data
rate (SDR) or half-width, double data rate (DDR). Operating from a
1.8V supply, performance is specified over the full industrial
temperature range (-40°C to +85°C).
Key Specifications
• SNR @ 125MSPS
- 74.9dBFS f = 30MHz
IN
- 70.9dBFS fIN = 363MHz
• SFDR @ 125MSPS
Applications
• Radar Array Processing
- 88dBc f = 30MHz
IN
- 84dBc f = 363MHz
IN
• Software Defined Radio
• Total Power Consumption = 310mW
• Broadband Communications
• High Performance Data Acquisition
• Communications Test Equipment
-
-
-
Pin-Compatible Family
SPEED
(MSPS)
MODEL
RESOLUTION
ISLA216P25
ISLA216P20
ISLA216P13
ISLA214P50
ISLA214P25
ISLA214P20
ISLA214P13
ISLA212P50
ISLA212P25
ISLA212P20
ISLA212P13
16
16
16
14
14
14
14
12
12
12
12
250
200
130
500
250
200
130
500
250
200
130
CLKP
CLKN
CLKOUTP
CLKOUTN
CLOCK
MANAGEMENT
VINP
VINN
14-BIT
125 MSPS
ADC
SHA
D[13:0]P
D[13:0]N
DIGITAL
ERROR
CORRECTION
+
–
VCM
SPI
CONTROL
June 27, 2012
FN7982.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2012. All Rights Reserved
Intersil (and design) and FemtoCharge are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
ISLA214P12
Pin Configuration - LVDS MODE
ISLA214P12
(72 LD QFN)
TOP VIEW
72 71 70 69 68 67 66 65 64 63
62 61 60 59 58 57 56 55
DNC
DNC
1
2
54 D3P
D3N
53
52
51
50
49
48
47
46
45
44
43
42
41
3
NAPSLP
VCM
D4P
4
D4N
5
AVSS
AVDD
AVSS
VINN
D5P
6
D5N
7
CLKOUTP
CLKOUTN
RLVDS
OVSS
D6P
8
9
VINN
10
11
12
13
14
VINP
VINP
AVSS
AVDD
AVSS
CLKDIV
DNC
D6N
D7P
D7N
15
16
17
40
D8P
39 D8N
38
Thermal Pad Not Drawn to Scale,
Consult Mechanical Drawing
for Physical Dimensions
DNC
D9P
37 D9N
Connect Thermal Pad to AVSS
RESETN 18
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
FN7982.2
June 27, 2012
2
ISLA214P12
Pin Descriptions - 72 Ld QFN, LVDS Mode
PIN NUMBER
LVDS PIN NAME
LVDS PIN FUNCTION
DDR MODE COMMENTS
1, 2, 16, 17
DNC
Do Not Connect
6, 13, 19, 20, 21, 70, 71,
72
AVDD
1.8V Analog Supply
5, 7, 12, 14
AVSS
OVDD
Analog Ground
1.8V Output Supply
Output Ground
27, 32, 62
26, 45, 61, 65
OVSS
3
4
NAPSLP
VCM
Tri-Level Power Control (Nap, Sleep modes)
Common Mode Output
8, 9
10, 11
15
VINN
Analog Input Negative
VINP
Analog Input Positive
CLKDIV
RESETN
CLKP, CLKN
Tri-Level Clock Divider Control
Power On Reset (Active Low)
Clock Input True, Complement
18
22, 23
24, 25
28
CLKDIVRSTP, CLKDIVRSTN Synchronous Clock Divider Reset True, Complement
D13N
D13P
D12N
D12P
D11N
D11P
D10N
D10P
D9N
LVDS Bit 13(MSB) Output Complement
LVDS Bit 13 (MSB) Output True
LVDS Bit 12 Output Complement
LVDS Bit 12 Output True
NC in DDR Mode
29
NC in DDR Mode
30
DDR Logical Bits 12, 13
DDR Logical Bits 12, 13
NC in DDR Mode
31
33
LVDS Bit 11 Output Complement
LVDS Bit 11 Output True
34
NC in DDR Mode
35
LVDS Bit 10 Output Complement
LVDS Bit 10 Output True
DDR Logical Bits 10, 11
DDR Logical Bits 10, 11
NC in DDR Mode
36
37
LVDS Bit 9 Output Complement
LVDS Bit 9 Output True
38
D9P
NC in DDR Mode
39
D8N
LVDS Bit 8 Output Complement
LVDS Bit 8 Output True
DDR Logical Bits 8, 9
DDR Logical Bits 8, 9
NC in DDR Mode
40
D8P
41
D7N
LVDS Bit 7 Output Complement
LVDS Bit 7 Output True
42
D7P
NC in DDR Mode
43
D6N
LVDS Bit 6 Output Complement
LVDS Bit 6 Output True
DDR Logical Bits 6, 7
DDR Logical Bits 6, 7
44
D6P
46
RLVDS
CLKOUTN, CLKOUTP
D5N
LVDS Bias Resistor (Connect to OVSS with 1% 10kΩ)
LVDS Clock Output Complement, True
LVDS Bit 5 Output Complement
LVDS Bit 5 Output True
47, 48
49
NC in DDR Mode
50
D5P
NC in DDR Mode
51
D4N
LVDS Bit 4 Output Complement
LVDS Bit 4 Output True
DDR Logical Bits 4, 5
DDR Logical Bits 4, 5
NC in DDR Mode
52
D4P
53
D3N
LVDS Bit 3 Output Complement
LVDS Bit 3 Output True
54
D3P
NC in DDR Mode
55
D2N
LVDS Bit 2 Output Complement
LVDS Bit 2 Output True
DDR Logical Bits 2, 3
DDR Logical Bits 2, 3
NC in DDR Mode
56
D2P
57
D1N
LVDS Bit 1 Output Complement
LVDS Bit 1 True
58
D1P
NC in DDR Mode
FN7982.2
June 27, 2012
3
ISLA214P12
Pin Descriptions - 72 Ld QFN, LVDS Mode (Continued)
PIN NUMBER
LVDS PIN NAME
LVDS PIN FUNCTION
LVDS Bit 0 (LSB) Output Complement
LVDS Bit 0 (LSB) Output True
LVDS Over Range Complement, True
SPI Serial Data Output
DDR MODE COMMENTS
DDR Logical Bits 0, 1
DDR Logical Bits 0, 1
DDR Over Range
59
D0N
60
D0P
63, 64
ORN, ORP
SDO
66
67
CSB
SPI Chip Select (active low)
SPI Clock
68
69
SCLK
SDIO
SPI Serial Data Input/Output
Analog Ground
Exposed Paddle
AVSS
Pin Configuration - CMOS MODE
ISLA214P12
(72 LD QFN)
TOP VIEW
72 71 70 69 68 67 66 65 64 63 62 61
60 59 58 57 56 55
DNC
DNC
1
2
54 D3
DNC
D4
53
52
51
50
49
48
47
46
45
44
43
42
3
NAPSLP
VCM
4
DNC
D5
5
AVSS
AVDD
AVSS
VINN
6
DNC
CLKOUT
DNC
RLVDS
OVSS
D6
7
8
9
VINN
10
11
12
13
VINP
VINP
AVSS
AVDD
AVSS
CLKDIV
DNC
DNC
D7
14
41
40
DNC
D8
15
16
17
39 DNC
38
Thermal Pad Not Drawn to Scale,
Consult Mechanical Drawing
for Physical Dimensions
DNC
D9
37 DNC
Connect Thermal Pad to AVSS
RESETN 18
19 20 21 22 23 24 25 26
27 28 29 30 31 32 33 34 35 36
FN7982.2
June 27, 2012
4
ISLA214P12
Pin Descriptions - 72 Ld QFN, CMOS Mode
PIN NUMBER
CMOS PIN NAME
CMOS PIN FUNCTION
DDR MODE COMMENTS
1, 2, 16, 17, 28, 30, 33,
35, 37, 39, 41, 43, 47,
49, 51, 53, 55, 57, 59, 63
DNC
Do Not Connect
6, 13, 19, 20, 21, 70, 71,
72
AVDD
1.8V Analog Supply
5, 7, 12, 14
AVSS
OVDD
Analog Ground
1.8V Output Supply
Output Ground
27, 32, 62
26, 45, 61, 65
OVSS
3
NAPSLP
VCM
Tri-Level Power Control (Nap, Sleep modes)
Common Mode Output
4
8, 9
VINN
Analog Input Negative
10, 11
VINP
Analog Input Positive
15
CLKDIV
RESETN
CLKP, CLKN
Tri-Level Clock Divider Control
Power On Reset (Active Low)
Clock Input True, Complement
18
22, 23
24, 25
CLKDIVRSTP, CLKDIVRSTN Synchronous Clock Divider Reset True, Complement
29
D13
D12
D11
D10
D9
CMOS Bit 13 (MSB) Output
CMOS Bit 12 Output
CMOS Bit 11 Output
CMOS Bit 10 Output
CMOS Bit 9 Output
NC in DDR Mode
31
DDR Logical Bits 12, 13
NC in DDR Mode
34
36
DDR Logical Bits 10, 11
NC in DDR Mode
38
40
D8
CMOS Bit 8 Output
DDR Logical Bits 8, 9
NC in DDR Mode
42
D7
CMOS Bit 7 Output
44
D6
CMOS Bit 6 Output
DDR Logical Bits 6, 7
46
RLVDS
CLKOUT
D5
LVDS Bias Resistor (connect to OVSS with 1% 10kΩ)
CMOS Clock Output
CMOS Bit 5 Output
48
50
NC in DDR Mode
52
D4
CMOS Bit 4 Output
DDR Logical Bits 4, 5
NC in DDR Mode
54
D3
CMOS Bit 3 Output
56
D2
CMOS Bit 2 Output
DDR Logical Bits 2, 3
NC in DDR Mode
58
D1
CMOS Bit 1 Output
60
D0
CMOS Bit 0 (LSB) Output
CMOS Over Range
DDR Logical Bits 0, 1
DDR Over Range
64
OR
66
SDO
CSB
SCLK
SDIO
AVSS
SPI Serial Data Output
SPI Chip Select (active low)
SPI Clock
67
68
69
SPI Serial Data Input/Output
Analog Ground
Exposed Paddle
FN7982.2
June 27, 2012
5
ISLA214P12
Ordering Information
PART NUMBER
(Notes 1,2)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISLA214P12IRZ
ISLA214IR72EV1Z
KMB-001LEVALZ
KMB-001CEVALZ
NOTES:
ISLA214P12 IRZ
-40°C to +85°C
72 Ld QFN
L72.10x10E
Evaluation Board - Supports 125/130/200/250Msps Grades
LVDS Motherboard (Interfaces with ISLA214IR72EV1Z operating in LVDS Output Mode)
CMOS Motherboard (Interfaces with ISLA214IR72EV1Z operating in CMOS Output Mode)
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate-e4
termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. For Moisture Sensitivity Level (MSL), please see device information page for ISLA214P12. For more information on MSL please see techbrief TB363.
FN7982.2
June 27, 2012
6
ISLA214P12
Table of Contents
Key Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin-Compatible Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin Descriptions - 72 Ld QFN, LVDS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Descriptions - 72 Ld QFN, CMOS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
Digital Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Switching Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Power-On Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
User Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Temperature Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Nap/Sleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Clock Divider Synchronous Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SPI Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Device Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Device Configuration/Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Global Device Configuration/Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SPI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Equivalent Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
A/D Evaluation Platform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Split Ground and Power Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Clock Input Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Exposed Paddle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Bypass and Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
LVDS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
LVCMOS Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Package Outline Drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
FN7982.2
June 27, 2012
7
ISLA214P12
Absolute Maximum Ratings
Thermal Information
AVDD to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V
OVDD to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V
AVSS to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
Analog Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Clock Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Logic Input to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Logic Inputs to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Latchup (Tested per JESD-78C;Class 2,Level A) . . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
72 Ld QFN (Notes 3, 4) . . . . . . . . . . . . . . . .
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
θ
(°C/W)
23
θ
(°C/W)
0.9
JA
JC
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
3. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
4. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
T
= -40°C to +85°C (Typical specifications at +25°C), A = -1dBFS, f
= 125Msps. Boldface limits apply over the operating temperature
A
IN
SAMPLE
range, -40°C to +85°C.
ISLA214P12
MIN
MAX
PARAMETER
DC SPECIFICATIONS (Note 6)
Analog Input
SYMBOL
CONDITIONS
(Note 5)
TYP
(Note 5)
UNITS
Full-Scale Analog Input Range
Input Resistance
V
Differential
Differential
Differential
Full Temp
1.95
-5.0
2.0
600
4.5
2.1
5.0
V
P-P
FS
R
Ω
IN
IN
Input Capacitance
C
pF
ppm/°C
mV
Full Scale Range Temp. Drift
Input Offset Voltage
A
74
VTC
V
-1.7
0.94
2.6
OS
CM
CM
Common-Mode Output Voltage
V
V
Common-Mode Input Current
(per pin)
I
µA/MSPS
Clock Inputs
Inputs Common Mode Voltage
CLKP,CLKN Input Swing (Note 7)
Power Requirements
0.9
1.8
V
V
1.8V Analog Supply Voltage
1.8V Digital Supply Voltage
1.8V Analog Supply Current
1.8V Digital Supply Current (Note 6)
Power Supply Rejection Ratio
Total Power Dissipation
Normal Mode
AVDD
OVDD
1.7
1.7
1.8
1.8
1.9
1.9
161
77
V
V
I
I
152
68.5
40
mA
mA
dB
AVDD
3mA LVDS (SDR)
OVDD
PSRR
30MHz, 30mV
signal on AVDD
P-P
P
CMOS (DDR)
CMOS (SDR)
310
313
369
360
397
mW
mW
mW
D
2mA LVDS (SDR)
3mA LVDS (DDR)
3mA LVDS (SDR)
428
mW
FN7982.2
June 27, 2012
8
ISLA214P12
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
T
= -40°C to +85°C (Typical specifications at +25°C), A = -1dBFS, f
= 125Msps. Boldface limits apply over the operating temperature
A
IN
SAMPLE
range, -40°C to +85°C. (Continued)
ISLA214P12
MIN
MAX
PARAMETER
Nap Mode
SYMBOL
CONDITIONS
(Note 5)
TYP
48.6
6
(Note 5)
UNITS
mW
mW
µs
P
53
10
D
D
Sleep Mode
P
CSB at logic high
Sample Clock Running
Nap/Sleep Mode Wakeup Time
AC SPECIFICATIONS
Differential Nonlinearity
Integral Nonlinearity
630
DNL
INL
f
f
= 105MHz
= 105MHz
±0.25
±2.5
LSB
LSB
IN
IN
Minimum Conversion Rate (Note 8)
Maximum Conversion Rate
f
MIN
40
MSPS
MSPS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
S
f
MAX
125
S
Signal-to-Noise Ratio
(Note 9)
SNR
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
= 30MHz
74.9
74.3
73.3
70.9
69.5
67.8
74.6
73.6
72.2
70.6
65.9
61.1
12.10
11.93
11.70
11.44
10.65
9.86
88
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
= 105MHz
= 190MHz
= 363MHz
= 461MHz
= 605MHz
= 30MHz
73.0
Signal-to-Noise and Distortion
(Note 9)
SINAD
ENOB
SFDR
= 105MHz
= 190MHz
= 363MHz
= 461MHz
= 605MHz
= 30MHz
70.8
11.47
70
Effective Number of Bits
(Note 9)
= 105MHz
= 190MHz
= 363MHz
= 461MHz
= 605MHz
= 30MHz
Bits
Bits
Bits
Bits
Bits
Spurious-Free Dynamic Range
(Note 9)
dBc
= 105MHz
= 190MHz
= 363MHz
= 461MHz
= 605MHz
83
dBc
78
dBc
84
dBc
68
dBc
61
dBc
FN7982.2
June 27, 2012
9
ISLA214P12
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
T
= -40°C to +85°C (Typical specifications at +25°C), A = -1dBFS, f
= 125Msps. Boldface limits apply over the operating temperature
A
IN
SAMPLE
range, -40°C to +85°C. (Continued)
ISLA214P12
MIN
MAX
PARAMETER
SYMBOL
CONDITIONS
(Note 5)
TYP
99
(Note 5)
UNITS
dBc
Spurious-Free Dynamic Range
Excluding H2, H3
SFDRX23
f
f
f
f
f
f
f
f
= 30MHz
IN
IN
IN
IN
IN
IN
IN
IN
= 105MHz
= 190MHz
= 363MHz
= 461MHz
= 605MHz
= 70MHz
95
dBc
91
dBc
95
dBc
94
dBc
87
dBc
Intermodulation Distortion
IMD
-85
-105
dBFS
dBFS
= 170MHz
-12
10
Word Error Rate
Full Power Bandwidth
NOTES:
WER
FPBW
700
MHz
5. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
6. Digital Supply Current is dependent upon the capacitive loading of the digital outputs. I
7. See “Clock Input” on page 20.
specifications apply for 10pF load on each digital output
OVDD
8. The DLL Range setting must be changed for low-speed operation.
9. Minimum specification guaranteed when calibrated at +85°C.
Digital Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C.
MIN
MAX
PARAMETER
SYMBOL
CONDITIONS
(Note 5)
TYP
(Note 5) UNITS
INPUTS (Note 10)
Input Current High (RESETN)
Input Current Low (RESETN)
Input Current High (SDIO)
Input Current Low (SDIO)
Input Current High (CSB)
Input Current Low (CSB)
Input Current High (CLKDIV)
Input Current Low (CLKDIV)
I
V
V
V
V
V
V
= 1.8V
= 0V
0
1
-12
4
10
-8
µA
µA
µA
µA
IH
IN
IN
IN
IN
IN
IN
I
-25
IL
I
= 1.8V
= 0V
12
IH
I
-600
40
-415
58
5
-300
75
IL
I
= 1.8V
= 0V
IH
I
10
IL
I
16
-34
25
-25
34
µA
µA
V
IH
I
-16
IL
Input Voltage High (SDIO, RESETN)
Input Voltage Low (SDIO, RESETN)
Input Capacitance
V
1.17
IH
V
0.63
V
IL
C
4
pF
DI
LVDS INPUTS (CLKDIVRSTP, CLKDIVRSTN)
Input Common Mode Range
V
825
250
1575
450
mV
mV
kΩ
kΩ
ICM
Input Differential Swing (peak to peak, single-ended)
CLKDIVRSTP Input Pull-down Resistance
CLKDIVRSTN Input Pull-up Resistance
V
ID
R
R
100
100
Ipd
Ipu
FN7982.2
June 27, 2012
10
ISLA214P12
Digital Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
MIN
(Note 5)
MAX
(Note 5) UNITS
PARAMETER
SYMBOL
CONDITIONS
TYP
LVDS OUTPUTS
Differential Output Voltage (Note 11)
Output Offset Voltage
Output Rise Time
Output Fall Time
V
3mA Mode
3mA Mode
612
1150
240
mV
T
P-P
V
1120
1200
mV
OS
t
ps
ps
R
t
240
F
CMOS OUTPUTS
Voltage Output High
Voltage Output Low
Output Rise Time
Output Fall Time
V
I
I
= -500µA
= 1mA
OVDD - 0.3 OVDD - 0.1
V
V
OH
OH
V
0.1
1.8
1.4
0.3
OL
OL
t
ns
ns
R
t
F
NOTES:
10. The Tri-Level Inputs internal switching thresholds are approximately. 0.43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD
depending on desired function.
11. The voltage is expressed in peak-to-peak differential swing. The peak-to-peak singled-ended swing is 1/2 of the differential swing.
Timing Diagrams
INP
INN
tA
CLKN
CLKP
LATENCY = L CYCLES
tCPD
CLKOUTN
CLKOUTP
tDC
tPD
D[12/10/8/6/4/2/0]N
ODD
N-L
EVEN
N-L
ODD
N-L+1
EVEN
N-L+1
EVEN
N-1
ODD
N
EVEN
N
D[12/10/8/6/4/2/0]P
FIGURE 1A. LVDS DDR
FN7982.2
June 27, 2012
11
ISLA214P12
Timing Diagrams(Continued)
INP
INN
tA
CLKN
CLKP
LATENCY = L CYCLES
tCPD
CLKOUTN
CLKOUTP
tDC
tPD
D[13:0]N
D[13:0]P
DATA
N-L
DATA
N-L+1
DATA
N
FIGURE 1B. LVDS SDR
FIGURE 1. LVDS TIMING DIAGRAMS
INP
INN
tA
CLKN
CLKP
LATENCY = L CYCLES
tCPD
CLKOUT
tDC
tPD
ODD
N-L
EVEN
N-L
ODD
N-L+1
EVEN
N-L+1
EVEN
N-1
ODD
N
EVEN
N
D[12/10/8/6/4/2/0]
FIGURE 2A. CMOS DDR
FN7982.2
June 27, 2012
12
ISLA214P12
Timing Diagrams(Continued)
INP
INN
tA
CLKN
CLKP
LATENCY = L CYCLES
tCPD
CLKOUT
tDC
tPD
DATA
N-L
DATA
N-L+1
DATA
N
D[13:0]
FIGURE 2B. CMOS SDR
FIGURE 2. CMOS TIMING DIAGRAMS
Switching Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C.
MIN
(Note 5)
MAX
(Note 5)
PARAMETER
SYMBOL
CONDITION
TYP
UNITS
ADC OUTPUT
Aperture Delay
t
114
75
ps
fs
A
RMS Aperture Jitter
j
A
Input Clock to Output Clock Propagation
Delay
t
t
AVDD, OVDD = 1.7V to 1.9V,
1.65
2.4
3
ns
CPD
T
= -40°C to +85°C
A
AVDD, OVDD = 1.8V, T = +25°C
A
1.9
2.3
2.75
450
ns
ps
CPD
Relative Input Clock to Output Clock
Propagation Delay (Note 12)
dt
AVDD, OVDD = 1.7V to 1.9V,
-450
CPD
T
= -40°C to +85°C
A
Input Clock to Data Propagation Delay
t
t
1.65
-0.1
2.4
3.5
0.5
ns
ns
PD
Output Clock to Data Propagation Delay,
LVDS Mode
Rising/Falling Edge
Rising/Falling Edge
0.16
DC
Output Clock to Data Propagation Delay,
CMOS Mode
t
-0.1
0.4
0.2
0.65
ns
ns
DC
Synchronous Clock Divider Reset Setup
Time (with respect to the positive edge of
CLKP)
t
0.06
RSTS
Synchronous Clock Divider Reset Hold Time
(with respect to the positive edge of CLKP)
t
0.02
30
0.35
ns
RSTH
Synchronous Clock Divider Reset Recovery
Time
t
DLL recovery time after
Synchronous Reset
cycles
RSTRT
(sample clock not interrupted)
Latency (Pipeline Delay)
Overvoltage Recovery
L
10
1
cycles
cycles
t
OVR
FN7982.2
June 27, 2012
13
ISLA214P12
Switching Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
MIN
MAX
PARAMETER
SPI INTERFACE (Notes 13, 14)
SCLK Period
SYMBOL
CONDITION
(Note 5)
TYP
(Note 5)
UNITS
t
Write Operation
16
16
28
5
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
CLK
t
Read Operation
Read or Write
Write
CLK
CSB↓ to SCLK↑ Setup Time
CSB↑ after SCLK↑ Hold Time
CSB↑ after SCLK↓ Hold Time
Data Valid to SCLK↑ Setup Time
Data Valid after SCLK↑ Hold Time
Data Valid after SCLK↓ Time
NOTES:
t
S
t
H
t
Read
16
6
HR
t
Write
DS
DH
t
Read or Write
Read
4
5
t
DVR
12. The relative propagation delay is the difference in propagation time between any two devices that are matched in temperature and voltage, and is
specified over the full operating temperature and voltage range.
13. SPI Interface timing is directly proportional to the ADC sample period (t ). Values above reflect multiples of a 4ns sample period, and must be scaled
S
proportionally for lower sample rates. ADC sample clock must be running for SPI communication.
14. The SPI may operate asynchronously with respect to the ADC sample clock.
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, T = +25°C, A = -1dBFS,
A
IN
f
= 105MHz, f
= 125MSPS.
IN
SAMPLE
90
-55
-60
-65
-70
SFDR @ 125MSPS
85
80
75
70
65
60
H2 @ 125MSPS
-75
-80
-85
SNR @ 125MSPS
-90
-95
H3 @ 125MSPS
-100
55
0
100
200
300
400
500
600
0
100
200
300
400
500
600
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
FIGURE 4. HD2 AND HD3 vs f
FIGURE 3. SNR AND SFDR vs f
IN
IN
100
90
-45
-55
HD3(dBc)
SFDR (dBFS)
80
-65
70
SNR (dBFS)
SFDR (dBc)
HD2 (dBc)
-75
60
50
40
30
20
10
-85
HD3 (dBFS)
-95
SNR (dBc)
-30
-105
HD2 (dBFS)
-115
-60
-50
-40
-20
-10
0
-60
-50
-40
-30
-20
-10
0
INPUT AMPLITUDE (dBFS)
INPUT AMPLITUDE (dBFS)
FIGURE 5. SNR AND SFDR vs A
FIGURE 6. HD2 AND HD3 vs A
IN
IN
FN7982.2
June 27, 2012
14
ISLA214P12
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, T = +25°C, A = -1dBFS,
A
IN
f
= 105MHz, f
= 125MSPS. (Continued)
IN
SAMPLE
90
-75
-80
85
80
75
H3
-85
SFDR
-90
-95
H2
-100
-105
SNR
70
40
40
50
60
70
80
90
100
110
120
60
80
100
120
SAMPLE RATE (MSPS)
SAMPLE RATE (MSPS)
FIGURE 8. HD2 AND HD3 vs f
FIGURE 7. SNR AND SFDR vs f
SAMPLE
SAMPLE
400
375
350
325
300
275
250
225
1.0
0.8
0.6
0.4
0.2
0
LVDS
-0.2
-0.4
-0.6
-0.8
-1.0
CMOS
200
40
60
80
100
120
0
2000 4000 6000 8000 10000 12000 14000 16000
CODES
SAMPLE RATE (MSPS)
IN 3mA LVDS MODE (SDR) AND
FIGURE 9. POWER vs f
FIGURE 10. DIFFERENTIAL NONLINEARITY
SAMPLE
CMOS MODE (DDR)
4
3
95
90
85
80
75
70
65
60
SFDR A = -2dBFS
IN
2
1
SFDR A = -1dBFS
IN
0
-1
-2
-3
-4
SNR A = -1dBFS
IN
0.75
0.85
0.95
1.05
1.15
0
2000 4000 6000 8000 10000 12000 14000 16000
CODES
INPUT COMMON MODE (V)
FIGURE 11. INTEGRAL NONLINEARITY
FIGURE 12. SNR AND SFDR vs VCM
FN7982.2
June 27, 2012
15
ISLA214P12
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, T = +25°C, A = -1dBFS,
A
IN
f
= 105MHz, f
= 125MSPS. (Continued)
IN
SAMPLE
0
-20
80000
70000
75501
71821
STDEV = 0.95 CODES
A
= -1.0 dBFS
IN
SNR = 74.7 dBFS
SFDR = 84.5 dBc
SINAD = 74.1 dBFS
60000
50000
40000
30000
-40
-60
24535
22204
-80
20000
10000
-100
-120
2939
2775
118
0
106
1
0
0
8169 8170 8171 8172 8173 8174 8175 8176 8177 8178 8179
CODE
0
10
20
30
40
50
60
FREQUENCY (MHz)
FIGURE 13. NOISE HISTOGRAM
FIGURE 14. SINGLE-TONE SPECTRUM @ 105MHz
0
0
A
= -1.0 dBFS
A
= -1.0 dBFS
IN
IN
SNR = 73.5 dBFS
SFDR = 82.2 dBc
SINAD = 72.9 dBFS
SNR = 70.3 dBFS
SFDR = 81.0 dBc
SINAD = 69.9 dBFS
-20
-40
-20
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
10
20
30
40
50
60
0
10
20
30
40
50
60
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 16. SINGLE-TONE SPECTRUM @ 363MHz
FIGURE 15. SINGLE-TONE SPECTRUM @ 190MHz
0
0
IMD2
IMD3
2ND HARMONICS
3RD HARMONICS
IMD2
-20
-40
-20
IMD3
2ND HARMONICS
3RD HARMONICS
-40
-60
-60
IMD3 = -85 dBFS
IMD3 = -105 dBFS
-80
-80
-100
-120
-100
-120
0
10
20
30
40
50
60
0
10
20
30
40
50
60
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 17. TWO-TONE SPECTRUM (F1 = 70MHz, F2 = 71MHz AT
-7dBFS)
FIGURE 18. TWO-TONE SPECTRUM (F1 = 170MHz, F2 = 171MHz AT
-7dBFS)
FN7982.2
June 27, 2012
16
ISLA214P12
A user-initiated reset can subsequently be invoked in the event
that the above conditions cannot be met at power-up.
Theory of Operation
Functional Description
The ISLA214P12 is based on a 14-bit, 125MSPS A/D converter
core that utilizes a pipelined successive approximation
After the power supply has stabilized the internal POR releases
RESETN and an internal pull-up pulls it high, which starts the
calibration sequence. If a subsequent user-initiated reset is
desired, the RESETN pin should be connected to an open-drain
driver with an off-state/high impedance state leakage of less
than 0.5mA to assure exit from the reset state so calibration can
start.
architecture (see Figure 19). The input voltage is captured by a
Sample-Hold Amplifier (SHA) and converted to a unit of charge.
Proprietary charge-domain techniques are used to successively
compare the input to a series of reference charges. Decisions
made during the successive approximation operations determine
the digital code for each input value. Digital error correction is also
applied, resulting in a total latency of 10 clock cycles. This is
evident to the user as a latency between the start of a conversion
and the data being available on the digital outputs.
The calibration sequence is initiated on the rising edge of
RESETN, as shown in Figure 20. Calibration status can be
determined by reading the cal_status bit (LSB) at 0xB6. This bit is
‘0’ during calibration and goes to a logic ‘1’ when calibration is
complete. The data outputs produce 0xCCCC during calibration;
this can also be used to determine calibration status.
Power-On Calibration
While RESETN is low, the output clock (CLKOUTP/CLKOUTN) is
set low. Normal operation of the output clock resumes at the
next input clock edge (CLKP/CLKN) after RESETN is de-asserted.
At 125MSPS the nominal calibration time is 560ms, while the
maximum calibration time is 1000ms.
As mentioned previously, the cores perform a self-calibration at
start-up. An internal power-on-reset (POR) circuit detects the
supply voltage ramps and initiates the calibration when the
analog and digital supply voltages are above a threshold. The
following conditions must be adhered to for the power-on
calibration to execute successfully.
• A frequency-stable conversion clock must be applied to the
CLKP/CLKN pins
• DNC pins must not be connected
• SDO has an internal pull-up and should not be driven externally
• RESETN is pulled low by the ADC internally during POR.
External driving of RESETN is optional.
• SPI communications must not be attempted
CLOCK
GENERATION
INP
2.5-BIT
2.5-BIT
6- STAGE
1.5-BIT/ STAGE
3- STAGE
1-BIT/ STAGE
3-BIT
FLASH
SHA
FLASH
FLASH
INN
+
1.25V
–
DIGITAL
ERROR
CORRECTION
LVDS/ LVCMOS
OUTPUTS
FIGURE 19. A/D CORE BLOCK DIAGRAM
FN7982.2
June 27, 2012
17
ISLA214P12
The performance of the ISLA214P12 changes with variations in
CLKN
CLKP
temperature, supply voltage or sample rate. The extent of these
changes may necessitate recalibration, depending on system
performance requirements. Best performance will be achieved
by recalibrating the A/D under the environmental conditions at
which it will operate.
CALIBRATION
TIME
RESETN
CALIBRATION
BEGINS
A supply voltage variation of <100mV will generally result in an
SNR change of <0.5dBFS and SFDR change of <3dBc.
CAL_STATUS
BIT
CALIBRATION
COMPLETE
In situations where the sample rate is not constant, best results
will be obtained if the device is calibrated at the highest sample
rate. Reducing the sample rate by less than 80MSPS will typically
result in an SNR change of <0.5dBFS and an SFDR change of
<3dBc.
CLKOUTP
FIGURE 20. CALIBRATION TIMING
Figures 21 through 26 show the effect of temperature on SNR
and SFDR performance with power on calibration performed at
-40°C, +25°C, and +85°C. Each plot shows the variation of
SNR/SFDR across temperature after a single power on
calibration at -40°C, +25°C and +85°C. Best performance is
typically achieved by a user-initiated power on calibration at the
operating conditions, as stated earlier. However, it can be seen
that performance drift with temperature is not a very strong
function of the temperature at which the power on calibration is
performed.
User Initiated Reset
Recalibration of the A/D can be initiated at any time by driving
the RESETN pin low for a minimum of one clock cycle. An
open-drain driver with a drive strength in its high impedance
state of less than 0.5mA is recommended, as RESETN has an
internal high impedance pull-up to OVDD. As is the case during
power-on reset, RESETN and DNC pins must be in the proper
state for the calibration to successfully execute.
Temperature Calibration
75.50
95
90
85
75.25
75.00
74.75
74.50
-2dBFS ANALOG INPUT
-1dBFS ANALOG INPUT
74.25
74.00
-2dBFS ANALOG INPUT
-1dBFS ANALOG INPUT
80
-40
-40
-35
-30
-25
-20
-35
-30
-25
-20
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 22. TYPICAL SFDR PERFORMANCE vs TEMPERATURE,
FIGURE 21. TYPICAL SNR PERFORMANCE vs TEMPERATURE,
DEVICE CALIBRATED AT -40°C, f = 105MHz
DEVICE CALIBRATED AT -40°C, f = 105MHz
IN
IN
75.50
75.25
75.00
74.75
74.50
95
90
85
74.25
-2dBFS ANALOG INPUT
-2dBFS ANALOG INPUT
-1dBFS ANALOG INPUT
-1dBFS ANALOG INPUT
74.00
80
5
10
15
20
25
30
35
40
45
5
10
15
20
25
30
35
40
45
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 23. TYPICAL SNR PERFORMANCE vs TEMPERATURE,
FIGURE 24. TYPICAL SFDR PERFORMANCE vs TEMPERATURE,
DEVICE CALIBRATED AT +25°C, f = 105MHz
DEVICE CALIBRATED AT +25°C, f = 105MHz
IN
IN
FN7982.2
June 27, 2012
18
ISLA214P12
Temperature Calibration(Continued)
75.50
75.25
75.00
74.75
74.50
74.25
74.00
95
90
85
80
-2dBFS ANALOG INPUT
-1dBFS ANALOG INPUT
-2dBFS ANALOG INPUT
-1dBFS ANALOG INPUT
65
70
75
80
85
65
70
75
80
85
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 26. TYPICAL SFDR PERFORMANCE vs TEMPERATURE,
DEVICE CALIBRATED AT +85°C, f = 105MHz
FIGURE 25. TYPICAL SNR PERFORMANCE vs TEMPERATURE,
DEVICE CALIBRATED AT +85°C, f = 105MHz
IN
IN
FN7982.2
June 27, 2012
19
ISLA214P12
transformer and low shunt resistance are recommended for
optimal performance.
Analog Input
A single fully differential input (VINP/VINN) connects to the
sample and hold amplifier (SHA) of each unit A/D. The ideal
full-scale input voltage is 2.0V, centered at the VCM voltage of
0.94V as shown in Figure 27.
A/D
1.8
1.4
1.0
0.6
0.2
VINN
VINP
VCM
0.94V
1.0V
FIGURE 30. DIFFERENTIAL AMPLIFIER INPUT
A differential amplifier, as shown in the simplified block diagram
in Figure 30, can be used in applications that require
DC-coupling. In this configuration, the amplifier will typically
dominate the achievable SNR and distortion performance.
Intersil’s new ISL552xx differential amplifier family can also be
used in certain AC applications with minimal performance
degradation. Contact the factory for more information.
FIGURE 27. ANALOG INPUT RANGE
Best performance is obtained when the analog inputs are driven
differentially. The common-mode output voltage, VCM, should be
used to properly bias the inputs as shown in Figures 28 through
30. An RF transformer will give the best noise and distortion
performance for wideband and/or high intermediate frequency
(IF) inputs. Two different transformer input schemes are shown in
Figures 28 and 29.
Clock Input
The clock input circuit is a differential pair (see Figure 44).
Driving these inputs with a high level (up to 1.8V
on each
P-P
input) sine or square wave will provide the lowest jitter
performance. A transformer with 4:1 impedance ratio will
provide increased drive levels. The clock input is functional with
AC-coupled LVDS, LVPECL, and CML drive levels. To maintain the
lowest possible aperture jitter, it is recommended to have high
slew rate at the zero crossing of the differential clock input
signal.
ADT1-1WT
ADT1-1WT
1000pF
A/D
VCM
0.1µF
The recommended drive circuit is shown in Figure 31. A duty
range of 40% to 60% is acceptable. The clock can be driven
single-ended, but this will reduce the edge rate and may impact
SNR performance. The clock inputs are internally self-biased to
AVDD/2 to facilitate AC coupling.
FIGURE 28. TRANSFORMER INPUT FOR GENERAL PURPOSE
APPLICATIONS
TX-2-5-1
ADTL1-12
1000pF
TC4-19G2+
CLKP
200
1000pF
A / D
VCM
0.01µF
1000pF
FIGURE 29. TRANSMISSION-LINE TRANSFORMER INPUT FOR
HIGH IF APPLICATIONS
CLKN
1000pF
1000pF
This dual transformer scheme is used to improve common-mode
rejection, which keeps the common-mode level of the input
matched to VCM. The value of the shunt resistor should be
determined based on the desired load impedance. The
differential input resistance of the ISLA214P12 is 600Ω.
FIGURE 31. RECOMMENDED CLOCK DRIVE
A selectable 2x or 4x frequency divider is provided in series with
the clock input. The divider can be used in the 2x mode with a
sample clock equal to twice the desired sample rate or in 4x
mode with a sample clock equal to four times the desired
sample rate. This allows the use of the Phase Slip feature, which
enables synchronization of multiple ADCs. The Phase Slip feature
can be used as an alternative to using the CLKDIVRST pins to
synchronize ADCs in a multiple ADC system.
The SHA design uses a switched capacitor input stage (see
Figure 43), which creates current spikes when the sampling
capacitance is reconnected to the input voltage. This causes a
disturbance at the input which must settle before the next
sampling point. Lower source impedance will result in faster
settling and improved performance. Therefore a 2:1 or 1:1
FN7982.2
June 27, 2012
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ISLA214P12
TABLE 1. CLKDIV PIN SETTINGS
Digital Outputs
Output data is available as a parallel bus in
CLKDIV PIN
DIVIDE RATIO
LVDS-compatible(default) or CMOS modes. In either case, the data
is presented in either double data rate (DDR) or single data rate
(default) format. Figures 1A and 1B show the timing relationships
for LVDS and CMOS modes, respectively.
AVSS
Float
AVDD
2
1
4
Additionally, the drive current for LVDS mode can be set to a
nominal 3mA(default) or a power-saving 2mA. The lower current
setting can be used in designs where the receiver is in close
physical proximity to the A/D. The applicability of this setting is
dependent upon the PCB layout, therefore the user should
experiment to determine if performance degradation is
observed. Note that a far-end termination resistor is required in
LVDS mode for correct operation.
The clock divider can also be controlled through the SPI port,
which overrides the CLKDIV pin setting. See “SPI Physical
Interface” on page 25. A delay-locked loop (DLL) generates
internal clock signals for various stages within the charge
pipeline. If the frequency of the input clock changes, the DLL may
take up to 100μs to regain lock at 125MSPS. The lock time is
inversely proportional to the sample rate.
The DLL has two ranges of operation, slow and fast. The slow
range can be used for sample rates between 40MSPS and
100MSPS, while the default fast range can be used from
80MSPS to the maximum specified sample rate.
The output mode can be controlled through the SPI port, by
writing to address 0x73, see “Serial Peripheral Interface” on
page 25.
An external resistor creates the bias for the LVDS drivers. A 10kΩ,
1% resistor must be connected from the RLVDS pin to OVSS.
Jitter
In a sampled data system, clock jitter directly impacts the
achievable SNR performance. The theoretical relationship
Over-Range Indicator
The over-range (OR) bit is asserted when the magnitude of the
analog input exceeds positive or negative fullscale of the ADC.
The output code does not wrap around during an over-range
condition. The OR bit is updated at the sample rate.
between clock jitter (t ) and SNR is shown in Equation 1 and is
J
illustrated in Figure 32.
1
⎛
⎝
⎞
⎠
-------------------
SNR = 20 log
(EQ. 1)
10
2πf
t
IN J
Power Dissipation
100
95
90
85
80
75
70
65
60
55
The power dissipated by the ISLA214P12 is primarily dependent
on the sample rate and the output modes: LVDS vs CMOS and
DDR vs SDR. There is a static bias in the analog supply, while the
remaining power dissipation is linearly related to the sample
rate. The output supply dissipation changes to a lesser degree in
LVDS mode, but is more strongly related to the clock frequency in
CMOS mode.
tj = 0.1ps
14 BITS
tj = 1ps
12 BITS
tj = 10ps
10 BITS
Nap/Sleep
tj = 100ps
Portions of the device may be shut down to save power during
times when operation of the A/D is not required. Two power saving
modes are available: Nap, and Sleep. Nap mode reduces power
dissipation to < 60mW while Sleep mode reduces power
dissipation to 9mW typically.
50
1M
10M
INPUT FREQUENCY (Hz)
FIGURE 32. SNR vs CLOCK JITTER
100M
1G
This relationship shows the SNR that would be achieved if clock
jitter were the only non-ideal factor. In reality, achievable SNR is
limited by internal factors such as linearity, aperture jitter and
thermal noise. Internal aperture jitter is the uncertainty in the
sampling instant shown in Figure1A. The internal aperture jitter
combines with the input clock jitter in a root-sum-square fashion,
since they are not statistically correlated, and this determines
the total jitter in the system. The total jitter, combined with other
noise sources, then determines the achievable SNR.
All digital outputs (Data, CLKOUT and OR) are placed in a high
impedance state during Nap or Sleep. The input clock should
remain running and at a fixed frequency during Nap or Sleep, and
CSB should be high. Recovery time from Nap mode will increase
if the clock is stopped, since the internal DLL can take up to
100µs to regain lock at 125MSPS.
By default after the device is powered on, the operational state is
controlled by the NAPSLP pin as shown in Table 2.
TABLE 2. NAPSLP PIN SETTINGS
Voltage Reference
NAPSLP PIN
AVSS
MODE
Normal
Sleep
Nap
A temperature compensated internal voltage reference provides
the reference charges used in the successive approximation
operations. The full-scale range of each A/D is proportional to the
reference voltage. The nominal value of the voltage reference is
1.25V.
Float
AVDD
FN7982.2
June 27, 2012
21
ISLA214P12
The power-down mode can also be controlled through the SPI
port, which overrides the NAPSLP pin setting. Details on this are
contained in “Serial Peripheral Interface” on page 25.
Mapping of the input voltage to the various data formats is
shown in Table 3.
TABLE 3. INPUT VOLTAGE TO OUTPUT CODE MAPPING
Data Format
INPUT
VOLTAGE
TWO’S
COMPLEMENT
OFFSET BINARY
GRAY CODE
Output data can be presented in three formats: two’s
complement (default), Gray code and offset binary. The data
format can be controlled through the SPI port, by writing to
address 0x73. Details on this are contained in “Serial Peripheral
Interface” on page 25.
–Full Scale 00 0000 0000 0000 10 0000 0000 0000 00 0000 0000 0000
–Full Scale 00 0000 0000 0001 10 0000 0000 0001 00 0000 0000 0001
+ 1LSB
Mid–Scale 10 0000 0000 0000 00 0000 0000 0000 11 0000 0000 0000
Offset binary coding maps the most negative input voltage to
code 0x000 (all zeros) and the most positive input to 0xFFF (all
ones). Two’s complement coding simply complements the MSB
of the offset binary representation.
+Full Scale 11 1111 1111 1110 01 1111 1111 1110 10 0000 0000 0001
– 1LSB
+Full Scale 11 1111 1111 1111 01 1111 1111 1111 10 0000 0000 0000
When calculating Gray code the MSB is unchanged. The
remaining bits are computed as the XOR of the current bit
position and the next most significant bit. Figure 33 shows this
operation.
Clock Divider Synchronous Reset
An output clock (CLKOUTP, CLKOUTN) is provided to facilitate
latching of the sampled data. The output clock frequency is
equal to the input clock frequency divided by the internal clock
divider setting. (See clock input description).
BINARY
13
12
11
1
0
• • • •
For clock divide settings > ‘1’, the absolute phase of the output
clocks for multiple A/Ds is indeterminate - there will be a phase
ambiguity between the output clocks of ADCs in a multiple ADC
system. The CLKDIVRST feature allows the phase of multiple
A/Ds to be synchronized (see Figure35) when the internal clock
divider is used, greatly simplifying data capture in systems
employing multiple A/Ds. For clock divide setting=’1’, there is no
phase ambiguity between clock outputs in a multiple ADC
system and CLKDIVRST can be left as a DNC (do not connect)
• • • •
• • • •
GRAY CODE
13
12
11
1
0
FIGURE 33. BINARY TO GRAY CODE CONVERSION
The CLKDIVRST signal must be well-timed with respect to the
sample clock (See “Switching Specifications” on page 13). Figure
35 shows assertion of CLKDIVRSTP by a positive edge
(CLKDIVRSTN must be driven but is not shown); CLKDIVRSTP can
remain high indefinitely after a synchronization event.
CLKDIVRSTP can also be a pulse if needed, with CLKDIVRSTP
returning to a logic ‘0’ after assertion; in this case the CLKDIVRST
pulse width should be a minimum of 3 input sample clock
periods. In applications where multiple CLKDIVRST pulse events
are required a user should wait a minimum of 30 clock cycles
before starting a second CLKDIVRST pulse event.
Converting back to offset binary from Gray code must be done
recursively, using the result of each bit for the next lower bit as
shown in Figure 34.
GRAY CODE
13
12
11
1
0
• • • •
• • • •
• • • •
• • • •
It will take a maximum of 30 input clock cycles to attain
synchronization (t
) in applications where the input clock is
RSTRT
not interrupted; if the input clock is interrupted CLKOUT will be
static or indeterminate until synchronization is attained.
In some applications, interrupting the input sample clock briefly
(~ 150 cycles max) can simplify the timing requirements for
synchronization using CLKDIVRST), in this case the total
CLKDIVRST recovery time will increase by the number of input
clock cycles the sample clock is held static. Valid data is
available (after recovery) in all cases after the normal pipeline
latency. Assertion of CLKDIVRST resets
BINARY
13
12
11
1
0
Intersil Application Note 1604 describes the synchronization of
multiple ISLA1xxP50s. This document discusses the topic of
synchronization in more detail and can be used to better
understand the ISLA2XXPxx ADCs’ operation.
FIGURE 34. GRAY CODE TO BINARY CONVERSION
FN7982.2
June 27, 2012
22
ISLA214P12
SAMPLE CLOCK
INPUT
(CLKDIV=2)
s1
L+td
ANALOG INPUT
(Note 15)
tRSTH
(Note 16)
CLKDIVRSTP
tRSTS
tRSTRT
ADC1 OUTPUT DATA
s0
s0
s1
s1
s2
s2
s3
s3
ADC1 CLKOUTP
ADC2 OUTPUT DATA
(Note 16)
ADC2 CLKOUTP
(phase 1)
(Note 17)
ADC2 CLKOUTP
(phase 2)
NOTES:
15. Delay equals fixed pipeline latency (L cycles) plus fixed analog propagation delay td.
16. CLKDIVRSTP setup and hold times are with respect to input sample clock rising edge.
CLKDIVRSTN is not shown, but must be driven, and is the compliment of CLKDIVRSTP.
17. Either Output Clock Phase (phase 1 or phase 2 ) equally likely prior to synchronization.
FIGURE 35. SYNCHRONOUS RESET OPERATION
CSB
SCLK
SDIO
R/W
W1
W0
A12
A11
A10
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
FIGURE 36. MSB-FIRST ADDRESSING
CSB
SCLK
SDIO
A0
A1
A2
A11
A12
W0
W1
R/W
D0
D1
D2
D3
D4
D5
D6
D7
FIGURE 37. LSB-FIRST ADDRESSING
FN7982.2
June 27, 2012
23
ISLA214P12
t
DSW
t
t
t
CLK
HI
H
t
DHW
CSB
t
t
S
LO
SCLK
SDIO
R/W W1 W0 A12 A11 A10 A9
A8
A7
D0
D5
D4
D3
D2
D1
SPI WRITE
FIGURE 38. SPI WRITE
tDSW
tCLK
tHR
tHI
tDVR
tS
CSB
tDHW
tLO
SCLK
WRITING A READ COMMAND
A9 A2 A1
READING DATA
)
( 3 WIRE MODE
D2 D1 D0
SDIO
SDO
A0
D7
D6
D3
W1 W 0
A12 A11
A10
R/W
( 4 WIRE MODE)
D3 D2 D1
D7
D0
SPI READ
FIGURE 39. SPI READ
CSB STALLING
CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD 2
FIGURE 40. 2-BYTE TRANSFER
LAST LEGAL
CSB STALLING
CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD N
FIGURE 41. N-BYTE TRANSFER
FN7982.2
June 27, 2012
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ISLA214P12
A/D (based on the R/W bit status). The data transfer will
continue as long as CSB remains low and SCLK is active. Stalling
of the CSB pin is allowed at any byte boundary
(instruction/address or data) if the number of bytes being
transferred is three or less. For transfers of four bytes or more,
CSB is allowed to stall in the middle of the instruction/address
bytes or before the first data byte. If CSB transitions to a high
state after that point the state machine will reset and terminate
the data transfer.
Serial Peripheral Interface
A serial peripheral interface (SPI) bus is used to facilitate
configuration of the device and to optimize performance. The
SPI bus consists of chip select (CSB), serial clock (SCLK) serial
data output (SDO), and serial data input/output (SDIO). The
maximum SCLK rate is equal to the A/D sample rate (f
)
SAMPLE
divided by 16 for both write operations and read operations. At
= 125MHz, maximum SCLK is 7.8125MHz for writing
f
SAMPLE
and read operations. There is no minimum SCLK rate.
TABLE 4. BYTE TRANSFER SELECTION
The following sections describe various registers that are used to
configure the SPI or adjust performance or functional parameters.
Many registers in the available address space (0x00 to 0xFF) are
not defined in this document. Additionally, within a defined
register there may be certain bits or bit combinations that are
reserved. Undefined registers and undefined values within defined
registers are reserved and should not be selected. Setting any
reserved register or value may produce indeterminate results.
[W1:W0]
00
BYTES TRANSFERRED
1
01
2
3
10
11
4 or more
Figures 40 and 41 on page 24 illustrate the timing relationships
for 2-byte and N-byte transfers, respectively. The operation for a
3-byte transfer can be inferred from these diagrams.
SPI Physical Interface
The serial clock pin (SCLK) provides synchronization for the data
transfer. By default, all data is presented on the serial data
input/output (SDIO) pin in three-wire mode. The state of the SDIO
pin is set automatically in the communication protocol
(described in the following). A dedicated serial data output pin
(SDO) can be activated by setting 0x00[7] high to allow operation
in four-wire mode.
SPI Configuration
ADDRESS 0X00: CHIP_PORT_CONFIG
Bit ordering and SPI reset are controlled by this register. Bit order
can be selected as MSB to LSB (MSB first) or LSB to MSB (LSB
first) to accommodate various micro controllers.
The SPI port operates in a half duplex master/slave
configuration, with the ISLA214P12 functioning as a slave.
Multiple slave devices can interface to a single master in
three-wire mode only, since the SDO output of an unaddressed
device is asserted in four wire mode.
Bit 7 SDO Active
Bit 6 LSB First
Setting this bit high configures the SPI to interpret serial data
as arriving in LSB to MSB order.
The chip-select bar (CSB) pin determines when a slave device is
being addressed. Multiple slave devices can be written to
concurrently, but only one slave device can be read from at a
given time (again, only in three-wire mode). If multiple slave
devices are selected for reading at the same time, the results will
be indeterminate.
Bit 5 Soft Reset
Setting this bit high resets all SPI registers to default values.
Bit 4 Reserved
This bit should always be set high.
The communication protocol begins with an instruction/address
phase. The first rising SCLK edge following a high-to-low
transition on CSB determines the beginning of the two-byte
instruction/address command; SCLK must be static low before
the CSB transition. Data can be presented in MSB-first order or
LSB-first order. The default is MSB-first, but this can be changed
by setting 0x00[6] high. Figures 36 and 37 show the appropriate
bit ordering for the MSB-first and LSB-first modes, respectively. In
MSB-first mode, the address is incremented for multi-byte
transfers, while in LSB-first mode it’s decremented.
Bits 3:0 These bits should always mirror bits 4:7 to avoid
ambiguity in bit ordering.
ADDRESS 0X02: BURST_END
If a series of sequential registers are to be set, burst mode can
improve throughput by eliminating redundant addressing. The
burst is ended by pulling the CSB pin high. Setting the burst_end
address determines the end of the transfer; during a write
operation, the user must be cautious to transmit the correct
number of bytes based on the starting and ending addresses.
In the default mode, the MSB is R/W, which determines if the
data is to be read (active high) or written. The next two bits, W1
and W0, determine the number of data bytes to be read or
written (see Table 4). The lower 13 bits contain the first address
for the data transfer. This relationship is illustrated in Figure 38,
and timing values are given in “Switching Specifications” on
page 13.
Bits 7:0 Burst End Address
This register value determines the ending address of the burst
data.
After the instruction/address bytes have been read, the
appropriate number of data bytes are written to or read from the
FN7982.2
June 27, 2012
25
ISLA214P12
TABLE 6. COARSE GAIN ADJUSTMENT
Device Information
0x22[3:0] core 0 NOMINAL COARSE GAIN ADJUST
ADDRESS 0X08: CHIP_ID
(%)
+2.8
+1.4
-2.8
-1.4
Bit3
Bit2
Bit1
Bit0
ADDRESS 0X09: CHIP_VERSION
The generic die identifier and a revision number, respectively, can
be read from these two registers.
Device Configuration/Control
A common SPI map, which can accommodate single-channel or
multi-channel devices, is used for all Intersil A/D products. Single
core ADCs use ADC0, while multiple-core devices use both ADC0
and ADC1.
TABLE 7. MEDIUM AND FINE GAIN ADJUSTMENTS
0x23[7:0]
0x24[7:0]
PARAMETER
Steps
MEDIUM GAIN
FINE GAIN
256
-2%
256
ADDRESS 0X20: OFFSET_COARSE_ADC0
ADDRESS 0X21: OFFSET_FINE_ADC0
–Full Scale (0x00)
Mid–Scale (0x80)
+Full Scale (0xFF)
Nominal Step Size
-0.20%
0.00%
0.00%
+2%
The input offset of the A/D core can be adjusted in fine and
coarse steps. Both adjustments are made via an 8-bit word as
detailed in Table 5. The data format is twos complement. Bit 0 in
register 0xFE must be set high to enable updates written to 0x20
and 0x21 to be used by the ADC.(See description for 0xFE)
+0.2%
0.016%
0.0016%
ADDRESS 0X25: MODES
Two distinct reduced power modes can be selected. By default,
the tri-level NAPSLP pin can select normal operation, nap or
sleep modes (refer to“Nap/Sleep” on page 21). This functionality
can be overridden and controlled through the SPI. This is an
indexed function when controlled from the SPI, but a global
function when driven from the pin. This register is not changed by
a Soft Reset.
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented value
back to the same register.
TABLE 5. OFFSET ADJUSTMENTS
TABLE 8. POWER-DOWN CONTROL
0x25[2:0]
0x20[7:0]
COARSE OFFSET
0x21[7:0]
FINE OFFSET
PARAMETER
Steps
VALUE
000
001
POWER DOWN MODE
255
255
Pin Control
–Full Scale (0x00)
Mid–Scale (0x80)
+Full Scale (0xFF)
Nominal Step Size
-133LSB (-47mV)
0.0LSB (0.0mV)
+133LSB (+47mV)
1.04LSB (0.37mV)
-5LSB (-1.75mV)
0.0LSB
Normal Operation
Nap Mode
010
+5LSB (+1.75mV)
0.04LSB (0.014mV)
100
Sleep Mode
ADDRESS 0X22: GAIN_COARSE_ADC0
ADDRESS 0X23: GAIN_MEDIUM_ADC0
ADDRESS 0X24: GAIN_FINE_ADC0
Global Device Configuration/Control
ADDRESS 0X71: PHASE_SLIP
The output data clock is generated by dividing down the A/D input
sample clock. Some systems with multiple A/Ds can more easily latch
the data from each A/D by controlling the phase of the output data
clock. This control is accomplished through the use of the phase_slip
SPI feature, which allows the rising edge of the output data clock to be
advanced by one input clock period, as shown in the Figure 42.
Execution of a phase_slip command is accomplished by first writing a
Gain of the A/D core can be adjusted in coarse, medium and fine
steps. Coarse gain is a 4-bit adjustment while medium and fine
are 8-bit. Multiple Coarse Gain Bits can be set for a total
adjustment range of ±4.2%. (‘0011’ ≅ -4.2% and ‘1100’ ≅ +4.2%)
It is recommended to use one of the coarse gain settings (-4.2%,
-2.8%, -1.4%, 0, 1.4%, 2.8%, 4.2%) and fine-tune the gain using the
registers at 0x0023 and 0x24.
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented value
back to the same register. Bit 0 in register 0xFE must be set high
to enable updates written to 0x23 and 0x24 to be used by the
ADC.(See description for 0xFE)
FN7982.2
June 27, 2012
26
ISLA214P12
TABLE 11. OUTPUT FORMAT CONTROL
0x73[2:0]
'0' to bit 0 at address 0x71, followed by writing a '1' to bit 0 at address
0x71.
VALUE
OUTPUT FORMAT
ADC Input
Clock (500MHz)
010
Gray Code
2ns
4ns
100
Offset Binary
Output Data
Clock (250MHz)
No clock_slip
ADDRESS 0X74: OUTPUT_MODE_B
2ns
Bit 6 DLL Range
Output Data
Clock (250MHz)
1 clock_slip
This bit sets the DLL operating range to fast (default) or slow.
Output Data
Clock (250MHz)
2 clock_slip
Internal clock signals are generated by a delay-locked loop (DLL),
which has a finite operating range. Table 12 shows the allowable
sample rate ranges for the slow and fast settings.
Bit 4 DDR Enable
FIGURE 42. PHASE SLIP
Set to a ‘1’ to enable DDR.
ADDRESS 0X72: CLOCK_DIVIDE
TABLE 12. DLL RANGES
The ISLA214P12 has a selectable clock divider that can be set to
divide by four, two or one (no division). By default, the tri-level
CLKDIV pin selects the divisor. This functionality can be
overridden and controlled through the SPI, as shown in Table 9.
This register is not changed by a Soft Reset.
DLL RANGE
Slow
MIN
40
MAX
100
125
UNIT
MSPS
MSPS
Fast
80
ADDRESS 0XB6: CALIBRATION STATUS
TABLE 9. CLOCK DIVIDER SELECTION
The LSB at address 0xB6 can be read to determine calibration
status. The bit is ‘0’ during calibration and goes to a logic ‘1’
when calibration is complete.This register is unique in that it can
be read after POR at calibration, unlike the other registers on
chip, which can’t be read until calibration is complete.
0x72[2:0]
CLOCK DIVIDER
VALUE
000
Pin Control
001
Divide by 1
010
Divide by 2
DEVICE TEST
100
Divide by 4
The ISLA214P12 can produce preset or user defined patterns on
the digital outputs to facilitate in-situ testing. A user can pick
from preset built-in patterns by writing to the output test mode
field [7:4] at 0xC0 or user defined patterns by writing to the user
test mode field [2:0] at 0xC0. The user defined patterns should
be loaded at address space 0xC1 through 0xD0, see the “SPI
Memory Map” on page 29 for more detail.The predefined
patterns are shown in Table 13. The test mode is enabled
asynchronously to the sample clock, therefore several sample
clock cycles may elapse before the data is present on the output
bus.
other
Not Allowed
ADDRESS 0X73: OUTPUT_MODE_A
The output_mode_A register controls the physical output format
of the data, as well as the logical coding. The ISLA214P12 can
present output data in two physical formats: LVDS (default) or
LVCMOS. Additionally, the drive strength in LVDS mode can be set
high (default,3mA or low (2mA).
Data can be coded in three possible formats: two’s complement
(default), Gray code or offset binary. See Table 11.
ADDRESS 0XC0: TEST_IO
This register is not changed by a Soft Reset.
Bits 7:4 Output Test Mode
TABLE 10. OUTPUT MODE CONTROL
0x73[7:5]
These bits set the test mode according to Table 13. Other
values are reserved.User test patterns loaded at 0xC1 through
0xD0 are also available by writing ‘1000’ to [7:4] at 0xC0 and a
pattern depth value to [2:0] at 0xC0. See the memory map.
VALUE
OUTPUT MODE
LVDS 3mA (Default)
LVDS 2mA
000
Bits 2:0 User Test Mode
001
The three LSBs in this register determine the test pattern in
combination with registers 0xC1 through 0xD0. Refer to the
SPI Memory Map on page 29.
100
LVCMOS
TABLE 11. OUTPUT FORMAT CONTROL
0x73[2:0]
VALUE
OUTPUT FORMAT
000
Two’s Complement (Default)
FN7982.2
June 27, 2012
27
ISLA214P12
ADDRESS 0XC7: USER_PATT4_LSB
TABLE 13. OUTPUT TEST MODES
0xC0[7:4]
ADDRESS 0XC8: USER_PATT4_MSB
VALUE
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
OUTPUT TEST MODE
WORD 1
WORD 2
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 4.
Off
Midscale
0x8000
0xFFFF
0x0000
N/A
N/A
N/A
ADDRESS 0XC9: USER_PATT5_LSB
ADDRESS 0XCA: USER_PATT5_MSB
Positive Full-Scale
Negative Full-Scale
SDR/DDR Dependent
Reserved
N/A
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 5.
N/A
N/A
N/A
ADDRESS 0XCB: USER_PATT6_LSB
ADDRESS 0XCC: USER_PATT6_MSB
Reserved
N/A
N/A
SDR/DDR Dependent
User Pattern
Reserved
N/A
N/A
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 6.
user_patt1
N/A
user_patt2
N/A
ADDRESS 0XCD: USER_PATT7_LSB
ADDRESS 0XCE: USER_PATT7_MSB
Ramp
N/A
N/A
ADDRESS 0XC1: USER_PATT1_LSB
ADDRESS 0XC2: USER_PATT1_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 7.
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 1.
ADDRESS 0XCF: USER_PATT8_LSB
ADDRESS 0XD0: USER_PATT8_MSB
ADDRESS 0XC3: USER_PATT2_LSB
ADDRESS 0XC4: USER_PATT2_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 8.
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 2
ADDRESS 0XFE: OFFSET/GAIN_ADJUST_ENABLE
Bit 0 at this register must be set high to enable adjustment of
offset coarse and fine adjustments (0x20 and 0x21) and gain
medium and gain fine adjustments(0x23 and 0x24). It is
recommended that new data be written to the offset and gain
adjustment registers (0x20, 0x21, 0x23, 0x24) while Bit 0 is a
‘0’. Subsequently, Bit 0 should be set to ‘1’ to allow the values
written to the aforementioned registers to be used by the ADC.
Bit 0 should be set to a ‘0’ upon completion.
ADDRESS 0XC5: USER_PATT3_LSB
ADDRESS 0XC6: USER_PATT3_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 3
FN7982.2
June 27, 2012
28
ISLA214P12
SPI Memory Map
ADDR.
DEF. VALUE
(HEX)
(Hex)
PARAMETER NAME
Port_config
Reserved
BIT 7 (MSB)
SDO Active
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0 (LSB)
00
LSB First
Soft Reset
Mirror (bit5) Mirror (bit6) Mirror (bit7)
00h
01
Reserved
02
Burst_end
Burst end address [7:0]
Reserved
00h
03-07
Reserved
08
09
Chip_id
Chip_version
Chip ID #
Chip Version #
Reserved
Read only
Read only
0A-0F
10-1F
20
Reserved
Reserved
Reserved
Offset_coarse_adc0
Offset_fine_adc0
Gain_coarse_adc0
Gain_medium_adc0
Gain_fine_adc0
Modes_adc0
Coarse Offset
Fine Offset
cal. value
cal. value
cal. value
cal. value
cal. value
21
22
Reserved
Coarse Gain
23
Medium Gain
Fine Gain
24
25
Reserved
Power Down Mode ADC0 [2:0]
000 = Pin Control
001 = Normal Operation
010 = Nap
00h
NOTresetbySoft
Reset
100 = Sleep
Other codes = Reserved
26
27
28
29
2A
2B
Offset_coarse_adc1
Offset_fine_adc1
Gain_coarse_adc1
Gain_medium_adc1
Gain_fine_adc1
Coarse Offset
Fine Offset
cal. value
cal. value
cal. value
cal. value
cal. value
Reserved
Coarse Gain
Medium Gain
Fine Gain
Modes_adc1
Reserved
Power Down Mode ADC1 [2:0]
000 = Pin Control
001 = Normal Operation
00h
NOTresetbySoft
Reset
010 = Nap
100 = Sleep
Other codes = Reserved
2C-2F
33-4A
4B
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Skew_diff
Phase_slip
Reserved
Reserved
Reserved
Read only
Read only
00h
4C
Reserved
Reset
4D
Enable
PD
Divider [2:0]
Select
4E-6F
70
Reserved
Differential Skew
Reserved
80h
00h
71
Next Clock
Edge
72
Clock_divide
Clock Divide [2:0]
00h
NOTresetbySoft
Reset
000 = Pin Control
001 = divide by 1
010 = divide by 2
100 = divide by 4
Other codes = Reserved
73
Output_mode_A
Output Mode [7:5]
000 = LVDS 3mA (Default)
001 = LVDS 2mA
Output Format [2:0]
000 = Two’s Complement (Default)
010 = Gray Code
00h
NOTresetbySoft
Reset
100 = LVCMOS
100 = Offset Binary
Other codes = Reserved
Other codes = Reserved
74
Output_mode_B
Reserved
DLL Range
0 = Fast
1 = Slow
DDR Enable
Reserved
00h
NOTresetbySoft
Reset
Default=’0’
75-B5
FN7982.2
June 27, 2012
29
ISLA214P12
SPI Memory Map (Continued)
ADDR.
DEF. VALUE
(HEX)
(Hex)
PARAMETER NAME
Cal_status
BIT 7 (MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0 (LSB)
B6
Calibration
Done
Read Only
B7-BF
C0
Reserved
Test_io
Output Test Mode [7:4]
User Test Mode [2:0]
00h
Part in SDR Mode
0 = Off (Note 15)
1 = Midscale Short
2 = +FS Short
Part in SDR Mode
0 = User pattern 1 only
1 = Cycle pattern 1 through 2
2 = Cycle pattern 1 through 3
3 = Cycle pattern 1 through 4
4 = Cycle pattern 1 through 5
5= Cycle pattern 1 through 6
6 = Cycle pattern 1 through7
7 = Cycle pattern 1 through 8
3 = -FS Short
4 = Checkerboard Output (0xAAAA, 0x5555) (Note16
7 = 0xFFFF, 0x0000 all on pattern (Note17)
8 = User Pattern (1 to 8 deep, MSB Justified)
10 = Ramp
5, 6, 9, 11-15 = Reserved
Part in DDR Mode
Part in DDR Mode
0 = Off (Note 15)
1 = Midscale Short
2 = +FS Short
3 = -FS Short
4 = Reserved (Note16)
7 = Reserved (Note17)
8 = User Pattern (1 to 4 deep, MSB Justified)
10 = Ramp
0 = User pattern 1 only
1 = Cycle pattern 1,3
2 = Cycle pattern 1,3,5
3 = Cycle pattern 1,3,5,7
4-7 = NA
5, 6, 9, 11-15 = Reserved
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
User_patt1_lsb
User_patt1_msb
User_patt2_lsb
User_patt2_msb
User_patt3_lsb
User_patt3_msb
User_patt4_lsb
User_patt4_msb
User_patt5_lsb
User_patt5_msb
User_patt6_lsb
User_patt6_msb
User_patt7_lsb
User_patt7_msb
User_patt8_lsb
User_patt8_msb
Reserved
B7
B15
B7
B6
B14
B6
B5
B13
B5
B4
B12
B4
B3
B11
B3
B2
B10
B2
B1
B9
B1
B9
B1
B9
B1
B9
B1
B9
B1
B9
B1
B9
B1
B9
B0
B8
B0
B8
B0
B8
B0
B8
B0
B8
B0
B8
B0
B8
B0
B8
0x00
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
B15
B7
B14
B6
B13
B5
B12
B4
B11
B3
B10
B2
B15
B7
B14
B6
B13
B5
B12
B4
B11
B3
B10
B2
B15
B7
B14
B6
B13
B5
B12
B4
B11
B3
B10
B2
B15
B7
B14
B6
B13
B5
B12
B4
B11
B3
B10
B2
B15
B7
B14
B6
B13
B5
B12
B4
B11
B3
B10
B2
CD
CE
B15
B7
B14
B6
B13
B5
B12
B4
B11
B3
B10
B2
CF
D0
D1-FD
FE
B15
B14
B13
B12
B11
B10
Reserved
Reserved
Offset/Gain_Adjust_Enable
00h
Enable
‘1’ = Enable
FF
Reserved
Reserved
NOTES:
15. During Calibration xCCCC (MSB justified) is presented at the output data bus, toggling on the LSB (and higher) data bits occurs at completion of calibration. This behavior
can be used as an option to determine calibration state.
16. Use test_io = 0x80 and User Pattern 1 = 0x9999 for Checkerboard outputs in DDR mode. In SDR mode, write ‘0x41’ to test_io for Checkerboard outputs.
17. Use test_io = 0x80 and User Pattern 1 = 0xAAAA for all ones/zeroes outputs in DDR mode. In SDR mode, write ‘0x71’ to test_io for all ones/zeroes outputs
FN7982.2
June 27, 2012
30
ISLA214P12
Equivalent Circuits
AVDD
AVDD
TO
CLOCK-PHASE
GENERATION
CLKP
AVDD
AVDD
CSAMP
4pF
TO
11k
11k
INP
INN
CHARGE
PIPELINE
18k
E2
E3
E3
E1
600
AVDD
CSAMP
4pF
18k
AVDD
TO
CHARGE
PIPELINE
E2
CLKN
E1
FIGURE 43. ANALOG INPUTS
FIGURE 44. CLOCK INPUTS
AVDD
AVDD
(20k PULL-UP
ON RESETN
ONLY)
OVDD
AVDD
75k
OVDD
AVDD
TO
SENSE
LOGIC
75k
280
OVDD
20k
INPUT
INPUT
TO
LOGIC
280
75k
75k
FIGURE 45. TRI-LEVEL DIGITAL INPUTS
FIGURE 46. DIGITAL INPUTS
OVDD
2mA OR
3mA
OVDD
DATA
DATA
OVDD
OVDD
D[13:0]P
OVDD
DATA
D[13:0]
D[13:0]N
DATA
DATA
2mA OR
3mA
FIGURE 48. CMOS OUTPUTS
FIGURE 47. LVDS OUTPUTS
FN7982.2
June 27, 2012
31
ISLA214P12
Equivalent Circuits(Continued)
AVDD
VCM
+
0.94V
–
FIGURE 49. VCM_OUT OUTPUT
LVCMOS Outputs
Output traces and connections must be designed for 50Ω
A/D Evaluation Platform
Intersil offers an A/D Evaluation platform which can be used to
evaluate any of Intersil’s high speed A/D products. The platform
consists of a FPGA based data capture motherboard and a family
of A/D daughtercards. This USB based platform allows a user to
quickly evaluate the A/D’s performance at a user’s specific
application frequency requirements. More information is
available at
characteristic impedance.
Unused Inputs
Standard logic inputs (RESETN, CSB, SCLK, SDIO, SDO) which will
not be operated do not require connection to ensure optimal A/D
performance. These inputs can be left floating if they are not
used. Tri-level inputs (NAPSLP) accept a floating input as a valid
state, and therefore should be biased according to the desired
functionality.
http://www.intersil.com/converters/adc_eval_platform/
Layout Considerations
Split Ground and Power Planes
Definitions
Data converters operating at high sampling frequencies require
extra care in PC board layout. Many complex board designs
benefit from isolating the analog and digital sections. Analog
supply and ground planes should be laid out under signal and
clock inputs. Locate the digital planes under outputs and logic
pins. Grounds should be joined under the chip.
Analog Input Bandwidth is the analog input frequency at which
the spectral output power at the fundamental frequency (as
determined by FFT analysis) is reduced by 3dB from its full-scale
low-frequency value. This is also referred to as Full Power
Bandwidth.
Aperture Delay or Sampling Delay is the time required after the
rise of the clock input for the sampling switch to open, at which
time the signal is held for conversion.
Clock Input Considerations
Use matched transmission lines to the transformer inputs for the
analog input and clock signals. Locate transformers and
terminations as close to the chip as possible.
Aperture Jitter is the RMS variation in aperture delay for a set of
samples.
Clock Duty Cycle is the ratio of the time the clock wave is at logic
high to the total time of one clock period.
Exposed Paddle
The exposed paddle must be electrically connected to analog
ground (AVSS) and should be connected to a large copper plane
using numerous vias for optimal thermal performance.
Differential Non-Linearity (DNL) is the deviation of any code width
from an ideal 1 LSB step.
Effective Number of Bits (ENOB) is an alternate method of
specifying Signal to Noise-and-Distortion Ratio (SINAD). In dB, it
is calculated as: ENOB = (SINAD - 1.76)/6.02
Bypass and Filtering
Bulk capacitors should have low equivalent series resistance.
Tantalum is a good choice. For best performance, keep ceramic
bypass capacitors very close to device pins. Longer traces will
increase inductance, resulting in diminished dynamic
performance and accuracy. Make sure that connections to
ground are direct and low impedance. Avoid forming ground
loops.
Gain Error is the ratio of the difference between the voltages that
cause the lowest and highest code transitions to the full-scale
voltage less than 2 LSB. It is typically expressed in percent.
I2E The Intersil Interleave Engine. This highly configurable
circuitry performs estimates of offset, gain, and sample time
skew mismatches between the core converters, and updates
analog adjustments for each to minimize interleave spurs.
LVDS Outputs
Output traces and connections must be designed for 50Ω (100Ω
differential) characteristic impedance. Keep traces direct and
minimize bends where possible. Avoid crossing ground and
power-plane breaks with signal traces.
Integral Non-Linearity (INL) is the maximum deviation of the
A/D’s transfer function from a best fit line determined by a least
squares curve fit of that transfer function, measured in units of
LSBs.
FN7982.2
June 27, 2012
32
ISLA214P12
Least Significant Bit (LSB) is the bit that has the smallest value or
weight in a digital word. Its value in terms of input voltage is
Signal to Noise-and-Distortion (SINAD) is the ratio of the RMS
signal amplitude to the RMS sum of all other spectral
components below one half the clock frequency, including
harmonics but excluding DC.
N
V
/(2 -1) where N is the resolution in bits.
FS
Missing Codes are output codes that are skipped and will never
appear at the A/D output. These codes cannot be reached with
any input value.
Signal-to-Noise Ratio (without Harmonics) is the ratio of the RMS
signal amplitude to the RMS sum of all other spectral
components below one-half the sampling frequency, excluding
harmonics and DC.
Most Significant Bit (MSB) is the bit that has the largest value or
weight.
SNR and SINAD are either given in units of dB when the power of
the fundamental is used as the reference, or dBFS (dB to full
scale) when the converter’s full-scale input power is used as the
reference.
Pipeline Delay is the number of clock cycles between the
initiation of a conversion and the appearance at the output pins
of the data.
Power Supply Rejection Ratio (PSRR) is the ratio of the observed
magnitude of a spur in the A/D FFT, caused by an AC signal
superimposed on the power supply voltage.
Spurious-Free-Dynamic Range (SFDR) is the ratio of the RMS
signal amplitude to the RMS value of the largest spurious
spectral component. The largest spurious spectral component
may or may not be a harmonic.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE
REVISION
FN7982.2
CHANGE
June 27, 2012
Initial Release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: ISLA214P12
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For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
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FN7982.2
June 27, 2012
33
ISLA214P12
Package Outline Drawing
L72.10x10E
72 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 11/09
10.00
A
Z
X
6
EXPOSED
PAD AREA
9.75
B
PIN #1
72
72
INDEX AREA
1
1
6
PIN 1
INDEX AREA
9.75
10.00
0.100 M C A B
(4X)
0.15
4.150 REF.
7.150 REF.
TOP VIEW
9.75 ±0.10
0.100 M C A B
BOTTOM VIEW
11°
Y
ALL AROUND
C0.400X45° (4X)
10.00 ±0.10
SIDE VIEW
(0.350)
R0.200
(7.15)
(4.15 REF)
1
0.500 ±0.100
R0.115 TYP.
72
(4X 9.70)
(4X 8.50)
(3.00 )
DETAIL "X"
DETAIL "Z"
(6.00)
R0.200 MAX.
ALL AROUND
( 72X 0 .23)
0.100 C
( 72X 0 .70)
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
SEATING
PLANE
0.080C
0.190~0.245
0.23 ±0.050
2. Dimensioning and tolerancing conform to ANSI Y14.5m-1994.
0.50
C
0.025 ±0.020
3.
Unless otherwise specified, tolerance : Decimal ± 0.10
Angular ±2.50°
0.100M C A B
0.050M C
4. Dimension applies to the metallized terminal and is measured
between 0.015mm and 0.30mm from the terminal tip.
DETAIL "Y"
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
Package outline compliant to JESD-M0220.
7.
FN7982.2
June 27, 2012
34
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