KAD2708L-17Q68 [INTERSIL]
8-Bit, 350/275/210/170/105MSPS A/D Converter; 8位，二百七十五分之三百五十〇 / 170分之210 / 105MSPS A / D转换器
| 型号： | KAD2708L-17Q68 |
| 厂家： | 
Intersil |
| 描述： | 8-Bit, 350/275/210/170/105MSPS A/D Converter |
| 文件： | 总15页 (文件大小：339K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
KAD2708L
®
Data Sheet
December 5, 2008
FN6813.0
8-Bit, 350/275/210/170/105MSPS A/D
Converter
Features
• On-Chip Reference
The Intersil KAD2708L is the industry’s lowest power, 8-bit,
350MSPS, high performance Analog-to-Digital converter. It is
designed with Intersil’s proprietary FemtoCharge™ technology
on a standard CMOS process. The KAD2708L offers high
• Internal Track and Hold
• 1.5V
P-P
Differential Input Voltage
• 600MHz Analog Input Bandwidth
• Two’s Complement or Binary Output
• Over-Range Indicator
dynamic performance (48.8dBFS SNR @ f = 175MHz) while
IN
consuming less than 330mW. Features include an over-range
indicator and a selectable divide-by-2 input clock divider. The
KAD2708L is one member of a pin-compatible family offering 8
and 10-bit ADCs with sample rates from 105MSPS to
350MSPS and LVDS-compatible or LVCMOS outputs (Table 1).
This family of products is available in 68 Ld RoHS-compliant
QFN packages with exposed paddle. Performance is specified
over the full industrial temperature range (-40°C to +85°C).
• Selectable ÷2 Clock Divider
• LVDS Compatible Outputs
Applications
• High-Performance Data Acquisition
• Portable Oscilloscope
• Medical Imaging
• Cable Head Ends
CLK_P
CLKOUTP
Clock
Generation
• Power-Amplifier Linearization
CLK_N
CLKOUTN
• Radar and Satellite Antenna Array Processing
• Broadband Communications
D7P – D0P
D7N – D0N
• Point-to-Point Microwave Systems
• Communications Test Equipment
INP
INN
8-bit
350MSPS
ADC
ORP
ORN
8
LVDS
Drivers
S/H
VREF
Key Specifications
1.21 V
2SC
VREFSEL
+
–
• SNR = 48.8dBFS at f = 350MSPS, f = 175MHz
IN
S
VCM
• SFDR = 64dBc at f = 350MSPS, f = 175MHz
IN
S
• Power Consumption < 330mW at f = 350MSPS
S
Pin-Compatible Family
TABLE 1. PIN-COMPATIBLE PRODUCTS
Ordering Information
RESOLUTION, SPEED LVDS OUTPUTS LVCMOS OUTPUTS
TEMP.
RANGE
(°C)
SPEED
PART NUMBER (MSPS)
PKG.
DWG. #
8 Bits 350MSPS
10 Bits 275MSPS
8 Bits 275MSPS
10 Bits 210MSPS
8 Bits 210MSPS
10 Bits 170MSPS
8 Bits 170MSPS
10 Bits 105MSPS
8 Bits 105MSPS
KAD2708L-35
KAD2710L-27
KAD2708L-27
KAD2710L-21
KAD2708L-21
KAD2710L-17
KAD2708L-17
KAD2710L-10
KAD2708L-10
PACKAGE
KAD2710C-27
KAD2708C-27
KAD2710C-21
KAD2708C-21
KAD2710C-17
KAD2708C-17
KAD2710C-10
KAD2708C-10
KAD2708L-35Q68
KAD2708L-27Q68
KAD2708L-21Q68
KAD2708L-17Q68
KAD2708L-10Q68
350
275
210
170
105
-40 to +85 68 Ld QFN L68.10x10B
-40 to +85 68 Ld QFN L68.10x10B
-40 to +85 68 Ld QFN L68.10x10B
-40 to +85 68 Ld QFN L68.10x10B
-40 to +85 68 Ld QFN L68.10x10B
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish,
which is RoHS compliant and compatible with both SnPb and Pb-free
soldering operations). Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
FemtoCharge is a trademark of Kenet Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1
KAD2708L
Table of Contents
Absolute Maximum Ratings ......................................... 3
Thermal Information...................................................... 3
Electrical Specifications............................................... 3
Digital Specifications.................................................... 4
Timing Diagram ............................................................. 5
Timing Specifications ................................................... 5
Thermal Impedance....................................................... 5
ESD................................................................................. 5
Pin Description.............................................................. 6
Pin Configuration .......................................................... 7
Typical Performance Curves........................................ 8
Functional Description ................................................. 11
Reset .......................................................................... 11
Voltage Reference...................................................... 11
Analog Input ............................................................... 11
Clock Input ................................................................. 12
Jitter............................................................................ 12
Digital Outputs............................................................ 13
Equivalent Circuits........................................................ 13
Layout Considerations ................................................. 14
Split Ground and Power Planes ................................. 14
Clock Input Considerations......................................... 14
Bypass and Filtering................................................... 14
LVDS Outputs ............................................................ 14
Unused Inputs ............................................................ 14
Definitions...................................................................... 14
Package Outline Drawing ............................................. 15
L68.10x10B ................................................................ 15
FN6813.0
December 5, 2008
2
KAD2708L
Absolute Maximum Ratings
Thermal Information
AVDD2 to AVSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V
AVDD3 to AVSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 3.7V
OVDD2 to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V
Analog Inputs to AVSS. . . . . . . . . . . . . . . . . -0.4V to AVDD3 + 0.3V
Clock Inputs to AVSS. . . . . . . . . . . . . . . . . . -0.4V to AVDD2 + 0.3V
Logic Inputs to AVSS (VREFSEL, CLKDIV) -0.4V to AVDD3 + 0.3V
Logic Inputs to OVSS (RST, 2SC) . . . . . . . . -0.4V to OVDD2 + 0.3V
VREF to AVSS. . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD3 + 0.3V
Analog Output Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
Logic Output Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
LVDS Output Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD2 = 1.8V, AVDD3 = 3.3V,
OVDD = 1.8V, T = -40°C to +85°C (typical specifications at +25°C), f
= 350MSPS, 270MSPS,
SAMPLE
A
210MSPS, 170MSPS and 105MSPS, f = Nyquist at -0.5dBFS.
IN
KAD2708L-35
KAD2708L-27
KAD2708L-21
KAD2708L-17
KAD2708L-10
PARAMETER SYMBOL CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
DC SPECIFICATIONS
Analog Input
Full-Scale Analog
Input Range
V
1.4 1.5 1.6 1.4 1.5 1.6 1.4 1.5 1.6 1.4 1.5 1.6 1.4 1.5 1.6
V
P-P
FS
Full Scale Range
Temp. Drift
A
Full Temp
257
860
230
860
210
860
198
860
176
860
ppm/°C
mV
VTC
Common-Mode
Output Voltage
V
CM
Power Requirements
1.8V Analog
Supply Voltage
AVDD2
AVDD3
OVDD
1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9
3.15 3.3 3.45 3.15 3.3 3.45 3.15 3.3 3.45 3.15 3.3 3.45 3.15 3.3 3.45
1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9
V
V
3.3V Analog
Supply Voltage
1.8V Digital
V
Supply Voltage
1.8V Analog
Supply Current
I
I
51
50
39
60
54
44
44
41
34
51
45
39
38
33
33
42
37
36
35
28
31
39
32
36
29
21
28
33
24
32
mA
mA
mA
mW
AVDD2
AVDD3
3.3V Analog
Supply Current
1.8V Digital
Supply Current
I
OVDD
Power
P
327 365
275 310
237 263
211 241
172 196
D
Dissipation
AC SPECIFICATIONS
Maximum
f
MAX
350
275
210
170
105
MSPS
S
Conversion Rate
Minimum
f
MIN
50
50
50
50
50 MSPS
S
Conversion Rate
Differential
Nonlinearity
DNL
INL
f
= 10MHz
-0.3 ±0.2 0.4 -0.3 ±0.2 0.4 -0.3 ±0.2 0.4 -0.3 ±0.2 0.4 -0.3 ±0.2 0.4
-0.8 ±0.2 0.8 -0.8 ±0.2 0.8 -0.8 ±0.2 0.8 -0.8 ±0.2 0.8 -0.8 ±0.2 0.8
LSB
LSB
IN
(for -17 and -10
versions only)
Integral
f
= 10MHz
IN
Nonlinearity
(for -17 and -10
versions only)
FN6813.0
December 5, 2008
3
KAD2708L
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD2 = 1.8V, AVDD3 = 3.3V,
OVDD = 1.8V, T = -40°C to +85°C (typical specifications at +25°C), f
= 350MSPS, 270MSPS,
A
SAMPLE
210MSPS, 170MSPS and 105MSPS, f = Nyquist at -0.5dBFS. (Continued)
IN
KAD2708L-27
PARAMETER SYMBOL CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
KAD2708L-35
KAD2708L-21
KAD2708L-17
KAD2708L-10
Signal-to-Noise
Ratio
SNR
f
f
f
f
f
f
f
f
f
f
f
f
= 10MHz
= Nyquist
= 430MHz
= 10MHz
= Nyquist
= 430MHz
= 10MHz
= Nyquist
= 430MHz
= 10MHz
= Nyquist
= 430MHz
49.0
46.5 48.8
48.0
50.4
46.5 49.2
49.0
49.5
46.5 49.2
49.1
49.5
46.5 49.2
49.1
49.5
46.5 49.2
49.1
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
Signal-to-Noise
and Distortion
SINAD
48.9
49.2
49.5
49.5
49.5
46.5 48.2
47.7
46.5 49.2
48.9
46.5 49.2
48.9
46.5 49.2
49.0
46.5 49.2
48.9
Effective Number ENOB
of Bits
7.8
7.9
7.9
7.9
7.9
7.4 7.9
7.6
7.4 7.9
7.8
7.4 7.9
7.8
7.4 7.9
7.8
7.4 7.9
7.8
Bits
Bits
Spurious-Free
Dynamic Range
SFDR
65.0
67.6
69.1
69.1
69.1
dBc
61
64
62
61
61 66.6
66.1
61 69.1
69.0
61 69.1
69.0
61 69.1
68.9
dBc
dBc
Two-Tone SFDR 2TSFDR f = 133MHz,
IN
63
65
65
65
dBc
135MHz
-12
10
-12
10
-12
10
-12
10
-12
10
Word Error Rate
WER
Full Power
Bandwidth
FPBW
600
600
600
600
600
MHz
Digital Specifications
PARAMETER
INPUTS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
High Input Voltage (VREFSEL)
Low Input Voltage (VREFSEL)
Input Current High (VREFSEL)
Input Current Low (VREFSEL)
High Input Voltage (CLKDIV)
Low Input Voltage (CLKDIV)
Input Current High (CLKDIV)
Input Current Low (CLKDIV)
High Input Voltage (RST,2SC)
Low Input Voltage (RST,2SC)
Input Current High (RST,2SC)
Input Current Low (RST,2SC)
Input Capacitance
VREFSEL V
0.8*AVDD3
V
V
IH
VREFSEL V
0.2*AVDD3
IL
VREFSEL I
V
V
= AVDD3
= AVSS
0
25
1
10
75
µA
µA
V
IH
IN
IN
VREFSEL I
65
IL
CLKDIV V
0.8*AVDD3
IH
CLKDIV V
0.2*AVDD3
V
IL
CLKDIV I
V
V
= AVDD3
= AVSS
25
0
65
1
75
10
µA
µA
V
IH
IN
IN
CLKDIV I
IL
RST,2SC V
0.8*OVDD2
IH
RST,2SC V
0.2*OVDD2
V
IL
RST,2SC I
VIN = OVDD
VIN = OVSS
0
1
50
3
10
75
µA
µA
pF
IH
RST,2SC I
25
IL
C
DI
CLKP, CLKN P-P Differential Input Voltage
CLKP, CLKN Differential Input Resistance
CLKP, CLKN Common-Mode Input Voltage
LVDS OUTPUTS
V
R
V
0.5
3.6
V
P-P
CDI
CDI
CCI
10
MΩ
0.9
V
Differential Output Voltage
Output Offset Voltage
V
210
1.15
500
500
mV
V
T
V
OS
Output Rise Time
t
ps
ps
R
Output Fall Time
t
F
FN6813.0
December 5, 2008
4
KAD2708L
Timing Diagram
Sample N
INP
INN
tA
CLKN
CLKP
L
tPID
CLKOUTN
CLKOUTP
tPCD
tPH
D[7:0]P
D[7:0]N
Data N-L
invalid
Data N-L+1
Data N
FIGURE 1. LVDS TIMING DIAGRAM
Timing Specifications
PARAMETER
SYMBOL
MIN
TYP
1.7
MAX
UNITS
ns
Aperture Delay
t
A
RMS Aperture Jitter
j
200
5.0
fs
A
Input Clock to Data Propagation Delay
Data Hold Time
t
3.5
6.5
3.7
ns
PID
t
-300
ps
PH
Output Clock to Data Propagation Delay
Latency (Pipeline Delay)
Overvoltage Recovery
t
2.8
28
1
ns
PCD
L
cycles
cycle
t
OVR
Thermal Impedance
PARAMETER
Junction to Paddle (Note 1)
NOTE:
SYMBOL
TYP
UNIT
θ
30
°C/W
JP
1. Paddle soldered to ground plane.
ESD
Electrostatic charge accumulates on humans, tools and
equipment and may discharge through any metallic package
contacts (pins, balls, exposed paddle, etc.) of an integrated
circuit. Industry-standard protection techniques have been
utilized in the design of this product. However, reasonable
care must be taken in the storage and handling of ESD
sensitive products. Contact Intersil for the specific ESD
sensitivity rating of this product.
FN6813.0
December 5, 2008
5
KAD2708L
Pin Description
PIN NUMBER
NAME
AVDD2
FUNCTION
1, 14, 18, 20
1.8V Analog Supply
2, 7, 10, 19, 21, 24
AVSS
Analog Supply Return
3
VREF
Reference Voltage Out/In
4
VREFSEL
VCM
Reference Voltage Select (0:Int 1:Ext)
Common-Mode Voltage Output
3.3V Analog Supply
5
6, 15, 16, 25
8, 9
AVDD3
INP, INN
DNC
Analog Input Positive, Negative
Do Not Connect
11-13, 29-36, 62, 63, 67
17
CLKDIV
Clock Divide by Two (Active Low)
Clock Input Complement, True
Output Supply Return
22, 23
CLKN, CLKP
OVSS
26, 45, 61
27, 41, 44, 60
28
OVDD2
1.8V LVDS Supply
RST
Power On Reset (Active Low)
LVDS Bit 0 (LSB) Output Complement, True
LVDS Bit 1 Output Complement, True
LVDS Clock Output Complement, True
LVDS Bit 2 Output Complement, True
LVDS Bit 3 Output Complement, True
LVDS Bit 4 Output Complement, True
LVDS Bit 5 Output Complement, True
LVDS Bit 6 Output Complement, True
LVDS Bit 7 Output Complement, True
Over-Range Complement, True
Connect to OVDD2
37, 38
D0N, D0P
D1N, D1P
CLKOUTN, CLKOUTP
D2N, D2P
D3N, D3P
D4N, D4P
D5N, D5P
D6N, D6P
D7N, D7P
ORN, ORP
39, 40
42, 43
46, 47
48, 49
50, 51
52, 53
54, 55
56, 57
58, 59
64-66
68
2SC
Two’s Complement Select (Active Low)
Analog Supply Return
Exposed Paddle
AVSS
FN6813.0
December 5, 2008
6
KAD2708L
Pin Configuration
AVDD2
AVSS
VREF
1
2
3
4
5
6
7
8
9
51 D4P
50 D4N
49 D3P
VREFSEL
VCM
AVDD3
AVSS
INP
48 D3N
47 D2P
46 D2N
45 OVSS
44 OVDD2
43 CLKOUTP
42 CLKOUTN
41 OVDD2
40 D1P
INN
AVSS 10
DNC 11
DNC 12
DNC 13
39 D1N
Top View
Not to Scale
AVDD2 14
AVDD3 15
AVDD3 16
CLKDIV 17
38 D0P
37 D0N
36 DNC
35 DNC
FIGURE 2. PIN CONFIGURATION
FN6813.0
December 5, 2008
7
KAD2708L
Typical Performance Curves AVDD2 = OVDD2 = 1.8V, AVDD3 = 3.3V, T = +25°C, f
= 350MHz, f = 175MHz,
SAMPLE IN
A
A
= -0.5dBFS unless noted.
IN
-50
-55
-60
-65
-70
-75
-80
-85
-90
70
65
60
55
50
45
40
SFDR
HD3
HD2
SNR
5
105
205
305
fIN(MHz)
405
505
5
105
205
305
fIN (MHz)
405
505
FIGURE 4. HD2 AND HD3 vs f
FIGURE 3. SNR AND SFDR vs f
IN
IN
80
70
60
50
40
30
20
-20
HD3
-30
-40
-50
-60
-70
-80
SNR
HD2
SFDR
-30
-25
-20
Input Amplitude (dBFS)
FIGURE 6. HD2 AND HD3 vs A
-15
-10
-5
0
-30
-25
-20
-15
IN (dBF S )
-10
-5
0
A
FIGURE 5. SNR AND SFDR vs A
IN
IN
80
76
72
68
64
60
56
52
48
44
40
-65
-70
-75
-80
-85
-90
SFDR
HD3
HD2
SNR
50
100
150
200
SAMPLE (MSPS)
FIGURE 8. HD2 AND HD3 vs f
250
300
350
50
100
150
200
250
300
350
fSAMP LE (fS) (MSPS)
f
FIGURE 7. SNR AND SFDR vs f
SAMPLE
SAMPLE
FN6813.0
December 5, 2008
8
KAD2708L
Typical Performance Curves AVDD2 = OVDD2 = 1.8V, AVDD3 = 3.3V, T = +25°C, f
= 350MHz, f = 175MHz,
IN
A
SAMPLE
A
= -0.5dBFS unless noted. (Continued)
IN
1
0.75
0.5
350
330
310
290
270
250
230
210
19 0
17 0
15 0
0.25
0
-0.25
-0.5
-0.75
-1
100
150
200
250
300
350
0
32
64
96
128
CODE
160
192
224
255
f
SAMPLE (fS)(MSPS)
FIGURE 10. DIFFERENTIAL NONLINEARITY vs OUTPUT CODE
FIGURE 9. POWER DISSIPATION vs f
SAMPLE
50,000
45,000
40,000
35,000
30,000
25,000
20,000
15,000
10,000
5,000
1
0.75
0.5
0.25
0
-0.25
-0.5
-0.75
0
-1
124
125
126
127
128
129
130
0
32
64
96
128
160
192
224
255
CODE
CODE
FIGURE 11. INTEGRAL NONLINEARITY vs OUTPUT CODE
FIGURE 12. NOISE HISTOGRAM
0
0
-20
Ain= -0.47dBFS
Ain= -0.47dBFS
SNR = 49.4dBFS
-20
SNR= 49.4dBFS
SFDR = 69.2dBc
SINAD = 49.4dBFS
HD2 = -81dBc
SFDR = 68.4dBc
-40
-60
SINAD= 49.3dBFS
HD2 = -86dBc
-40
-60
HD3 = -69dBc
HD3 = -91dBc
-80
-80
-100
-100
-120
-120
0
20
40
60
80
100
120
0
20
40
60
80
100
120
FREQUENCY (MHz)
FREQUENCY(MHz)
FIGURE 13. OUTPUT SPECTRUM @ 9.865MHz
FIGURE 14. OUTPUT SPECTRUM @ 133.805MHz
FN6813.0
December 5, 2008
9
KAD2708L
Typical Performance Curves AVDD2 = OVDD2 = 1.8V, AVDD3 = 3.3V, T = +25°C, f
= 350MHz, f = 175MHz,
IN
A
SAMPLE
A
= -0.5dBFS unless noted. (Continued)
IN
0
-20
0
Ain = -0.48dBFS
Ain = -7.1dBFS
SNR= 49.3dBFS
SFDR = 63dBc
SINAD = 49.1dBFS
HD2 = -63dBc
-20
-40
2TSFDR = 67dBc
IMD3 = -74dBFS
-40
HD3 = -67dBc
-60
-60
-80
-80
-100
-120
-100
-120
0
20
40
60
80
100
120
0
20
40
60
80
100
120
FREQUENCY (MHz)
FRE QUE NCY (MHz)
FIGURE 15. OUTPUT SPECTRUM @ 299.645MHz
FIGURE 16. TWO-TONE SPECTRUM @ 69MHz, 70MHz
0
-20
0
-20
Ain = -7dBFS
Ain = -7dBFS
2TSFD R = 63dBc
IM D 3 = - 76 dB FS
2TSFDR = 73dBc
IMD3 = -81dBFS
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
20
40
60
80
100
120
0
20
40
60
80
100
120
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 17. TWO-TONE SPECTRUM @ 140MHz, 141MHz
FIGURE 18. TWO-TONE SPECTRUM @ 300MHz, 305MHz
75
70
65
60
55
50
45
40
700
600
500
400
300
200
100
SFDR
SNR
100 125 150 175 200 225 250 275 300 325 350
SAMPLE (fS) (MSPS)
-40
-20
0
20
40
60
80
f
AMBIENT TEMPERATURE, C
FIGURE 19. SNR AND SFDR vs TEMPERATURE
FIGURE 20. CALIBRATION TIME vs f
S
FN6813.0
December 5, 2008
10
KAD2708L
Voltage Reference
Functional Description
The VREF pin is the full-scale reference, which sets the full-
scale input voltage for the chip and requires a bypass
capacitor of 0.1µF or larger.An internally generated
reference voltage is provided from a bandgap voltage buffer.
This buffer can sink or source up to 50µA externally.
The KAD2708L is an eight bit, 350MSPS A/D converter in a
pipelined architecture. The input voltage is captured by a
sample and hold circuit and converted to a unit of charge.
Proprietary charge-domain techniques are used to compare
the input to a series of reference charges. These
comparisons determine the digital code for each input value.
The converter pipeline requires 24 sample clocks to produce
a result. Digital error correction is also applied, resulting in a
total latency of 28 clock cycles. This is evident to the user as
a latency between the start of a conversion and the data
being available on the digital outputs.
An external voltage may be applied to this pin to provide a
more accurate reference than the internally generated
bandgap voltage or to match the full-scale reference among
a system of KAD2708L chips. One option in the latter
configuration is to use one KAD2708L's internally generated
reference as the external reference voltage for the other
chips in the system. Additionally, an externally provided
reference can be changed from the nominal value to adjust
the full-scale input voltage within a limited range.
At start-up, a self-calibration is performed to minimize gain
and offset errors. The reset pin (RST) is initially held low
internally at power-up and will remain in that state until the
calibration is complete. The clock frequency should remain
fixed during this time.
To select whether the full-scale reference is internally
generated or externally provided, the digital input port
VREFSEL should be set appropriately, low for internal or
high for external.This pin also has an internal 18kΩ pull-up
resistor. To use the internally generated reference VREFSEL
can be tied directly to AVSS, and to use an external
reference VREFSEL can be left unconnected.
Calibration accuracy is maintained for the sample rate at
which it is performed, and therefore should be repeated if the
clock frequency is changed by more than 10%. Recalibration
can be initiated via the RST pin, or power cycling, at any
time.
Analog Input
Reset
The fully differential ADC input (INP/INN) connects to the
sample and hold circuit. The ideal full-scale input voltage is
Recalibration of the ADC can be initiated at any time by
driving the RST pin low for a minimum of one clock cycle. An
open-drain driver is recommended.
1.5V , centered at the VCM voltage of 0.86V as shown in
P-P
Figure 22.
The calibration sequence is initiated on the rising edge of
RST, as shown in Figure 21. The over-range output (ORP) is
set high once RST is pulled low, and remains in that state
until calibration is complete. The ORP output returns to
normal operation at that time, so it is important that the
analog input be within the converter’s full-scale range in
order to observe the transition. If the input is in an over-
range state the ORP pin will stay high and it will not be
possible to detect the end of the calibration cycle.
V
1.8
INN
INP
1.4
0.75V
VCM
1.0
0.86V
0.6
-0.75V
0.2
While RST is low, the output clock (CLKOUTP/CLKOUTN)
stops toggling and is set low. Normal operation of the output
clock resumes at the next input clock edge (CLKP/CLKN)
after RST is deasserted. At 350MSPS the nominal
calibration time is ~190ms.
t
FIGURE 22. ANALOG INPUT RANGE
Best performance is obtained when the analog inputs are
driven differentially. The common-mode output voltage,
VCM, should be used to properly bias each input as shown
in Figures 23 and 24. An RF transformer will give the best
noise and distortion performance for wideband and/or high
intermediate frequency (IF) inputs. Two different transformer
input schemes are shown in Figures 23 and 24.
CLKN
CLKP
Calibration Time
RST
Calibration Begins
ORP
Calibration Complete
CLKOUTP
FIGURE 21. CALIBRATION TIMING
FN6813.0
December 5, 2008
11
KAD2708L
Clock Input
The clock input circuit is a differential pair (see Figure 29).
Driving these inputs with a high level (up to 1.8V on each
input) sine or square wave will provide the lowest jitter
performance. The recommended drive circuit is shown in
Figure 26. The clock can be driven single-ended, but this will
reduce the edge rate and may impact SNR performance.
0.01µF
Analog
In
P-P
KAD2708
VCM
50Ω
ADT1-1WT
ADT1-1WT
0.1µF
1kΩ
1kΩ
FIGURE 23. TRANSFORMER INPUT, GENERAL APPLICATION
AVDD2
CLKP
CLKN
1nF
25Ω
ADTL1-12
ADTL1-12
1nF
Clock
Input
1nF
1nF
Analog
Input
200Ω
KAD2708
VCM
25Ω
0.1µF
TC4-1W
FIGURE 26. RECOMMENDED CLOCK DRIVE
FIGURE 24. TRANSFORMER INPUT, HIGH IF APPLICATION
Use of the clock divider is optional. The KAD2708L's ADC
requires a clock with 50% duty cycle for optimum
performance. If such a clock is not available, one option is to
generate twice the desired sampling rate, then use the
KAD2708L's divide-by-2 to generate a 50%-duty-cycle clock.
This frequency divider uses the rising edge of the clock, so
50% clock duty cycle is assured. Table 2 describes the
CLKDIV connection.
A back-to-back transformer scheme is used to improve
common-mode rejection, which keeps the common-mode
level of the input matched to V . The value of the
CM
termination resistor should be determined based on the
desired impedance.
The sample and hold circuit design uses a switched
capacitor input stage, which creates current spikes when the
sampling capacitance is reconnected to the input voltage.
This creates a disturbance at the input which must settle
before the next sampling point. Lower source impedance will
result in faster settling and improved performance. Therefore
a 1:1 transformer and low shunt resistance are
TABLE 2. CLKDIV PIN SETTINGS
CLKDIV PIN
AVSS
DIVIDE RATIO
2
1
AVDD
recommended for optimal performance.
A differential amplifier can be used in applications that
require DC coupling, at the expense of reduced dynamic
performance. In this configuration the amplifier will typically
reduce the achievable SNR and distortion performance. A
typical differential amplifier configuration is shown in
Figure 25.
CLKDIV is internally pulled low, so a pull-up resistor or logic
driver must be connected for undivided clock.
Jitter
In a sampled data system, clock jitter directly impacts the
achievable SNR performance. The theoretical relationship
between clock jitter and maximum SNR is shown in
Equation 1 and illustrated in Figure 27.
348OΩ
69.8OΩ
100O
25OΩ
1
⎛
⎝
⎞
⎠
-------------------
SNR = 20 log
(EQ. 1)
Ω
10
2πf
t
IN J
+
Vin
-
0.22µF
151ΩO
KAD2708
VCM
CM
Where t is the RMS uncertainty in the sampling instant.
J
100OΩ
69.8OΩ
25OΩ
This relationship shows the SNR that would be achieved if
clock jitter were the only non-ideal factor. In reality,
achievable SNR is limited by internal factors such as
differential nonlinearity aperture jitter and thermal noise.
49.9OΩ
0.1µF
348OΩ
FIGURE 25. DIFFERENTIAL AMPLIFIER INPUT
FN6813.0
December 5, 2008
12
KAD2708L
Any internal aperture jitter combines with the input clock jitter
100
95
90
85
80
75
in a root-sum-square fashion since they are not statistically
correlated, and this determines the total jitter in the system.
The total jitter, combined with other noise sources, then
determines the achievable SNR.
tj = 0. 1 ps
14 Bits
12 Bits
tj = 1 ps
Digital Outputs
70
65
60
tj = 10 p s
10 Bits
Data is output on a parallel bus with LVDS-compatible
drivers.
tj = 1 00 ps
55
50
The output format (Binary or Two’s Complement) is selected
via the 2SC pin as shown in Table 3.
1
10
100
1000
Input Frequency - MH z
TABLE 3. 2SC PIN SETTINGS
FIGURE 27. SNR vs CLOCK JITTER
2SC PIN
AVSS
MODE
Two’s Complement
Binary
AVDD (or unconnected)
Equivalent Circuits
AVDD2
AVDD3
To
Charge
Pipeline
AVDD2
To Clock
Generation
INP
Csamp
0.3pF
Φ
2
Φ
1
CLKP
AVDD3
To
Charge
Pipeline
INN
AVDD2
2pF
Csamp
0.3pF
Φ
2
Φ
1
CLKN
FIGURE 28. ANALOG INPUTS
FIGURE 29. CLOCK INPUTS
OVDD
OVDD
DATA
DATA
D[7:0]P
OVDD
D[7:0]N
DATA
DATA
FIGURE 30. LVDS OUTPUTS
FN6813.0
December 5, 2008
13
KAD2708L
Aperture Jitter is the RMS variation in aperture delay for a
set of samples.
Layout Considerations
Split Ground and Power Planes
Clock Duty Cycle is the ratio of the time the clock wave is at
logic high to the total time of one clock period.
Data converters operating at high sampling frequencies
require extra care in PC board layout. Many complex board
designs benefit from isolating the analog and digital
sections. Analog supply and ground planes should be laid
out under signal and clock inputs. Locate the digital planes
under outputs and logic pins. Ground planes, if separated,
should be joined at the exposed paddle under the chip.
Differential Non-Linearity (DNL) is the deviation of any
code width from an ideal 1 LSB step.
Effective Number of Bits (ENOB) is an alternate method of
specifying Signal to Noise-and-Distortion Ratio (SINAD). In
dB, it is calculated as: ENOB = (SINAD - 1.76)/6.02.
Clock Input Considerations
Integral Non-Linearity (INL) is the deviation of each individual
code from a line drawn from negative full-scale (1/2 LSB below
the first code transition) through positive full-scale (1/2 LSB
above the last code transition). The deviation of any given code
from this line is measured from the center of that code.
Use matched transmission lines to the inputs for the analog
input and clock signals. Locate transformers, drivers and
terminations as close to the chip as possible.
Bypass and Filtering
Least Significant Bit (LSB) is the bit that has the smallest
value or weight in a digital word. Its value in terms of input
voltage is VFS/(2N-1) where N is the resolution in bits.
Bulk capacitors should have low equivalent series resistance.
Tantalum is a good choice. For best performance, keep
ceramic bypass capacitors very close to device pins. Longer
traces will increase inductance, resulting in diminished
dynamic performance and accuracy. Make sure that
connections to ground are direct and low impedance.
Missing Codes are output codes that are skipped and will
never appear at the ADC output. These codes cannot be
reached with any input value.
LVDS Outputs
Most Significant Bit (MSB) is the bit that has the largest
Output traces and connections must be designed for 50Ω
(100Ω differential) characteristic impedance. Keep traces
direct, and minimize bends where possible. Avoid crossing
ground and power-plane breaks with signal traces.
value or weight. Its value in terms of input voltage is VFS/2.
Pipeline Delay is the number of clock cycles between the
initiation of a conversion and the appearance at the output
pins of the corresponding data.
Unused Inputs
Power Supply Rejection Ratio (PSRR) is the ratio of a
change in power supply voltage to the input voltage
necessary to negate the resultant change in output code.
The RST and 2SC inputs are internally pulled up, and can be
left open-circuit if not used.
CLKDIV is internally pulled low, which divides the input clock
by two.
Signal to Noise-and-Distortion (SINAD) is the ratio of the
RMS signal amplitude to the RMS sum of all other spectral
components below one half the clock frequency, including
harmonics but excluding DC.
VREFSEL is internally pulled up. It must be held low for
internal reference, but can be left open for external
reference.
Signal-to-Noise Ratio (SNR) (without Harmonics) is the
ratio of the RMS signal amplitude to the RMS sum of all
other spectral components below one-half the sampling
frequency, excluding harmonics and DC.
Definitions
Analog Input Bandwidth is the analog input frequency at
which the spectral output power at the fundamental
frequency (as determined by FFT analysis) is reduced by
3dB from its full-scale low-frequency value. This is also
referred to as Full Power Bandwidth.
Spurious-Free-Dynamic Range (SFDR) is the ratio of the
RMS signal amplitude to the RMS value of the peak spurious
spectral component. The peak spurious spectral component
may or may not be a harmonic.
Aperture Delay or Sampling Delay is the time required
after the rise of the clock input for the sampling switch to
open, at which time the signal is held for conversion.
Two-Tone SFDR is the ratio of the RMS value of either input
tone to the RMS value of the peak spurious component. The
peak spurious component may or may not be an IMD product.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6813.0
December 5, 2008
14
KAD2708L
Package Outline Drawing
L68.10x10B
68 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 11/08
PIN 1
INDEX AREA
10.00
A
4X 8.00
PIN 1
6
INDEX AREA
B
52
68
6
1
51
64X 0.50
Exp. DAP
7.70 Sq.
10.00
17
35
(4X)
0.15
34
18
68X 0.55
BOTTOM VIEW
68X 0.25
4
0.10 M C A B
TOP VIEW
SEE DETAIL "X"
C
0.10
0.08 C
SEATING PLANE
0.90 Max
8.00 Sq
C
64X 0.50
68X 0.25
SIDE VIEW
9.65 Sq
5
0 . 2 REF
C
7.70 Sq
0 . 00 MIN.
0 . 05 MAX.
68X 0.75
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSEY14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN6813.0
December 5, 2008
15
相关型号：
©2020 ICPDF网 联系我们和版权申明