KAD5510P-50_0910 [INTERSIL]
10-Bit, 500MSPS A/D Converter; 10位，500Msps， A / D转换器
| 型号： | KAD5510P-50_0910 |
| 厂家： | 
Intersil |
| 描述： | 10-Bit, 500MSPS A/D Converter |
| 文件： | 总29页 (文件大小：815K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
KAD5510P-50
®
Data Sheet
October 8, 2009
FN6811.2
10-Bit, 500MSPS A/D Converter
Features
The KAD5510P-50 is a low-power, high-performance, 10-bit,
500MSPS analog-to-digital converter designed with Intersil’s
proprietary FemtoCharge™ technology on a standard
CMOS process. The KAD5510P-50 is part of a
pin-compatible portfolio of 10, 12 and 14-bit A/Ds with
sample rates ranging from 125MSPS to 500MSPS.
• Programmable Gain, Offset and Skew Control
• 1.3GHz Analog Input Bandwidth
• 60fs Clock Jitter
• Over-Range Indicator
• Selectable Clock Divider: ÷1 or ÷2
• Clock Phase Selection
The device utilizes two time-interleaved 10-bit, 250MSPS
A/D cores to achieve the ultimate sample rate of 500MSPS.
A single 500MHz conversion clock is presented to the
converter, and all interleave clocking is managed internally.
• Nap and Sleep Modes
• Two’s Complement, Gray Code or Binary Data Format
• DDR LVDS-Compatible or LVCMOS Outputs
• Programmable Built-in Test Patterns
• Single-Supply 1.8V Operation
• Pb-Free (RoHS Compliant)
A serial peripheral interface (SPI) port allows for extensive
configurability, as well as fine control of matching
characteristics (gain, offset, skew) between the two
converter cores. These adjustments allow the user to
minimize spurs associated with the interleaving process.
Applications
Digital output data is presented in selectable LVDS or CMOS
formats. The KAD5510P-50 is available in a 72-contact QFN
package with an exposed paddle. Performance is specified
over the full industrial temperature range (-40°C to +85°C).
• Radar and Satellite Antenna Array Processing
• Broadband Communications
• High-Performance Data Acquisition
Pin-Compatible Family
Key Specifications
• SNR = 60.7dBFS for f = 105MHz (-1dBFS)
IN
SPEED
MODEL
KAD5514P-25
RESOLUTION
(MSPS)
250
210
170
125
500
250
• SFDR = 83.2dBc for f = 105MHz (-1dBFS)
IN
14
14
14
14
12
12
12
12
12
10
• Power Consumption = 414mW
KAD5514P-21
KAD5514P-17
KAD5514P-12
KAD5512P-50
CLKP
CLOCK GENERATION
&
CLKOUTP
CLKOUTN
KAD5512P-25, KAD5512HP-25
KAD5512P-21, KAD5512HP-21
KAD5512P-17, KAD5512HP-17
KAD5512P-12, KAD5512HP-12
KAD5510P-50
CLKN
INTERLEAVE CONTROL
210
170
125
10-BIT
250 MSPS
ADC
D[9:0]P
D[9:0]N
500
SHA
VREF
ORP
ORN
VINP
VINN
DIGITAL
ERROR
CORRECTION
OUTFMT
OUTMODE
10-BIT
250 MSPS
ADC
VCM
SHA
VREF
+
1.25V
–
SPI
CONTROL
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
FemtoCharge is a trademark of Kenet Inc. Copyright Intersil Americas Inc. 2008, 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
KAD5510P-50
Ordering Information
PART NUMBER
(Note)
SPEED
(MSPS)
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PART MARKING
PKG. DWG. #
L72.10x10D
KAD5510P-50Q72
KAD5510P-50 Q72EP-I
500
-40 to +85
72 Ld QFN
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu
plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN6811.2
October 8, 2009
2
KAD5510P-50
Over-Range Indicator . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table of Contents
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Nap/Sleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Pin-Compatible Family. . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Key Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . 20
SPI Physical Interface. . . . . . . . . . . . . . . . . . . . . . . . . 20
SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Indexed Device Configuration/Control . . . . . . . . . . . . 21
Global Device Configuration/Control. . . . . . . . . . . . . . 22
Device Test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . 4
Thermal Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . .4
Digital Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Switching Specifications. . . . . . . . . . . . . . . . . . . . . . . . . 7
Pinout/Package Information . . . . . . . . . . . . . . . . . . . . . . 8
Equivalent Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
ADC Evaluation Platform . . . . . . . . . . . . . . . . . . . . . . . 26
Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . 26
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Split Ground and Power Planes . . . . . . . . . . . . . . . . . 26
Clock Input Considerations. . . . . . . . . . . . . . . . . . . . . 26
Exposed Paddle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Bypass and Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . 26
LVDS Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
LVCMOS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Unused Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . 11
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . 14
Power-On Calibration . . . . . . . . . . . . . . . . . . . . . . . . . 14
User Initiated Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Voltage Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Digital Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Revision History ........................................................... 28
Package Outline Drawings........................................... 29
L72.10x10D................................................................ 29
FN6811.2
October 8, 2009
3
KAD5510P-50
Absolute Maximum Ratings
Thermal Information
AVDD to AVSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V
OVDD to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V
AVSS to OVSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
Analog Inputs to AVSS. . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Clock Inputs to AVSS. . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Logic Inputs to AVSS . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Logic Inputs to OVSS. . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Thermal Resistance (Typical, Note 1)
θ
(°C/W)
24
JA
72 Ld QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
T
= -40°C to +85°C (typical specifications at +25°C), A = -1dBFS, f
= 500MSPS.
SAMPLE
A
IN
KAD5510P-50
(Note 2)
PARAMETER
DC SPECIFICATIONS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Analog Input
Full-Scale Analog Input Range
Input Resistance
V
Differential
Differential
Differential
Full Temp
1.40
1.47
500
1.9
90
1.54
V
P-P
FS
R
C
Ω
IN
IN
Input Capacitance
pF
ppm/°C
mV
Full Scale Range Temp. Drift
Input Offset Voltage
A
VTC
V
-10
±2
10
OS
Gain Error
E
±2
%
G
Common-Mode Output Voltage
Clock Inputs
V
435
535
635
mV
CM
Inputs Common Mode Voltage
CLKP,CLKN Input Swing
Power Requirements
1.8V Analog Supply Voltage
1.8V Digital Supply Voltage
1.8V Analog Supply Current
.9
V
V
1.8
AVDD
OVDD
1.7
1.7
1.8
1.8
171
58
1.9
1.9
178
65
V
V
I
I
mA
mA
dB
AVDD
1.8V Digital Supply Current (Note 3)
Power Supply Rejection Ratio
Total Power Dissipation
Normal Mode
3mA LVDS
OVDD
PSRR
30MHz, 200mV
-36
P-P
P
P
P
3mA LVDS
414
148
2
438
163
6
mW
mW
mW
µs
D
D
D
Nap Mode
Sleep Mode
CSB at logic high
Nap Mode Wakeup Time (Note 4)
Sleep Mode Wakeup Time (Note 4)
AC SPECIFICATIONS (Notes 5, 6)
Differential Nonlinearity
Sample Clock Running
Sample Clock Running
1
1
ms
DNL
INL
-0.5
±0.1
±0.2
0.5
0.75
80
LSB
LSB
Integral Nonlinearity
-0.75
Minimum Conversion Rate (Note 7)
Maximum Conversion Rate
f
MIN
MSPS
MSPS
S
f
MAX
500
S
FN6811.2
October 8, 2009
4
KAD5510P-50
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
T
= -40°C to +85°C (typical specifications at +25°C), A = -1dBFS, f
= 500MSPS. (Continued)
SAMPLE
A
IN
KAD5510P-50
(Note 2)
PARAMETER
Signal-to-Noise Ratio
SYMBOL
CONDITIONS
= 10MHz
MIN
TYP
60.7
60.7
60.6
60.5
59.9
59.0
60.7
60.6
60.5
60.4
57.5
49.3
9.8
MAX
UNITS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
SNR
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
= 105MHz
= 190MHz
= 364MHz
= 695MHz
= 995MHz
= 10MHz
59.5
Signal-to-Noise and Distortion
SINAD
ENOB
SFDR
IMD
= 105MHz
= 190MHz
= 364MHz
= 695MHz
= 995MHz
= 10MHz
59.3
Effective Number of Bits
= 105MHz
= 190MHz
= 364MHz
= 695MHz
= 995MHz
= 10MHz
9.6
9.8
Bits
9.8
Bits
9.7
Bits
9.3
Bits
7.9
Bits
Spurious-Free Dynamic Range
83.2
83.2
80.6
75.7
61.0
49.1
-91.0
-90.3
dBc
= 105MHz
= 190MHz
= 364MHz
= 695MHz
= 995MHz
= 70MHz
dBc
70
dBc
dBc
dBc
dBc
Intermodulation Distortion
dBc
= 170MHz
dBc
-12
10
Word Error Rate
Full Power Bandwidth
NOTES:
WER
FPBW
1.3
GHz
2. Parameters with Min and/or MAX limits are 100% production tested at their worst case temperature extreme ( +85°C).
3. Digital Supply Current is dependent upon the capacitive loading of the digital outputs. I
output.
specifications apply for 10pF load on each digital
OVDD
4. See “Nap/Sleep” on page 17 for more details.
5. AC Specifications apply after internal calibration of the ADC is invoked at the given sample rate and temperature. Refer to “Power-On Calibration”
on page 14 and “User Initiated Reset” on page 15 for more detail.
6. SFDR, SINAD and ENOB specifications apply after gain error and timing skew between ADC cores have been minimized through external
calibration.
7. The DLL Range setting must be changed for low speed operation. See Table 15 on page 23 for more detail.
FN6811.2
October 8, 2009
5
KAD5510P-50
Digital Specifications
PARAMETER
INPUTS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Current High (SDIO, RESETN)
Input Current Low (SDIO, RESETN)
Input Voltage High (SDIO, RESETN)
Input Voltage Low (SDIO, RESETN)
I
V
V
= 1.8V
0
1
10
-5
µA
µA
V
IH
IN
IN
I
= 0V
-25
1.17
-12
IL
V
IH
V
.63
40
V
IL
Input Current High (OUTMODE, NAPSLP,
CLKDIV, OUTFMT) (Note 8)
I
15
25
25
3
µA
IH
Input Current Low (OUTMODE, NAPSLP,
CLKDIV, OUTFMT)
I
-40
-15
µA
pF
IL
Input Capacitance
LVDS OUTPUTS
C
DI
Differential Output Voltage
Output Offset Voltage
Output Rise Time
Output Fall Time
V
620
965
500
500
mV
T
P-P
V
950
980
mV
OS
t
ps
ps
R
t
F
CMOS OUTPUTS
Voltage Output High
Voltage Output Low
Output Rise Time
Output Fall Time
V
I
I
= -500µA
= 1mA
OVDD - 0.3 OVDD - 0.1
V
V
OH
OH
OL
V
0.1
1.8
1.4
0.3
OL
t
ns
ns
R
t
F
Timing Diagrams
SAMPLE N
INP
SAMPLE N
INP
INN
INN
tA
tA
CLKN
CLKP
CLKN
CLKP
LATENCY = L CYCLES
LATENCY = L CYCLES
tCPD
tCPD
CLKOUTN
CLKOUTP
CLKOUTN
CLKOUTP
tDC
tPD
tDC
tPD
D[9:0]P
D[9:0]N
D[9:0]P
D[9:0]N
DATA
N-L
DATA
N-L+1
DATA
N-L+2
DATA
N
DATA
N-L
DATA
N-L+1
DATA
N-L+2
DATA
N
FIGURE 1. LVDS TIMING DIAGRAM (See “Digital Outputs” on
page 17)
FIGURE 2. CMOS TIMING DIAGRAM (See “Digital Outputs”
on page 17)
FN6811.2
October 8, 2009
6
KAD5510P-50
Switching Specifications
PARAMETER
CONDITION
SYMBOL
MIN
TYP
MAX
UNITS
ADC OUTPUT
Aperture Delay
t
375
60
ps
fs
A
RMS Aperture Jitter
j
A
Output Clock to Data Propagation Delay, Rising Edge
t
t
t
t
-260
-160
-220
-310
-50
10
120
230
200
110
ps
DC
DC
DC
LVDS Mode (Note 9)
Falling Edge
ps
Output Clock to Data Propagation Delay, Rising Edge
-10
-90
15
ps
CMOS Mode (Note 9)
Falling Edge
ps
DC
L
Latency (Pipeline Delay)
Overvoltage Recovery
cycles
cycles
t
1
OVR
SPI INTERFACE (Notes 10, 11)
t
SCLK Period
Write Operation
32
cycles
(Note 10)
CLK
CLK
Read Operation
Read or Write
Read or Write
Read or Write
Write
t
132
25
2
cycles
%
SCLK Duty Cycle (t /t
HI CLK
or t /t
LO CLK)
50
75
CSB↓ to SCLK↑ Setup Time
CSB↑ after SCLK↑ Hold Time
t
cycles
cycles
cycles
cycles
cycles
cycles
µs
S
t
6
H
Data Valid to SCLK↑ Setup Time
Data Valid after SCLK↑ Hold Time
Data Valid after SCLK↓ Time
Data Invalid after SCLK↑ Time
t
2
DSW
Write
t
6
DHW
Read
t
33
DVR
Read
t
6
DHR
Sleep Mode CSB↓ to SCLK↑ Setup Time Read or Write in Sleep Mode
t
150
S
(Note 12)
NOTES:
8. The Tri-Level Inputs internal switching thresholds are approximately 0.43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD
depending on desired function.
9. The input clock to output clock delay is a function of sample rate, using the output clock to latch the data simplifies data capture for most
applications. Contact factory for more info if needed.
10. SPI Interface timing is directly proportional to the ADC sample period (t ). (2ns at 500Msps)
S
11. The SPI may operate asynchronously with respect to the ADC sample clock.
12. The CSB setup time increases in sleep mode due to the reduced power state, CSB setup time in Nap mode is equal to normal mode CSB setup
time (4ns min).
FN6811.2
October 8, 2009
7
KAD5510P-50
Pinout/Package Information
Pin Descriptions
PIN NUMBER
LVDS [LVCMOS] NAME
LVDS [LVCMOS] FUNCTION
1, 6, 12, 19, 24, 71
AVDD
DNC
1.8V Analog Supply
2-5, 13, 14, 17, 18, 28-35
Do Not Connect
Analog Ground
7, 8, 11, 72
AVSS
9, 10
VINN, VINP
VCM
Analog Input Negative, Positive
Common Mode Output
15
16
CLKDIV
CLKP, CLKN
OUTMODE
NAPSLP
RESETN
OVSS
Clock Divider Control
20, 21
Clock Input True, Complement
Output Mode (LVDS, LVCMOS)
Power Control (Nap, Sleep modes)
Power On Reset (Active Low, See “User Initiated Reset” on page 15)
Output Ground
22
23
25
26, 45, 55, 65
27, 36, 56
37
OVDD
1.8V Output Supply
D0N
[NC]
LVDS Bit 0 (LSB) Output Complement
[NC in LVCMOS]
38
39
40
41
42
43
44
D0P
[D0]
LVDS Bit 0 (LSB) Output True
[ LVCMOS Bit 0]
D1N
[NC]
LVDS Bit 1 Output Complement
[NC in LVCMOS]
D1P
[D1]
LVDS Bit 1 Output True
[ LVCMOS Bit 1]
D2N
[NC]
LVDS Bit 2 Output Complement
[NC in LVCMOS]
D2P
[D2]
LVDS Bit 2 Output True
[ LVCMOS Bit 2]
D3N
[NC]
LVDS Bit 3 Output Complement
[NC in LVCMOS]
D3P
[D3]
LVDS Bit 3 Output True
[ LVCMOS Bit 3]
46
47
RLVDS
LVDS Bias Resistor (connect to OVSS with a 10kΩ, 1% resistor)
CLKOUTN
[NC]
LVDS Clock Output Complement
[NC in LVCMOS]
48
49
50
51
52
53
54
CLKOUTP
[CLKOUT]
LVDS Clock Output True
[LVCMOS CLKOUT]
D4N
[NC]
LVDS Bit 4 Output Complement
[NC in LVCMOS]
D4P
[D4]
LVDS Bit 4 Output True
[ LVCMOS Bit 4]
D5N
[NC]
LVDS Bit 5 Output Complement
[NC in LVCMOS]
D5P
[D5]
LVDS Bit 5 Output True
[ LVCMOS Bit 5]
D6N
[NC]
LVDS Bit 6 Output Complement
[NC in LVCMOS]
D6P
[D6]
LVDS Bit 6 Output True
[ LVCMOS Bit 6]
FN6811.2
October 8, 2009
8
KAD5510P-50
Pin Descriptions
PIN NUMBER
57
LVDS [LVCMOS] NAME
LVDS [LVCMOS] FUNCTION
LVDS Bit 7 Output Complement
D7N
[NC]
[NC in LVCMOS]
58
59
60
61
62
63
64
D7P
[D7]
LVDS Bit 7 Output True
[ LVCMOS Bit 7]
D8N
[NC]
LVDS Bit 8 Output Complement
[NC in LVCMOS]
D8P
[D8]
LVDS Bit 8 Output True
[ LVCMOS Bit 8]
D9N
[NC]
LVDS Bit 9 Output Complement
[NC in LVCMOS]
D9P
[D9]
LVDS Bit 9 Output True
[ LVCMOS Bit 9]
ORN
[NC]
LVDS Over Range Complement
[NC in LVCMOS]
ORP
[OR]
LVDS Over Range True
[LVCMOS Over Range]
66
SDO
CSB
SPI Serial Data Output (4.7kΩ pull-up to OVDD is required)
SPI Chip Select (active low)
67
68
SCLK
SDIO
SPI Clock
69
70
SPI Serial Data Input/Output
OUTFMT
AVSS
Output Data Format (Two’s Comp., Gray Code, Offset Binary)
Analog Ground
Exposed Paddle
NOTE: LVCMOS Output Mode Functionality is shown in brackets (NC = No Connection)
FN6811.2
October 8, 2009
9
KAD5510P-50
Pinout
KAD5510P-50
(72 LD QFN)
TOP VIEW
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
AVDD
DNC
1
2
54 D6P
D6N
53
52
51
50
49
48
47
46
45
44
43
42
41
3
DNC
D5P
4
DNC
D5N
5
DNC
D4P
6
AVDD
AVSS
AVSS
VINN
VINP
AVSS
AVDD
DNC
D4N
7
CLKOUTP
CLKOUTN
RLVDS
OVSS
D3P
8
9
10
11
12
13
14
D3N
D2P
DNC
D2N
15
16
17
40
39
38
VCM
D1P
CLKDIV
DNC
D1N
CONNECT THERMAL PAD TO AVSS
D0P
DNC 18
37 D0N
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
FIGURE 3. PIN CONFIGURATION
FN6811.2
October 8, 2009
10
KAD5510P-50
Typical Performance Curves All Typical Performance Characteristics apply under the following conditions
unless otherwise noted: AVDD = OVDD = 1.8V, T = +25°C, A = -1dBFS, f = 105MHz,
A
IN
IN
f
= 500MSPS.
SAMPLE
90
85
80
75
70
65
60
55
50
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
SFDR
HD3
HD2
SNR
0M
200M
400M
600M
800M
1G
0M
200M
400M
600M
800M
1G
INPUT FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
FIGURE 4. SNR AND SFDR vs f
FIGURE 5. HD2 AND HD3 vs f
IN
IN
100
-10
-20
SFDRFS (dBFS)
SFDR (dBc)
90
80
70
60
50
40
30
20
10
0
HD2 (dBc)
HD3 (dBc)
-30
SNRFS (dBFS)
-40
-50
-60
HD2 (dBFS)
-70
-80
SNR (dBc)
-90
-100
-110
HD3 (dBFS)
-50
-60-
50
-40
-30
-20-
10
0
-60
-40
-30
-20
-10
0
INPUT AMPLITUDE (dBFS)
INPUT AMPLITUDE (dBFS)
FIGURE 6. SNR AND SFDR vs A
FIGURE 7. HD2 AND HD3 vs A
IN
IN
90
-60
-70
SFDR
85
80
75
70
65
60
55
HD3
-80
-90
HD2
-100
-110
-120
SNR
300
325
350
375
400
425
450
475
500
300
325
350
375
400
425
450
475
500
SAMPLE RATE (MSPS)
SAMPLE RATE (MSPS)
FIGURE 8. SNR AND SFDR vs f
FIGURE 9. HD2 AND HD3 vs f
SAMPLE
SAMPLE
FN6811.2
October 8, 2009
11
KAD5510P-50
Typical Performance Curves All Typical Performance Characteristics apply under the following conditions
unless otherwise noted: AVDD = OVDD = 1.8V, T = +25°C, A = -1dBFS, f = 105MHz,
A
IN
IN
f
= 500MSPS. (Continued)
SAMPLE
450
400
350
300
250
200
150
100
50
0.25
0.20
0.15
0.10
0.05
0.00
-0.05
-0.10
-0.15
-0.20
-0.25
0
0
128
256
384
512
640
768
896
1024
80
140
200
260
320
380
440
500
CODE
SAMPLE RATE (MSPS)
FIGURE 11. DIFFERENTIAL NONLINEARITY
FIGURE 10. POWER vs f
IN 3mA LVDS MODE
SAMPLE
0.25
0.20
0.15
0.10
0.05
0.00
-0.05
-0.10
-0.15
-0.20
-0.25
90
85
80
75
70
65
60
55
50
SFDR
SNR
300
400
500
600
700
800
0
128
256
384
512
640
768
896
1024
CODE
INPUT COMMON MODE (mV)
FIGURE 12. INTEGRAL NONLINEARITY
FIGURE 13. SNR AND SFDR vs VCM
0
-20
1000000
Ain = -1.0dBFS
900000
800000
700000
600000
500000
400000
300000
200000
100000
0
SNR = 60.7dBFS
SFDR = 82.4dBc
SINAD = 60.6dBFS
-40
-60
-80
-100
-120
0M
50M
100M
150M
200M
250M
508 509 510 511 512
513 514 515 516 517
CODE
FREQUENCY (Hz)
FIGURE 14. NOISE HISTOGRAM
FIGURE 15. SINGLE-TONE SPECTRUM @ 105MHz
FN6811.2
October 8, 2009
12
KAD5510P-50
Typical Performance Curves All Typical Performance Characteristics apply under the following conditions
unless otherwise noted: AVDD = OVDD = 1.8V, T = +25°C, A = -1dBFS, f = 105MHz,
A
IN
IN
f
= 500MSPS. (Continued)
SAMPLE
0
-20
0
A
= -1.0dBFS
IN
A
= -1.0dBFS
IN
SNR = 60.5dBFS
SFDR = 77.7dBc
SINAD = 60.4dBFS
SNR = 60.2dBFS
SFDR = 69.4dBc
SINAD = 59.8dBFS
-20
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
0M
50M
100M
150M
200M
250M
0M
50M
100M
150M
200M
250M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 17. SINGLE-TONE SPECTRUM @ 495MHz
FIGURE 16. SINGLE-TONE SPECTRUM @ 190MHz
0
-20
-40
-60
-80
0
IMD = -91.0dBFS
A
= -1.0dBFS
IN
SNR = 58.7dBFS
SFDR = 49.6dBc
SINAD = 49.7dBFS
-20
-40
-60
-80
-100
-120
-100
-120
0M
50M
100M
150M
200M
250M
0M
50M
100M
150M
200M
250M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 19. TWO-TONE SPECTRUM @ 70MHz
FIGURE 18. SINGLE-TONE SPECTRUM @ 995MHz
0
IMD = -90.3dBFS
-20
-40
-60
-80
-100
-120
0M
50M
100M
150M
200M
250M
FREQUENCY (Hz)
FIGURE 20. TWO-TONE SPECTRUM @ 170MHz
FN6811.2
October 8, 2009
13
KAD5510P-50
The design of the KAD5510P-50 minimizes the effect of
Theory of Operation
process, voltage and temperature variations on the matching
characteristics of the two unit ADCs. The gain and offset of
the two unit ADCs are adjusted after power-on calibration to
minimize the mismatch between the channels. All calibration
is performed using internally generated signals, with the
analog input signal disconnected from the sample and hold
amplifier (SHA).
Functional Description
The KAD5510P-50 is based upon a 10-bit, 250MSPS A/D
converter core that utilizes a pipelined successive
approximation architecture (Figure 21). The input voltage is
captured by a Sample-Hold Amplifier (SHA) and converted
to a unit of charge. Proprietary charge-domain techniques
are used to successively compare the input to a series of
reference charges. Decisions made during the successive
approximation operations determine the digital code for each
input value. The converter pipeline requires twelve samples
to produce a result. Digital error correction is also applied,
resulting in a total latency of fifteen clock cycles. This is
evident to the user as a latency between the start of a
conversion and the data being available on the digital
outputs.
The KAD5510P-50 does not have the ability to adjust timing
skew mismatches as part of the internal calibration
sequence. Clock routing to each unit ADC is carefully
matched, however some timing skew will exist that may
result in a detectable fundamental image spur at f
NYQUIST
± f
.
IN
Power-On Calibration
As mentioned previously, the cores perform a self-calibration
at start-up. An internal power-on-reset (POR) circuit detects
the supply voltage ramps and initiates the calibration when
the analog and digital supply voltages are above a threshold.
The following conditions must be adhered to for the
power-on calibration to execute successfully:
The device contains two units A/D converters with carefully
matched transfer characteristics. The cores are clocked on
alternate clock edges, resulting in a doubling of the sample
rate. The gain, offset and skew errors between the two unit
ADCs can be adjusted via the SPI port to minimize spurs
associated with the interleaving process.
• A frequency-stable conversion clock must be applied to
the CLKP/CLKN pins
Time–interleaved ADC systems can exhibit non–ideal
artifacts in the frequency domain if the individual unit ADC
characteristics are not well matched. Gain, offset and timing
skew mismatches are of primary concern.
• DNC pins (especially 3, 4 and 18) must not be pulled up or
down
• SDO (pin 66) must be high
Gain mismatch results in fundamental image spurs at
• RESETN (pin 25) must begin low
• SPI communications must not be attempted
f
± f . Mismatches in timing skew, which shift the
NYQUIST
IN
sampling instances for the two unit ADCs, will result in spurs
in the same locations. Offset mismatches create spurs at DC
A user-initiated reset can subsequently be invoked in the
event that the above conditions cannot be met at power-up.
and multiples of f
.
NYQUIST
CLOCK
GENERATION
INP
2.5-BIT
FLASH
6-STAGE
1.5-BIT/STAGE
3-STAGE
1-BIT/STAGE
3-BIT
FLASH
SHA
INN
+
–
1.25V
DIGITAL
ERROR
CORRECTION
LVDS/LVCMOS
OUTPUTS
FIGURE 21. ADC CORE BLOCK DIAGRAM
FN6811.2
October 8, 2009
14
KAD5510P-50
The SDO pin requires an external 4.7kΩ pull-up to OVDD. If
the SDO pin is pulled low externally during power-up,
calibration will not be executed properly.
A supply voltage variation of less than 100mV will generally
result in an SNR change of less than 0.1dBFS and SFDR
change of less than 3dBc.
After the power supply has stabilized the internal POR
releases RESETN and an internal pull-up pulls it high, which
starts the calibration sequence. If a subsequent
user-initiated reset is required, the RESETN pin should be
connected to an open-drain driver with a drive strength of
less than 0.5mA.
In situations where the sample rate is not constant, best
results will be obtained if the device is calibrated at the
highest sample rate. Reducing the sample rate by less than
80MSPS will typically result in an SNR change of less than
0.1dBFS and an SFDR change of less than 3dBc.
Figures 23 and 24 show the effect of temperature on SNR
and SFDR performance with calibration performed at -40°C,
+25°C, and +85°C. Each plot shows the variation of
SNR/SFDR across temperature after a single calibration at
-40°C, +25°C and +85°C. Best performance is typically
achieved by calibration at the operating conditions as stated
earlier but it can be seen that performance drift with
temperature is not a very strong function of the temperature
at which the calibration is performed.
The calibration sequence is initiated on the rising edge of
RESETN, as shown in Figure 22. The over-range output
(OR) is set high once RESETN is pulled low, and remains in
that state until calibration is complete. The OR output returns
to normal operation at that time, so it is important that the
analog input be within the converter’s full-scale range to
observe the transition. If the input is in an over-range
condition the OR pin will stay high, and it will not be possible
to detect the end of the calibration cycle.
While RESETN is low, the output clock
3
CAL DONE AT
(CLKOUTP/CLKOUTN) is set low. Normal operation of the
output clock resumes at the next input clock edge
(CLKP/CLKN) after RESETN is deasserted. At 500MSPS
the nominal calibration time is 200ms, while the maximum
calibration time is 550ms.
2
+85°C
1
0
-1
CAL DONE AT
+25°C
-2
-3
-4
CLKN
CLKP
CAL DONE AT
-40°C
CALIBRATION
TIME
-40
-15
10
35
60
85
RESETN
TEMPERATURE (°C)
CALIBRATION
BEGINS
FIGURE 23. SNR PERFORMANCE vs TEMPERATURE
ORP
15
CALIBRATION
COMPLETE
CAL DONE AT
10
CLKOUTP
-40°C
5
FIGURE 22. CALIBRATION TIMING
0
User Initiated Reset
-5
Recalibration of the ADC can be initiated at any time by
driving the RESETN pin low for a minimum of one clock
cycle. An open-drain driver with a drive strength of less than
0.5mA is recommended, RESETN has an internal high
impedance pull-up to OVDD. As is the case during power-on
reset, the SDO, RESETN and DNC pins must be in the
proper state for the calibration to successfully execute.
CAL DONE AT
+25°C
CAL DONE AT
+85°C
-10
-15
-40
-15
10
35
60
85
TEMPERATURE (°C)
FIGURE 24. SFDR PERFORMANCE vs TEMPERATURE
Analog Input
The performance of the KAD5510P-50 changes with
variations in temperature, supply voltage or sample rate. The
extent of these changes may necessitate recalibration,
depending on system performance requirements. Best
performance will be achieved by recalibrating the ADC under
the environmental conditions at which it will operate.
A single fully differential input (VINP/VINN) connects to the
sample and hold amplifier (SHA) of each unit ADC. The ideal
full-scale input voltage is 1.45V, centered at the VCM voltage
of 0.535V as shown in Figure 25.
FN6811.2
October 8, 2009
15
KAD5510P-50
Ω
348O
1.8
1.4
1.0
0.6
0.2
Ω
69.8O
Ω
25O
Ω
100O
INN
INP
217OΩ
KAD5510P-50
VCM
0.725V
CM
VCM
Ω
100O
0.22µF
0.535V
25OΩ
Ω
49.9O
Ω
69.8O
0.1µF
348OΩ
FIGURE 28. DIFFERENTIAL AMPLIFIER INPUT
FIGURE 25. ANALOG INPUT RANGE
A differential amplifier, as shown in Figure 28, can be used in
applications that require DC-coupling. In this configuration
the amplifier will typically dominate the achievable SNR and
distortion performance.
Best performance is obtained when the analog inputs are
driven differentially. The common-mode output voltage,
VCM, should be used to properly bias the inputs as shown in
Figures 26 through 28. An RF transformer will give the best
noise and distortion performance for wideband and/or high
intermediate frequency (IF) inputs. Two different transformer
input schemes are shown in Figures 26 and 27.
Clock Input
The clock input circuit is a differential pair (see Figure 42).
Driving these inputs with a high level (up to 1.8V
on each
P-P
input) sine or square wave will provide the lowest jitter
performance. A transformer with 4:1 impedance ratio will
provide increased drive levels.
ADT1-1WT
ADT1-1WT
1000pF
KAD5510P-50
VCM
The recommended drive circuit is shown in Figure 29. A
duty range of 40% to 60% is acceptable. The clock can be
driven single-ended, but this will reduce the edge rate and
may impact SNR performance. The clock inputs are
internally self-biased to AVDD/2 to facilitate AC-coupling.
0.1µF
Ω
1k
Ω
1k
FIGURE 26. TRANSFORMER INPUT FOR GENERAL
PURPOSE APPLICATIONS
AVDD
200pF
TC4-1W
CLKP
CLKN
1000pF
ADTL1-12 ADTL1-12
200pF
Ω
200
0.1µF
1000pF
KAD5510P-50
VCM
1000pF
200pF
FIGURE 29. RECOMMENDED CLOCK DRIVE
FIGURE 27. TRANSMISSION-LINE TRANSFORMER INPUT
FOR HIGH IF APPLICATIONS
A selectable 2x frequency divider is provided in series with
the clock input. The divider can be used in the 2x mode with
a sample clock equal to twice the desired sample rate. This
allows the use of the Phase Slip feature, which enables
synchronization of multiple ADCs.
This dual transformer scheme is used to improve
common-mode rejection, which keeps the common-mode
level of the input matched to VCM. The value of the shunt
resistor should be determined based on the desired load
impedance. The differential input resistance of the
KAD5510P-50 is 500Ω.
TABLE 1. CLKDIV PIN SETTINGS
The SHA design uses a switched capacitor input stage
(see Figure 41), which creates current spikes when the
sampling capacitance is reconnected to the input voltage.
This causes a disturbance at the input which must settle
before the next sampling point. Lower source impedance will
result in faster settling and improved performance. Therefore
a 1:1 transformer and low shunt resistance are
CLKDIV PIN
AVSS
DIVIDE RATIO
2
Float
1
AVDD
Not Allowed
The clock divider can also be controlled through the SPI
port, which overrides the CLKDIV pin setting. Details on this
are contained in “Serial Peripheral Interface” on page 20.
recommended for optimal performance.
FN6811.2
October 8, 2009
16
KAD5510P-50
The output mode and LVDS drive current are selected via
Jitter
the OUTMODE pin as shown in Table 2.
In a sampled data system, clock jitter directly impacts the
achievable SNR performance. The theoretical relationship
TABLE 2. OUTMODE PIN SETTINGS
between clock jitter (t ) and SNR is shown in Equation 1 and
J
OUTMODE PIN
AVSS
MODE
is illustrated in Figure 30.
1
LVCMOS
⎛
⎝
⎞
⎠
-------------------
SNR = 20 log
(EQ. 1)
10
2πf
t
Float
LVDS, 3mA
LVDS, 2mA
IN J
AVDD
100
95
90
85
80
75
70
65
60
The output mode can also be controlled through the SPI
port, which overrides the OUTMODE pin setting. Details on
this are contained in “Serial Peripheral Interface” on
page 20.
tj = 0.1ps
14 BITS
tj = 1ps
12 BITS
An external resistor creates the bias for the LVDS drivers. A
10kΩ, 1% resistor must be connected from the RLVDS pin to
OVSS.
tj = 10ps
10 BITS
tj = 100ps
55
50
Over-Range Indicator
The over-range (OR) bit is asserted when the output code
reaches positive full-scale (e.g. 0xFFF in offset binary
mode). The output code does not wrap around during an
over-range condition. The OR bit is updated at the sample
rate.
1M
10M
100M
1G
INPUT FREQUENCY (Hz)
FIGURE 30. SNR vs CLOCK JITTER
This relationship shows the SNR that would be achieved if
clock jitter were the only non-ideal factor. In reality,
achievable SNR is limited by internal factors such as
linearity, aperture jitter and thermal noise. Internal aperture
jitter is the uncertainty in the sampling instant shown in
Figure 1. The internal aperture jitter combines with the input
clock jitter in a root-sum-square fashion, since they are not
statistically correlated, and this determines the total jitter in
the system. The total jitter, combined with other noise
sources, then determines the achievable SNR.
Power Dissipation
The power dissipated by the KAD5510P-50 is primarily
dependent on the sample rate and the output modes: LVDS
vs CMOS and DDR vs SDR. There is a static bias in the
analog supply, while the remaining power dissipation is
linearly related to the sample rate. The output supply
dissipation changes to a lesser degree in LVDS mode, but is
more strongly related to the clock frequency in CMOS mode.
Voltage Reference
Nap/Sleep
A temperature compensated voltage reference provides the
reference charges used in the successive approximation
operations. The full-scale range of each A/D is proportional
to the reference voltage. The nominal value of the voltage
reference is 1.25V.
Portions of the device may be shut down to save power during
times when operation of the ADC is not required. Two power
saving modes are available: Nap, and Sleep. Nap mode
reduces power dissipation to less than 163mW and recovers
to normal operation in approximately 1µs. Sleep mode
reduces power dissipation to less than 6mW but requires
approximately 1ms to recover from a sleep command.
Digital Outputs
Output data is available as a parallel bus in
LVDS-compatible or CMOS modes. In either case, the data
is presented in double data rate (DDR) format. Figures 1
and 2 show the timing relationships for LVDS and CMOS
modes, respectively.
Wake-up time from sleep mode is dependent on the state of
CSB; in a typical application CSB would be held high during
sleep, requiring a user to wait 150µs max after CSB is
asserted (brought low) prior to writing ‘001x’ to SPI
Register 25. The device would be fully powered up, in
normal mode 1ms after this command is written.
Additionally, the drive current for LVDS mode can be set to a
nominal 3mA or a power-saving 2mA. The lower current
setting can be used in designs where the receiver is in close
physical proximity to the ADC. The applicability of this setting
is dependent upon the PCB layout, therefore the user
should experiment to determine if performance degradation
is observed.
Wake-up from Sleep Mode Sequence (CSB high)
• Pull CSB Low
• Wait 150µs
• Write ‘001x’ to Register 25
• Wait 1ms until ADC fully powered on
FN6811.2
October 8, 2009
17
KAD5510P-50
In an application where CSB was kept low in sleep mode, the
position and the next most significant bit. Figure 31 shows
this operation.
150µs CSB setup time is not required as the SPI registers are
powered on when CSB is low, the chip power dissipation
increases by ~ 15mW in this case. The 1ms wake-up time
after the write of a ‘001x’ to register 25 still applies. It is
generally recommended to keep CSB high in sleep mode to
avoid any unintentional SPI activity on the ADC
BINARY
9
8
7
1
0
• • • •
• • • •
• • • •
All digital outputs (Data, CLKOUT and OR) are placed in a
high impedance state during Nap or Sleep. The input clock
should remain running and at a fixed frequency during Nap
or Sleep, and CSB should be high. Recovery time from Nap
mode will increase if the clock is stopped, since the internal
DLL can take up to 52µs to regain lock at 250MSPS.
GRAY CODE
9
8
7
1
0
FIGURE 31. BINARY TO GRAY CODE CONVERSION
Converting back to offset binary from Gray code must be
done recursively, using the result of each bit for the next
lower bit as shown in Figure 32.
By default after the device is powered on, the operational
state is controlled by the NAPSLP pin as shown in Table 3.
TABLE 3. NAPSLP PIN SETTINGS
GRAY CODE
9
8
7
1
0
• • • •
NAPSLP PIN
AVSS
MODE
Normal
Sleep
Nap
Float
AVDD
• • • •
• • • •
• • • •
The power-down mode can also be controlled through the
SPI port, which overrides the NAPSLP pin setting. Details on
this are contained in “Serial Peripheral Interface” on
page 20. This is an indexed function when controlled from
the SPI, but a global function when driven from the pin.
Data Format
Output data can be presented in three formats: two’s
complement, Gray code and offset binary. The data format is
selected via the OUTFMT pin as shown in Table 4.
TABLE 4. OUTFMT PIN SETTINGS
BINARY
9
8
7
1
0
OUTFMT PIN
AVSS
MODE
Offset Binary
Two’s Complement
Gray Code
FIGURE 32. GRAY CODE TO BINARY CONVERSION
Mapping of the input voltage to the various data formats is
shown in Table 5.
Float
AVDD
TABLE 5. INPUT VOLTAGE TO OUTPUT CODE MAPPING
The data format can also be controlled through the SPI port,
which overrides the OUTFMT pin setting. Details on this are
contained in “Serial Peripheral Interface” on page 20.
INPUT
VOLTAGE
OFFSET
BINARY
TWO’S
COMPLEMENT
GRAY CODE
000 00 000 00
000 00 000 01
–Full Scale 000 00 000 00
100 00 000 00
100 00 000 01
Offset binary coding maps the most negative input voltage to
code 0x000 (all zeros) and the most positive input to 0xFFF
(all ones). Two’s complement coding simply complements
the MSB of the offset binary representation.
–Full Scale 000 00 000 01
+ 1LSB
Mid–Scale 100 00 000 00
000 00 000 00
011 11 111 10
110 00 000 00
100 00 000 01
+Full Scale
– 1LSB
111 11 111 10
When calculating Gray code, the MSB is unchanged. The
remaining bits are computed as the XOR of the current bit
+Full Scale
111 11 111 11
011 11 111 11
100 00 000 00
FN6811.2
October 8, 2009
18
KAD5510P-50
CSB
SCLK
SDIO
R/W
W1
W0
A12
A11
A10
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
FIGURE 33. MSB-FIRST ADDRESSING
CSB
SCLK
SDIO
A0
A1
A2
A11
A12
W0
W1
R/W
D0
D1
D2
D3
D4
D5
D6
D7
FIGURE 34. LSB-FIRST ADDRESSING
t
DSW
t
t
t
CLK
HI
H
t
DHW
CSB
t
t
S
LO
SCLK
SDIO
R/W W1 W0 A12 A11 A10 A9
A8
A7
D0
D5
D4
D3
D2
D1
SPI WRITE
FIGURE 35. SPI WRITE
t
DSW
t
t
t
CLK
HI
H
t
DHW
t
t
CSB
t
S
DVR
DHR
t
LO
SCLK
WRITING A READ COMMAND
R/W W1 W0 A12 A11 A10 A9 A2 A1 A0
READING DATA
(3 WIRE MODE)
SDIO
SDO
D3
D7 D6
D7
D2
D1 D0
(4 WIRE MODE)
D3 D2 D1 D0
SPI READ
FIGURE 36. SPI READ
FN6811.2
October 8, 2009
19
KAD5510P-50
CSB STALLING
CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD 2
FIGURE 37. 2-BYTE TRANSFER
LAST LEGAL
CSB STALLING
CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD N
FIGURE 38. N-BYTE TRANSFER
The chip-select bar (CSB) pin determines when a slave
device is being addressed. Multiple slave devices can be
written to concurrently, but only one slave device can be
read from at a given time (again, only in three-wire mode). If
multiple slave devices are selected for reading at the same
time, the results will be indeterminate.
Serial Peripheral Interface
A serial peripheral interface (SPI) bus is used to facilitate
configuration of the device and to optimize performance. The
SPI bus consists of chip select (CSB), serial clock (SCLK)
serial data input (SDI), and serial data input/output (SDIO).
The maximum SCLK rate is equal to the ADC sample rate
(f
) divided by 32 for write operations and f
The communication protocol begins with an
SAMPLE
SAMPLE
divided by 132 for reads. At f
SAMPLE
SCLK is 15.63MHz for writing and 3.79MHz for read
operations. There is no minimum SCLK rate.
= 250MHz, maximum
instruction/address phase. The first rising SCLK edge
following a high to low transition on CSB determines the
beginning of the two-byte instruction/address command;
SCLK must be static low before the CSB transition Data can
be presented in MSB-first order or LSB-first order. The
default is MSB-first, but this can be changed by setting
0x00[6] high. Figures 33 and 34 show the appropriate bit
ordering for the MSB-first and LSB-first modes, respectively.
In MSB-first mode the address is incremented for multi-byte
transfers, while in LSB-first mode it’s decremented.
The following sections describe various registers that are
used to configure the SPI or adjust performance or functional
parameters. Many registers in the available address space
(0x00 to 0xFF) are not defined in this document. Additionally,
within a defined register there may be certain bits or bit
combinations that are reserved. Undefined registers and
undefined values within defined registers are reserved and
should not be selected. Setting any reserved register or value
may produce indeterminate results.
In the default mode the MSB is R/W, which determines if the
data is to be read (active high) or written. The next two bits,
W1 and W0, determine the number of data bytes to be read
or written (see Table 6). The lower 13 bits contain the first
address for the data transfer. This relationship is illustrated in
Figure 35, and timing values are given in “Switching
Specifications” on page 7.
SPI Physical Interface
The serial clock pin (SCLK) provides synchronization for the
data transfer. By default, all data is presented on the serial
data input/output (SDIO) pin in three-wire mode. The state of
the SDIO pin is set automatically in the communication
protocol (described in the following paragraphs). A dedicated
serial data output pin (SDO) can be activated by setting
0x00[7] high to allow operation in four-wire mode.
After the instruction/address bytes have been read, the
appropriate number of data bytes are written to or read from
the ADC (based on the R/W bit status). The data transfer will
continue as long as CSB remains low and SCLK is active.
Stalling of the CSB pin is allowed at any byte boundary
(instruction/address or data) if the number of bytes being
transferred is three or less. For transfers of four bytes or
more, CSB is allowed stall in the middle of the
The SPI port operates in a half duplex master/slave
configuration, with the KAD5510P-50 functioning as a slave.
Multiple slave devices can interface to a single master in
three-wire mode only, since the SDO output of an
unaddressed device is asserted in four wire mode.
instruction/address bytes or before the first data byte. If CSB
FN6811.2
October 8, 2009
20
KAD5510P-50
transitions to a high state after that point the state machine
Indexed Device Configuration/Control
will reset and terminate the data transfer.
ADDRESS 0X10: DEVICE_INDEX_A
TABLE 6. BYTE TRANSFER SELECTION
Bits 1:0 ADC01, ADC00
[W1:W0]
BYTES TRANSFERRED
Determines which ADC is addressed. Valid states for this
register are 0x01 or 0x10. The two ADC cores cannot be
adjusted concurrently.
00
01
10
11
1
2
3
A common SPI map, which can accommodate single-channel
or multi-channel devices, is used for all Intersil ADC products.
Certain configuration commands (identified as Indexed in the
SPI map) can be executed on a per-converter basis. This
register determines which converter is being addressed for an
Indexed command. It is important to note that only a single
converter can be addressed at a time.
4 or more
Figures 37 and 38 illustrate the timing relationships for
2-byte and N-byte transfers, respectively. The operation for a
3-byte transfer can be inferred from these diagrams.
SPI Configuration
This register defaults to 00h, indicating that no ADC is
addressed. Error code ‘AD’ is returned if any indexed register
is read from without properly setting device_index_A.
ADDRESS 0X00: CHIP_PORT_CONFIG
Bit ordering and SPI reset are controlled by this register. Bit
order can be selected as MSB to LSB (MSB first) or LSB to
MSB (LSB first) to accommodate various microcontrollers.
ADDRESS 0X20: OFFSET_COARSE
ADDRESS 0X21: OFFSET_FINE
Bit 7 SDO Active
Bit 6 LSB First
The input offset of the ADC core can be adjusted in fine and
coarse steps. Both adjustments are made via an 8-bit word
as detailed in Table 7. The data format is two’s complement.
Setting this bit high configures the SPI to interpret serial
data as arriving in LSB to MSB order.
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented
value back to the same register.
Bit 5 Soft Reset
Setting this bit high resets all SPI registers to default
values.
Bit 4 Reserved
TABLE 7. OFFSET ADJUSTMENTS
This bit should always be set high.
0x20[7:0]
0x21[7:0]
Bits 3:0 These bits should always mirror bits 4:7 to avoid
ambiguity in bit ordering.
PARAMETER
Steps
COARSE OFFSET
FINE OFFSET
255
255
ADDRESS 0X02: BURST_END
-Full Scale (0x00)
Mid–Scale (0x80)
+Full Scale (0xFF)
Nominal Step Size
-133LSB (-47mV)
0.0LSB (0.0mV)
+133LSB (+47mV)
1.04LSB (0.37mV)
-5LSB (-1.75mV)
0.0LSB
If a series of sequential registers are to be set, burst mode
can improve throughput by eliminating redundant addressing.
In 3-wire SPI mode the burst is ended by pulling the CSB pin
high. If the device is operated in 2-wire mode the CSB pin is
not available. In that case, setting the burst_end address
determines the end of the transfer. During a write operation,
the user must be cautious to transmit the correct number of
bytes based on the starting and ending addresses.
+5LSB (+1.75mV)
0.04LSB (0.014mV)
ADDRESS 0X22: GAIN_COARSE
ADDRESS 0X23: GAIN_MEDIUM
ADDRESS 0X24: GAIN_FINE
Bits 7:0 Burst End Address
Gain of the ADC core can be adjusted in coarse, medium and
fine steps. Coarse gain is a 4-bit adjustment while medium
and fine are 8-bit. Multiple Coarse Gain Bits can be set for a
total adjustment range of ± 4.2%. ( ‘0011’ ≅ -4.2% and ‘1100’
≅ +4.2% ) It is recommended to use one of the coarse gain
settings (-4.2%, -2.8%, -1.4%, 0, 1.4%, 2.8%, 4.2%) and
fine-tune the gain using the registers at 23h and 24h.
This register value determines the ending address of the
burst data.
Device Information
ADDRESS 0X08: CHIP_ID
ADDRESS 0X09: CHIP_VERSION
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
The generic die identifier and a revision number,
respectively, can be read from these two registers.
FN6811.2
October 8, 2009
21
KAD5510P-50
register value then write the incremented or decremented
value back to the same register.
ADDRESS 0X71: PHASE_SLIP
When using the clock divider, it’s not possible to determine the
synchronization of the incoming and divided clock phases.
This is particularly important when multiple ADCs are used in
a time-interleaved system. The phase slip feature allows the
rising edge of the divided clock to be advanced by one input
clock cycle when in CLK/2 mode, as shown in Figure 39.
Execution of a phase_slip command is accomplished by first
writing a ‘0’ to bit 0 at address 71h followed by writing a ‘1’ to
bit 0 at address 71h (32 sclk cycles.)
TABLE 8. COARSE GAIN ADJUSTMENT
NOMINAL COARSE GAIN ADJUST
(%)
0x22[3:0]
Bit3
+2.8
+1.4
-2.8
-1.4
Bit2
Bit1
Bit0
CLK
TABLE 9. MEDIUM AND FINE GAIN ADJUSTMENTS
1.00ns
0x23[7:0]
0x24[7:0]
PARAMETER
Steps
MEDIUM GAIN
FINE GAIN
CLKℜ÷
256
-2%
256
2.00ns
–Full Scale (0x00)
Mid–Scale (0x80)
+Full Scale (0xFF)
Nominal Step Size
-0.20%
0.00%
ADC0 CLOCK
0.00%
+2%
+0.2%
0.0016%
ADC1 CLOCK
0.016%
4.00ns
ADDRESS 0X25: MODES
ADC0 CLOCK
SLIP ONCE
Two distinct reduced power modes can be selected. By
default, the tri-level NAPSLP pin can select normal
operation, nap or sleep modes (refer to “Nap/Sleep” on
page 17). This functionality can be overridden and controlled
through the SPI. This is an indexed function when controlled
from the SPI, but a global function when driven from the pin.
This register is not changed by a Soft Reset.
ADC1 CLOCK
SLIP ONCE
ADC0 CLOCK
SLIP TWICE
ADC1 CLOCK
SLIP TWICE
TABLE 10. POWER-DOWN CONTROL
0x25[2:0]
FIGURE 39. PHASE SLIP: CLK÷2 MODE, f
= 1000MHz
CLOCK
VALUE
POWER-DOWN MODE
ADDRESS 0X72: CLOCK_DIVIDE
000
Pin Control
The KAD5510P-50 has a selectable clock divider that can be
set to divide by two or one (no division). By default, the
tri-level CLKDIV pin selects the divisor (refer to “Clock Input
Considerations” on page 26). This functionality can be
overridden and controlled through the SPI, as shown in
Table 12. This register is not changed by a Soft Reset.
001
Normal Operation
Nap Mode
010
100
Sleep Mode
Global Device Configuration/Control
TABLE 12. CLOCK DIVIDER SELECTION
ADDRESS 0X70: SKEW_DIFF
0x72[2:0]
The value in the skew_diff register adjusts the timing skew
between the two ADCs cores. The nominal range and
resolution of this adjustment are given in Table 11. The
default value of this register after power-up is 80h.
VALUE
000
CLOCK DIVIDER
Pin Control
001
Divide by 1
TABLE 11. DIFFERENTIAL SKEW ADJUSTMENT
010
Divide by 2
0x70[7:0]
DIFFERENTIAL SKEW
100
Not Allowed
PARAMETER
Steps
256
-6.5ps
0.0ps
+6.5ps
51fs
ADDRESS 0X73: OUTPUT_MODE_A
–Full Scale (0x00)
Mid–Scale (0x80)
+Full Scale (0xFF)
Nominal Step Size
The output_mode_A register controls the physical output
format of the data, as well as the logical coding. The
KAD5510P-50 can present output data in two physical
formats: LVDS or LVCMOS. Additionally, the drive strength
FN6811.2
October 8, 2009
22
KAD5510P-50
in LVDS mode can be set high (3mA) or low (2mA). By
The procedure for setting output_mode_B is shown in
Figure 40. Read the contents of output_mode_B and
config_status and XOR them. Then XOR this result with the
desired value for output_mode_B and write that XOR result
to the register.
default, the tri-level OUTMODE pin selects the mode and
drive level (refer to “Digital Outputs” on page 17). This
functionality can be overridden and controlled through the
SPI, as shown in Table 13.
Device Test
Data can be coded in three possible formats: two’s
complement, Gray code or offset binary. By default, the
tri-level OUTFMT pin selects the data format (refer to “Data
Format” on page 18). This functionality can be overridden
and controlled through the SPI, as shown in Table 14.
The KAD5510P-50 can produce preset or user defined
patterns on the digital outputs to facilitate in-situ testing. A
static word can be placed on the output bus, or two different
words can alternate. In the alternate mode, the values
defined as Word 1 and Word 2 (as shown in Table 16) are
set on the output bus on alternating clock phases. The test
mode is enabled asynchronously to the sample clock,
therefore several sample clock cycles may elapse before the
data is present on the output bus.
This register is not changed by a Soft Reset.
TABLE 13. OUTPUT MODE CONTROL
VALUE
000
0x93[7:5]
Pin Control
LVDS 2mA
LVDS 3mA
LVCMOS
ADDRESS 0XC0: TEST_IO
001
010
Bits 7:6 User Test Mode
100
These bits set the test mode to static (0x00) or alternate
(0x01) mode. Other values are reserved.
TABLE 14. OUTPUT FORMAT CONTROL
0x93[2:0]
The four LSBs in this register (Output Test Mode) determine
the test pattern in combination with registers 0xC2 through
0xC5. Refer to “” on page 24.
VALUE
OUTPUT FORMAT
TABLE 16. OUTPUT TEST MODES
000
Pin Control
001
Two’s Complement
Gray Code
0xC0[3:0]
OUTPUT TEST
010
VALUE
0000
0001
0010
0011
0100
0101
0110
0111
MODE
WORD 1
WORD 2
100
Offset Binary
Off
Midscale
0x8000
0xFFFF
0x0000
0xAAAA
N/A
N/A
N/A
ADDRESS 0X74: OUTPUT_MODE_B
ADDRESS 0X75: CONFIG_STATUS
Bit 6 DLL Range
Positive Full-Scale
Negative Full-Scale
Checkerboard
Reserved
N/A
0x5555
N/A
This bit sets the DLL operating range to fast (default) or
slow.
Reserved
N/A
N/A
Internal clock signals are generated by a delay-locked loop
(DLL), which has a finite operating range. Table 15 shows the
allowable sample rate ranges for the slow and fast settings.
TABLE 15. DLL RANGES
One/Zero
0xFFFF
user_patt1
0x0000
user_patt2
1000
User Pattern
ADDRESS 0XC2: USER_PATT1_LSB
ADDRESS 0XC3: USER_PATT1_MSB
DLL RANGE
Slow
MIN
80
MAX
200
UNIT
MSPS
MSPS
These registers define the lower and upper eight bits,
respectively, of the first user-defined test word.
Fast
160
500
The output_mode_B and config_status registers are used in
conjunction to enable DDR mode and select the frequency
range of the DLL clock generator. The method of setting
these options is different from the other registers.
ADDRESS 0XC4: USER_PATT2_LSB
ADDRESS 0XC5: USER_PATT2_MSB
These registers define the lower and upper eight bits,
respectively, of the second user-defined test word.
READ
OUTPUT_MODE_B
0x74
READ
CONFIG_STATUS
WRITE TO
0x74
0x75
DESIRED
VALUE
FIGURE 40. SETTING OUTPUT_MODE_B REGISTER
FN6811.2
October 8, 2009
23
KAD5510P-50
TABLE 17. SPI MEMORY MAP
Addr
(Hex)
Parameter
Name
Bit 7
(MSB)
Bit 0
(LSB)
Def. Value
(Hex)
Indexed/
Global
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
00
port_config
SDO
Active
LSB
First
Soft
Reset
Mirror
(bit5)
Mirror
(bit6)
Mirror
(bit7)
00h
G
01
02
Reserved
burst_end
Reserved
Burst end address [7:0]
Reserved
00h
G
03-07
08
Reserved
chip_id
Chip ID #
Read only
Read only
00h
G
G
I
09
chip_version
device_index_A
Reserved
Chip Version #
10
Reserved
ADC01 ADC00
11-1F
20
Reserved
Coarse Offset
Fine Offset
offset_coarse
offset_fine
gain_coarse
gain_medium
gain_fine
cal. value
cal. value
cal. value
cal. value
cal. value
I
I
I
I
I
I
21
22
Reserved
Coarse Gain
23
Medium Gain
Fine Gain
24
25
modes
Reserved
Power-Down Mode [2:0]
000 = Pin Control
00h
NOT
001 = Normal Operation
010 = Nap
affected by
Soft
100 = Sleep
Reset
Other codes = Reserved
26-5F
60-6F
70
Reserved
Reserved
skew_diff
phase_slip
Reserved
Reserved
Differential Skew
Reserved
80h
00h
71
Next
Clock
Edge
G
G
72
73
74
clock_divide
Clock Divide [2:0]
000=Pin Control
001=divide by 1
010=divide by 2
100=divide by 4
00h
NOT
affected by
Soft Reset
Other codes=Reserved
output_mode_A Output Mode [2:0]
000 = Pin Control
Output Format [2:0]
000 = Pin Control
001 = Twos Complement
010 = Gray Code
100 = Offset Binary
Other codes = Reserved
00h
NOT
affected by
Soft Reset
G
001 = LVDS 2mA
010 = LVDS 3mA
100 = LVCMOS
other codes = Reserved
output_mode_B
DLL
00h
NOT
affected by
Soft
G
G
Range
0 = fast
1 = slow
Reset
75
config_status
Reserved
XOR
Result
Read Only
76-BF
Reserved
FN6811.2
October 8, 2009
24
KAD5510P-50
TABLE 17. SPI MEMORY MAP (Continued)
Addr
(Hex)
Parameter
Name
Bit 7
(MSB)
Bit 0
(LSB)
Def. Value
(Hex)
Indexed/
Global
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
C0
test_io
User Test Mode
[1:0]
Output Test Mode [3:0]
00h
G
0 = Off
7 = One/Zero
1 = Midscale Short Word Toggle
00 = Single
2 = +FS Short
3 = -FS Short
4 = Checker Board
5 = Reserved
6 = Reserved
8 = User Input
9-15 = Reserved
01 = Alternate
10 = Reserved
11 = Reserved
C1
C2
Reserved
Reserved
00h
00h
00h
00h
00h
G
G
G
G
G
user_patt 1_lsb
user_patt1_msb
user_patt 2_lsb
user_patt2_msb
Reserved
B7
B15
B7
B6
B14
B6
B5
B13
B5
B4
B12
B4
B3
B11
B3
B2
B10
B2
B1
B9
B1
B9
B0
B8
B0
B8
C3
C4
C5
B15
B14
B13
B12
B11
B10
C6-FF
Reserved
Equivalent Circuits
AVDD
TO
CLOCK-
AVDD
PHASE
GENERATION
CLKP
AVDD
AVDD
CSAMP
1.6pF
TO
CHARGE
PIPELINE
11kOΩ
INP
18kOΩ
Φ
2
Φ
3
Φ
F 1
Ω
500
CSAMP
1.6pF
Ω
18kO
AVDD
AVDD
11kOΩ
TO
INN
CHARGE
PIPELINE
CLKN
Φ
F 2
3
Φ
Φ
1
FIGURE 41. ANALOG INPUTS
FIGURE 42. CLOCK INPUTS
AVDD
AVDD
(20k PULL-UP
ON RESETN
ONLY)
AVDD
OVDD
Ω
75kO
AVDD
OVDD
TO
SENSE
LOGIC
75kOΩ
280OΩ
OVDD
INPUT
20kΩ
INPUT
TO
LOGIC
280Ω
Ω
75kO
75kOΩ
FIGURE 43. TRI-LEVEL DIGITAL INPUTS
FIGURE 44. DIGITAL INPUTS
FN6811.2
October 8, 2009
25
KAD5510P-50
Equivalent Circuits (Continued)
OVDD
2mA OR
3mA
OVDD
DATA
DATA
D[9:0]P
OVDD
OVDD
D[9:0]N
OVDD
DATA
DATA
DATA
D[9:0]
2mA OR
3mA
FIGURE 45. LVDS OUTPUTS
FIGURE 46. CMOS OUTPUTS
AVDD
VCM
+
–
0.535V
FIGURE 47. VCM_OUT OUTPUT
Clock Input Considerations
ADC Evaluation Platform
Use matched transmission lines to the transformer inputs for
the analog input and clock signals. Locate transformers and
terminations as close to the chip as possible.
Intersil offers an ADC Evaluation platform which can be used
to evaluate any of the KADxxxxx ADC family. The platform
consists of a FPGA based data capture motherboard and a
family of ADC daughtercards. This USB based platform
allows a user to quickly evaluate the ADC’s performance at a
user’s specific application frequency requirements. More
information is available at
Exposed Paddle
The exposed paddle must be electrically connected to analog
ground (AVSS) and should be connected to a large copper
plane using numerous vias for optimal thermal performance.
http://www.intersil.com/converters/adc_eval_platform/
Bypass and Filtering
Layout Considerations
Bulk capacitors should have low equivalent series
resistance. Tantalum is a good choice. For best
performance, keep ceramic bypass capacitors very close to
device pins. Longer traces will increase inductance, resulting
in diminished dynamic performance and accuracy. Make
sure that connections to ground are direct and low
impedance. Avoid forming ground loops.
Split Ground and Power Planes
Data converters operating at high sampling frequencies require
extra care in PC board layout. Many complex board designs
benefit from isolating the analog and digital sections. Analog
supply and ground planes should be laid out under signal and
clock inputs. Locate the digital planes under outputs and logic
pins. Grounds should be joined under the chip.
LVDS Outputs
Output traces and connections must be designed for 50Ω
(100Ω differential) characteristic impedance. Keep traces
FN6811.2
October 8, 2009
26
KAD5510P-50
direct and minimize bends where possible. Avoid crossing
ground and power-plane breaks with signal traces.
Integral Non-Linearity (INL) is the maximum deviation of
the ADC’s transfer function from a best fit line determined by
a least squares curve fit of that transfer function, measured
in units of LSBs.
LVCMOS Outputs
Output traces and connections must be designed for 50Ω
characteristic impedance.
Least Significant Bit (LSB) is the bit that has the smallest
value or weight in a digital word. Its value in terms of input
N
Unused Inputs
voltage is V /(2 -1) where N is the resolution in bits.
FS
Standard logic inputs (RESETN, CSB, SCLK, SDIO, SDO)
which will not be operated do not require connection to
ensure optimal ADC performance. These inputs can be left
floating if they are not used. Tri-level inputs (NAPSLP,
OUTMODE, OUTFMT, CLKDIV) accept a floating input as a
valid state, and therefore should be biased according to the
desired functionality.
Missing Codes are output codes that are skipped and will
never appear at the ADC output. These codes cannot be
reached with any input value.
Most Significant Bit (MSB) is the bit that has the largest
value or weight.
Pipeline Delay is the number of clock cycles between the
initiation of a conversion and the appearance at the output
pins of the data.
Definitions
Analog Input Bandwidth is the analog input frequency at
which the spectral output power at the fundamental
frequency (as determined by FFT analysis) is reduced by
3dB from its full-scale low-frequency value. This is also
referred to as Full Power Bandwidth.
Power Supply Rejection Ratio (PSRR) is the ratio of the
observed magnitude of a spur in the ADC FFT, caused by an
AC signal superimposed on the power supply voltage.
Signal to Noise-and-Distortion (SINAD) is the ratio of the
RMS signal amplitude to the RMS sum of all other spectral
components below one half the clock frequency, including
harmonics but excluding DC.
Aperture Delay or Sampling Delay is the time required
after the rise of the clock input for the sampling switch to
open, at which time the signal is held for conversion.
Signal-to-Noise Ratio (without Harmonics) is the ratio of
the RMS signal amplitude to the RMS sum of all other
spectral components below one-half the sampling frequency,
excluding harmonics and DC.
Aperture Jitter is the RMS variation in aperture delay for a
set of samples.
Clock Duty Cycle is the ratio of the time the clock wave is at
logic high to the total time of one clock period.
SNR and SINAD are either given in units of dB when the
power of the fundamental is used as the reference, or dBFS
(dB to full scale) when the converter’s full-scale input power
is used as the reference.
Differential Non-Linearity (DNL) is the deviation of any
code width from an ideal 1 LSB step.
Effective Number of Bits (ENOB) is an alternate method of
specifying Signal to Noise-and-Distortion Ratio (SINAD). In
dB, it is calculated as: ENOB = (SINAD - 1.76)/6.02
Spurious-Free-Dynamic Range (SFDR) is the ratio of the
RMS signal amplitude to the RMS value of the largest
spurious spectral component. The largest spurious spectral
component may or may not be a harmonic.
Gain Error is the ratio of the difference between the voltages
that cause the lowest and highest code transitions to the
full-scale voltage less 2 LSB. It is typically expressed in percent.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
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FN6811.2
October 8, 2009
27
KAD5510P-50
Revision History
DATE
8/6/08
12/5/08
REVISION
Rev 1
CHANGE
Initial Release of Production Datasheet
FN6811.0
Converted to intersil template. Assigned file number FN6811. Rev 0 - first release (as
preliminary datasheet) with new file number.
1/19/09
FN6811.1
P1; revised Key Specs
P2; added Part Marking column to Order Info
P4; Moved Thermal Impedance under Thermal Info (used to be on p. 7). Added Theta JA
Note 2.
P4-7; edits throughout the Specs table. Added Notes 8 and 9. Revised Notes 6 and 7.
P7; Removed ESD section
P10-12; revised Performance Curves throughout
P14; User Inititated Reset section; revised 2nd sentence of 1st paragraph
P16; Nap/Sleep; revised 3rd and 4th sentences of 1st paragraph
P19; Serial Peripheral Interface; revised 2nd to last sentence of 1st paragraph. SPI
Physical Interface; revised 2nd and 3rd sentences of 4th paragraph
P20; added last 2 sentences to 1st paragraph of "ADDRESS 0X24: GAIN_FINE". Revised
Table 8
P21; revised last 2 sentences of "ADDRESS 0X71: PHASE_SLIP". Removed Figure of
"PHASE SLIP: CLK÷1 MODE, fCLOCK = 500MHz"
P24; revised Figure 43
P24; Table 17; revised Bits7:4, Addr C0
Throughout; formatted graphics to Intersil standards
2/25/09
5/8/09
6811.1
6811.2
Changed date to 2009 from 2008 no rev
1)Added nap mode, sleep mode wake up times to spec table
2) Added CSB,SCLK Setup time specs for nap,sleep modes to spec table
3) Changed SPI setup spec wording in
spec table
4) Change to pin description table for clarification
5) Added thermal pad note
6) Updated fig 23 and fig 24 and description in text.
7) Update multple device usage note on at “SPI Physical Interface” on page 20
8) Added ‘Reserved’ to SPI memory map
at address 25H
9) Added section on “ADC Evaluation Platform” on page 26
10) Updated table “DIFFERENTIAL SKEW ADJUSTMENT” on page 22..
11) Intersil Standards - Added Pb-free reflow link
8/25/09
9/10/09
12) Change to SPI interface section in spec table, timing in cycles now, added write, read
specific timing specs.
13) Updated SPI timing diagrams, Figures 35, 36
14) Updated wakeup time description in “Nap/Sleep” on page 17.
15) Updated sleep mode power spec
16) Changed label in Figure 44
17) Updated cal paragraph in user initiated reset section per DC
Changed standard over-temp from “Parameters with MIN and/or MAX limits are 100%
tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested” TO “Parameters with Min and/or MAX limits
are 100% production tested at their worst case temperature extreme ( +85°C) per Jeff
Rogers and Gary Hendrickson.” Updated Note references in Electrical Spec Table.
FN6811.2
October 8, 2009
28
KAD5510P-50
Package Outline Drawing
L72.10x10D
72 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 11/08
10.00
A
4X 8.50
PIN 1
INDEX AREA
PIN 1
INDEX AREA
B
55
72
6
6
1
54
68X 0.50
Exp. DAP
6.00 Sq.
10.00
18
37
(4X)
0.15
36
19
72X 0.24
72X 0.40
BOTTOM VIEW
4
TOP VIEW
0.10 M C A B
SEE DETAIL "X"
0.90 Max
C
C
0.10
0.08 C
SEATING PLANE
68X 0.50
SIDE VIEW
72X 0.24
9.80 Sq
6.00 Sq
5
0 . 2 REF
C
0 . 00 MIN.
0 . 05 MAX.
72X 0.60
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSEY14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN6811.2
October 8, 2009
29
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