MD80C86-2/B 概述
CMOS 16-Bit Microprocessor CMOS 16位微处理器
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80C86
CMOS 16-Bit Microprocessor
August 22, 2006
Features
• Compatible with NMOS 8086
Description
The Intersil 80C86 high performance 16-bit CMOS CPU is
manufactured using a self-aligned silicon gate CMOS pro-
cess (Scaled SAJI IV). Two modes of operation, minimum for
small systems and maximum for larger applications such as
multiprocessing, allow user configuration to achieve the
highest performance level. Full TTL compatibility (with the
exception of CLOCK) and industry standard operation allow
use of existing NMOS 8086 hardware and software designs.
• Completely Static CMOS Design
- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . .8MHz (80C86-2)
• Low Power Operation
- lCCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500μA Max
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . 10mA/MHz Typ
• 1MByte of Direct Memory Addressing Capability
• 24 Operand Addressing Modes
• Bit, Byte, Word and Block Move Operations
• 8-Bit and 16-Bit Signed/Unsigned Arithmetic
- Binary, or Decimal
Ordering Information
TEMP.
- Multiply and Divide
RANGE
(°C)
PART
MARKING
PKG.
NO.
• Wide Operating Temperature Range
- C80C86 . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
- M80C86 . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
PACKAGE
8MHz
PDIP
0 to +70
0 to +70
CP80C86-2
CP80C86-2Z
CP80C86-2
E40.6
E40.6
CP80C86-2Z
CERDIP
SMD#
-55 to +125 MD80C86-2/B MD80C86-2/B F40.6
-55 to +125 8405202QA
8405202QA
F40.6
Pinouts
80C86 (DIP)
80C86 (PLCC, CLCC)
TOP VIEW
TOP VIEW
MAX
(MIN)
GND
AD14
AD13
AD12
AD11
AD10
AD9
1
2
3
4
5
6
7
8
9
40 V
CC
MAX MODE
80C86
39 AD15
38 A16/S3
37 A17/S4
36 A18/S5
35 A19/S6
34 BHE/S7
33 MN/MX
32 RD
MIN MODE
80C86
44
43 42 41 40
6
5
4
3
2
1
7
39
38
37
36
35
34
33
32
31
30
29
AD10
AD9
AD10
AD9
NC
NC
A19/S6
A19/S6
8
AD8
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD8
AD7
AD6
AD5
AD4
AD3
AD2
9
BHE/S7 BHE/S7
AD7
10
11
12
13
14
15
16
17
MN/MX
RD
MN/MX
RD
AD6 10
AD5 11
AD4 12
AD3 13
AD2 14
AD1 15
AD0 16
NMI 17
INTR 18
CLK 19
GND 20
31 RQ/GT0 (HOLD)
30 RQ/GT1 (HLDA)
HOLD
HLDA
WR
RQ/GT0
RQ/GT1
LOCK
S2
29 LOCK
28 S2
(WR)
(M/IO)
(DT/R))
(DEN)
(ALE)
(INTA)
M/IO
27 S1
AD1
AD0
AD1
AD0
DT/R
DEN
S1
S0
26 S0
25 QS0
24 QS1
23 TEST
22 READY
21 RESET
18 19 20 21 22 23 24 25 26 27 28
MIN MODE
80C86
MAX MODE
80C86
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
FN2957.2
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
141
80C86
Functional Diagram
EXECUTION UNIT
REGISTER FILE
BUS INTERFACE UNIT
RELOCATION
REGISTER FILE
DATA POINTER
AND
INDEX REGS
(8 WORDS)
SEGMENT REGISTERS
AND
INSTRUCTION POINTER
(5 WORDS)
BHE/S7
A19/S6
A16/S3
16-BIT ALU
FLAGS
4
AD15-AD0
16
3
BUS INTERFACE UNIT
INTA, RD, WR
DT/R, DEN, ALE, M/IO
4
6-BYTE
INSTRUCTION
QUEUE
TEST
INTR
NMI
LOCK
2
QS0, QS1
S2, S1, S0
CONTROL AND TIMING
RQ/GT0, 1
2
HOLD
HLDA
3
3
CLK
RESET READY MN/MX GND
V
CC
MEMORY INTERFACE
C-BUS
INSTRUCTION
STREAM BYTE
QUEUE
B-BUS
ES
CS
SS
DS
IP
BUS
INTERFACE
UNIT
EXECUTION UNIT
CONTROL SYSTEM
A-BUS
AH
BH
CH
DH
AL
BL
CL
DL
ARITHMETIC/
LOGIC UNIT
EXECUTION
UNIT
SP
BP
SI
FLAGS
DI
142
80C86
Pin Description
The following pin function descriptions are for 80C86 systems in either minimum or maximum mode. The “Local Bus” in these description is
the direct multiplexed bus interface connection to the 80C86 (without regard to additional bus buffers).
PIN
SYMBOL
NUMBER
TYPE
DESCRIPTION
AD15-AD0
2-16, 39
I/O
ADDRESS DATA BUS: These lines constitute the time multiplexed memory/lO address (T1) and
data (T2, T3, TW, T4) bus. A0 is analogous to BHE for the lower byte of the data bus, pins D7-
D0. It is LOW during Ti when a byte is to be transferred on the lower portion of the bus in memory
or I/O operations. Eight-bit oriented devices tied to the lower half would normally use A0 to con-
dition chip select functions (See BHE). These lines are active HIGH and are held at high imped-
ance to the last valid logic level during interrupt acknowledge and local bus “hold acknowledge”
or “grant sequence”.
A19/S6
A18/S5
A17/S4
A16/S3
35-38
O
ADDRESS/STATUS: During T1, these are the four most significant address lines for memory op-
erations. During I/O operations these lines are LOW. During memory and I/O operations, status
information is available on these lines during T2, T3, TW, T4. S6 is always LOW. The status of
the interrupt enable FLAG bit (S5) is updated at the beginning of each clock cycle. S4 and S3
are encoded as shown.
This information indicates which segment register is presently being used for data accessing.
These lines are held at high impedance to the last valid logic level during local bus “hold ac-
knowledge” or “grant sequence”.
S4
0
S3
0
CHARACTERISTICS
Alternate Data
Stack
0
1
1
0
Code or None
Data
1
1
BHE/S7
34
O
BUS HIGH ENABLE/STATUS: During T1 the bus high enable signal (BHE) should be used to
enable data onto the most significant half of the data bus, pins D15-D8. Eight bit oriented devices
tied to the upper half of the bus would normally use BHE to condition chip select functions. BHE
is LOW during T1 for read, write, and interrupt acknowledge cycles when a byte is to be trans-
ferred on the high portion of the bus. The S7 status information is available during T2, T3 and
T4. The signal is active LOW, and is held at high impedance to the last valid logic level during
interrupt acknowledge and local bus “hold acknowledge” or “grant sequence”, it is LOW during
T1 for the first interrupt acknowledge cycle.
BHE
A0
0
CHARACTERISTICS
Whole Word
0
0
1
1
1
Upper Byte From/to Odd Address
Lower Byte From/to Even address
None
0
1
RD
32
22
O
READ: Read strobe indicates that the processor is performing a memory or I/O read cycle, de-
pending on the state of the M/IO or S2 pin. This signal is used to read devices which reside on
the 80C86 local bus. RD is active LOW during T2, T3 and TW of any read cycle, and is guaran-
teed to remain HIGH in T2 until the 80C86 local bus has floated.
This line is held at a high impedance logic one state during “hold acknowledge” or “grand se-
quence”.
READY
I
READY: is the acknowledgment from the addressed memory or I/O device that will complete the
data transfer. The RDY signal from memory or I/O is synchronized by the 82C84A Clock Gen-
erator to form READY. This signal is active HIGH. The 80C86 READY input is not synchronized.
Correct operation is not guaranteed if the Setup and Hold Times are not met.
143
80C86
Pin Description (Continued)
The following pin function descriptions are for 80C86 systems in either minimum or maximum mode. The “Local Bus” in these description is
the direct multiplexed bus interface connection to the 80C86 (without regard to additional bus buffers).
PIN
SYMBOL
NUMBER
TYPE
DESCRIPTION
INTR
18
I
INTERRUPT REQUEST: is a level triggered input which is sampled during the last clock cycle
of each instruction to determine if the processor should enter into an interrupt acknowledge op-
eration. A subroutine is vectored to via an interrupt vector lookup table located in system mem-
ory. It can be internally masked by software resetting the interrupt enable bit.
lNTR is internally synchronized. This signal is active HIGH.
TEST
NMI
23
17
I
I
TEST: input is examined by the “Wait” instruction. If the TEST input is LOW execution continues,
otherwise the processor waits in an “Idle” state. This input is synchronized internally during each
clock cycle on the leading edge of CLK.
NON-MASKABLE INTERRUPT: is an edge triggered input which causes a type 2 interrupt. A
subroutine is vectored to via an interrupt vector lookup table located in system memory. NMI is
not maskable internally by software. A transition from LOW to HIGH initiates the interrupt at the
end of the current instruction. This input is internally synchronized.
RESET
21
I
I
RESET: causes the processor to immediately terminate its present activity. The signal must tran-
sition LOW to HIGH and remain active HIGH for at least four clock cycles. It restarts execution,
as described in the Instruction Set description, when RESET returns LOW. RESET is internally
synchronized.
CLK
VCC
19
40
CLOCK: provides the basic timing for the processor and bus controller. It is asymmetric with a
33% duty cycle to provide optimized internal timing.
VCC: +5V power supply pin. A 0.1μF capacitor between pins 20 and 40 is recommended for de-
coupling.
GND
1, 20
33
GND: Ground. Note: both must be connected. A 0.1μF capacitor between pins 1 and 20 is rec-
ommended for decoupling.
MN/MX
I
MINIMUM/MAXIMUM: Indicates what mode the processor is to operate in. The two modes are
discussed in the following sections.
Minimum Mode System
The following pin function descriptions are for the 80C86 in minimum mode (i.e., MN/MX = VCC). Only the pin functions which are unique to
minimum mode are described; all other pin functions are as described below.
PIN
SYMBOL
NUMBER
TYPE
DESCRIPTION
M/IO
28
O
STATUS LINE: logically equivalent to S2 in the maximum mode. It is used to distinguish a mem-
ory access from an I/O access. M/lO becomes valid in the T4 preceding a bus cycle and remains
valid until the final T4 of the cycle (M = HIGH, I/O = LOW). M/lO is held to a high impedance logic
one during local bus “hold acknowledge”.
WR
INTA
ALE
29
24
25
O
O
O
WRITE: indicates that the processor is performing a write memory or write I/O cycle, depending
on the state of the M/IO signal. WR is active for T2, T3 and TW of any write cycle. It is active
LOW, and is held to high impedance logic one during local bus “hold acknowledge”.
INTERRUPT ACKNOWLEDGE: is used as a read strobe for interrupt acknowledge cycles. It is
active LOW during T2, T3 and TW of each interrupt acknowledge cycle. Note that INTA is never
floated.
ADDRESS LATCH ENABLE: is provided by the processor to latch the address into the
82C82/82C83 address latch. It is a HIGH pulse active during clock LOW of T1 of any bus cycle.
Note that ALE is never floated.
144
80C86
Minimum Mode System (Continued)
The following pin function descriptions are for the 80C86 in minimum mode (i.e., MN/MX = VCC). Only the pin functions which are unique to
minimum mode are described; all other pin functions are as described below.
PIN
SYMBOL
NUMBER
TYPE
DESCRIPTION
DT/R
27
O
DATA TRANSMIT/RECEIVE: is needed in a minimum system that desires to use a data bus
transceiver. It is used to control the direction of data flow through the transceiver. Logically,
DT/R is equivalent to S1 in maximum mode, and its timing is the same as for M/IO (T = HIGH,
R = LOW). DT/R is held to a high impedance logic one during local bus “hold acknowledge”.
DEN
26
O
DATA ENABLE: provided as an output enable for a bus transceiver in a minimum system which
uses the transceiver. DEN is active LOW during each memory and I/O access and for INTA cy-
cles. For a read or INTA cycle it is active from the middle of T2 until the middle of T4, while for
a write cycle it is active from the beginning of T2 until the middle of T4. DEN is held to a high
impedance logic one during local bus “hold acknowledge”.
HOLD
HLDA
31, 30
I
O
HOLD: indicates that another master is requesting a local bus “hold”. To be an acknowledged,
HOLD must be active HIGH. The processor receiving the “hold” will issue a “hold acknowledge”
(HLDA) in the middle of a T4 or TI clock cycle. Simultaneously with the issuance of HLDA, the
processor will float the local bus and control lines. After HOLD is detected as being LOW, the
processor will lower HLDA, and when the processor needs to run another cycle, it will again drive
the local bus and control lines.
HOLD is not an asynchronous input. External synchronization should be provided if the system
cannot otherwise guarantee the setup time.
Maximum Mode System
The following pin function descriptions are for the 80C86 system in maximum mode (i.e., MN/MX - GND). Only the pin functions which are
unique to maximum mode are described below.
PIN
SYMBOL
NUMBER
TYPE
DESCRIPTION
S0
S1
S2
26
27
28
O
O
O
STATUS: is active during T4, T1 and T2 and is returned to the passive state (1, 1, 1) during T3
or during TW when READY is HIGH. This status is used by the 82C88 Bus Controller to generate
all memory and I/O access control signals. Any change by S2, S1 or S0 during T4 is used to
indicate the beginning of a bus cycle, and the return to the passive state in T3 or TW is used to
indicate the end of a bus cycle.
These signals are held at a high impedance logic one state during “grant sequence”.
S2
0
S1
0
S0
0
CHARACTERISTICS
Interrupt Acknowledge
0
0
1
Read I/O Port
Write I/O Port
Halt
0
1
0
0
1
1
1
0
0
Code Access
Read Memory
Write Memory
Passive
1
0
1
1
1
0
1
1
1
145
80C86
Maximum Mode System (Continued)
The following pin function descriptions are for the 80C86 system in maximum mode (i.e., MN/MX - GND). Only the pin functions which are
unique to maximum mode are described below.
PIN
SYMBOL
NUMBER
TYPE
DESCRIPTION
RQ/GT0
RQ/GT1
31, 30
I/O
REQUEST/GRANT: pins are used by other local bus masters to force the processor to release
the local bus at the end of the processor’s current bus cycle. Each pin is bidirectional with
RQ/GTO having higher priority than RQ/GT1. RQ/GT has an internal pull-up bus hold device so
it may be left unconnected. The request/grant sequence is as follows (see RQ/GT Sequence
Timing)
1. A pulse of 1 CLK wide from another local bus master indicates a local bus request (“hold”)
to the 80C86 (pulse 1).
2. During a T4 or TI clock cycle, a pulse 1 CLK wide from the 80C86 to the requesting master
(pulse 2) indicates that the 80C86 has allowed the local bus to float and that it will enter the
“grant sequence” state at the next CLK. The CPU’s bus interface unit is disconnected logi-
cally from the local bus during “grant sequence”.
3. A pulse 1 CLK wide from the requesting master indicates to the 80C86 (pulse 3) that the
“hold” request is about to end and that the 80C86 can reclaim the local bus at the next CLK.
The CPU then enters T4 (or TI if no bus cycles pending).
Each Master-Master exchange of the local bus is a sequence of 3 pulses. There must be one
idle CLK cycle after each bus exchange. Pulses are active low.
If the request is made while the CPU is performing a memory cycle, it will release the local
bus during T4 of the cycle when all the following conditions are met:
1. Request occurs on or before T2.
2. Current cycle is not the low byte of a word (on an odd address).
3. Current cycle is not the first acknowledge of an interrupt acknowledge sequence.
4. A locked instruction is not currently executing.
If the local bus is idle when the request is made the two possible events will follow:
1. Local bus will be released during the next cycle.
2. A memory cycle will start within three clocks. Now the four rules for a currently active memory
cycle apply with condition number 1 already satisfied.
LOCK
29
O
O
LOCK: output indicates that other system bus masters are not to gain control of the system bus
while LOCK is active LOW. The LOCK signal is activated by the “LOCK” prefix instruction and
remains active until the completion of the next instruction. This signal is active LOW, and is held
at a high impedance logic one state during “grant sequence”. In MAX mode, LOCK is automat-
ically generated during T2 of the first INTA cycle and removed during T2 of the second INTA
cycle.
QS1, QSO
24, 25
QUEUE STATUS: The queue status is valid during the CLK cycle after which the queue opera-
tion is performed.
QS1 and QS0 provide status to allow external tracking of the internal 80C86 instruction queue.
Note that QS1, QS0 never become high impedance.
QSI
0
QSO
0
1
0
1
No Operation
0
First byte of op code from queue
Empty the queue
1
1
Subsequent byte from queue
146
80C86
code, data, extra and stack segments of up to 64K bytes
each, with each segment falling on 16-byte boundaries. (See
Figure 1).
Functional Description
Static Operation
All 80C86 circuitry is of static design. Internal registers,
counters and latches are static and require no refresh as
with dynamic circuit design. This eliminates the minimum
operating frequency restriction placed on other microproces-
sors. The CMOS 80C86 can operate from DC to the speci-
fied upper frequency limit. The processor clock may be
stopped in either state (HIGH/LOW) and held there indefi-
nitely. This type of operation is especially useful for system
debug or power critical applications.
FFFFFH
64K-BIT
CODE SEGMENT
XXXXOH
STACK SEGMENT
DATA SEGMENT
+ OFFSET
The 80C86 can be single stepped using only the CPU clock.
This state can be maintained as long as is necessary. Single
step clock operation allows simple interface circuitry to pro-
vide critical information for bringing up your system.
SEGMENT
REGISTER FILE
CS
SS
DS
ES
Static design also allows very low frequency operation (down
to DC). In a power critical situation, this can provide
extremely low power operation since 80C86 power dissipa-
tion is directly related to operating frequency. As the system
frequency is reduced, so is the operating power until, ulti-
mately, at a DC input frequency, the 80C86 power require-
ment is the standby current, (500μA maximum).
EXTRA SEGMENT
00000H
Internal Architecture
FIGURE 1. 80C86 MEMORY ORGANIZATION
TABLE 1.
The internal functions of the 80C86 processor are partitioned
logically into two processing units. The first is the Bus Inter-
face Unit (BlU) and the second is the Execution Unit (EU) as
shown in the CPU functional diagram.
TYPE OF
MEMORY
REFERENCE
DEFAULT
SEGMENT
BASE
ALTERNATE
SEGMENT
BASE
These units can interact directly, but for the most part perform
as separate asynchronous operational processors. The bus
interface unit provides the functions related to instruction
fetching and queuing, operand fetch and store, and address
relocation. This unit also provides the basic bus control. The
overlap of instruction pre-fetching provided by this unit serves
to increase processor performance through improved bus
bandwidth utilization. Up to 6 bytes of the instruction stream
can be queued while waiting for decoding and execution.
OFFSET
IP
Instruction Fetch
Stack Operation
CS
SS
DS
None
None
SP
Variable (except
following)
CS, ES, SS
Effective
Address
String Source
DS
ES
SS
CS, ES, SS
None
SI
DI
String Destination
The instruction stream queuing mechanism allows the BIU to
keep the memory utilized very efficiently. Whenever there is
space for at least 2 bytes in the queue, the BlU will attempt a
word fetch memory cycle. This greatly reduces “dead-time”
on the memory bus. The queue acts as a First-In-First-Out
(FIFO) buffer, from which the EU extracts instruction bytes
as required. If the queue is empty (following a branch
instruction, for example), the first byte into the queue imme-
diately becomes available to the EU.
BP Used As Base
Register
CS, DS, ES
Effective
Address
All memory references are made relative to base addresses
contained in high speed segment registers. The segment
types were chosen based on the addressing needs of pro-
grams. The segment register to be selected is automatically
chosen according to the specific rules of Table 1. All informa-
tion in one segment type share the same logical attributes
(e.g. code or data). By structuring memory into re-locatable
areas of similar characteristics and by automatically select-
ing segment registers, programs are shorter, faster and
more structured. (See Table 1).
The execution unit receives pre-fetched instructions from the
BlU queue and provides un-relocated operand addresses to
the BlU. Memory operands are passed through the BIU for pro-
cessing by the EU, which passes results to the BIU for storage.
Word (16-bit) operands can be located on even or odd
address boundaries and are thus, not constrained to even
boundaries as is the case in many 16-bit computers. For
address and data operands, the least significant byte of the
word is stored in the lower valued address location and the
most significant byte in the next higher address location. The
BIU automatically performs the proper number of memory
Memory Organization
The processor provides a 20-bit address to memory, which
locates the byte being referenced. The memory is organized
as a linear array of up to 1 million bytes, addressed as
00000(H) to FFFFF(H). The memory is logically divided into
147
80C86
accesses; one, if the word operand is on an even byte 80C86 provides DEN and DT/R to control the transceiver, and
boundary and two, if it is on an odd byte boundary. Except ALE to latch the addresses. This configuration of the minimum
for the performance penalty, this double access is transpar- mode provides the standard demultiplexed bus structure with
ent to the software. The performance penalty does not occur heavy bus buffering and relaxed bus timing requirements.
for instruction fetches; only word operands.
The maximum mode employs the 82C88 bus controller (See
Physically, the memory is organized as a high bank (D15-
D8) and a low bank (D7-D0) of 512K bytes addressed in par-
allel by the processor’s address lines.
Figure 6B). The 82C88 decodes status lines S0, S1 and S2,
and provides the system with all bus control signals.
Moving the bus control to the 82C88 provides better source
and sink current capability to the control lines, and frees the
80C86 pins for extended large system features. Hardware
lock, queue status, and two request/grant interfaces are pro-
vided by the 80C86 in maximum mode. These features allow
coprocessors in local bus and remote bus configurations.
Byte data with even addresses is transferred on the D7-D0
bus lines, while odd addressed byte data (A0 HIGH) is trans-
ferred on the D15-D8 bus lines. The processor provides two
enable signals, BHE and A0, to selectively allow reading
from or writing into either an odd byte location, even byte
location, or both. The instruction stream is fetched from
memory as words and is addressed internally by the proces-
sor at the byte level as necessary.
Bus Operation
The 80C86 has a combined address and data bus com-
monly referred to as a time multiplexed bus. This technique
provides the most efficient use of pins on the processor
while permitting the use of a standard 40 lead package. This
“local bus” can be buffered directly and used throughout the
system with address latching provided on memory and I/O
modules. In addition, the bus can also be demultiplexed at
the processor with a single set of 82C82 address latches if a
standard non-multiplexed bus is desired for the system.
In referencing word data, the BlU requires one or two memory
cycles depending on whether the starting byte of the word is
on an even or odd address, respectively. Consequently, in ref-
erencing word operands performance can be optimized by
locating data on even address boundaries. This is an espe-
cially useful technique for using the stack, since odd address
references to the stack may adversely affect the context
switching time for interrupt processing or task multiplexing.
Each processor bus cycle consists of at least four CLK
cycles. These are referred to as T1, T2, T3 and T4 (see Fig-
ure 3). The address is emitted from the processor during T1
and data transfer occurs on the bus during T3 and T4. T2 is
used primarily for changing the direction of the bus during
read operations. In the event that a “NOT READY” indication
is given by the addressed device, “Wait” states (TW) are
inserted between T3 and T4. Each inserted wait state is the
same duration as a CLK cycle. Periods can occur between
80C86 driven bus cycles. These are referred to as idle”
states (TI) or inactive CLK cycles. The processor uses these
cycles for internal housekeeping and processing.
Certain locations in memory are reserved for specific CPU
operations (See Figure 2). Locations from address FFFF0H
through FFFFFH are reserved for operations including a jump
to the initial program loading routine. Following RESET, the
CPU will always begin execution at location FFFF0H where
the jump must be located. Locations 00000H through 003FFH
are reserved for interrupt operations. Each of the 256 possible
interrupt service routines is accessed thru its own pair of 16-
bit pointers (segment address pointer and offset address
pointer). The first pointer, used as the offset address, is
loaded into the lP and the second pointer, which designates
the base address is loaded into the CS. At this point program
control is transferred to the interrupt routine. The pointer ele-
ments are assumed to have been stored at the respective
places in reserved memory prior to occurrence of interrupts.
During T1 of any bus cycle, the ALE (Address Latch Enable)
signal is emitted (by either the processor or the 82C88 bus
controller, depending on the MN/MX strap). At the trailing
edge of this pulse, a valid address and certain status infor-
mation for the cycle may be latched.
Minimum and Maximum Operation Modes
The requirements for supporting minimum and maximum
80C86 systems are sufficiently different that they cannot be
met efficiently using 40 uniquely defined pins. Consequently,
the 80C86 is equipped with a strap pin (MN/MX) which
defines the system configuration. The definition of a certain
subset of the pins changes, dependent on the condition of the
strap pin. When the MN/MX pin is strapped to GND, the
80C86 defines pins 24 through 31 and 34 in maximum mode.
When the MN/MX pin is strapped to VCC, the 80C86 gener-
ates bus control signals itself on pins 24 through 31 and 34.
Status bits S0, S1 and S2 are used by the bus controller, in
maximum mode, to identify the type of bus transaction
according to Table 2.
TABLE 2.
S2
0
S1
0
S0
0
CHARACTERISTICS
Interrupt
0
0
1
Read I/O
0
1
0
Write I/O
The minimum mode 80C86 can be used with either a multi-
plexed or demultiplexed bus. This architecture provides the
80C86 processing power in a highly integrated form.
0
1
1
Halt
1
0
0
Instruction Fetch
Read Data from Memory
Write Data to Memory
Passive (No Bus Cycle)
1
0
1
The demultiplexed mode requires two 82C82 latches (for 64K
addressability) or three 82C82 latches (for a full megabyte of
addressing). An 82C86 or 82C87 transceiver can also be
used if data bus buffering is required. (See Figure 6A.) The
1
1
0
1
1
1
148
80C86
Status bits S3 through S7 are time multiplexed with high I/O Addressing
order address bits and the BHE signal, and are therefore
In the 80C86, I/O operations can address up to a maximum
valid during T2 through T4. S3 and S4 indicate which seg-
ment register (see Instruction Set Description) was used for
this bus cycle in forming the address, according to Table 3.
of 64K I/O byte registers or 32K I/O word registers. The I/O
address appears in the same format as the memory address
on bus lines A15-A0. The address lines A19-A16 are zero in
I/O operations. The variable I/O instructions which use regis-
ter DX as a pointer have full address capability while the
direct I/O instructions directly address one or two of the 256
I/O byte locations in page 0 of the I/O address space.
S5 is a reflection of the PSW interrupt enable bit. S3 is
always zero and S7 is a spare status bit.
TABLE 3.
S4
0
S3
0
CHARACTERISTICS
I/O ports are addressed in the same manner as memory loca-
tions. Even addressed bytes are transferred on the D7-D0 bus
lines and odd addressed bytes on D15-D8. Care must be taken
to ensure that each register within an 8-bit peripheral located on
the lower portion of the bus be addressed as even.
Alternate Data (Extra Segment)
0
1
Stack
1
0
Code or None
Data
1
1
FFFFFH
FFFF0H
RESET BOOTSTRAP
PROGRAM JUMP
TYPE 225 POINTER
(AVAILABLE)
3FFH
3FCH
AVAILABLE
INTERRUPT
POINTERS
(224)
TYPE 33 POINTER
(AVAILABLE)
084H
080H
07FH
TYPE 32 POINTER
(AVAILABLE)
TYPE 31 POINTER
(AVAILABLE)
RESERVED
INTERRUPT
POINTERS
(27)
TYPE 5 POINTER
(RESERVED)
014H
010H
TYPE 4 POINTER
OVERFLOW
TYPE 3 POINTER
1 BYTE INT INSTRUCTION
00CH
DEDICATED
TYPE 2 POINTER
NON MASKABLE
INTERRUPT
008H
POINTERS
(5)
TYPE 1 POINTER
SINGLE STEP
004H
TYPE 0 POINTER
DIVIDE ERROR
CS BASE ADDRESS
IP OFFSET
000H
16 BITS
FIGURE 2. RESERVED MEMORY LOCATIONS
149
80C86
(4 + NWAIT) = TCY
T3 TWAIT
(4 + NWAIT) = TCY
T3 TWAIT
T1
T2
T4
T1
T2
T4
CLK
GOES INACTIVE IN THE STATE
JUST PRIOR TO T
4
ALE
S2-S0
BHE,
A19-A16
BHE
A19-A16
ADDR/
STATUS
S7-S3
S7-S3
BUS RESERVED
FOR DATA IN
D15-D0
VALID
A15-A0
A15-A0
DATA OUT (D15-D0)
ADDR/DATA
RD, INTA
READY
READY
READY
WAIT
WAIT
DT/R
DEN
WR
MEMORY ACCESS TIME
FIGURE 3. BASIC SYSTEM TIMING
150
80C86
Interrupt Operations
External Interface
Interrupt operations fall into two classes: software or hard-
ware initiated. The software initiated interrupts and software
aspects of hardware interrupts are specified in the Instruc-
tion Set Description. Hardware interrupts can be classified
as non-maskable or maskable.
Processor RESET and Initialization
Processor initialization or start up is accomplished with activa-
tion (HIGH) of the RESET pin. The 80C86 RESET is required to
be HIGH for greater than 4 CLK cycles. The 80C86 will termi-
nate operations on the high-going edge of RESET and will
remain dormant as long as RESET is HIGH. The low-going
transition of RESET triggers an internal reset sequence for
approximately 7 clock cycles. After this interval, the 80C86
operates normally beginning with the instruction in absolute
location FFFF0H. (See Figure 2). The RESET input is internally
synchronized to the processor clock. At initialization, the HIGH-
to-LOW transition of RESET must occur no sooner than 50μs
(or 4 CLK cycles, whichever is greater) after power-up, to allow
complete initialization of the 80C86.
Interrupts result in a transfer of control to a new program loca-
tion. A 256-element table containing address pointers to the
interrupt service program locations resides in absolute loca-
tions 0 through 3FFH, which are reserved for this purpose.
Each element in the table is 4 bytes in size and corresponds
to an interrupt “type”. An interrupting device supplies an 8-bit
type number during the interrupt acknowledge sequence,
which is used to “vector” through the appropriate element to
the new interrupt service program location. All flags and both
the Code Segment and Instruction Pointer register are saved
as part of the lNTA sequence. These are restored upon exe-
cution of an Interrupt Return (IRET) instruction.
NMl will not be recognized prior to the second CLK cycle follow-
ing the end of RESET. If NMl is asserted sooner than nine clock
cycles after the end of RESET, the processor may execute one
instruction before responding to the interrupt.
Non-Maskable Interrupt (NMI)
The processor provides a single non-maskable interrupt pin
(NMI) which has higher priority than the maskable interrupt
request pin (INTR). A typical use would be to activate a
power failure routine. The NMI is edge-triggered on a LOW-
to-HIGH transition. The activation of this pin causes a type 2
interrupt.
Bus Hold Circuitry
To avoid high current conditions caused by floating inputs to
CMOS devices and to eliminate need for pull-up/down resistors,
“bus-hold” circuitry has been used on the 80C86 pins 2-16, 26-
32 and 34-39. (See Figure 4A and Figure 4B). These circuits
will maintain the last valid logic state if no driving source is
present (i.e., an unconnected pin or a driving source which goes
to a high impedance state). To overdrive the “bus hold” circuits,
an external driver must be capable of supplying approximately
400μA minimum sink or source current at valid input voltage
levels. Since this “bus hold” circuitry is active and not a “resis-
tive” type element, the associated power supply current is negli-
gible and power dissipation is significantly reduced when
compared to the use of passive pull-up resistors.
NMl is required to have a duration in the HIGH state of
greater than two CLK cycles, but is not required to be syn-
chronized to the clock. Any positive transition of NMI is
latched on-chip and will be serviced at the end of the current
instruction or between whole moves of a block-type instruc-
tion. Worst case response to NMI would be for multiply,
divide, and variable shift instructions. There is no specifica-
tion on the occurrence of the low-going edge; it may occur
before, during or after the servicing of NMI. Another positive
edge triggers another response if it occurs after the start of
the NMI procedure. The signal must be free of logical spikes
in general and be free of bounces on the low-going edge to
avoid triggering extraneous responses.
BOND
PAD
EXTERNAL
PIN
OUTPUT
DRIVER
INPUT
BUFFER
Maskable Interrupt (INTR)
INPUT
PROTECTION
CIRCUITRY
The 80C86 provides a single interrupt request input (lNTR)
which can be masked internally by software with the reset-
ting of the interrupt enable flag (IF) status bit. The interrupt
request signal is level triggered. It is internally synchronized
during each clock cycle on the high-going edge of CLK. To
be responded to, lNTR must be present (HIGH) during the
clock period preceding the end of the current instruction or
the end of a whole move for a block type instruction. lNTR
may be removed anytime after the falling edge of the first
INTA signal. During the interrupt response sequence further
interrupts are disabled. The enable bit is reset as part of the
response to any interrupt (lNTR, NMI, software interrupt or
single-step), although the FLAGS register which is automati-
cally pushed onto the stack reflects the state of the proces-
sor prior to the interrupt. Until the old FLAGS register is
restored, the enable bit will be zero unless specifically set by
an instruction.
FIGURE 4A. BUS HOLD CIRCUITRY PIN 2-16, 34-39
BOND
PAD
EXTERNAL
PIN
V
P
CC
OUTPUT
DRIVER
INPUT
BUFFER
INPUT
PROTECTION
CIRCUITRY
FIGURE 4B. BUS HOLD CIRCUITRY PIN 26-32
151
80C86
During the response sequence (Figure 5) the processor exe- External Synchronization Via TEST
cutes two successive (back-to-back) interrupt acknowledge
As an alternative to interrupts, the 80C86 provides a single
cycles. The 80C86 emits the LOCK signal (Max mode only)
from T2 of the first bus cycle until T2 of the second. A local
bus “hold” request will not be honored until the end of the
second bus cycle. In the second bus cycle, a byte is supplied
to the 80C86 by the 82C59A Interrupt Controller, which iden-
tifies the source (type) of the interrupt. This byte is multiplied
by four and used as a pointer into the interrupt vector lookup
table. An INTR signal left HIGH will be continually responded
to within the limitations of the enable bit and sample period.
The INTERRUPT RETURN instruction includes a FLAGS
pop which returns the status of the original interrupt enable
bit when it restores the FLAGS.
software-testable input pin (TEST). This input is utilized by
executing a WAIT instruction. The single WAIT instruction is
repeatedly executed until the TEST input goes active (LOW).
The execution of WAIT does not consume bus cycles once
the queue is full.
If a local bus request occurs during WAIT execution, the
80C86 three-states all output drivers while inputs and I/O
pins are held at valid logic levels by internal bus-hold cir-
cuits. If interrupts are enabled, the 80C86 will recognize
interrupts and process them when it regains control of the
bus. The WAIT instruction is then refetched, and re-exe-
cuted.
T1
T3
T1
T2
T3
T4 TI
T2
T4
TABLE 4. 80C86 REGISTER
ALE
ACCUMULATOR
AH
BH
CH
DH
AL
BL
CL
DL
AX
BX
CX
DX
LOCK
BASE
COUNT
DATA
INTA
FLOAT
SP
BP
SI
STACK POINTER
AD0-
AD15
TYPE
VECTOR
BASE POINTER
SOURCE INDEX
FIGURE 5. INTERRUPT ACKNOWLEDGE SEQUENCE
DI
DESTINATION INDEX
Halt
IP
INSTRUCTION POINTER
STATUS FLAG
When a software “HALT” instruction is executed the proces-
sor indicates that it is entering the “HALT” state in one of two
ways depending upon which mode is strapped. In minimum
mode, the processor issues one ALE with no qualifying bus
control signals. In maximum mode the processor issues
appropriate HALT status on S2, S1, S0 and the 82C88 bus
controller issues one ALE. The 80C86 will not leave the
“HALT” state when a local bus “hold” is entered while in
“HALT”. In this case, the processor reissues the HALT indi-
cator at the end of the local bus hold. An NMI or interrupt
request (when interrupts enabled) or RESET will force the
80C86 out of the “HALT” state.
FLAGS
FLAGS
H
L
CS
DS
SS
ES
CODE SEGMENT
DATA SEGMENT
STACK SEGMENT
EXTRA SEGMENT
Basic System Timing
Typical system configurations for the processor operating in
minimum mode and in maximum mode are shown in Figures
6A and 6B, respectively. In minimum mode, the MN/MX pin
is strapped to VCC and the processor emits bus control sig-
nals (e.g. RD, WR, etc.) directly. In maximum mode, the
MN/MX pin is strapped to GND and the processor emits
coded status information which the 82C88 bus controller
uses to generate MULTIBUS compatible bus control signals.
Figure 3 shows the signal timing relationships.
Read/Modify/Write (Semaphore)
Operations Via Lock
The LOCK status information is provided by the processor
when consecutive bus cycles are required during the execution
of an instruction. This gives the processor the capability of per-
forming read/modify/write operations on memory (via the
Exchange Register With Memory instruction, for example) with-
out another system bus master receiving intervening memory
cycles. This is useful in multiprocessor system configurations to
accomplish “test and set lock” operations. The LOCK signal is
activated (forced LOW) in the clock cycle following decoding of
the software “LOCK” prefix instruction. It is deactivated at the
end of the last bus cycle of the instruction following the “LOCK”
prefix instruction. While LOCK is active a request on a RQ/GT
pin will be recorded and then honored at the end of the LOCK.
System Timing - Minimum System
The read cycle begins in T1 with the assertion of the
Address Latch Enable (ALE) signal. The trailing (low-going)
edge of this signal is used to latch the address information,
which is valid on the address/data bus (AD0-AD15) at this
time, into the 82C82/82C83 latch. The BHE and A0 signals
address the low, high or both bytes. From T1 to T4 the M/lO
signal indicates a memory or I/O operation. At T2, the
address is removed from the address/data bus and the bus
152
80C86
is held at the last valid logic state by internal bus hold
devices. The read control signal is also asserted at T2. The
read (RD) signal causes the addressed device to enable its
data bus drivers to the local bus. Some time later, valid data
will be available on the bus and the addressed device will
drive the READY line HIGH. When the processor returns the
read signal to a HIGH level, the addressed device will again
three-state its bus drivers. If a transceiver (82C86/82C87) is
required to buffer the 80C86 local bus, signals DT/R and
DEN are provided by the 80C86.
A write cycle also begins with the assertion of ALE and the
emission of the address. The M/IO signal is again asserted
to indicate a memory or I/O write operation. In T2, immedi-
ately following the address emission, the processor emits
the data to be written into the addressed location. This data
remains valid until at least the middle of T4. During T2, T3
and TW, the processor asserts the write control signal. The
write (WR) signal becomes active at the beginning of T2 as
opposed to the read which is delayed somewhat into T2 to
provide time for output drivers to become inactive.
The BHE and A0 signals are used to select the proper
byte(s) of the memory/lO word to be read or written accord-
ing to Table 5.
TABLE 5.
BHE
A0
0
CHARACTERISTICS
Whole word
0
0
1
1
1
Upper Byte From/To Odd Address
Lower Byte From/To Even Address
None
0
1
I/O ports are addressed in the same manner as memory
location. Even addressed bytes are transferred on the D7-
D0 bus lines and odd address bytes on D15-D8.
The basic difference between the interrupt acknowledge
cycle and a read cycle is that the interrupt acknowledge sig-
nal (INTA) is asserted in place of the read (RD) signal and
the address bus is held at the last valid logic state by internal
bus hold devices. (See Figure 4). In the second of two suc-
cessive INTA cycles a byte of information is read from the
data bus (D7-D0) as supplied by the interrupt system logic
(i.e., 82C59A Priority Interrupt Controller). This byte identi-
fies the source (type) of the interrupt. It is multiplied by four
and used as a pointer into an interrupt vector lookup table,
as described earlier.
153
80C86
Bus Timing - Medium Size Systems
types of write strobes, normal and advanced, to be applied
as required. The normal write strobes have data valid at the
leading edge of write. The advanced write strobes have the
same timing as read strobes, and hence, data is not valid at
the leading edge of write. The 82C86/82C87 transceiver
receives the usual T and OE inputs from the 82C88 DT/R
and DEN signals.
For medium complexity systems the MN/MX pin is con-
nected to GND and the 82C88 Bus Controller is added to the
system as well as an 82C82/82C83 latch for latching the
system address, and an 82C86/82C87 transceiver to allow
for bus loading greater than the 80C86 is capable of han-
dling. Signals ALE, DEN, and DT/R are generated by the
82C88 instead of the processor in this configuration, The pointer into the interrupt vector table, which is passed
although their timing remains relatively the same. The during the second INTA cycle, can be derived from an
80C86 status outputs (S2, S1 and S0) provide type-of-cycle 82C59A located on either the local bus or the system bus. If
information and become 82C88 inputs. This bus cycle infor- the master 82C59A Priority Interrupt Controller is positioned
mation specifies read (code, data or I/O), write (data or I/O), on the local bus, the 82C86/82C87 transceiver must be dis-
interrupt acknowledge, or software halt. The 82C88 issues abled when reading from the master 82C59A during the
control signals specifying memory read or write, I/O read or interrupt acknowledge sequence and software “poll”.
write, or interrupt acknowledge. The 82C88 provides two
V
CC
MN/MX
M/IO
V
CC
82C8A/85
CLOCK
INTA
RD
CLK
GENERATOR
READY
RESET
WR
RES
RDY
DT/R
DEN
ALE
WAIT
STATE
GENERATOR
GND
80C86
STB
OE
CPU
GND
ADDR/DATA
GND
1
ADDR
AD0-AD15
A16-A19
82C82
LATCH
2 OR 3
C1
C2
V
CC
BHE
GND
20
T
V
CC
40
OE
DATA
82C86
C1 = C2 = 0.1μF
TRANSCEIVER
(2)
A0
BHE
E
E
L
W G
E
G
CS
RD WR
H
OPTIONAL
FOR INCREASED
HM-6516
CMOS RAM
HM-6616
CMOS PROM (2)
2K x 8 2K x 8
CMOS
DATA BUS DRIVE
82CXX
PERIPHERALS
2K x 8
2K x 8
FIGURE 6A. MINIMUM MODE 80C86 TYPICAL CONFIGURATION
154
80C86
V
CC
CLK
GND
MRDC
MN/MX
S0
CLK
MWTC
AMWC
IORC
82C84A/85
CLOCK
S0
82C88
S1
BUS
NC
NC
READY
RESET
S1
S2
GENERATOR/
S2 CTRLR
DEN
RES
RDY
IOWC
AIOWC
INTA
80C86
CPU
DT/R
ALE
NC
LOCK
WAIT
STATE
GENERATOR
GND
STB
OE
GND
ADDR/DATA
GND
1
ADDR
AD0-AD15
A16-A19
82C82
(2 OR 3)
C1
C2
V
CC
BHE
GND
20
T
V
CC
40
OE
82C86
TRANSCEIVER
(2)
DATA
C1 = C2 = 0.1μF
A0
BHE
E
G
CS
RDWR
E
E
W G
H
L
HM-6616
CMOS PROM (2)
2K x 8 2K x 8
CMOS
82CXX
PERIPHERALS
HM-65162
CMOS RAM
2K x 8
2K x 8
FIGURE 6B. MAXIMUM MODE 80C86 TYPICAL CONFIGURATION
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+8.0V Thermal Resistance (Typical, Note 1)
θ
JA (oC/W)
θ
JC (oC/W)
Input, Output or I/O Voltage . . . . . . . . . . . .GND -0.5V to VCC +0.5V
Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC
Junction Temperature
PDIP Package . . . . . . . . . . . . . . . . . . .
PLCC Package . . . . . . . . . . . . . . . . . .
SBDIP Package. . . . . . . . . . . . . . . . . .
CLCC Package . . . . . . . . . . . . . . . . . .
50
46
30
40
N/A
N/A
6
Ceramic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
Plastic Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC
Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300oC
(Lead tips only for surface mount packages)
6
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9750 Gates
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Operating Conditions
Operating Supply Voltage. . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
M80C86-2 ONLY. . . . . . . . . . . . . . . . . . . . . . . . +4.75V to +5.25V
Operating Temperature Range: C80C86/-2 . . . . . . . . 0oC to +70oC
I80C86/-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
M80C86/-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
DC Electrical Specifications VCC = 5.0V, ±10%; TA = 0oC to +70oC (C80C86, C80C86-2)
VCC = 5.0V, ±10%; TA = -40oC to +85oC (l80C86, I80C86-2)
VCC = 5.0V, ±10%; TA = -55oC to +125oC (M80C86)
VCC = 5.0V, ±5%; TA = -55oC to +125oC (M80C86-2)
SYMBOL
PARAMETER
MIN
MAX
UNITS
TEST CONDITION
VlH
Logical One
Input Voltage
2.0
2.2
V
V
C80C86, I80C86 (Note 5)
M80C86 (Note 5)
155
80C86
DC Electrical Specifications VCC = 5.0V, ±10%; TA = 0oC to +70oC (C80C86, C80C86-2)
VCC = 5.0V, ±10%; TA = -40oC to +85oC (l80C86, I80C86-2)
VCC = 5.0V, ±10%; TA = -55oC to +125oC (M80C86)
VCC = 5.0V, ±5%; TA = -55oC to +125oC (M80C86-2)
SYMBOL
VIL
PARAMETER
Logical Zero Input Voltage
CLK Logical One Input Voltage
CLK Logical Zero Input Voltage
Output High Voltage
MIN
VCC -0.8
3.0
MAX
UNITS
TEST CONDITION
0.8
V
V
V
VIHC
VILC
0.8
VOH
V
V
lOH = -2.5mA
lOH = -100μA
V
CC -0.4
VOL
II
Output Low Voltage
0.4
1.0
V
lOL = +2.5mA
Input Leakage Current
-1.0
μA
VIN = GND or VCC DIP
Pins 17-19, 21-23, 33
lBHH
lBHL
Input Current-Bus Hold High
Input Current-Bus Hold Low
Output Leakage Current
-40
-400
400
-10.0
500
10
μA
μA
VIN = - 3.0V (Note 1)
VIN = - 0.8V (Note 2)
VOUT = GND (Note 4)
VCC = - 5.5V (Note 3)
40
-
IO
μA
ICCSB
ICCOP
Standby Power Supply Current
Operating Power Supply Current
-
μA
-
mA/MHz
FREQ = Max, VIN = VCC or GND,
Outputs Open
Capacitance TA = 25oC
SYMBOL
CIN
PARAMETER
TYPICAL
UNITS
pF
TEST CONDITIONS
Input Capacitance
Output Capacitance
I/O Capacitance
25
25
25
FREQ = 1MHz. All measurements are referenced to device GND
FREQ = 1MHz. All measurements are referenced to device GND
FREQ = 1MHz. All measurements are referenced to device GND
COUT
pF
CI/O
pF
NOTES:
2. lBHH should be measured after raising VIN to VCC and then lowering to 3.0V on the following pins 2-16, 26-32, 34-39.
3. IBHL should be measured after lowering VIN to GND and then raising to 0.8V on the following pins: 2-16, 34-39.
4. lCCSB tested during clock high time after halt instruction executed. VIN = VCC or GND, VCC = 5.5V, Outputs unloaded.
5. IO should be measured by putting the pin in a high impedance state and then driving VOUT to GND on the following pins: 26-29 and 32.
6. MN/MX is a strap option and should be held to VCC or GND.
AC Electrical Specifications VCC = 5.0V ±10%; TA = 0oC to +70oC (C80C86, C80C86-2)
VCC = 5.0V ±100%; TA = -40oC to +85oC (I80C86, I80C86-2)
VCC = 5.0V ±100%; TA = -55oC to +125oC (M80C86)
VCC = 5.0V ±5%; TA = -55oC to +125oC (M80C86-2)
MINIMUM COMPLEXITY SYSTEM
80C86
MIN
80C86-2
MIN
TEST
CONDITIONS
SYMBOL
PARAMETER
MAX
MAX
UNITS
TIMING REQUIREMENTS
(1)
(2)
(3)
(4)
(5)
TCLCL
TCLCH
TCHCL
Cycle Period
200
118
69
125
68
ns
ns
ns
ns
ns
CLK Low Time
CLK High Time
44
TCH1CH2 CLK Rise Time
TCL2C1 CLK FaIl Time
10
10
10
10
From 1.0V to 3.5V
From 3.5V to 1.0V
156
80C86
AC Electrical Specifications VCC = 5.0V ±10%; TA = 0oC to +70oC (C80C86, C80C86-2)
VCC = 5.0V ±100%; TA = -40oC to +85oC (I80C86, I80C86-2)
VCC = 5.0V ±100%; TA = -55oC to +125oC (M80C86)
VCC = 5.0V ±5%; TA = -55oC to +125oC (M80C86-2) (Continued)
MINIMUM COMPLEXITY SYSTEM
80C86
MIN
80C86-2
MIN
TEST
CONDITIONS
SYMBOL
TDVCL
TCLDX1 Data In Hold Time
PARAMETER
MAX
MAX
UNITS
ns
(6)
(7)
(8)
Data In Setup Time
30
10
35
20
10
35
ns
TR1VCL
TCLR1X
RDY Setup Time into 82C84A
(Notes 7, 8)
ns
(9)
RDY Hold Time into 82C84A
(Notes 7, 8)
0
0
ns
(10)
(11)
(12)
(13)
(14)
TRYHCH READY Setup Time into 80C86
TCHRYX READY Hold Time into 80C86
TRYLCL READY Inactive to CLK (Note 9)
118
30
-8
68
20
-8
ns
ns
ns
ns
ns
THVCH
TINVCH
HOLD Setup Time
35
30
20
15
lNTR, NMI, TEST Setup Time
(Note 8)
(15)
(16)
TILIH
TIHIL
Input Rise Time (Except CLK)
Input FaIl Time (Except CLK)
15
15
15
15
ns
ns
From 0.8V to 2.0V
From 2.0V to 0.8V
TIMING RESPONSES
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
TCLAV
TCLAX
TCLAZ
TCHSZ
TCHSV
TLHLL
Address Valid Delay
Address Hold Time
Address Float Delay
Status Float Delay
Status Active Delay
ALE Width
10
10
110
10
10
60
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CL = 100pF
CL = 100pF
CL = 100pF
CL = 100pF
CL = 100pF
CL = 100pF
CL = 100pF
CL = 100pF
CL = 100pF
CL = 100pF
CL = 100pF
CL = 100pF
CL = 100pF
CL = 100pF
TCLAX
80
80
TCLAX
50
50
60
10
110
10
TCLCH-20
TCLCH-10
TCLLH
TCHLL
TLLAX
ALE Active Delay
80
85
50
55
ALE Inactive Delay
Address Hold Time to ALE Inactive
Data Valid Delay
TCHCL-10
TCHCL-10
TCLDV
TCLDX2
TWHDX
TCVCTV
10
10
110
10
10
60
Data Hold Time
Data Hold Time After WR
Control Active Delay 1
TCLCL-30
10
TCLCL-30
10
110
110
70
60
TCHCTV Control Active Delay 2
10
10
157
80C86
AC Electrical Specifications VCC = 5.0V ±10%; TA = 0oC to +70oC (C80C86, C80C86-2)
VCC = 5.0V ±100%; TA = -40oC to +85oC (I80C86, I80C86-2)
VCC = 5.0V ±100%; TA = -55oC to +125oC (M80C86)
VCC = 5.0V ±5%; TA = -55oC to +125oC (M80C86-2) (Continued)
MINIMUM COMPLEXITY SYSTEM
80C86
MIN
80C86-2
MIN
TEST
CONDITIONS
SYMBOL
TCVCTX
PARAMETER
Control Inactive Delay
Address Float to READ Active
RD Active Delay
MAX
MAX
UNITS
ns
(31)
(32)
10
0
110
10
0
70
CL = 100pF
TAZRL
TCLRL
TCLRH
TRHAV
TCLHAV
TRLRH
TWLWH
TAVAL
TOLOH
TOHOL
ns
CL = 100pF
(33)
10
165
150
10
100
80
ns
CL = 100pF
(34)
RD Inactive Delay
10
10
ns
CL = 100pF
(35)
RD Inactive to Next Address Active
HLDA Valid Delay
TCLCL-45
10
TCLCL-40
10
ns
CL = 100pF
(36)
160
100
ns
CL = 100pF
(37)
RD Width
2TCLCL-75
2TCLCL-60
TCLCH-60
2TCLCL-50
2TCLCL-40
TCLCH-40
ns
CL = 100pF
(38)
WR Width
ns
CL = 100pF
(39)
Address Valid to ALE Low
Output Rise Time
ns
CL = 100pF
(40)
20
20
15
15
ns
From 0.8V to 2.0V
From 2.0V to 0.8V
(41)
Output Fall Time
ns
NOTES:
7. Signal at 82C84A shown for reference only.
8. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.
9. Applies only to T2 state (8ns into T3).
158
80C86
Waveforms
T1
T2
T3
T4
T
W
(5)
TCL2CL1
(1)
TCLCL
TCH1CH2
(4)
CLK (82C84A OUTPUT)
(2)
TCLCH
(3)
TCHCTV
(30)
TCHCL
(30) TCHCTV
M/IO
(17)
TCLAV
(17)
TCLAV
(26) TCLDV
(18) TCLAX
S7-S3
BHE, A19-A16
TLHLL
BHE/S7, A19/S6-A16/S3
(23) TCLLH
(22)
TLLAX
(25)
ALE
(24)
TR1VCL (8)
TCHLL
V
IH
RDY (82C84A INPUT)
SEE NOTE
TAVAL
(39)
V
IL
TCLR1X (9)
(12)
TRYLCL
(11)
TCHRYX
READY (80C86 INPUT)
(10)
TRYHCH
(7)
TCLDX1
(19)
TCLAZ
(16)
TDVCL
AD15-AD0
DATA IN
(34) TCLRH
AD15-AD0
RD
(35)
TRHAV
(32) TAZRL
(30)
TCHCTV
(30)
TCHCTV
READ CYCLE
(WR, INTA = V
TRLRH
(37)
TCLRL
(33)
)
OH
DT/R
DEN
(29) TCVCTV
TCVCTX
(31)
FIGURE 7A. BUS TIMING - MINIMUM MODE SYSTEM
NOTE: Signals at 82C84A are shown for reference only. RDY is sampled near the end of T2, T3, TW to determine if TW machine states are
to be inserted.
159
80C86
Waveforms (Continued)
T1
T2
T3
(5)
TCL2CL1
TW
T4
(4)
TCH1CH2
TW
CLK (82C84A OUTPUT)
(26)
TCLDV
TCLAX
(27)
TCLDX2
(17)
TCLAV
(18)
AD15-AD0
DATA OUT
AD15-AD0
TWHDX
(28)
(29)
TCVCTV
(31) TCVCTX
WRITE CYCLE
DEN
WR
(RD, INTA,
DT/R = V
)
OH
(29) TCVCTV
(38)
TWLWH
TCVCTX
TDVCL
(31)
(6)
(19)
TCLAZ
TCLDX1 (7)
POINTER
AD15-AD0
TCHCTV (30)
TCHCTV
(30)
DT/R
INTA
INTA CYCLE
(SEE NOTE)
(29) TCVCTV
(RD, WR = V
OH
BHE = V
)
OL
TCVCTX
(31)
(29) TCVCTV
DEN
SOFTWARE
HALT -
INVALID ADDRESS
SOFTWARE HALT
AD15-AD0
DEN, RD,
TCLAV
(17)
WR, INTA = V
OH
DT/R = INDETERMINATE
FIGURE 7B. BUS TIMING - MINIMUM MODE SYSTEM
NOTE: Two INTA cycles run back-to-back. The 80C86 local ADDR/DATA bus is floating during both INTA cycles. Control signals are shown
for the second INTA cycle.
160
80C86
AC Electrical Specifications VCC = 5.0V ±10% TA = 0oC to +70oC (C80C86, C80C86-2)
VCC = 5.0V ±10%; TA = -40oC to +85oC (I80C86, I80C86-2)
VCC = 5.0V ±10%; TA = -55oC to +125oC (M80C86)
VCC = 5.0V ±5%; TA = -55oC to +125oC (M80C86-2)
MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER)
TIMING REQUIREMENTS
PARAMETER
80C86
MAX
80C86-2
SYMBOL
TCLCL
MIN
200
118
69
MIN
MAX
UNITS TEST CONDITIONS
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
CLK Cycle Period
CLK Low Time
CLK High Time
125
68
ns
ns
ns
TCLCH
TCHCL
44
TCH1CH2 CLK Rise Time
TCL2CL1 CLK Fall Time
10
10
10
10
ns
ns
ns
ns
ns
From 1.0V to 3.5V
From 3.5V to 1.0V
TDVCL
TCLDX1
TR1VCL
Data in Setup Time
Data In Hold Time
30
10
35
20
10
35
RDY Setup Time into 82C84A
(Notes 10, 11)
(9)
TCLR1X
RDY Hold Time into 82C84A
(Notes 10, 11)
0
0
ns
(10)
(11)
(12)
(13)
TRYHCH READY Setup Time into 80C86
TCHRYX READY Hold Time into 80C86
118
30
-8
68
20
-8
ns
ns
ns
ns
TRYLCL
TlNVCH
READY Inactive to CLK (Note 12)
Setup Time for Recognition (lNTR,
NMl, TEST) (Note 11)
30
15
(14)
(15)
TGVCH
TCHGX
RQ/GT Setup Time
30
40
15
30
ns
ns
RQ Hold Time into 80C86 (Note 13)
TCHCL+
10
TCHCL+
10
(16)
(17)
TILlH
TIHIL
Input Rise Time (Except CLK)
Input Fall Time (Except CLK)
15
15
15
15
ns
ns
From 0.8V to 2.0V
From 2.0V to 0.8V
TIMING RESPONSES
(18)
(19)
(20)
(21)
(22)
TCLML
Command Active Delay (Note 10)
5
5
35
35
5
5
35
35
65
60
70
ns
ns
ns
ns
ns
CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
TCLMH
Command Inactive (Note 10)
CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
TRYHSH READY Active to Status Passive
(Notes 12, 14)
110
110
130
CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
TCHSV
TCLSH
Status Active Delay
10
10
10
10
CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
Status Inactive Delay (Note 14)
CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
161
80C86
AC Electrical Specifications VCC = 5.0V ±10% TA = 0oC to +70oC (C80C86, C80C86-2)
VCC = 5.0V ±10%; TA = -40oC to +85oC (I80C86, I80C86-2)
VCC = 5.0V ±10%; TA = -55oC to +125oC (M80C86)
VCC = 5.0V ±5%; TA = -55oC to +125oC (M80C86-2) (Continued)
MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER)
TIMING REQUIREMENTS
PARAMETER
80C86
MAX
80C86-2
SYMBOL
TCLAV
MIN
MIN
MAX
UNITS TEST CONDITIONS
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
(31)
(32)
(33)
(34)
Address Valid Delay
10
110
10
60
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
TCLAX
TCLAZ
TCHSZ
TSVLH
Address Hold Time
10
10
CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
Address Float Delay
TCLAX
80
80
20
30
20
25
18
15
110
TCLAX
50
50
20
30
20
25
18
15
60
CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
Status Float Delay
CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
Status Valid to ALE High (Note 10)
CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
TSVMCH Status Valid to MCE High (Note 10)
CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
TCLLH
CLK low to ALE Valid (Note 10)
CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
TCLMCH CLK low to MCE High (Note 10)
CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
TCHLL
TCLMCL
TCLDV
ALE Inactive Delay (Note 10)
MCE Inactive Delay (Note 10)
Data Valid Delay
4
4
CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
10
10
10
10
CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
TCLDX2
Data Hold Time
CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
162
80C86
AC Electrical Specifications VCC = 5.0V ±10% TA = 0oC to +70oC (C80C86, C80C86-2)
VCC = 5.0V ±10%; TA = -40oC to +85oC (I80C86, I80C86-2)
VCC = 5.0V ±10%; TA = -55oC to +125oC (M80C86)
VCC = 5.0V ±5%; TA = -55oC to +125oC (M80C86-2) (Continued)
MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER)
TIMING REQUIREMENTS
PARAMETER
80C86
MAX
80C86-2
SYMBOL
TCVNV
MIN
MIN
MAX
UNITS TEST CONDITIONS
(35)
Control Active Delay (Note 10)
5
45
5
45
ns
CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
(36)
(37)
(38)
(39)
(40)
TCVNX
TAZRL
TCLRL
TCLRH
TRHAV
Control Inactive Delay (Note 10)
Address Float to Read Active
RD Active Delay
10
0
45
10
0
45
ns
ns
ns
ns
ns
CL = 100pF
CL = 100pF
CL = 100pF
CL = 100pF
CL = 100pF
10
10
165
150
10
10
100
80
RD Inactive Delay
RD Inactive to Next Address Active
TCLCL
-45
TCLCL
-40
(41)
(42)
TCHDTL
Direction Control Active Delay
(Note 10)
50
30
50
30
ns
ns
CL = 100pF
CL = 100pF
TCHDTH Direction Control Inactive Delay
(Note 10)
(43)
(44)
(45)
TCLGL
TCLGH
TRLRH
GT Active Delay
GT Inactive Delay
RD Width
10
10
85
85
0
0
50
50
ns
ns
ns
CL = 100pF
CL = 100pF
CL = 100pF
2TCLC
L -75
2TCLC
L -50
(46)
TOLOH
TOHOL
Output Rise Time
Output Fall Time
20
20
15
15
ns
ns
From 0.8V to 2.0V
From 2.0V to 0.8V
(47)
NOTES:
10. Signal at 82C84A or 82C88 shown for reference only.
11. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.
12. Applies only to T2 state (8ns into T3).
13. The 80C86 actively pulls the RQ/GT pin to a logic one on the following clock low time.
14. Status lines return to their inactive (logic one) state after CLK goes low and READY goes high.
163
80C86
Waveforms
T
T
T
T
4
1
2
3
(4)
TCH1CH2
(1)
TCLCL
(5)
TCL2CL1
T
W
CLK
(23)
TCLAV
TCLCH
(2)
TCHCL (3)
QS0, QS1
TCLSH
(21) TCHSV
S2, S1, S0 (EXCEPT HALT)
(23) TCLAV
(22)
(33)
(SEE NOTE 17)
TCLDV
TCLAX
TCLAV
(23)
(24)
BHE/S7, A19/S6-A16/S3
TSVLH
BHE, A19-A16
(31)
S7-S3
TCHLL
(27)
TCLLH
(29)
ALE (82C88 OUTPUT)
NOTE
TR1VCL
(8)
RDY (82C84 INPUT)
TCLR1X
(9)
(12) TRYLCL
(11)
TCHRYX
READY 80C86 INPUT)
TRYHSH
(20)
(24)
TCLAX
(10)
TRYHCH
(7)
TCLDX1
(6)
TDVCL
(25)
READ CYCLE
TCLAV
(23)
TCLAZ
AD15-AD0
(37) TAZRL
DATA IN
(39) TCLRH
AD15-AD0
RD
TRHAV
(40)
(42)
TCHDTH
(41) TCHDTL
TRLRH
(45)
TCLRL
(38)
DT/R
TCLML
(18)
TCLMH
(19)
82C88
OUTPUTS
SEE NOTES
15, 16
MRDC OR IORC
(35) TCVNV
DEN
(36)
TCVNX
FIGURE 8A. BUS TIMING - MAXIMUM MODE (USING 82C88)
NOTES:
15. Signals at 82C84A or 82C88 are shown for reference only. RDY is sampled near the end of T2, T3, TW to determine if TW machine states
are to be inserted.
16. The issuance of the 82C88 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA, and DEN) lags the active
high 82C88 CEN.
17. Status inactive in state just prior to T4.
164
80C86
Waveforms (Continued)
T1
T2
T3
T4
TW
CLK
TCHSV (21)
(SEE NOTE 20))
TCLDX2
S2, S1, S0 (EXCEPT HALT)
(23)
TCLAV
(22)
TCLDV
TCLAX
(33)
(24)
(34)
WRITE CYCLE
AD -AD
TCLSH
DATA
15
0
TCVNX (36)
TCVNV
(35)
DEN
TCLMH
(19)
82C88
OUTPUTS
(18) TCLML
SEE NOTES
18, 19
AMWC OR AIOWC
TCLMH (19)
(18)TCLML
MWTC OR IOWC
INTA CYCLE
AD15-AD0
(SEE NOTES 21, 22)
RESERVED FOR
CASCADE ADDR
(25) TCLAZ
AD15-AD0
(6)
TDVCL
POINTER
TCLDX1 (7)
(32)
TCLMCL
(28) TSVMCH
(41)
TCHDTL
MCE/PDEN
(30) TCLMCH
TCHDTH
(42)
DT/R
82C88 OUTPUTS
SEE NOTES 18, 19
(18) TCLML
INTA
(19) TCLMH
TCVNV
(35)
DEN
TCVNX
(36)
SOFTWARE
HALT - RD, MRDC, IORC, MWTC, AMWC, IOWC, AIOWC, INTA, S0, S1 = VOH
INVALID ADDRESS
AD15-AD0
TCLAV
(23)
S2
TCLSH
(22)
TCHSV
(21)
FIGURE 8B. BUS TIMING - MAXIMUM MODE (USING 82C88)
NOTES:
18. Signals at 82C84A or 82C86 are shown for reference only.
19. The issuance of the 82C88 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA and DEN) lags the active
high 82C88 CEN.
20. Status inactive in state just prior to T4.
21. Cascade address is valid between first and second INTA cycles.
22. Two INTA cycles run back-to-back. The 80C86 local ADDR/DATA bus is floating during both INTA cycles. Control for pointer address is
shown for second INTA cycle.
165
80C86
Waveforms (Continued)
ANY
CLK
CYCLE
>0-CLK
CYCLES
CLK
TCLGH
(44)
TGVCH (14)
TCHGX (15)
TCLGL
(43)
TCLGH (44)
(1)
TCLCL
PULSE 2
80C86 GT
RQ/GT
PREVIOUS GRANT
AD15-AD0
PULSE 3
PULSE 1
COPROCESSOR
RELEASE
COPROCESSOR
TCLAZ (25)
TCHSZ (26)
RQ
80C86
COPROCESSOR
TCHSV (21)
(SEE NOTE)
RD, LOCK
BHE/S7, A19/S0-A16/S3
S2, S1, S0
NOTE: The coprocessor may not drive the busses outside the region shown without risking contention.
FIGURE 9. REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY)
≥ 1CLK
CYCLE
1 OR 2
CYCLES
CLK
THVCH (13)
THVCH (13)
HOLD
TCLHAV (36)
TCLHAV (36)
HLDA
TCLAZ (19)
COPROCESSOR
TCHSZ (20)
80C86
80C86
TCHSV (21)
AD15-AD0
BHE/S7, A19/S6-A16/S3
RD, WR, M/IO, DT/R, DEN
FIGURE 10. HOLD/HOLD ACKNOWLEDGE TIMING (MINIMUM MODE ONLY)
ANY CLK CYCLE
ANY CLK CYCLE
CLK
CLK
(13)
TINVCH (SEE NOTE)
NMI
INTR
TEST
TCLAV
(23)
TCLAV
(23)
SIGNAL
LOCK
NOTE: Setup requirements for asynchronous signals only to guar-
antee recognition at next CLK.
FIGURE 12. BUS LOCK SIGNAL TIMING (MAXIMUM MODE
ONLY)
FIGURE 11. ASYNCHRONOUS SIGNAL RECOGNITION
166
80C86
Waveforms (Continued)
≥ 50μs
V
CC
CLK
(7) TCLDX1
(6) TDVCL
RESET
≥ 4 CLK CYCLES
FIGURE 13. RESET TIMING
AC Test Circuit
OUTPUT FROM
DEVICE UNDER TEST
TEST POINT
C
(SEE NOTE)
L
NOTE: Includes stay and jig capacitance.
AC Testing Input, Output Waveform
INPUT
OUTPUT
V
+ 20% V
IH
IH
V
V
OH
OL
1.5V
1.5V
V
- 50% V
IL
IL
NOTE: AC Testing: All input signals (other than CLK) must switch between VILMAX -50% VIL and VIHMIN +20% VIH. CLK must switch between
0.4V and VCC.-0.4 Input rise and fall times are driven at 1ns/V.
167
80C86
Burn-In Circuits
MD80C86 CERDIP
C
GND
1
2
3
4
5
6
7
8
9
GND
V
40
GND
GND
V
CC
CC
RIO
RIO
RIO
AD14
AD13
AD12
AD11
AD10
AD9
AD15 39
AD16 38
AD17 37
AD18 36
AD19 35
BHE 34
V
CL
RO
V
V
CL
CC/2
RIO
RIO
RIO
RO
RO
RO
GND
GND
V
V
V
V
CC/2
CC/2
V
CL
CC/2
CC/2
RIO
RIO
RIO
RIO
RIO
RIO
RO
GND
GND
GND
33
32
31
30
29
28
27
26
25
24
23
22
21
AD8
MX
RD
GND
RO
RI
AD7
V
CC/2
10 AD6
11 AD5
12 AD4
13 AD3
14 AD2
15 AD1
16 AD0
17 NMI
18 INTR
19 CLK
20 GND
RQ0
RQ1
LOCK
S2
V
V
CL
CL
RO
RO
V
V
CL
CL
V
V
CC/2
CL
RO
RO
V
OPEN
OPEN
CC/2
S1
V
CC/2
RO
RO
RO
S0
V
OPEN
OPEN
GND
CC/2
QS0
V
CC/2
QS2
V
CC/2
GND
TEST
READY
RESET
GND
RI
RI
RC
V
F
0
CL
NODE
FROM
GND
A
PROGRAM
CARD
NOTES:
COMPONENTS:
VCC = 5.5V ±0.5V, GND = 0V.
Input voltage limits (except clock):
1. RI = 10kΩ ±5%, 1/4W
2. RO = 1.2kΩ ±5%, 1/4W
3. RIO = 2.7kΩ ±5%, 1/4W
4. RC = 1kΩ ±±5%, 1/4W
5. C = 0.01μF (Minimum)
V
V
V
V
IL (maximum) = 0.4V
IH (minimum) = 2.6V, VIH (clock) = (VCC -0.4V) minimum.
CC/2 is external supply set to 2.7V ±10%.
CL is generated on program card (VCC - 0.65V).
Pins 13 - 16 input sequenced instructions from internal hold devices.
F0 = 100kHz ±10%.
Node
= a 40μs pulse every 2.56ms.
A
168
80C86
Burn-In Circuits (Continued)
MR80C86 CLCC
C
V
V
CC
CL
44
43 42 41 40
6
5
4
3
2
1
RIO
RIO
7
39
38
37
36
35
34
33
32
31
30
29
RO
RO
8
RIO
RIO
RIO
9
10
11
12
13
14
15
16
17
RO
RI
RIO
RIO
RI
RO
RO
RO
RO
18 19 20 21 22 23 24 25 26 27 28
V
CC/2
GND
F
0
A
(FROM PROGRAM CARD)
NOTES:
COMPONENTS:
VCC = 5.5V ±0.5V, GND = 0V.
Input voltage limits (except clock):
1. RI = 10kΩ ±5%, 1/4W
2. RO = 1.2kΩ ±5%, 1/4W
3. RIO = 2.7kΩ ±5%, 1/4W
4. RC = 1kΩ ±±5%, 1/4W
5. C = 0.01μF (Minimum)
V
V
V
V
IL (maximum) = 0.4V
IH (minimum) = 2.6V, VIH (clock) = (VCC -0.4V) minimum.
CC/2 is external supply set to 2.7V ±10%.
CL is generated on program card (VCC - 0.65V).
Pins 13 - 16 input sequenced instructions from internal hold devices.
F0 = 100kHz ±10%.
Node
= a 40μs pulse every 2.56ms.
A
169
80C86
Metallization Topology
DIE DIMENSIONS:
GLASSIVATION:
249.2 x 290.9 x 19
Type: Nitrox
Thickness: 10kÅ ±2kÅ
METALLIZATION:
Type: Silicon - Aluminum
Thickness: 11kÅ ±2kÅ
WORST CASE CURRENT DENSITY:
1.5 x 105 A/cm2
Metallization Mask Layout
80C86
AD11
AD12
AD13 AD14 GND
V
AD15 A16/S3 A17/S4 A18/S5
CC
A19/S6
AD10
AD9
BHE/S7
MN/MX
AD8
AD7
RD
RQ/GT0
AD6
AD5
RQ/GT1
AD4
AD3
LOCK
S2
AD2
AD1
AD0
S1
S0
NMI INTR CLK
GND
RESET READY TEST QS1 QS0
170
80C86
Instruction Set Summary
INSTRUCTION CODE
MNEMONIC AND DESCRIPTION
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
DATA TRANSFER
MOV = MOVE:
Register/Memory to/from Register
Immediate to Register/Memory
Immediate to Register
Memory to Accumulator
Accumulator to Memory
Register/Memory to Segment Register ††
Segment Register to Register/Memory
PUSH = Push:
1 0 0 0 1 0 d w
1 1 0 0 0 1 1 w
1 0 1 1 w reg
mod reg r/m
mod 0 0 0 r/m
data
data
data if w 1
data if w 1
addr-high
addr-high
1 0 1 0 0 0 0 w
1 0 1 0 0 0 1 w
1 0 0 0 1 1 1 0
1 0 0 0 1 1 0 0
addr-low
addr-low
mod 0 reg r/m
mod 0 reg r/m
Register/Memory
1 1 1 1 1 1 1 1
0 1 0 1 0 reg
0 0 0 reg 1 1 0
mod 1 1 0 r/m
mod 0 0 0 r/m
Register
Segment Register
POP = Pop:
Register/Memory
1 0 0 0 1 1 1 1
0 1 0 1 1 reg
0 0 0 reg 1 1 1
Register
Segment Register
XCHG = Exchange:
Register/Memory with Register
Register with Accumulator
IN = Input from:
1 0 0 0 0 1 1 w
1 0 0 1 0 reg
mod reg r/m
port
Fixed Port
1 1 1 0 0 1 0 w
1 1 1 0 1 1 0 w
Variable Port
OUT = Output to:
Fixed Port
1 1 1 0 0 1 1 w
1 1 1 0 1 1 1 w
1 1 0 1 0 1 1 1
1 0 0 0 1 1 0 1
1 1 0 0 0 1 0 1
1 1 0 0 0 1 0 0
1 0 0 1 1 1 1 1
1 0 0 1 1 1 1 0
1 0 0 1 1 1 0 0
1 0 0 1 1 1 0 1
port
Variable Port
XLAT = Translate Byte to AL
LEA = Load EA to Register2
LDS = Load Pointer to DS
LES = Load Pointer to ES
LAHF = Load AH with Flags
SAHF = Store AH into Flags
PUSHF = Push Flags
POPF = Pop Flags
mod reg r/m
mod reg r/m
mod reg r/m
ARITHMETIC
ADD = Add:
Register/Memory with Register to Either
Immediate to Register/Memory
Immediate to Accumulator
ADC = Add with Carry:
0 0 0 0 0 0 d w
1 0 0 0 0 0 s w
0 0 0 0 0 1 0 w
mod reg r/m
mod 0 0 0 r/m
data
data
data if s:w = 01
data if w = 1
Register/Memory with Register to Either
0 0 0 1 0 0 d w
mod reg r/m
171
80C86
Instruction Set Summary (Continued)
INSTRUCTION CODE
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MNEMONIC AND DESCRIPTION
Immediate to Register/Memory
Immediate to Accumulator
INC = Increment:
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
1 0 0 0 0 0 s w
mod 0 1 0 r/m
data
data
data if s:w = 01
0 0 0 1 0 1 0 w
data if w = 1
Register/Memory
1 1 1 1 1 1 1 w
0 1 0 0 0 reg
mod 0 0 0 r/m
Register
AAA = ASCll Adjust for Add
DAA = Decimal Adjust for Add
SUB = Subtract:
0 0 1 1 0 1 1 1
0 0 1 0 0 1 1 1
Register/Memory and Register to Either
Immediate from Register/Memory
Immediate from Accumulator
SBB = Subtract with Borrow
Register/Memory and Register to Either
Immediate from Register/Memory
Immediate from Accumulator
DEC = Decrement:
0 0 1 0 1 0 d w
1 0 0 0 0 0 s w
0 0 1 0 1 1 0 w
mod reg r/m
mod 1 0 1 r/m
data
data
data if s:w = 01
data if s:w = 01
data if w = 1
0 0 0 1 1 0 d w
1 0 0 0 0 0 s w
0 0 0 1 1 1 0 w
mod reg r/m
mod 0 1 1 r/m
data
data
data if w = 1
Register/Memory
1 1 1 1 1 1 1 w
0 1 0 0 1 reg
mod 0 0 1 r/m
mod 0 1 1 r/m
Register
NEG = Change Sign
1 1 1 1 0 1 1 w
CMP = Compare:
Register/Memory and Register
Immediate with Register/Memory
Immediate with Accumulator
AAS = ASCll Adjust for Subtract
DAS = Decimal Adjust for Subtract
MUL = Multiply (Unsigned)
IMUL = Integer Multiply (Signed)
AAM = ASCll Adjust for Multiply
DlV = Divide (Unsigned)
0 0 1 1 1 0 d w
1 0 0 0 0 0 s w
0 0 1 1 1 1 0 w
0 0 1 1 1 1 1 1
0 0 1 0 1 1 1 1
1 1 1 1 0 1 1 w
1 1 1 1 0 1 1 w
1 1 0 1 0 1 0 0
1 1 1 1 0 1 1 w
1 1 1 1 0 1 1 w
1 1 0 1 0 1 0 1
1 0 0 1 1 0 0 0
1 0 0 1 1 0 0 1
mod reg r/m
mod 1 1 1 r/m
data
data
data if s:w = 01
data if w = 1
mod 1 0 0 r/m
mod 1 0 1 r/m
0 0 0 0 1 0 1 0
mod 1 1 0 r/m
mod 1 1 1 r/m
0 0 0 0 1 0 1 0
IDlV = Integer Divide (Signed)
AAD = ASClI Adjust for Divide
CBW = Convert Byte to Word
CWD = Convert Word to Double Word
LOGIC
NOT = Invert
1 1 1 1 0 1 1 w
1 1 0 1 0 0 v w
1 1 0 1 0 0 v w
1 1 0 1 0 0 v w
1 1 0 1 0 0 v w
1 1 0 1 0 0 v w
1 1 0 1 0 0 v w
mod 0 1 0 r/m
mod 1 0 0 r/m
mod 1 0 1 r/m
mod 1 1 1 r/m
mod 0 0 0 r/m
mod 0 0 1 r/m
mod 0 1 0 r/m
SHL/SAL = Shift Logical/Arithmetic Left
SHR = Shift Logical Right
SAR = Shift Arithmetic Right
ROL = Rotate Left
ROR = Rotate Right
RCL = Rotate Through Carry Flag Left
172
80C86
Instruction Set Summary (Continued)
INSTRUCTION CODE
MNEMONIC AND DESCRIPTION
RCR = Rotate Through Carry Right
AND = And:
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
1 1 0 1 0 0 v w
mod 0 1 1 r/m
Reg./Memory and Register to Either
Immediate to Register/Memory
Immediate to Accumulator
TEST = And Function to Flags, No Result:
Register/Memory and Register
Immediate Data and Register/Memory
Immediate Data and Accumulator
OR = Or:
0 0 1 0 0 0 0 d w
1 0 0 0 0 0 0 w
0 0 1 0 0 1 0 w
mod reg r/m
mod 1 0 0 r/m
data
data
data if w = 1
data if w = 1
1 0 0 0 0 1 0 w
1 1 1 1 0 1 1 w
1 0 1 0 1 0 0 w
mod reg r/m
mod 0 0 0 r/m
data
data
data if w = 1
data if w = 1
data if w = 1
data if w = 1
Register/Memory and Register to Either
Immediate to Register/Memory
Immediate to Accumulator
XOR = Exclusive or:
0 0 0 0 1 0 d w
1 0 0 0 0 0 0 w
0 0 0 0 1 1 0 w
mod reg r/m
mod 1 0 1 r/m
data
data
data if w = 1
Register/Memory and Register to Either
Immediate to Register/Memory
Immediate to Accumulator
STRING MANIPULATION
REP = Repeat
0 0 1 1 0 0 d w
1 0 0 0 0 0 0 w
0 0 1 1 0 1 0 w
mod reg r/m
mod 1 1 0 r/m
data
data
data if w = 1
1 1 1 1 0 0 1 z
1 0 1 0 0 1 0 w
1 0 1 0 0 1 1 w
1 0 1 0 1 1 1 w
1 0 1 0 1 1 0 w
1 0 1 0 1 0 1 w
MOVS = Move Byte/Word
CMPS = Compare Byte/Word
SCAS = Scan Byte/Word
LODS = Load Byte/Word to AL/AX
STOS = Stor Byte/Word from AL/A
CONTROL TRANSFER
CALL = Call:
Direct Within Segment
1 1 1 0 1 0 0 0
1 1 1 1 1 1 1 1
1 0 0 1 1 0 1 0
disp-low
mod 0 1 0 r/m
offset-low
disp-high
Indirect Within Segment
Direct Intersegment
offset-high
seg-high
seg-low
Indirect Intersegment
1 1 1 1 1 1 1 1
mod 0 1 1 r/m
JMP = Unconditional Jump:
Direct Within Segment
1 1 1 0 1 0 0 1
1 1 1 0 1 0 1 1
1 1 1 1 1 1 1 1
1 1 1 0 1 0 1 0
disp-low
disp
disp-high
Direct Within Segment-Short
Indirect Within Segment
Direct Intersegment
mod 1 0 0 r/m
offset-low
seg-low
offset-high
seg-high
Indirect Intersegment
1 1 1 1 1 1 1 1
mod 1 0 1 r/m
RET = Return from CALL:
Within Segment
1 1 0 0 0 0 1 1
1 1 0 0 0 0 1 0
Within Seg Adding lmmed to SP
data-low
data-high
173
80C86
Instruction Set Summary (Continued)
INSTRUCTION CODE
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MNEMONIC AND DESCRIPTION
Intersegment
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
1 1 0 0 1 0 1 1
Intersegment Adding Immediate to SP
JE/JZ = Jump on Equal/Zero
1 1 0 0 1 0 1 0
0 1 1 1 0 1 0 0
0 1 1 1 1 1 0 0
0 1 1 1 1 1 1 0
0 1 1 1 0 0 1 0
0 1 1 1 0 1 1 0
0 1 1 1 1 0 1 0
0 1 1 1 0 0 0 0
data-low
disp
data-high
JL/JNGE = Jump on Less/Not Greater or Equal
JLE/JNG = Jump on Less or Equal/ Not Greater
JB/JNAE = Jump on Below/Not Above or Equal
JBE/JNA = Jump on Below or Equal/Not Above
JP/JPE = Jump on Parity/Parity Even
JO = Jump on Overflow
disp
disp
disp
disp
disp
disp
JS = Jump on Sign
0 1 1 1 1 0 0 0
0 1 1 1 0 1 0 1
0 1 1 1 1 1 0 1
disp
disp
disp
JNE/JNZ = Jump on Not Equal/Not Zero
JNL/JGE = Jump on Not Less/Greater or Equal
JNLE/JG = Jump on Not Less or Equal/Greater
JNB/JAE = Jump on Not Below/Above or Equal
JNBE/JA = Jump on Not Below or Equal/Above
JNP/JPO = Jump on Not Par/Par Odd
JNO = Jump on Not Overflow
JNS = Jump on Not Sign
0 1 1 1 1 1 1 1
0 1 1 1 0 0 1 1
0 1 1 1 0 1 1 1
0 1 1 1 1 0 1 1
0 1 1 1 0 0 0 1
0 1 1 1 1 0 0 1
1 1 1 0 0 0 1 0
1 1 1 0 0 0 0 1
1 1 1 0 0 0 0 0
1 1 1 0 0 0 1 1
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
LOOP = Loop CX Times
LOOPZ/LOOPE = Loop While Zero/Equal
LOOPNZ/LOOPNE = Loop While Not Zero/Equal
JCXZ = Jump on CX Zero
INT = Interrupt
Type Specified
1 1 0 0 1 1 0 1
1 1 0 0 1 1 0 0
1 1 0 0 1 1 1 0
1 1 0 0 1 1 1 1
type
Type 3
INTO = Interrupt on Overflow
IRET = Interrupt Return
PROCESSOR CONTROL
CLC = Clear Carry
1 1 1 1 1 0 0 0
1 1 1 1 0 1 0 1
1 1 1 1 1 0 0 1
1 1 1 1 1 1 0 0
CMC = Complement Carry
STC = Set Carry
CLD = Clear Direction
STD = Set Direction
CLl = Clear Interrupt
ST = Set Interrupt
1 1 1 1 1 1 0 1
1 1 1 1 1 0 1 0
1 1 1 1 1 0 1 1
1 1 1 1 0 1 0 0
1 0 0 1 1 0 1 1
1 1 0 1 1 x x x
1 1 1 1 0 0 0 0
HLT = Halt
WAIT = Wait
ESC = Escape (to External Device)
LOCK = Bus Lock Prefix
mod x x x r/m
174
Instruction Set Summary (Continued)
INSTRUCTION CODE
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MNEMONIC AND DESCRIPTION
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
NOTES:
AL = 8-bit accumulator
AX = 16-bit accumulator
if s:w = 01 then 16-bits of immediate data form the operand.
if s:w. = 11 then an immediate data byte is sign extended
to form the 16-bit operand.
CX = Count register
DS= Data segment
if v = 0 then “count” = 1; if v = 1 then “count” in (CL)
x = don't care
ES = Extra segment
z is used for string primitives for comparison with ZF FLAG.
Above/below refers to unsigned value.
Greater = more positive;
Less = less positive (more negative) signed values
if d = 1 then “to” reg; if d = 0 then “from” reg
if w = 1 then word instruction; if w = 0 then byte
instruction
if mod = 11 then r/m is treated as a REG field
if mod = 00 then DISP = O†, disp-low and disp-high
are absent
if mod = 01 then DISP = disp-low sign-extended
16-bits, disp-high is absent
if mod = 10 then DISP = disp-high:disp-low
if r/m = 000 then EA = (BX) + (SI) + DISP
if r/m = 001 then EA = (BX) + (DI) + DISP
if r/m = 010 then EA = (BP) + (SI) + DISP
if r/m = 011 then EA = (BP) + (DI) + DISP
if r/m = 100 then EA = (SI) + DISP
if r/m = 101 then EA = (DI) + DISP
if r/m = 110 then EA = (BP) + DISP †
if r/m = 111 then EA = (BX) + DISP
DISP follows 2nd byte of instruction (before data
if required)
SEGMENT OVERRIDE PREFIX
001 reg 11 0
REG is assigned according to the following table:
16-BIT (w = 1)
000 AX
001 CX
010 DX
011 BX
100 SP
101 BP
110 SI
8-BIT (w = 0)
000 AL
SEGMENT
00 ES
01 CS
10 SS
11 DS
00 ES
00 ES
00 ES
00 ES
001 CL
010 DL
011 BL
100 AH
101 CH
110 DH
111 BH
111 DI
Instructions which reference the flag register file as a 16-bit
object use the symbol FLAGS to represent the file:
FLAGS =
†
except if mod = 00 and r/m = 110 then
EA = disp-high: disp-low.
X:X:X:X:(OF):(DF):(IF):(TF):(SF):(ZF):X:(AF):X:(PF):X:(CF)
†† MOV CS, REG/MEMORY not allowed.
Mnemonics © Intel, 1978
175
80C86
Dual-In-Line Plastic Packages (PDIP)
E40.6 (JEDEC MS-011-AC ISSUE B)
N
40 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INCHES
MILLIMETERS
INDEX
1 2
3
N/2
AREA
SYMBOL
MIN
MAX
0.250
-
MIN
-
MAX
6.35
-
NOTES
-B-
-C-
A
A1
A2
B
-
4
-A-
0.015
0.125
0.014
0.030
0.008
1.980
0.005
0.600
0.485
0.39
3.18
0.356
0.77
0.204
4
D
E
0.195
0.022
0.070
0.015
2.095
-
4.95
0.558
1.77
0.381
53.2
-
-
BASE
PLANE
A2
A
-
SEATING
PLANE
B1
C
8
L
C
L
-
D1
B1
eA
A1
A
D1
e
D
50.3
5
eC
C
B
D1
E
0.13
15.24
12.32
5
eB
0.010 (0.25) M
C
B S
0.625
0.580
15.87
14.73
6
E1
e
5
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
0.100 BSC
0.600 BSC
2.54 BSC
15.24 BSC
-
eA
eB
L
6
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
-
0.700
0.200
-
17.78
5.08
7
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication No. 95.
0.115
2.93
4
9
4. Dimensions A, A1 and L are measured with the package seated in
N
40
40
JEDEC seating plane gauge GS-3.
Rev. 0 12/93
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
eA
6. E and
are measured with the leads constrained to be per-
-C-
pendicular to datum
.
7. eB and eC are measured at the lead tips with the leads uncon-
strained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dam-
bar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
176
80C86
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 LEAD FINISH
F40.6 MIL-STD-1835 GDIP1-T40 (D-5, CONFIGURATION A)
40 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
-D-
E
-A-
INCHES MILLIMETERS
MIN
BASE
(c)
METAL
SYMBOL
MAX
0.225
0.026
0.023
0.065
0.045
0.018
0.015
2.096
0.620
MIN
-
MAX
5.72
NOTES
b1
A
b
-
-
M
M
(b)
0.014
0.014
0.045
0.023
0.008
0.008
-
0.36
0.36
1.14
0.58
0.20
0.20
-
0.66
2
-B-
b1
b2
b3
c
0.58
3
SECTION A-A
bbb
C A - B
D
D
S
S
S
1.65
-
1.14
4
BASE
PLANE
Q
0.46
2
A
-C-
SEATING
PLANE
c1
D
0.38
3
L
α
53.24
15.75
5
S1
b2
eA
A A
e
E
0.510
12.95
5
b
C A - B
eA/2
aaa M C A - B S D S
c
e
0.100 BSC
2.54 BSC
-
eA
eA/2
L
0.600 BSC
0.300 BSC
15.24 BSC
7.62 BSC
-
ccc
D
S
M
S
-
NOTES:
0.125
0.200
0.070
-
3.18
5.08
1.78
-
-
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
Q
0.015
0.38
6
S1
0.005
0.13
7
90o
105o
0.015
0.030
0.010
0.0015
90o
105o
0.38
0.76
0.25
0.038
-
α
aaa
bbb
ccc
M
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
-
-
-
-
-
-
-
-
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
-
2, 3
8
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
40
40
Rev. 0 4/94
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
177
MD80C86-2/B 替代型号
型号 | 制造商 | 描述 | 替代类型 | 文档 |
CDP1806ACE | INTERSIL | CMOS 8-Bit Microprocessor with On-Chip RAM and Counter/Timer | 功能相似 |
MD80C86-2/B 相关器件
型号 | 制造商 | 描述 | 价格 | 文档 |
MD80C86-2B | INTERSIL | CMOS 16-Bit Microprocessor | 获取价格 | |
MD80C86/883 | ROCHESTER | 16-BIT, 5MHz, MICROPROCESSOR, CDIP40 | 获取价格 | |
MD80C86/B | RENESAS | 16-BIT, 5MHz, MICROPROCESSOR, CDIP40, CERDIP-40 | 获取价格 | |
MD80C86B | INTERSIL | CMOS 16-Bit Microprocessor | 获取价格 | |
MD80C88 | INTERSIL | CMOS 8/16-Bit Microprocessor | 获取价格 | |
MD80C88-2 | INTERSIL | CMOS 8/16-Bit Microprocessor | 获取价格 | |
MD80C88-2/883 | ROCHESTER | 8-BIT, 8 MHz, MICROPROCESSOR, CDIP40 | 获取价格 | |
MD80C88-2/B | RENESAS | 8-BIT, 8MHz, MICROPROCESSOR, CDIP40 | 获取价格 | |
MD80C88-2B | INTERSIL | CMOS 8/16-Bit Microprocessor | 获取价格 | |
MD80C88/883 | ROCHESTER | 8-BIT, 5MHz, MICROPROCESSOR, CDIP40 | 获取价格 |
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