MWS5114D2 [INTERSIL]
1024-Word x 4-Bit LSI Static RAM; 1024字×4位LSI静态RAM
| 型号： | MWS5114D2 |
| 厂家： | 
Intersil |
| 描述： | 1024-Word x 4-Bit LSI Static RAM |
| 文件： | 总7页 (文件大小：32K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MWS5114
1024-Word x 4-Bit
LSI Static RAM
March 1997
Features
Description
• Fully Static Operation
The MWS5114 is a 1024 word by 4-bit static random access
memory that uses the ion-implanted silicon gate comple-
mentary MOS (CMOS) technology. It is designed for use in
memory systems where low power and simplicity in use are
desirable. This type has common data input and data output
and utilizes a single power supply of 4.5V to 6.5V.
• Industry Standard 1024 x 4 Pinout (Same as Pinouts
for 6514, 2114, 9114, and 4045 Types)
• Common Data Input and Output
• Memory Retention for Standby Battery Voltage as Low
as 2V Min
The MWS5114 is supplied in 18 lead, hermetic, dual-in-line
sidebrazed ceramic packages (D suffix) and in 18 lead dual-
in-line plastic packages (E suffix).
• All Inputs and Outputs Directly TTL Compatible
• Three-State Outputs
• Low Standby and Operating Power
Ordering Information
200ns
MWS5114E3
250ns
300ns
MWS5114E1
TEMPERATURE RANGE
PACKAGE
PDIP
Burn-In
SBDIP
Burn-In
PKG. NO.
o
o
MWS5114E2
0 C to +70 C
E18.3
E18.3
MWS5114E2X
MWS5114D2
o
o
MWS5114D3
MWS5114D3X
MWS5114D1
0 C to +70 C
D18.3
D18.3
Pinout
MWS5114
(PDIP, SBDIP)
TOP VIEW
1
2
3
4
5
6
7
8
9
18 V
DD
A6
A5
A4
A3
A0
A1
A2
CS
17 A7
16 A8
15 A9
14 I/O1
13 I/O2
12 I/O3
11 I/O4
10
V
WE
SS
OPERATIONAL MODES
FUNCTION
CS
0
WE
1
DATA PINS
Output: Dependent on data
Input
Read
Write
0
0
Not Selected
1
X
High Impedance
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 1325.2
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 19969-160
MWS5114
Functional Block Diagram
A
A
A
A
A
A
4
5
6
7
8
9
V
V
DD
SS
MEMORY ARRAY
64 ROWS
64 COLUMNS
ROW
SELECT
I/O
I/O
I/O
I/O
1
2
3
4
COLUMN
I/O CIRCUITS
INPUT
DATA
CONTROL
COLUMN SELECT
A
A
A
A
3
0
1
2
CS
ENABLE
WE
6-161
MWS5114
Absolute Maximum Ratings
Thermal Information
o
o
DC Supply Voltage Range, (V
DD
)
Thermal Resistance (Typical)
θ
( C/W)
θ
( C/W)
JA
JC
(All Voltages Referenced to V Terminal). . . . . . . . -0.5V to +7V
SS
Plastic DIP Package . . . . . . . . . . . . . .
SBDIP Package. . . . . . . . . . . . . . . . . .
75
75
N/A
20
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to V
+0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA
DD
Operating Temperature Range (T )
A
o
o
Package Type D. . . . . . . . . . . . . . . . . . . . . . . . . .-55 C to +125 C
Package Type E. . . . . . . . . . . . . . . . . . . . . . . . . . .-40 C to +85 C
Maximum Storage Temperature Range (T
Maximum Junction Temperature
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
o
o
o
o
) . . .-65 C to +150 C
STG
o
o
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150 C
Maximum Lead Temperature. . . . . . . . . . . . . . . . . . . . . . . . . +265 C
o
Recommended Operating Conditions
At T = Full Package Temperature Range. For maximum reliability, operating
A
conditions should be selected so that operation is always within the following ranges:
LIMITS
ALL TYPES
PARAMETER
DC Operating Voltage Range
MIN
MAX
UNITS
4.5
6.5
V
V
Input Voltage Range
V
V
DD
SS
o
o
Static Electrical Specifications At T = 0 C to +70 C, V = ±5%, Except as Noted
A
DD
CONDITIONS
LIMITS
MWS5114-3
MWS5114-2
MWS5114-1
V
V
V
(NOTE 1)
(NOTE 1)
(NOTE 1)
O
IN
DD
PARAMETER
SYMBOL (V)
(V)
(V)
MIN
TYP
MAX MIN
TYP
MAX MIN
TYP
MAX UNITS
Quiescent
Device
IDD
-
0, 5
5
-
75
100
-
75
100
-
75
250
µA
Current
Output Low
(Sink) Current
I
0.4
4.6
0, 5
0, 5
5
5
2
4
-
-
2
4
-
-
2
4
-
-
mA
mA
OL
Output High
(Source)
Current
I
-0.4
-1
-0.4
-1
-0.4
-1
OH
Output Voltage
Low-Level
VOL
VOH
-
-
0, 5
0, 5
-
5
5
5
5
5
5
-
4.9
-
0
5
0.1
-
-
4.9
-
0
5
0.1
-
-
4.9
-
0
5
0.1
-
V
V
Output Voltage
High-Level
Input Low
Voltage
V
0.5,
4.5
1.2
-
0.8
-
1.2
-
0.8
-
1.2
-
0.8
-
V
IL
Input High
Voltage
V
0.5,
4.5
-
2.4
-
2.4
-
2.4
-
V
IH
Input Leakage
Current (Note 2)
IIN
-
-
0, 5
0, 5
±0.1
4
±5
8
±0.1
4
±5
8
±0.1
4
±5
8
µA
mA
Operating
IDD1
-
-
-
Current (Note 3)
6-162
MWS5114
o
o
Static Electrical Specifications At T = 0 C to +70 C, V = ±5%, Except as Noted (Continued)
A
DD
CONDITIONS
LIMITS
MWS5114-3
MWS5114-2
MWS5114-1
V
V
V
(V)
(NOTE 1)
TYP
(NOTE 1)
TYP
(NOTE 1)
TYP
O
IN
(V)
DD
PARAMETER
SYMBOL (V)
MIN
MAX MIN
MAX MIN
MAX UNITS
Three-State
I
0, 5 0, 5
5
-
±0.5
±5
-
±0.5
±5
−
±0.5
±5
µA
OUT
Output Leakage
Current (Note 4)
Input
Capacitance
CI
-
-
-
-
-
-
-
-
5
7.5
15
-
-
5
7.5
15
-
-
5
7.5
15
pF
pF
N
Output
C
10
10
10
OUT
Capacitance
NOTES:
o
1. Typical values are for T = 25 C and nominal V
A
.
DD
2. All inputs in parallel.
3. Outputs open circuited; cycle time = 1µs.
4. All outputs in parallel.
6-163
MWS5114
o
o
Dynamic Electrical Specifications at T = 0 C to +70 C, V = 5V ±5%, Input t , t = 10ns; C = 50pF and 1 TTL Load
A
DD
R
F
L
LIMITS
MWS5114-3
MWS5114-2
MWS5114-1
(NOTE 1) (NOTE 2)
(NOTE 1) (NOTE 2)
(NOTE 1) (NOTE 2)
PARAMETER
SYMBOL
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
READ CYCLE TIMES (FIGURE 1)
Read Cycle
tRC
tAA
200
-
160
160
-
250
-
200
200
-
300
-
250
250
-
ns
ns
Access from
Address
200
250
300
Chip Selection to
Output Valid
tCO
tCX
-
110
100
75
150
-
150
100
75
200
-
200
100
75
250
ns
ns
ns
ns
Chip Selection to
Output Active
20
-
-
125
-
20
-
-
125
-
20
-
-
125
-
Output Three-State
from Deselection
tOTD
tOHA
Output Hold from
Address Change
50
100
50
100
50
100
WRITE CYCLE TIMES (FIGURE 2)
Write Cycle
Write
tWC
tW
200
125
50
160
100
40
-
-
-
-
250
150
50
200
120
40
-
-
-
-
300
200
50
220
140
40
-
-
-
-
ns
ns
ns
ns
Write Release
tWR
tACS
Address to Chip
0
0
0
0
0
0
Select Setup Time
Address to Write
Setup Time
tAW
tDSU
tDH
25
75
30
20
50
10
-
-
-
50
75
30
40
50
10
-
-
-
50
75
30
40
50
10
-
-
-
ns
ns
ns
Data to Write
Setup Time
Data Hold from
Write
NOTES:
1. Time required by a limit device to allow for the indicated function.
o
2. Typical values are for T = 25 C and nominal V
.
DD
A
6-164
MWS5114
tRC
tAA
ADDRESS
CS
tCO
tCX
tOTD
tOHA
D
ACTIVE
VALID
OUT
NOTE:
1. WE is high during the Read Cycle. Timing measurement reference level is 1.5V.
FIGURE 1. READ CYCLE TIMING WAVEFORMS
tWC
ADDRESS
tACS
tWR
CS
tAW
tW
WE
tDSU
tDH
DON’T CARE
VALID
D
IN
NOTE:
1. WE is low during the Write Cycle. Timing measurement reference level is 1.5V.
FIGURE 2. WRITE CYCLE TIMING WAVEFORMS
o
o
Data Retention Specifications at T = 0 C to +70 C; See Figure 3
A
TEST
CONDITIONS
LIMITS
ALL TYPES
V
V
(NOTE 1)
DR
DD
PARAMETER
SYMBOL
VDR
(V)
(V)
MIN
TYP
MAX
UNITS
V
Minimum Data Retention Voltage
-
-
2
-
25
25
60
-
-
50
50
125
-
Data Retention Quiescent
Current
MWS5114-3
MWS5114-2
MWS5114-1
IDD
2
2
2
-
-
-
-
µA
µA
µA
ns
-
-
-
Chip Deselect to Data Retention Time
Recovery to Normal Operation Time
tCDR
tRC
5
5
5
300
300
1
-
-
-
ns
V
to V
Rise and Fall Time
t , t
R F
2
-
-
µs
DD
NOTE:
1. Typical Values are for T = 25 C and nominal V
DR
o
A
DD.
6-165
MWS5114
DATA
RETENTION
MODE
V
DD
0.95 V
0.95 V
DD
DD
V
DR
tCDR
tRC
t
t
R
F
V
V
IH
IH
V
DR
CS
V
V
IL
IL
FIGURE 3. LOW V
DD
DATA RETENTION TIMING WAVEFORMS
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notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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