PX3511ADAG_技术文档

PX3511A, PX3511B

®

Data Sheet

February 26, 2007

FN6462.0

Advanced Synchronous Rectified Buck

MOSFET Drivers with Protection Features

Features

• Dual MOSFET Drives for Synchronous Rectified Bridge

• Adjustable Gate Voltage (5V to 12V) for Optimal Efficiency

• 36V Internal Bootstrap Schottky Diode

The PX3511A and PX3511B are high frequency MOSFET

drivers specifically designed to drive upper and lower power

N-Channel MOSFETs in a synchronous rectified buck

converter topology. These drivers combined with the

ISL6595 Digital Multi-Phase Buck PWM controller and

N-Channel MOSFETs form a complete core-voltage

regulator solution for advanced microprocessors.

• Bootstrap Capacitor Overcharging Prevention

• Supports High Switching Frequency (up to 2MHz)

- 3A Sinking Current Capability

- Fast Rise/Fall Times and Low Propagation Delays

The PX3511A drives the upper gate to 12V, while the lower

gate can be independently driven over a range from 5V to

12V. The PX3511B drives both upper and lower gates over a

range of 5V to 12V. This drive-voltage provides the flexibility

necessary to optimize applications involving trade-offs

between gate charge and conduction losses.

• Three-State PWM Input for Output Stage Shutdown

• Three-State PWM Input Hysteresis for Applications With

Power Sequencing Requirement

• Pre-POR Overvoltage Protection

• VCC Undervoltage Protection

An adaptive zero shoot-through protection is integrated to

prevent both the upper and lower MOSFETs from conducting

simultaneously and to minimize the dead time. These

products add an overvoltage protection feature operational

before VCC exceeds its turn-on threshold, at which the

PHASE node is connected to the gate of the low side

MOSFET (LGATE). The output voltage of the converter is

then limited by the threshold of the low side MOSFET, which

provides some protection to the microprocessor if the upper

MOSFET(s) is shorted during initial start-up.

• Expandable Bottom Copper Pad for Enhanced Heat

Sinking

• Dual Flat No-Lead (DFN) Package

- Near Chip-Scale Package Footprint; Improves PCB

Efficiency and Thinner in Profile

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• Core Regulators for Intel® and AMD® Microprocessors

• High Current DC/DC Converters

These drivers also feature a three-state PWM input which,

working together with Intersil’s multi-phase PWM controllers,

prevents a negative transient on the output voltage when the

output is shut down. This feature eliminates the Schottky

diode that is used in some systems for protecting the load

from reversed output voltage events.

• High Frequency and High Efficiency VRM and VRD

Related Literature

• Technical Brief TB363 “Guidelines for Handling and

Processing Moisture Sensitive Surface Mount Devices

(SMDs)”

• Technical Brief TB417 for Power Train Design, Layout

Guidelines, and Feedback Compensation Design

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

PX3511A, PX3511B

Ordering Information

PART NUMBER

PART MARKING

PX3511 ADAG

TEMP. RANGE (°C)

PACKAGE

PKG. DWG. #

M8.15

PX3511ADAG (Note)

PX3511ADAG-R3 (Note)

PX3511ADDG

0 to +85

8 Ld SOIC (Pb-free)

8 Ld SOIC (Pb-free) Tape and Reel

10 Ld 3x3 DFN

M8.15

11AD

L10.3x3

M8.15

PX3511ADDG-RA

PX3511BDAG (Note)

PX3511BDAG-R3 (Note)

PX3511BDDG

11AD

10 Ld 3x3 DFN Tape and Reel

8 Ld SOIC (Pb-free)

PX351 BDAG

PX3511 BDAG

11BD

8 Ld SOIC (Pb-free) Tape and Reel

10 Ld 3x3 DFN

M8.15

L10.3x3

PX3511BDDG-RA

11BD

10 Ld 3x3 DFN Tape and Reel

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

Pinouts

PX3511ACB, PX3511BCB

(8 LD SOIC)

PX3511ACR, PX3511BCR

(10 LD 3x3 DFN)

TOP VIEW

1

UGATE

BOOT

PWM

1

2

3

4

8

7

6

5

PHASE

PVCC

VCC

10

9

CRDL

UGATE

BAT

PHASE

2

3

4

BOOT

USB

PVCC

ICDL

8

GND

N/C

PPR

7

VCC

USBP

PWM

CHG

GND

LGATE

GND

LIUGSABTE

5

6

NTC or OVP

or EN

Block Diagram

PX3511A AND PX3511B

UVCC

BOOT

VCC

UGATE

Pre-POR OVP

FEATURES

+5V

PHASE

PVCC

SHOOT-

THROUGH

(LVCC)

10K

PROTECTION

UVCC = VCC FOR PX3511A

UVCC = PVCC FOR PX3511B

PWM

POR/

CONTROL

LOGIC

LGATE

GND

8K

FOR DFN -DEVICES, THE PAD ON THE BOTTOM SIDE OF

PAD

THE PACKAGE MUST BE SOLDERED TO THE CIRCUIT’S GROUND.

FN6462.0

February 26, 2007

2

PX3511A, PX3511B

Absolute Maximum Ratings

Thermal Information

Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V

Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3V

Thermal Resistance

θ

(°C/W)

θ

(°C/W)

JC

JA

SOIC Package (Note 1) . . . . . . . . . . . .

DFN Package (Notes 2, 3). . . . . . . . . .

Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C

(SOIC - Lead Tips Only)

100

48

N/A

7

BOOT Voltage (V

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36V

) . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to 7V

BOOT

Input Voltage (V

PWM

UGATE. . . . . . . . . . . . . . . . . . . V

- 0.3V

to V

+ 0.3V

= 12V)

PHASE

DC

BOOT

PVCC

V

- 3.5V (<100ns Pulse Width, 2µJ) to V

PHASE

LGATE . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V

to V

DC

GND - 5V (<100ns Pulse Width, 2µJ) to V

PHASE. . . . . . . . . . . . . . . GND - 0.3V to 15V (V

DC DC PVCC

GND - 8V (<400ns, 20µJ) to 30V (<200ns, VBOOT-GND<36V)

ESD Rating

Human Body Model . . . . . . . . . . . . . . . . . . . . Class I JEDEC STD

Recommended Operating Conditions

Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . 0°C to +85°C

Maximum Operating Junction Temperature. . . . . . . . . . . . . +125°C

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V ±10%

Supply Voltage Range, PVCC . . . . . . . . . . . . . . . . 5V to 12V ±10%

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air.

JA

2. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

JA

Tech Brief TB379.

3. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted.

PARAMETER

VCC SUPPLY CURRENT

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Bias Supply Current

I

PX3511A, f

PX3511B, f

PX3511A, f

PX3511B, f

PX3511A, f

PX3511B, f

PX3511A, f

PX3511B, f

= 300kHz, V

= 12V

-

8

4.5

10.5

5

-

mA

VCC

PWM

VCC

= 1MHz, V

= 12V

VCC

= 12V

Gate Drive Bias Current

I

= 300kHz, V

= 12V

4

PVCC

= 12V

7.5

5

= 1MHz, V

= 12V

PVCC

(Note 4)

PVCC

8.5

POWER-ON RESET AND ENABLE

VCC Rising Threshold

9.35

7.35

9.8

7.6

10.0

8.0

V

VCC Falling Threshold

PWM INPUT (See Timing Diagram on Page 6)

Input Current

I

V

= 3.3V

-

505

-460

1.70

1.30

-

µA

V

PWM

= 0V

-

PWM Rising Threshold (Note 4)

VCC = 12V

-

PWM Falling Threshold (Note 4)

-

V

Typical Three-State Shutdown Window

Three-State Lower Gate Falling Threshold

Three-State Lower Gate Rising Threshold

Three-State Upper Gate Rising Threshold

1.23

1.82

V

-

1.18

0.76

2.36

-

V

FN6462.0

February 26, 2007

4

PX3511A, PX3511B

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. (Continued)

PARAMETER

Three-State Upper Gate Falling Threshold

Shutdown Holdoff Time

SYMBOL

TEST CONDITIONS

VCC = 12V

MIN

TYP

1.96

245

26

MAX

UNITS

V

-

t

ns

TSSHD

UGATE Rise Time

t

V

= 12V, 3nF Load, 10% to 90%

= 12V, 3nF Load, 90% to 10%

= 12V, 3nF Load, Adaptive

= 12V, 3nF Load

ns

RU

PVCC

LGATE Rise Time

t

18

ns

RL

UGATE Fall Time (Note 4)

t

18

ns

FU

LGATE Fall Time (Note 4)

t

12

ns

FL

UGATE Turn-On Propagation Delay (Note 4)

LGATE Turn-On Propagation Delay (Note 4)

UGATE Turn-Off Propagation Delay (Note 4)

LGATE Turn-Off Propagation Delay (Note 4)

LG/UG Three-State Propagation Delay (Note 4)

OUTPUT

t

10

ns

PDHU

t

10

ns

PDHL

t

10

ns

PDLU

t

= 12V, 3nF Load

10

ns

PDLL

t

= 12V, 3nF Load

10

ns

PDTS

Upper Drive Source Current (Note 4)

Upper Drive Source Impedance

Upper Drive Sink Current (Note 4)

Upper Drive Sink Impedance

Lower Drive Source Current (Note 4)

Lower Drive Source Impedance

Lower Drive Sink Current (Note 4)

Lower Drive Sink Impedance

NOTE:

I

V

= 12V, 3nF Load

-

1.4

-

1.25

2.0

2

-

3.0

-

A

Ω

A

Ω

A

Ω

A

Ω

U_SOURCE

PVCC

R

150mA Source Current

U_SOURCE

I

V

= 12V, 3nF Load

U_SINK

PVCC

150mA Sink Current

V = 12V, 3nF Load

R

0.9

-

1.65

2

3.0

-

U_SINK

I

L_SOURCE

PVCC

150mA Source Current

R

0.85

-

1.3

3

2.2

-

L_SOURCE

I

V

= 12V, 3nF Load

L_SINK

PVCC

R

150mA Sink Current

0.60

0.94

1.35

L_SINK

4. Guaranteed by design. Not 100% tested in production.

Functional Pin Description

PACKAGE PIN #

SOIC

DFN

SYMBOL

FUNCTION

1

2

1

2

UGATE Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.

BOOT

Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the

PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the Internal Bootstrap

Device section under DESCRIPTION for guidance in choosing the capacitor value.

-

3,8

4

N/C

No Connection.

3

PWM

The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation, see

the three-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM output of the

controller.

4

5

6

7

5

6

7

9

GND

Bias and reference ground. All signals are referenced to this node. It is also the power ground return of the driver.

LGATE Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.

VCC

Connect this pin to a +12V bias supply. Place a high quality low ESR ceramic capacitor from this pin to GND.

PVCC

This pin supplies power to both upper and lower gate drives in PX3511B; only the lower gate drive in PX3511A.

Its operating range is +5V to 12V. Place a high quality low ESR ceramic capacitor from this pin to GND.

8

9

10

11

PHASE Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides

a return path for the upper gate drive.

PAD

Connect this pad to the power ground plane (GND) via thermally enhanced connection.

FN6462.0

February 26, 2007

5

PX3511A, PX3511B

Description

1.18V<PWM<2.36V

0.76V<PWM<1.96V

PWM

t

PDLU

PDHU

t

TSSHD

t

PDTS

t

PDTS

t

FU

UGATE

LGATE

t

RU

t

FL

RL

t

TSSHD

PDLL

t

PDHL

FIGURE 1. TIMING DIAGRAM

Operation

Adaptive Zero Shoot-Through Deadtime Control

Designed for versatility and speed, the PX3511A and

PX3511B MOSFET drivers control both high-side and low-

side N-Channel FETs of a half-bridge power train from one

externally provided PWM signal.

These drivers incorporate an adaptive deadtime control

technique to minimize deadtime, resulting in high efficiency

from the reduced freewheeling time of the lower MOSFETs’

body-diode conduction, and to prevent the upper and lower

MOSFETs from conducting simultaneously. This is

accomplished by ensuring either rising gate turns on its

MOSFET with minimum and sufficient delay after the other

has turned off.

Prior to VCC exceeding its POR level, the Pre-POR

overvoltage protection function is activated during initial

startup; the upper gate (UGATE) is held low and the lower

gate (LGATE), controlled by the Pre-POR overvoltage

protection circuits, is connected to the PHASE. Once the

VCC voltage surpasses the VCC Rising Threshold (See

Electrical Specifications), the PWM signal takes control of

gate transitions. A rising edge on PWM initiates the turn-off

of the lower MOSFET (see Timing Diagram). After a short

During turn-off of the lower MOSFET, the LGATE voltage is

monitored until it drops below 1.75V, at which time the

UGATE is released to rise after 20ns of propagation delay.

Once the PHASE is high, the adaptive shoot-through

circuitry monitors the PHASE and UGATE voltages during a

PWM falling edge and the subsequent UGATE turn-off. If

either the UGATE falls to less than 1.75V above the PHASE

or the PHASE falls to less than +0.8V, the LGATE is

released to turn on.

propagation delay [t

], the lower gate begins to fall.

PDLL

Typical fall times [t ] are provided in the Electrical

FL

Specifications section. Adaptive shoot-through circuitry

monitors the LGATE voltage and determines the upper gate

delay time [t

]. This prevents both the lower and upper

MOSFETs from conducting simultaneously. Once this delay

PDHU

Three-State PWM Input

A unique feature of these drivers and other Intersil drivers is

the addition of a shutdown window to the PWM input. If the

PWM signal enters and remains within the shutdown window

for a set holdoff time, the driver outputs are disabled and

both MOSFET gates are pulled and held low. The shutdown

state is removed when the PWM signal moves outside the

shutdown window. Otherwise, the PWM rising and falling

thresholds outlined in the ELECTRICAL SPECIFICATIONS

determine when the lower and upper gates are enabled.

period is complete, the upper gate drive begins to rise [t

and the upper MOSFET turns on.

]

RU

A falling transition on PWM results in the turn-off of the upper

MOSFET and the turn-on of the lower MOSFET. A short

propagation delay [t

] is encountered before the upper

PDLU

gate begins to fall [t ]. Again, the adaptive shoot-through

FU

circuitry determines the lower gate delay time, t

. The

PDHL

PHASE voltage and the UGATE voltage are monitored, and

the lower gate is allowed to rise after PHASE drops below a

level or the voltage of UGATE to PHASE reaches a level

depending upon the current direction (See next section for

This feature helps prevent a negative transient on the output

voltage when the output is shut down, eliminating the

Schottky diode that is used in some systems for protecting

the load from reversed output voltage events.

details). The lower gate then rises [t ], turning on the lower

RL

MOSFET.

In addition, more than 400mV hysteresis also incorporates

into the three-state shutdown window to eliminate PWM

FN6462.0

February 26, 2007

6

PX3511A, PX3511B

input oscillations due to the capacitive load seen by the

200mV droop in drive voltage over the PWM cycle. We find

PWM input through the body diode of the controller’s PWM

output when the power-up and/or power-down sequence of

bias supplies of the driver and PWM controller are required.

that a bootstrap capacitance of at least 0.267μF is required.

1.6

1.4

1.2

1.

Power-On Reset (POR) Function

During initial startup, the VCC voltage rise is monitored.

Once the rising VCC voltage exceeds 9.8V (typically),

operation of the driver is enabled and the PWM input signal

takes control of the gate drives. If VCC drops below the

falling threshold of 7.6V (typically), operation of the driver is

disabled.

0.8

0.6

Q

= 100nC

GATE

Pre-POR Overvoltage Protection

0.4

Prior to VCC exceeding its POR level, the upper gate is held

low and the lower gate is controlled by the overvoltage

protection circuits during initial startup. The PHASE is

connected to the gate of the low side MOSFET (LGATE),

which provides some protection to the microprocessor if the

upper MOSFET(s) is shorted during initial startup. For

complete protection, the low side MOSFET should have a

gate threshold well below the maximum voltage rating of the

load/microprocessor.

50nC

0.2

0.0

20nC

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

ΔV (V)

BOOT_CAP

FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE

VOLTAGE

Gate Drive Voltage Versatility

When VCC drops below its POR level, both gates pull low

and the Pre-POR overvoltage protection circuits are not

activated until VCC resets.

The PX3511A and PX3511B provide the user flexibility in

choosing the gate drive voltage for efficiency optimization.

The PX3511A upper gate drive is fixed to VCC [+12V], but

the lower drive rail can range from 12V down to 5V

depending on what voltage is applied to PVCC. The

PX3511B ties the upper and lower drive rails together.

Simply applying a voltage from 5V up to 12V on PVCC sets

both gate drive rail voltages simultaneously.

Internal Bootstrap Device

Both drivers feature an internal bootstrap schottky diode.

Simply adding an external capacitor across the BOOT and

PHASE pins completes the bootstrap circuit. The bootstrap

function is also designed to prevent the bootstrap capacitor

from overcharging due to the large negative swing at the

trailing-edge of the PHASE node. This reduces voltage

stress on the boot to phase pins.

Power Dissipation

Package power dissipation is mainly a function of the

switching frequency (F ), the output drive impedance, the

SW

The bootstrap capacitor must have a maximum voltage

rating above UVCC + 5V and its capacitance value can be

chosen from the following equation:

external gate resistance, and the selected MOSFET’s

internal gate resistance and total gate charge. Calculating

the power dissipation in the driver for a desired application is

critical to ensure safe operation. Exceeding the maximum

allowable power dissipation level will push the IC beyond the

maximum recommended operating junction temperature of

+125°C. The maximum allowable IC power dissipation for

the SO8 package is approximately 800mW at room

temperature, while the power dissipation capacity in the DFN

package with an exposed heat escape pad is more than

1.5W. The DFN package is more suitable for high frequency

applications. See Layout Considerations paragraph for

thermal transfer improvement suggestions. When designing

the driver into an application, it is recommended that the

following calculation is used to ensure safe operation at the

desired frequency for the selected MOSFETs. The total gate

drive power losses due to the gate charge of MOSFETs and

the driver’s internal circuitry and their corresponding average

Q

GATE

-------------------------------------

C

≥

BOOT_CAP

ΔV

BOOT_CAP

(EQ. 1)

Q

• UVCC

G1

-----------------------------------

Q

=

• N

Q1

GATE

V

GS1

where Q is the amount of gate charge per upper MOSFET

G1

at V

gate-source voltage and N is the number of

GS1

control MOSFETs. The ΔV

Q1

term is defined as the

BOOT_CAP

allowable droop in the rail of the upper gate drive.

As an example, suppose two IRLR7821 FETs are chosen as

the upper MOSFETs. The gate charge, Q , from the data

G

sheet is 10nC at 4.5V (V ) gate-source voltage. Then the

GS

Q

is calculated to be 53nC for UVCC (i.e. PVCC in

GATE

PX3511B, VCC in PX3511A) = 12V. We will assume a

FN6462.0

February 26, 2007

7

PX3511A, PX3511B

driver current can be estimated with Equations 2 and 3,

respectively,

UVCC

BOOT

D

C

R

GD

(EQ. 2)

P

= P

+ P

+ I • VCC

Q

Qg_TOT

Qg_Q1

Qg_Q2

2

R

HI1

G

C

DS

Q

• UVCC

G1

R

---------------------------------------

P

=

• F

• N

LO1

R

GI1

C

G1

Qg_Q1

SW

Q1

V

GS1

GS

Q1

2

Q

• LVCC

S

G2

--------------------------------------

P

• F

• N

Qg_Q2

SW

Q2

V

GS2

PHASE

FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH

Q

• UVCC • N

Q

• LVCC • N

G2 Q2

⎛

⎜

⎝

⎞

⎟

⎠

G1

Q1

----------------------------------------------------- ----------------------------------------------------

I

=

+

• F

+ I

DR

SW

Q

V

GS2

GS1

(EQ. 3)

LVCC

D

where the gate charge (Q and Q ) is defined at a

G1

G2

particular gate to source voltage (V

and V

) in the

C

GS1

GS2

GD

corresponding MOSFET datasheet; I is the driver’s total

Q

R

HI2

G

C

DS

quiescent current with no load at both drive outputs; N

Q1

R

LO2

R

GI2

C

and N are number of upper and lower MOSFETs,

G2

Q2

respectively; UVCC and LVCC are the drive voltages for

GS

Q2

both upper and lower FETs, respectively. The I VCC

Q*

S

product is the quiescent power of the driver without

capacitive load and is typically 116mW at 300kHz.

The total gate drive power losses are dissipated among the

resistive components along the transition path. The drive

resistance dissipates a portion of the total gate drive power

losses, the rest will be dissipated by the external gate

FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH

Layout Considerations

For heat spreading, place copper underneath the IC whether

it has an exposed pad or not. The copper area can be

extended beyond the bottom area of the IC and/or

connected to buried copper plane(s) with thermal vias. This

combination of vias for vertical heat escape, extended

copper plane, and buried planes for heat spreading allows

the IC to achieve its full thermal potential.

resistors (R and R ) and the internal gate resistors

G1 G2

(R

GI1

and R ) of MOSFETs. Figures 3 and 4 show the

GI2

typical upper and lower gate drives turn-on transition path.

The power dissipation on the driver can be roughly

estimated as:

P

= P

+ P

+ I • VCC

(EQ. 4)

DR

DR_UP

DR_LOW

Q

Place each channel power component as close to each

other as possible to reduce PCB copper losses and PCB

parasitics: shortest distance between DRAINs of upper FETs

and SOURCEs of lower FETs; shortest distance between

DRAINs of lower FETs and the power ground. Thus, smaller

amplitudes of positive and negative ringing are on the

switching edges of the PHASE node. However, some space

in between the power components is required for good

airflow. The traces from the drivers to the FETs should be

kept short and wide to reduce the inductance of the traces

and to promote clean drive signals.

P

R

⎛

⎞

Qg_Q1

HI1

LO1

-------------------------------------- --------------------------------------- ---------------------

=

+

•

⎜

⎝

⎟

DR_UP

R

+ R

R

+ R

EXT1

2

⎠

HI1

EXT1

LO1

P

R

⎛

⎜

⎝

⎞

Qg_Q2

HI2

LO2

-------------------------------------- --------------------------------------- ---------------------

P

R

=

+

•

⎟

DR_LOW

R

+ R

R

+ R

EXT2

2

⎠

HI2

EXT2

LO2

R

GI1

GI2

-------------

= R

+

R

= R +

G2

EXT1

G1

EXT2

N

Q1

Q2

FN6462.0

February 26, 2007

8

PX3511A, PX3511B

Dual Flat No-Lead Plastic Package (DFN)

2X

L10.3x3

0.15

C A

2X

10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE

D

A

MILLIMETERS

0.15 C

B

SYMBOL

MIN

0.80

NOMINAL

0.90

MAX

1.00

NOTES

A

A1

A3

b

-

0.18

1.95

1.55

-

0.05

-

E

0.20 REF

0.23

-

6

0.28

2.05

1.65

5,8

INDEX

AREA

D

3.00 BSC

2.00

-

D2

E

7,8

TOP VIEW

B

A

3.00 BSC

1.60

-

E2

e

7,8

0.10 C

0.08 C

0.50 BSC

-

k

0.25

0.30

-

L

0.35

0.40

8

SIDE VIEW

C

A3

SEATING

PLANE

N

10

2

Nd

5

3

7

8

Rev. 3 6/04

D2

NOTES:

(DATUM B)

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

D2/2

1

2

6

3. Nd refers to the number of terminals on D.

INDEX

AREA

k

NX

E2

4. All dimensions are in millimeters. Angles are in degrees.

(DATUM A)

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

E2/2

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

NX L

8

N

N-1

e

7. Dimensions D2 and E2 are for the exposed pads which provide

improved electrical and thermal performance.

NX b

5

8. Nominal dimensions are provided to assist with PCB Land

Pattern Design efforts, see Intersil Technical Brief TB389.

(Nd-1)Xe

0.10 M C A B

REF.

BOTTOM VIEW

C

L

0.415

NX (b)

(A1)

L

0.200

NX b

NX L

5

e

SECTION "C-C"

TERMINAL TIP

FOR ODD TERMINAL/SIDE

C C

C

FN6462.0

February 26, 2007

9

PX3511A, PX3511B

Small Outline Plastic Packages (SOIC)

M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

N

INDEX

AREA

0.25(0.010)

M

B M

H

INCHES MILLIMETERS

E

SYMBOL

MIN

MAX

MIN

1.35

0.10

0.33

0.19

4.80

3.80

MAX

1.75

0.25

0.51

0.25

5.00

4.00

NOTES

-B-

A

A1

B

C

D

E

e

0.0532

0.0040

0.013

0.0688

0.0098

0.020

-

1

2

3

L

9

SEATING PLANE

A

0.0075

0.1890

0.1497

0.0098

0.1968

0.1574

-

-A-

3

h x 45°

D

4

-C-

0.050 BSC

1.27 BSC

-

α

H

h

0.2284

0.0099

0.016

0.2440

0.0196

0.050

5.80

0.25

0.40

6.20

0.50

1.27

-

e

A1

C

5

B

0.10(0.004)

L

6

0.25(0.010) M

C

A M B S

N

α

8

7

NOTES:

0°

8°

0°

8°

-

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

Rev. 1 6/05

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per

side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6462.0

February 26, 2007

10


型号：	PX3511ADAG
厂家：	Intersil
描述：	Advanced Synchronous Rectified Buck MOSFET Drivers with Protection Features 与保护功能先进的同步整流降压MOSFET驱动器驱动器
文件：	总10页 (文件大小：230K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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