RF1S60P03SM [INTERSIL]
60A, 30V, 0.027 Ohm, P-Channel Power MOSFETs; 60A ， 30V ， 0.027欧姆，P沟道功率MOSFET
| 型号： | RF1S60P03SM |
| 厂家： | 
Intersil |
| 描述： | 60A, 30V, 0.027 Ohm, P-Channel Power MOSFETs |
| 文件： | 总7页 (文件大小：92K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RFG60P03, RFP60P03, RF1S60P03SM
Data Sheet
July 1999
File Number 3951.3
60A, 30V, 0.027 Ohm, P-Channel Power
MOSFETs
Features
• 60A, 30V
These P-Channel power MOSFETs are manufactured using
the MegaFET process. This process, which uses feature
sizes approaching those of LSI integrated circuits gives
optimum utilization of silicon, resulting in outstanding
performance. They were designed for use in applications
such as switching regulators, switching converters, motor
drivers and relay drivers. These transistors can be operated
directly from integrated circuits.
• r
= 0.027Ω
DS(ON)
®
• Temperature Compensating PSPICE Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
o
• 175 C Operating Temperature
• Related Literature
Formerly developmental type TA49045.
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Ordering Information
Symbol
PART NUMBER
PACKAGE
BRAND
RFG60P03
D
RFG60P03
TO-247
RFP60P03
TO-220AB
TO-263AB
RFP60P03
F1S60P03
G
RF1S60P03SM
NOTE: When ordering, use the entire part number. Add the suffix 9A to
obtain the TO-263AB variant in tape and reel, i.e. RF1S60P03SM9A.
S
Packaging
JEDEC STYLE TO-247
JEDEC TO-220AB
SOURCE
DRAIN
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
GATE
DRAIN
(BOTTOM
SIDE METAL)
JEDEC TO-263AB
DRAIN
(FLANGE)
GATE
SOURCE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE® is a registered trademark of MicroSim Corporation.
4-140
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
RFG60P03, RFP60P03, RF1S60P03SM
o
Absolute Maximum Ratings T = 25 C, Unless Otherwise Specified
C
RFG60P03, RFP60P03, RFS60P03SM
UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
-30
-30
±20
V
V
V
A
DSS
Drain to Gate Voltage, (R = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
gs
DGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
GS
Continuous Drain Current (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
60
D
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Refer to Peak Current Curve
DM
Single Pulse Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E
AS
Figure 6
Maximum Power Dissipation (Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P
Derate Above 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
176
1.17
W
W/ C
D
o
o
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T , T
J
-55 to 175
C
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
o
300
260
C
C
L
o
pkg
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
o
o
1. T = 25 C to 150 C.
J
o
Electrical Specifications
T = 25 C, Unless Otherwise Specified
C
PARAMETER
SYMBOL
BV
TEST CONDITIONS
= 250µA, V = 0V (Figure 11)
MIN
TYP
MAX UNITS
Drain to Source Breakdown Voltage
Gate Threshold Voltage
I
-30
-2
-
-
-
-4
V
DSS
D
GS
V
V
= V , I = 250µA (Figure 10)
-
V
GS(TH)
GS
DS
D
Zero Gate Voltage Drain Current
I
V
V
= Rated BV
, V
= 0V
, T = 150 C
-
-
-1
µA
µA
nA
Ω
DSS
DS
DS
DSS GS
o
= 0.8 x Rated BV
-
-50
±100
0.027
140
-
DSS
C
Gate to Source Leakage Current
I
V
= ±20V
-
-
GSS
GS
Drain to Source On Resistance (Note 2)
Turn-On Time
r
I
= 60A, V
= 10V
= 15V, ID ≈ 60A, R = 0.25Ω,
-
-
DS(ON)
D GS
t
V
V
-
-
ns
ON
DD
L
= -10V, R = 2.5Ω,
GS
(Figure 13)
G
Turn-On Delay Time
t
-
20
75
35
40
-
ns
d(ON)
Rise Time
t
-
-
ns
r
Turn-Off Delay Time
t
-
-
ns
d(OFF)
Fall Time
t
-
-
ns
f
Turn-Off Time
t
-
115
230
120
9
ns
OFF
Total Gate Charge
Q
V
= 0 to -20V
= 0 to -10V
= 0 to -2V
GS
V
R
= -24V, I ≈ 60A,
= 0.4Ω
-
190
100
7.5
3000
1500
525
-
nC
nC
nC
pF
pF
pF
C/W
C/W
C/W
g(TOT)
GS
DD
D
L
Gate Charge at 10V
Q
V
-
g(-10)
GS
I
= -3mA
g(REF)
Threshold Gate Charge
Input Capacitance
Q
V
-
g(TH)
C
V
= 25V, V
DS GS
= 0V, f = 1MHz
-
-
ISS
OSS
RSS
(Figure 12)
Output Capacitance
C
-
-
Reverse Transfer Capacitance
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Ambient
C
-
-
o
o
o
R
(Figure 3)
-
0.85
62
30
θJC
θJA
R
TO-220AB, TO- 263AB
TO-247
-
-
-
-
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage (Note 2)
Diode Reverse Recovery Time
NOTE:
SYMBOL
TEST CONDITIONS
= -60A
MIN
TYP
MAX
UNITS
V
V
I
I
-
-
-
-
-1.75
200
SD
SD
t
= -60A, dI /dt = 100A/µs
SD
ns
rr
SD
2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%.
3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3)
4-141
RFG60P03, RFP60P03, RF1S60P03SM
Typical Performance Curves Unless Otherwise Specified
1.2
1.0
0.8
0.6
0.4
0.2
0
-70
-60
-50
-40
-30
-20
-10
0
25
50
75
T , CASE TEMPERATURE ( C)
C
100
125
150
175
0
25
50
75
100
125
o
150
175
o
T
, CASE TEMPERATURE ( C)
C
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
1
0.5
P
DM
0.2
0.1
0.1
t
1
0.05
t
2
NOTES:
DUTY FACTOR: D = t /t
0.02
0.01
1
2
PEAK T = P
x Z
x R
+ T
JC C
SINGLE PULSE
0.01
J
DM
10
JC
θ
θ
-5
-4
-3
-2
10
-1
0
1
10
10
10
10
10
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
3
-500
-100
-10
o
o
T
= 25 C
C
FOR TEMPERATURES ABOVE 25 C
DERATE PEAK CURRENT
CAPABILITY AS FOLLOWS:
100µs
1ms
175 – T
V
= -20V
C
GS
I = I
-----------------------
25
150
10ms
OPERATION IN THIS
AREA MAY BE
-10
-1
100ms
DC
LIMITED BY r
V
GS
= -10V
DS(ON)
o
2
T
T
= 25 C
-10
C
J
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
= MAX RATED
-50
-6
10
-5
10
-4
10
-3
10
-2
10
-1
0
1
-1
-10
, DRAIN TO SOURCE VOLTAGE (V)
-60
10
10
10
V
t, PULSE WIDTH (ms)
DS
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
4-142
RFG60P03, RFP60P03, RF1S60P03SM
Typical Performance Curves Unless Otherwise Specified (Continued)
-200
-120
V
= -20V
GS
o
STARTING T = 25 C
J
V
= -10V
GS
-100
-90
V
= -8V
GS
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
T = 25 C
C
o
-60
o
STARTING T = 150 C
J
V
= -7V
= -6V
GS
If R = 0
V
GS
-30
0
t
= (L) (I ) / (1.3RATED BV
- V
DD
)
AV
If R ≠ 0
AS DSS
V
= -4.5V
V
= -5V
GS
GS
t
= (L/R) ln [(I *R) / (1.3 RATED BV
AS
- V ) + 1]
DD
AV
DSS
1
-10
0
-1.5
-3.0
-4.5
-6.0
-7.5
200
200
0.01
0.1
10
t
, TIME IN AVALANCHE (ms)
V
, DRAIN TO SOURCE VOLTAGE (V)
AV
DS
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
FIGURE 7. SATURATION CHARACTERISTICS
2
-120
o
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
-55 C
o
25 C
V
= 1.5V, I = 60A
GS
D
V
= -15V
DD
1.5
1
-90
-60
o
175 C
-30
0
0.5
0
0
-2
-4
-6
-8
-10
-80
-40
0
40
80
120
160
o
V
, GATE TO SOURCE VOLTAGE (V)
T , JUNCTION TEMPERATURE ( C)
GS
J
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
2
2
1.5
1
V
= V , I = 250µA
DS D
GS
I
= 250µA
D
1.5
1
0.5
0.5
0
0
-80
-40
0
40
80
120
160
-80
-40
0
40
80
120
160
200
o
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
4-143
RFG60P03, RFP60P03, RF1S60P03SM
Typical Performance Curves Unless Otherwise Specified (Continued)
-10
-7.5
-5.0
-2.5
0
-30
-22.5
-15
5000
V
= 0V, f = 1MHz
GS
V
= BV
DSS
DD
C
C
C
= C + C
V
= BV
DSS
ISS
GS GD
DD
= C
≈ C + C
4000
RSS
OSS
GD
C
C
DS
GS
ISS
R
= 0.5Ω
L
3000
2000
I
V
= -3mA
G(REF)
= -10V
GS
OSS
0.75 BV
0.50 BV
0.25 BV
DSS 0.75 BV
DSS 0.50 BV
DSS 0.25 BV
DSS
DSS
DSS
-7.5
0
C
RSS
1000
0
I
I
I
I
G(REF)
G(ACT)
G(REF)
G(ACT)
0
-5
-10
-15
-20
-25
t, TIME (µs)
20
80
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
Test Circuits and Waveforms
V
DS
t
AV
L
0
VARY t TO OBTAIN
P
-
R
REQUIRED PEAK I
G
AS
V
DD
+
DUT
0V
V
DD
t
P
I
AS
V
GS
V
DS
I
AS
t
P
0.01Ω
BV
DSS
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORM
t
t
ON
OFF
t
t
d(OFF)
d(ON)
t
t
f
V
r
DS
0
R
L
10%
10%
V
GS
V
DS
-
90%
90%
V
DD
V
0
GS
+
V
GS
10%
50%
DUT
R
GS
50%
90%
PULSE WIDTH
FIGURE 16. SWITCHING TIME TEST CIRCUIT
FIGURE 17. RESISTIVE SWITCHING WAVEFORMS
4-144
RFG60P03, RFP60P03, RF1S60P03SM
Test Circuits and Waveforms (Continued)
V
DS
V
DS
Q
R
g(TH)
L
0
V
= -2V
GS
V
GS
-
V
= -10V
-V
GS
GS
V
DD
Q
+
g(-10)
V
= -20V
GS
DUT
V
DD
I
G(REF)
Q
g(TOT)
0
I
G(REF)
FIGURE 18. GATE CHARGE TEST CIRCUIT
FIGURE 19. GATE CHARGE WAVEFORMS
4-145
RFG60P03, RFP60P03, RF1S60P03SM
PSPICE Electrical Model
.SUBCKT RFP60P03 2 1 3
REV 6/21/94
CA 12 8 5.01e-9
CB 15 14 3.9e-9
CIN 6 8 3.09e-9
5
+
DRAIN
2
-
6
8
10
LDRAIN
DBODY 5 7 DBDMOD
DBREAK 7 11 DBKMOD
DPLCAP 10 6 DPLCAPMOD
ESG
+
RDRAIN
17
18
EBREAK 5 11 17 18 -36.59
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 5 10 8 6 1
EVTO 20 6 8 18 1
EBREAK
DPLCAP
-
11
DBODY
16
VTO
6
+
MOS2
EVTO
GATE
1
21
IT 8 17 1
+
-
9
20
18
8
MOS1
DBREAK
LGATE RGATE
LDRAIN 2 5 1e-9
LGATE 1 9 4.92e-9
LSOURCE 3 7 2.36e-9
RIN
CIN
LSOURCE
RSOURCE
8
7
3
SOURCE
MOS1 16 6 8 8 MOSMOD M=0.99
MOS2 16 21 8 8 MOSMOD M=0.01
S1A
S2A
12
RBREAK
15
13
8
14
13
17
18
RBREAK 17 18 RBKMOD 1
RDRAIN 5 16 RDSMOD 1e-4
RGATE 9 20 3.25
RIN 6 8 1e9
RSOURCE 8 7 RDSMOD 11.28e-3
RVTO 18 19 RVTOMOD 1
S1B
CA
S2B
13
RVTO
19
CB
+
IT
14
+
VBAT
5
8
6
8
EGS
EDS
+
-
-
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 8 19 DC 1
VTO 21 6 -0.92
.MODEL DBDMOD D (IS=4.21e-13 RS=1e-2 TRS1=-2.69e-4 TRS2=-1.33e-6 CJO=5.05e-9 TT=5.33e-8)
.MODEL DBKMOD D (RS=3.80e-2 TRS1=-4.76e-4 TRS2=-4.17e-12)
.MODEL DPLCAPMOD D (CJO=4.05e-9 IS=1e-30 N=10)
.MODEL MOSMOD PMOS (VTO=-3.98 KP=16.27 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL RBKMOD RES (TC1=8.05e-4 TC2=1.48e-6)
.MODEL RDSMOD RES (TC1=2.80e-3 TC2=2.62e-6)
.MODEL RVTOMOD RES (TC1=-3.34e-3 TC2=1.46e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=7.5 VOFF=4.5)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=4.5 VOFF=7.5)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=1.43 VOFF=-3.57)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.57 VOFF=1.43)
.ENDS
NOTE: For further discussion of the PSPICE model consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; authors, William J. Hepp and C. Frank Wheatley.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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