X28C010_07 [INTERSIL]
5V, Byte Alterable EEPROM; 5V ，字节EEPROM可变
| 型号： | X28C010_07 |
| 厂家： | 
Intersil |
| 描述： | 5V, Byte Alterable EEPROM |
| 文件： | 总20页 (文件大小：440K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X28C010, X28HT010
®
Data Sheet
February 12, 2007
FN8105.1
5V, Byte Alterable EEPROM
Features
The Intersil X28C010/X28HT010 is a 128K x 8 EEPROM,
fabricated with Intersil's proprietary, high performance,
floating gate CMOS technology. Like all Intersil
programmable non-volatile memories, the
X28C010/X28HT010 is a 5V only device. The
X28C010/X28HT010 features the JEDEC approved pin out
for byte-wide memories, compatible with industry standard
EEPROMs.
• Access time: 120ns
• Simple byte and page write
- Single 5V supply
- No external high voltages or V control
PP
circuits
- Self-timed
• No erase before write
• No complex programming algorithms
• No overerase problem
The X28C010/X28HT010 supports a 256-byte page write
operation, effectively providing a 19µs/byte write cycle and
enabling the entire memory to be typically written in less
than 2.5 seconds. The X28C010/X28HT010 also features
DATA Polling and Toggle Bit Polling, system software
support schemes used to indicate the early completion of a
write cycle. In addition, the X28C010/X28HT010 supports
Software Data Protection option.
• Low power CMOS
- Active: 50mA
- Standby: 500µA
• Software data protection
- Protects data against system level inadvertent writes
• High speed page write capability
™
Intersil EEPROMs are designed and tested for applications
requiring extended endurance. Data retention is specified to
be greater than 100 years.
• Highly reliable Direct Write cell
- Endurance: 100,000 write cycles
- Data retention: 100 years
• Early end of write detection
- DATA polling
- Toggle bit polling
• X28HT010 is fuly functional @ +175°C
Pinouts
CERDIP
PGA
EXTENDED LCC
Flat Pack
I/O
15
I/O
17
I/O
19
I/O
21
I/O
22
SOIC (R)
0
2
3
5
6
4
3
2
32 31 30
CE
24
NC
1
32
V
CC
A
13
A
14
I/O
16
V
SS
I/O
20
I/O
23
1
0
1
4
7
1
A
18
5
29
A
14
7
A
2
3
31
30
WE
16
A
A
6
7
28
27
26
25
24
23
22
21
A
A
8
6
13
A
A
A
10
OE
26
2
3
A
5
NC
12
11
25
15
A
A
8
9
4
9
X28C010
(Top View)
A
4
5
29
28
A
A
A
11
A
A
A
A
12
14
3
4
5
11
9
X28C010
(Bottom View)
10
9
7
27
28
A
10
11
OE
A
2
A
7
13
A
A
1
10
A
A
A
A
13
A
6
6
27
A
8
6
7
8
A
12
13
CE
0
8
6
29
30
I/O
I/O
0
7
A
7
8
26
25
A
5
9
A
A
NC
NC
V
NC
34
NC
32
A
14
31
12
15
CC
14 15 1617 18 1920
A
4
A
5
4
2
3
36
11
X28C010
A
9
24
23
OE
3
A
NC
1
NC
33
WE
35
16
A
2
10
A
10
A
11
12
13
14
15
16
22
21
20
19
18
17
CE
1
A
0
I/O
7
I/O
I/O
0
6
I/O
I/O
5
1
I/O
I/O
2
4
V
I/O
3
SS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X28C010, X28HT010
Ordering Information
ACCESS
TIME
TEMP RANGE
(°C)
PART NUMBER
X28C010D-12
PART MARKING
PACKAGE
32-Ld Cerdip
PKG. DWG #
F32.6
X28C010D-12
120ns
150ns
-
0 to +70
0 to +70
X28C010D-15
X28C010D-15
32-Ld Cerdip
F32.6
F32.6
F32.6
F32.6
F32.6
F32.6
F32.6
F32.6
F32.6
X28C010DI
X28C010DI
-40 to +85
32-Ld Cerdip
X28C010DI-12
X28C010DI-15
X28C010DM
X28C010DI-12
120ns
150ns
-
-40 to +85
32-Ld Cerdip
X28C010DI-15
-40 to +85
32-Ld Cerdip
X28C010DM
-55 to +125
-55 to +125
-55 to +125
MIL-STD-883
MIL-STD-883
MIL-STD-883
-40 to +85
32-Ld Cerdip
X28C010DM-12
X28C010DM-15
X28C010DMB-12
X28C010DMB-15
X28C010DMB-20
X28C010FI-12
X28C010FI-15
X28C010FI-20
X28C010FM
X28C010DM-12
X28C010DM-15
C X28C010DMB-12
C X28C010DMB-15
C X28C010DMB-20
X28C010FI-12
120ns
150ns
120ns
150ns
200ns
120ns
150ns
200ns
-
32-Ld Cerdip
32-Ld Cerdip
32-Ld Cerdip
32-Ld Cerdip
32-Ld Cerdip
32-Ld Flat Pack
X28C010FI-15
-40 to +85
32-Ld Flat Pack
X28C010FI-20
-40 to +85
32-Ld Flat Pack
X28C010FM
-55 to +125
-55 to +125
MIL-STD-883
MIL-STD-883
0 to +70
32-Ld Flat Pack
X28C010FM-12
X28C010FMB-12
X28C010FMB-15
X28C010K-25
X28C010FM-12
C X28C010FMB-12
C X28C010FMB-15
X28C010K-25
120ns
120ns
150ns
250ns
120ns
250ns
120ns
150ns
120ns
150ns
120ns
150ns
120ns
200ns
200ns
150ns
250ns
200ns
32-Ld Flat Pack
32-Ld Flat Pack
32-Ld Flat Pack
36-Ld Pin Grid Array
36-Ld Pin Grid Array
36-Ld Pin Grid Array
36-Ld Pin Grid Array
36-Ld Pin Grid Array
32-Ld Extended LCC
32-Ld Extended LCC
32-Ld Extended LCC
32-Ld Extended LCC
32-Ld Ceramic SOIC (Gull Wing)
32-Ld Ceramic SOIC (Gull Wing)
32-Ld Ceramic SOIC (Gull Wing)
32-Ld Ceramic SOIC (Gull Wing)
32-Ld Ceramic SOIC (Gull Wing)
Wafer
G36.760x760A
G36.760x760A
G36.760x760A
G36.760x760A
G36.760x760A
X28C010KM-12
X28C010KM-25
X28C010KMB-12
X28C010KMB-15
X28C010NM-12
X28C010NM-15
X28C010NMB-12
X28C010NMB-15
X28C010RI-12
X28C010RI-20
X28C010RI-20T1
X28C010RM-15
X28C010RMB-25
X28HT010W
X28C010KM-12
X28C010KM-25
C X28C010KMB-12
C X28C010KMB-15
X28C010NM-12
X28C010NM-15
C X28C010NMB-12
C X28C010NMB-15
X28C010RI-12
-55 to +125
-55 to +125
MIL-STD-883
MIL-STD-883
-55 to +125
-55 to +125
MIL-STD-883
MIL-STD-883
-40 to +85
X28C010RI-20
-40 to +85
X28C010RI-20
-40 to +85
X28C010RM-15
C X28C010RMB-25
-55 to +125
MIL-STD-883
-40 to +175
FN8105.1
February 12, 2007
2
X28C010, X28HT010
Block Diagram
X Buffers
Latches and
Decoder
1Mbit
A -A
EEPROM
Array
8
16
Y Buffers
Latches and
Decoder
I/O Buffers
and Latches
A -A
0
7
CE
OE
Control
Logic and
Timing
I/O -I/O
0
7
Data Inputs/Outputs
WE
V
CC
SS
V
Pin Descriptions
Pin Names
Addresses (A0-A16
)
SYMBOL
DESCRIPTION
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
The Address inputs select an 8-bit memory location during a
read or write operation.
A -A
0
16
I/O -I/O
0
7
Chip Enable (CE)
WE
CE
OE
The Chip Enable input must be LOW to enable all read/write
operations. When CE is HIGH, power consumption is
reduced.
Output Enable (OE)
V
CC
The Output Enable input controls the data output buffers,
and is used to initiate read operations.
V
Ground
SS
NC
No Connect
-3V
Data In/Data Out (I/O0-I/O7)
V
*
BB
Data is written to or read from the X28C010/X28HT010
through the I/O pins.
*V applies to X28HT010 only.
BB
Write Enable (WE)
Device Operation
The Write Enable input controls the writing of data to the
X28C010/X28HT010.
Read
Read operations are initiated by both OE and CE LOW. The
read operation is terminated by either CE or OE returning
HIGH. This two line control architecture eliminates bus
contention in a system environment. The data bus will be in
a high impedance state when either OE or CE is HIGH.
Back Bias Voltage (V ) (X28HT010 only)
BB
It is required to provide -3V on pin 1. This negative voltage
improves higher temperature functionality.
Write
Write operations are initiated when both CE and WE are
LOW and OE is HIGH. The X28C010/X28HT010 supports
both a CE and WE controlled write cycle. That is, the
address is latched by the falling edge of either CE or WE,
whichever occurs last. Similarly, the data is latched internally
by the rising edge of either CE or WE, whichever occurs first.
A byte write operation, once initiated, will automatically
continue to completion, typically within 5ms.
FN8105.1
February 12, 2007
3
X28C010, X28HT010
Page Write Operation
The page write feature of the X28C010/X28HT010 allows
the entire memory to be written in 5 seconds. Page write
allows two to two hundred fifty-six bytes of data to be
consecutively written to the X28C010/X28HT010 prior to the
commencement of the internal programming cycle. The host
can fetch data from another device within the system during
a page write operation (change the source address), but the
page address (A8 through A16) for each subsequent valid
write cycle to the part during this operation must be the same
as the initial page address.
I/O
DP
TB
5
4
3
2
1
0
Reserved
Toggle Bit
DATA Polling
FIGURE 1. STATUS BIT ASSIGNMENT
DATA Polling (I/O7)
The X28C010/X28HT010 features DATA Polling as a
method to indicate to the host system that the byte write or
page write cycle has completed. DATA Polling allows a
simple bit test operation to determine the status of the
X28C010/X28HT010, eliminating additional interrupt inputs
or external hardware. During the internal programming cycle,
any attempt to read the last byte written will produce the
complement of that data on I/O7 (i.e., write data = 0xxx xxxx,
read data = 1xxx xxxx). Once the programming cycle is
complete, I/O7 will reflect true data. Note: If the
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host can
write an additional one to two hundred fifty six bytes in the
same manner as the first byte was written. Each successive
byte load cycle, started by the WE HIGH to LOW transition,
must begin within 100µs of the falling edge of the preceding
WE. If a subsequent WE HIGH to LOW transition is not
detected within 100µs, the internal automatic programming
cycle will commence. There is no page write window
limitation. Effectively the page write window is infinitely wide,
so long as the host continues to access the device within the
byte load cycle time of 100µs.
X28C010/X28HT010 is in the protected state, and an illegal
write operation is attempted, DATA Polling will not operate.
Toggle Bit (I/O6)
Write Operation Status Bits
The X28C010/X28HT010 also provides another method for
determining when the internal write cycle is complete. During
the internal programming cycle, I/O6 will toggle from HIGH to
LOW and LOW to HIGH on subsequent attempts to read the
device. When the internal cycle is complete the toggling will
cease and the device will be accessible for additional read or
write operations.
The X28C010/X28HT010 provides the user two write
operation status bits. These can be used to optimize a
system write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
DATA Polling I/O7
Last
Write
WE
CE
OE
V
IH
V
OH
HIGH Z
I/O
7
V
OL
X28C010
Ready
A -A
A
A
A
A
A
A
A
n
0
14
n
n
n
n
n
n
FIGURE 2. DATA POLLING BUS SEQUENCE
FN8105.1
February 12, 2007
4
X28C010, X28HT010
DATA Polling can effectively halve the time for writing to the
X28C010/X28HT010. The timing diagram in Figure 2
illustrates the sequence of events on the bus. The software
flow diagram in Figure 3 illustrates one method of
implementing the routine.
Write Data
No
Writes
Complete?
Yes
Save Last Data
and Address
Read Last
Address
IO
7
No
Compare?
Yes
X28C010
Ready
FIGURE 3. DATA POLLING SOFTWARE FLOW
The Toggle Bit I/O6
Last
Write
WE
CE
OE
V
OH
HIGH Z
I/O
6
*
*
V
OL
X28C010
Ready
* Beginning and ending state of I/O will vary
6
FIGURE 4. TOGGLE BIT BUS SEQUENCE
FN8105.1
February 12, 2007
5
X28C010, X28HT010
Software Data Protection
The X28C010/X28HT010 offers a software controlled data
protection feature. The X28C010/X28HT010 is shipped from
Intersil with the software data protection NOT ENABLED:
that is the device will be in the standard operating mode. In
this mode data should be protected during power-up/-down
operations through the use of external circuits. The host
would then have open read and write access of the device
once VCC was stable.
Last Write
Load Accum
From Addr N
Compare
Accum with
Addr N
The X28C010/X28HT010 can be automatically protected
during power-up and power-down without the need for
external circuits by employing the software data protection
feature. The internal software data protection circuit is
enabled after the first write operation utilizing the software
algorithm. This circuit is nonvolatile and will remain set for
the life of the device unless the reset command is issued.
No
Compare
Ok?
Once the software protection is enabled, the
X28C010/X28HT010 is also protected from inadvertent and
accidental writes in the powered-up state. That is, the
software algorithm must be issued prior to writing additional
data to the device.
Yes
Ready
FIGURE 5. TOGGLE BIT SOFTWARE FLOW
Software Algorithm
Selecting the software data protection mode requires the
host system to precede data write operations by a series of
three write operations to three specific addresses. Refer to
Figures 6 and 7 for the sequence. The three byte sequence
opens the page write window enabling the host to write from
one to two hundred fifty-six bytes of data. Once the page
load cycle has been completed, the device will automatically
be returned to the data protected state.
The Toggle Bit can eliminate the software housekeeping
chore of saving and fetching the last address and data
written to a device in order to implement DATA Polling. This
can be especially helpful in an array comprised of multiple
X28C010/X28HT010 memories that is frequently updated.
Toggle Bit Polling can also provide a method for status
checking in multiprocessor applications. The timing diagram
in Figure 4 illustrates the sequence of events on the bus.
The software flow diagram in Figure 5 illustrates a method
for polling the Toggle Bit.
Hardware Data Protection
The X28C010/X28HT010 provides three hardware features
that protect nonvolatile data from inadvertent writes.
• Noise Protection—A WE pulse less than 10ns will not
initiate a write cycle.
• Default VCC Sense—All functions are inhibited when VCC
is ≤ 3.5V.
• Write inhibit—Holding either OE LOW, WE HIGH, or CE
HIGH will prevent an inadvertent write cycle during power-
up and power-down, maintaining data integrity.
FN8105.1
February 12, 2007
6
X28C010, X28HT010
Software Data Protection
V
CC
0V
(V
)
CC
Data
Addr
AA
5555
55
2AAA
A0
5555
Write
Protected
t
WC
Writes
Ok
CE
≤ t
Byte
or
Page
BLC MAX
WE
FIGURE 6. TIMING SEQUENCE—BYTE OR PAGE WRITE
Regardless of whether the device has previously been
protected or not, once the software data protection algorithm
is used and data has been written, the X28C010/X28HT010
will automatically disable further writes unless another
command is issued to cancel it. If no further commands are
issued the X28C010/X28HT010 will be write protected
during power-down and after any subsequent power-up. The
state of A15 and A16 while executing the algorithm is don’t
care.
Write Data AA
to Address
5555
Write Data 55
to Address
2AAA
Note: Once initiated, the sequence of write operations
should not be interrupted.
Write Data A0
to Address
5555
Write Data XX
to Any
Address
Optional
Byte/Page
Load Operation
Write Last
Byte
Last Address
After t
WC
Re-Enters Data
Protected State
FIGURE 7. WRITE SEQUENCE FOR SOFTWARE DATA
PROTECTION
FN8105.1
February 12, 2007
7
X28C010, X28HT010
Resetting Software Data Protection
V
CC
Data
Addr
AA
5555
55
2AAA
80
5555
AA
5555
55
2AAA
20
5555
Standard
Operating
Mode
≥ t
WC
CE
WE
FIGURE 8. RESET SOFTWARE DATA PROTECTION TIMING SEQUENCE
System Considerations
Write Data AA
to Address
5555
Because the X28C010/X28HT010 is frequently used in large
memory arrays, it is provided with a two line control
architecture for both read and write operations. Proper
usage can provide the lowest possible power dissipation and
eliminate the possibility of contention where multiple I/O pins
share the same bus.
Write Data 55
to Address
2AAA
To gain the most benefit, it is recommended that CE be
decoded from the address bus and be used as the primary
device selection input. Both OE and WE would then be
common among all devices in the array. For a read operation
this assures that all deselected devices are in their standby
mode and that only the selected device(s) is outputting data
on the bus.
Write Data80
to Address
5555
Write Data AA
to Address
5555
Because the X28C010/X28HT010 has two power modes,
standby and active, proper decoupling of the memory array
is of prime concern. Enabling CE will cause transient current
spikes. The magnitude of these spikes is dependent on the
output capacitive loading of the I/Os. Therefore, the larger
the array sharing a common bus, the larger the transient
spikes. The voltage peaks associated with the current
transients can be suppressed by the proper selection and
placement of decoupling capacitors. As a minimum, it is
recommended that a 0.1µF high frequency ceramic
capacitor be used between VCC and VSS at each device.
Depending on the size of the array, the value of the capacitor
may have to be larger.
Write Data 55
to Address
2AAA
Write Data 20
to Address
5555
FIGURE 9. SOFTWARE SEQUENCE TO DEACTIVATE
SOFTWARE DATA PROTECTION
In addition, it is recommended that a 4.7µF electrolytic bulk
capacitor be placed between VCC and VSS for each eight
devices employed in the array. This bulk capacitor is
employed to overcome the voltage droop caused by the
inductive effects of the PC board traces.
In the event the user wants to deactivate the software data
protection feature for testing or reprogramming in an
EEPROM programmer, the following six step algorithm will
reset the internal protection circuit. After tWC, the
X28C010/X28HT010 will be in standard operating mode.
Note: Once initiated, the sequence of write operations
should not be interrupted.
FN8105.1
February 12, 2007
8
X28C010, X28HT010
Active Supply Current vs. Ambient Temperature
18
16
14
12
10
V
= 5V
CC
-55
-10
+35
+80
+125
Ambient Temperature (°C)
Standby Supply Current vs. Ambient Temperature
0.3
V
= 5V
CC
0.25
0.2
0.15
0.1
0.05
-55
-10
+35
+80
+125
Ambient Temperature (°C)
ICC (RD) by Temperature Over Frequency
60
5.0 V
CC
50
40
30
20
10
-55°C
+25°C
+125°C
0
3
6
9
12
15
Frequency (MHz)
FN8105.1
February 12, 2007
9
X28C010, X28HT010
Absolute Maximum Ratings
Recommended Operating Conditions
Temperature under bias
Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C tp +85°C
Military . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V ±10%
High Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +175°C
X28C010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +85°C
X28C010I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
X28C010M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
X28HT010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +175°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on any pin with respect to V . . . . . . . . . . . . . . -1V to +7V
SS
D.C. output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Lead temperature
(soldering, 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+300°C
CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of
the device at these or any other conditions (above those indicated in the operational sections of this specification) is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
DC Electrical Specifications Over the recommended operating conditions, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
I
V
Current (Active) (TTL Inputs)
CE = OE = V , WE = V , All I/O’s = Open,
50
mA
CC
CC
IL IH
Address Inputs = 0.4V/2.4V Levels @ f = 5MHz
I
I
V
V
Current (Standby) (TTL Inputs) CE = V , OE = V , All I/O’s = Open, Other Inputs = V
3
mA
µA
SB1
SB2
CC
CC
IH
IL
IH
Current (Standby) (CMOS
CE = V
- 0.3V, OE = V , All I/O’s = Open,
500
CC
IL
Inputs)
Other Inputs = V
CC
I
Input Leakage Current
V
V
V
V
= V to V
SS CC
10
20
µA
µA
µA
µA
V
LI
IN
= V to V
SS
(Note 2)
CC
IN
I
Output Leakage Current
= V to V , CE = V
SS CC IH
10
LO
OUT
OUT
= V to V , CE = V (Note 2)
SS CC IH
20
V
(Note 1) Input LOW Voltage
(Note 1) Input HIGH Voltage
-1
-1
0.8
0.6
lL
(Note 2)
V
V
2
V
V
+ 1
V
IH
CC
CC
(Note 2)
2.2
+ 1
V
V
Output LOW Voltage
Output HIGH Voltage
Back Bias Current
I
I
I
I
= 2.1mA
0.4
V
OL
OH
BB
OL
OL
OH
OH
= 1mA (Note 2)
= -400µA
0.5
V
V
2.4
2.6
V
= -400µA
V
I
V
= -3V ±10% (Note 2)
200
µA
BB
NOTE:
1. VIL min. and VIH max. are for reference only and are not tested.
2. X28HT010W
Power-Up Timing
SYMBOL
PARAMETER
Power-up to Read operation
Power-up to Write operation
MAX
100
5
UNIT
t
(Note 3)
(Note 3)
µs
PUR
t
ms
PUW
Capacitance
T
= +25°C, f = 1MHz, V
= 5V
A
CC
SYMBOL
PARAMETER
TEST CONDITIONS
MAX
10
UNIT
C
(Note 3)
(Note 3)
Input/Output capacitance
Input capacitance
V
= 0V
= 0V
pF
pF
I/O
I/O
C
V
10
IN
IN
NOTE:
3. This parameter is periodically sampled and not 100% tested.
FN8105.1
February 12, 2007
10
X28C010, X28HT010
Endurance and Data Retention
PARAMETER
MIN
10,000
100,000
100
MAX
UNIT
Endurance
Cycles per byte
Cycles per page
Years
Endurance
Data Retention
Symbol Table
A.C. Conditions of Test
Input pulse levels
0V to 3V
10ns
WAVEFORM
INPUTS
OUTPUTS
Input rise and fall times
Input and output timing levels
Must be
steady
Will be
steady
1.5V
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
Mode Selection
CE
OE
WE
MODE
Read
Write
I/O
POWER
Active
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
L
L
H
D
OUT
L
H
L
D
Active
IN
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
H
X
X
Standby and
Write Inhibit
High Z
Standby
N/A
Center Line
is High
Impedance
X
X
L
X
H
Write Inhibit
Write Inhibit
—
—
—
—
X
Equivalent A.C. Load Circuit
5V
1.92kΩ
Output
1.37kΩ
100pF
AC Electrical Specifications Over the recommended operating conditions, unless otherwise specified.
X28C010-20,
X28C010-12
X28C010-15
X28HT010W
X28C010-25
SYMBOL
PARAMETER
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
READ CYCLE LIMITS
t
Read cycle time
120
150
200
250
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
t
Chip enable access time
Address access time
120
120
50
150
150
50
200
200
50
250
250
50
CE
t
AA
t
Output enable access time
CE LOW to active output
OE
t
(Note 4)
0
0
0
0
0
0
0
0
LZ
t
(Note 4) OE LOW to active output
(Note 4) CE HIGH to high Z output
OLZ
t
50
50
50
50
50
50
50
50
HZ
t
(Note 4) OE HIGH to high Z output
OHZ
t
Output hold from address change
0
0
0
0
OH
FN8105.1
February 12, 2007
11
X28C010, X28HT010
Read Cycle
Address
CE
t
RC
t
CE
t
OE
OE
V
IH
WE
t
t
OHZ
OLZ
t
t
t
t
HZ
LZ
OH
HIGH Z
Data I/O
Data Valid
Data Valid
AA
NOTE:
4. tLZ min.,tHZ, tOLZ min., and tOHZ are periodically sampled and not 100% tested. tHZ max. and tOHZ max. are measured, with CL = 5pF, from the point
when CE or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven.
Write Cycle Limits
SYMBOL
(Note 5) Write cycle time
PARAMETER
MIN
MAX
UNIT
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
µs
µs
t
10
WC
t
Address setup time
Address hold time
Write setup time
Write hold time
CE pulse width
OE HIGH setup time
OE HIGH hold time
WE pulse width
WE HIGH recovery
Data valid
0
50
0
AS
AH
CS
CH
t
t
t
0
t
100
10
10
100
100
CW
t
OES
OEH
t
t
WP
t
WPH
t
1
DV
DS
DH
t
Data setup
50
0
t
Data hold
t
Delay to next write
Byte load cycle
10
0.2
DW
t
100
BLC
FN8105.1
February 12, 2007
12
X28C010, X28HT010
WE Controlled Write Cycle
t
WC
Address
t
t
AH
AS
t
t
CS
CH
CE
OE
t
t
OEH
OES
t
WP
WE
t
WPH
t
DV
Data In
Data Valid
t
t
DH
DS
Data Out
HIGH Z
NOTE:
5. tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device
requires to complete internal write operation.
CE Controlled Write Cycle
t
WC
Address
CE
t
t
AH
AS
t
CW
t
WPH
t
OES
OE
t
OEH
t
t
t
CS
CH
WE
t
DV
Data Valid
Data In
t
DS
DH
HIGH Z
Data Out
FN8105.1
February 12, 2007
13
X28C010, X28HT010
Page Write Cycle
(Note 5)
OE
CE
t
t
BLC
WP
WE
t
WPH
(Note 7)
Address*
Last Byte
Byte n+2
I/O
Byte 0
Byte 1
Byte 2
Byte n
Byte n+1
t
WC
*For each successive write within the page write operation, A -A should be the same or
16
8
writes to an unknown address could occur.
NOTES:
6. Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch
data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation.
7. The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the
CE or WE controlled write cycle timing.
DATA Polling Timing Diagram (Note 8)
Address
CE
A
A
A
n
n
n
WE
t
t
OEH
OES
OE
t
DW
= X
D
= X
D
= X
D
OUT
I/O
7
IN
OUT
t
WC
FN8105.1
February 12, 2007
14
X28C010, X28HT010
Toggle Bit Timing Diagram
CE
WE
t
OES
t
OEH
OE
t
DW
HIGH Z
I/O
*
6
*
t
WC
* I/O beginning and ending state will vary.
6
NOTE:
8. Polling operations are by definition read cycles and are therefore subject to read cycle timings.
FN8105.1
February 12, 2007
15
X28C010, X28HT010
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 LEAD FINISH
F32.6 MIL-STD-1835 GDIP1-T32 (D-16, CONFIGURATION A)
32 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
-D-
E
-A-
INCHES
MIN
MILLIMETERS
BASE
(c)
METAL
SYMBOL
MAX
0.232
0.026
0.023
0.065
0.045
0.018
0.015
1.690
0.610
MIN
-
MAX
5.92
NOTES
b1
A
b
-
-
M
M
(b)
0.014
0.014
0.045
0.023
0.008
0.008
-
0.36
0.36
1.14
0.58
0.20
0.20
-
0.66
2
-B-
b1
b2
b3
c
0.58
3
SECTION A-A
bbb
C A - B
D
D
S
S
S
1.65
-
1.14
4
BASE
Q
PLANE
0.46
2
A
-C-
SEATING
PLANE
c1
D
0.38
3
L
α
42.95
15.49
5
S1
b2
eA
A A
e
E
0.500
12.70
5
b
C A - B
eA/2
aaa M C A - B S D S
c
e
0.100 BSC
2.54 BSC
-
eA
eA/2
L
0.600 BSC
0.300 BSC
15.24 BSC
7.62 BSC
-
ccc
D
S
M
S
-
NOTES:
0.125
0.200
0.060
-
3.18
5.08
1.52
-
-
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
Q
0.015
0.38
6
S1
0.005
0.13
7
90°
105°
0.015
0.030
0.010
0.0015
90°
105°
0.38
0.76
0.25
0.038
-
α
aaa
bbb
ccc
M
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
-
-
-
-
-
-
-
-
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
-
2, 3
8
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
32
32
Rev. 0 8/06
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
FN8105.1
February 12, 2007
16
X28C010, X28HT010
Packaging Information
32-Lead Ceramic Flat Pack Type F
1.228 (31.19)
1.000 (25.40)
Pin 1 Index
0.019 (0.48)
0.015 (0.38)
1
32
0.050 (1.27) BSC
0.830 (21.08) Max.
0.045 (1.14) Max.
0.005 (0.13) Min.
0.440
0.430 (10.93)
0.120 (3.05)
0.090 (2.29)
0.007 (0.18)
0.004 (0.10)
0.370 (9.40)
0.270 (6.86)
0.347 (8.82)
0.330 (8.38)
0.026 (0.66)
Min.
0.030 (0.76)
Min.
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
FN8105.1
February 12, 2007
17
X28C010, X28HT010
Packaging Information
32-Pad Stretched Ceramic Leadless Chip Carrier Package Type N
0.300 BSC
0.035 x 45° Ref.
Detail A
0.085 ± 0.010
Pin 1
0.005/0.015
0.006/0.022
0.025 ± 0.003
Detail A
0.400 BSC
0.050 ± 0.005
0.020 (1.02) x 45° Ref.
0.050 BSC
Typ. (3) Plcs.
0.450 ± 0.008
0.458 Max.
0.060/0.120
0.700 ± 0.010
0.708 Max.
Pin #1 Index Corner
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. TOLERANCE: ±1% NLT±0.005 (0.127)
FN8105.1
February 12, 2007
18
X28C010, X28HT010
Packaging Information
32-Lead Ceramic Small Outline Gull Wing Package Type R
0.060 Nom.
See Detail “A”
For Lead
Information
0.020 Min.
0.165 Typ.
0.340
0.015 R Typ.
±0.007
0.015 R
Typ.
0.035 Typ.
0.035 Min.
Detail “A”
0.050"
Typical
0.019
0.015
0.050"
Typical
0.560"
Typical
0.830
Max.
0.750
±0.005
0.030" Typical
32 Places
0.050
FOOTPRINT
0.440 Max.
0.560 Nom.
NOTES:
1. ALL DIMENSIONS IN INCHES
2. FORMED LEAD SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.004 INCHES
FN8105.1
February 12, 2007
19
X28C010, X28HT010
Packaging Information
36 Lead Ceramic Pin Grid Array Package
Package Code G36.760x760A
15
17
16
19
18
21
20
22
23
25
27
29
32
33
A
A
0.008 (0.20)
0.050 (1.27)
13
12
10
8
14
11
9
24
26
28
30
31
NOTE:Leads 5, 14,23, & 32
7
Typ. 0.100 (2.54)
All Leads
6
5
2
3
36
1
34
35
Typ. 0.180 (.010)
(4.57 ± .25)
4 Corners
4
Typ. 0.180 (.010)
(4.57 ± .25)
4 Corners
0.120 (3.05)
0.100 (2.54)
0.072 (1.83)
0.062 (1.57)
Pin 1 Index
0.770 (19.56)
0.750 (19.05)
SQ
0.020 (0.51)
0.016 (0.41)
A
A
0.185 (4.70)
0.175 (4.45)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8105.1
February 12, 2007
20
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