X28HC64JZ-12 [INTERSIL]
5 Volt, Byte Alterable EEPROM; 5伏，可变的字节EEPROM
| 型号： | X28HC64JZ-12 |
| 厂家： | 
Intersil |
| 描述： | 5 Volt, Byte Alterable EEPROM |
| 文件： | 总17页 (文件大小：358K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X28HC64
64k, 8k x 8-Bit
®
Data Sheet
August 28, 2009
FN8109.2
5 Volt, Byte Alterable EEPROM
Features
The X28HC64 is an 8K x 8 EEPROM, fabricated with Intersil’s
proprietary, high performance, floating gate CMOS
technology. Like all Intersil programmable nonvolatile
memories, the X28HC64 is a 5V only device. It features the
JEDEC approved pinout for byte-wide memories, compatible
with industry standard RAMs.
• 70ns access time
• Simple byte and page write
- Single 5V supply
- No external high voltages or VPP control circuits
- Self-timed
- No erase before write
The X28HC64 supports a 64-byte page write operation,
effectively providing a 32µs/byte write cycle, and enabling the
entire memory to be typically written in 0.25 seconds. The
X28HC64 also features DATA Polling and Toggle Bit Polling,
two methods providing early end of write detection. In addition,
the X28HC64 includes a user-optional software data protection
mode that further enhances Intersil’s hardware write protect
capability.
- No complex programming algorithms
- No overerase problem
• Low power CMOS
- 40mA active current max.
• 200µA standby current max.
• Fast write cycle times
- 64-byte page write operation
- Byte or page write cycle: 2ms typical
- Complete memory rewrite: 0.25 sec. typical
- Effective byte write cycle time: 32µs typical
Intersil EEPROMs are designed and tested for applications
requiring extended endurance. Inherent data retention is
greater than 100 years.
• Software data protection
• End of write detection
- DATA polling
- Toggle bit
• High reliability
- Endurance: 100000 cycles
- Data retention: 100 years
• JEDEC approved byte-wide pin out
• Pb-free available (RoHS compliant)
Pinouts
X28HC64
(28 LD PDIP, SOIC)
TOP VIEW
X28HC64
(32 LD PLCC)
TOP VIEW
1
28
VCC
NC
A12
A7
2
27
WE
NC
A8
4
3
2
1
32 31 30
29
3
26
A6
A5
A4
A3
A2
A1
A0
5
A8
A9
4
25
A6
6
7
28
27
5
24
A9
A5
A11
NC
OE
A10
6
23
A11
A4
8
9
26
25
7
X28HC64 22
A3
OE
A10
X28HC64
(Top View)
8
21
20
19
18
17
16
15
A2
10
11
24
23
9
A1
CE
CE
I/O7
I/O6
I/O5
I/O4
I/O3
10
11
12
13
14
A0
I/O7
I/O6
12
13
22
21
NC
I/O0
I/O1
I/O0
14 15 16 17 18 19 20
I/O2
VSS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006, 2009. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
X28HC64
Ordering Information
TEMPERATURE
RANGE (°C)
ACCESS TIME
(ns)
PKG.
DWG. #
PART NUMBER
PART MARKING
PACKAGE
32 Ld PLCC
X28HC64J-70 RR
X28HC64JI-70 ZRR
X28HC64J-70 ZRR
X28HC64SI-70 RR
X28HC64S-70 RRZ
X28HC64J-90 RR
X28HC64JI-90 RR
X28HC64JI-90 ZRR
X28HC64P-90 RR
X28HC64PI-90 RR
X28HC64PI-90 RRZ
X28HC64P-90 RRZ
X28HC64J-12 RR
X28HC64JI-12 RR
X28HC64JI-12 Z RR
X28HC64J-12 RRZ
X28HC64P-12 RR
X28HC64PI-12 RR
0 to +70
70
N32.45x55
N32.45x55
N32.45x55
M28.3
X28HC64J-70*
-40 to +85
0 to +70
32 Ld PLCC (Pb-free)
32 Ld PLCC (Pb-free)
28 Ld SOIC (300 mil)
X28HC64JIZ-70* (Note 1)
X28HC64JZ-70* (Note 1)
X28HC64SIZ-70
-40 to +85
0 to +70
28 Ld SOIC (300 mil) (Pb-free) M28.3
X28HC64SZ-70 (Note 1)
X28HC64J-90*
0 to +70
90
32 Ld PLCC
N32.45x55
-40 to +85
-40 to +85
0 to +70
32 Ld PLCC
N32.45x55
N32.45x55
E28.6
X28HC64JI-90**
32 Ld PLCC (Pb-free)
28 Ld PDIP
X28HC64JIZ-90* (Note 1)
X28HC64P-90
-40 to +85
-40 to +85
0 to +70
28 Ld PDIP
E28.6
X28HC64PI-90
28 Ld PDIP (Pb-free)
28 Ld PDIP (Pb-free)
32 Ld PLCC
E28.6
X28HC64PIZ-90 (Notes 1, 2)
E28.6
X28HC64PZ-90 (Notes 1, 2)
X28HC64J-12*
0 to +70
120
N32.45x55
N32.45x55
N32.45x55
N32.45x55
E28.6
X28HC64JI-12*
-40 to +85
-40 to +85
0 to +70
32 Ld PLCC
X28HC64JIZ-12* (Note 1)
X28HC64JZ-12* (Note 1)
X28HC64P-12
32 Ld PLCC (Pb-free)
32 Ld PLCC (Pb-free)
28 Ld PDIP
0 to +70
X28HC64PI-12
-40 to +85
-40 to +85
0 to +70
28 Ld PDIP
E28.6
X28HC64PIZ-12 (Notes 1, 2) X28HC64PI-12 RRZ
X28HC64PZ-12 (Notes 1, 2) X28HC64P-12 RRZ
28 Ld PDIP (Pb-free)
28 Ld PDIP (Pb-free)
28 Ld SOIC (300 mil)
28 Ld SOIC (300 mil)
E28.6
E28.6
X28HC64S-12*, **
X28HC64S-12 RR
X28HC64SI-12 RR
X28HC64SI-12 RRZ
X28HC64S-12 RRZ
0 to +70
M28.3
X28HC64SI-12*
-40 to +85
-40 to +85
0 to +70
M28.3
X28HC64SIZ-12* (Note 1)
X28HC64SZ-12 (Note 1)
28 Ld SOIC (300 mil) (Pb-free) M28.3
28 Ld SOIC (300 mil) (Pb-free) M28.3
*Add “T1” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
***Add “T2” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC
J STD-020.
2. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing
applications.
FN8109.2
August 28, 2009
2
X28HC64
Device Operation
Pin Descriptions
Addresses (A -A )
Read
0
12
The Address inputs select an 8-bit memory location during a
read or write operation.
Read operations are initiated by both OE and CE LOW. The
read operation is terminated by either CE or OE returning
HIGH. This two line control architecture eliminates bus
contention in a system environment. The data bus will be in
a high impedance state when either OE or CE is HIGH.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/write
operations. When CE is HIGH, power consumption is reduced.
Write
Output Enable (OE)
Write operations are initiated when both CE and WE are
LOW and OE is HIGH. The X28HC64 supports both a CE
and WE controlled write cycle. That is, the address is latched
by the falling edge of either CE or WE, whichever occurs
last. Similarly, the data is latched internally by the rising edge
of either CE or WE, whichever occurs first. A byte write
operation, once initiated, will automatically continue to
completion, typically within 2ms.
The Output Enable input controls the data output buffers and
is used to initiate read operations.
Data In/Data Out (I/O -I/O )
0
7
Data is written to or read from the X28HC64 through the I/O
pins.
Write Enable (WE)
The Write Enable input controls the writing of data to the
X28HC64.
Page Write Operation
The page write feature of the X28HC64 allows the entire
memory to be written in 0.25 seconds. Page write allows two
to sixty-four bytes of data to be consecutively written to the
X28HC64 prior to the commencement of the internal
programming cycle. The host can fetch data from another
device within the system during a page write operation
(change the source address), but the page address (A6
through A12) for each subsequent valid write cycle to the part
during this operation must be the same as the initial page
address.
TABLE 1. PIN NAMES
SYMBOL
A0-A12
I/O0-I/O7
WE
DESCRIPTION
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
CE
OE
VCC
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host can
write an additional one to sixty-three bytes in the same
manner. Each successive byte load cycle, started by the WE
HIGH to LOW transition, must begin within 100µs of the
falling edge of the preceding WE. If a subsequent WE HIGH
to LOW transition is not detected within 100µs, the internal
automatic programming cycle will commence. There is no
page write window limitation. Effectively the page write
window is infinitely wide, so long as the host continues to
access the device within the byte load cycle time of 100µs.
VSS
Ground
NC
No Connect
Block Diagram
65,536-BIT
X BUFFERS
LATCHES AND
DECODER
EEPROM
ARRAY
A –A
0
12
ADDRESS
INPUTS
Write Operation Status Bits
Y BUFFERS
LATCHES
AND
The X28HC64 provides the user two write operation status
bits. These can be used to optimize a system write cycle
time. The status bits are mapped onto the I/O bus as shown
in Figure 1.
I/O BUFFERS
AND LATCHES
DECODER
CE
I/O
DP
TB
5
4
3
2
1
0
CONTROL
LOGIC AND
TIMING
I/O –I/O
DATA INPUTS/OUTPUTS
0
7
OE
WE
RESERVED
TOGGLE BIT
DATA POLLING
V
CC
SS
V
FIGURE 1. STATUS BIT ASSIGNMENT
FN8109.2
August 28, 2009
3
X28HC64
DATA Polling (I/O )
Toggle Bit (I/O )
7
6
The X28HC64 features DATA Polling as a method to indicate
to the host system that the byte write or page write cycle has
completed. DATA Polling allows a simple bit test operation to
determine the status of the X28HC64, eliminating additional
interrupt inputs or external hardware. During the internal
programming cycle, any attempt to read the last byte written
will produce the complement of that data on I/O7 (i.e. write
data = 0xxx xxxx, read data = 1xxx xxxx). Once the
The X28HC64 also provides another method for determining
when the internal write cycle is complete. During the internal
programming cycle I/O6 will toggle from HIGH to LOW and
LOW to HIGH on subsequent attempts to read the device.
When the internal cycle is complete the toggling will cease
and the device will be accessible for additional read or write
operations.
programming cycle is complete, I/O7 will reflect true data.
DATA Polling I/O
7
Last
Write
WE
CE
OE
V
IH
V
OH
HIGH Z
I/O
7
V
OL
X28HC64
Ready
A –A
0
12
An
An
An
An
An
An
An
FIGURE 2. DATA POLLING BUS SEQUENCE
DATA Polling can effectively reduce the time for writing to the
X28HC64. The timing diagram in Figure 2 illustrates the
sequence of events on the bus. The software flow diagram in
Figure 3 illustrates one method of implementing the routine.
WRITE DATA
NO
WRITES
COMPLETE?
YES
SAVE LAST DATA
AND ADDRESS
READ LAST
ADDRESS
IO
7
NO
COMPARE?
YES
READY
FIGURE 3. DATA POLLING SOFTWARE FLOW
FN8109.2
August 28, 2009
4
X28HC64
The Toggle Bit I/O
6
LAST
WRITE
WE
CE
OE
V
OH
HIGH Z
I/O
6
*
*
V
OL
X28HC64
READY
* BEGINNING AND ENDING STATE OF I/O WILL VARY.
6
FIGURE 4. TOGGLE BIT BUS SEQUENCE
Hardware Data Protection
The X28HC64 provides two hardware features that protect
nonvolatile data from inadvertent writes.
LAST WRITE
YES
• Default VCC Sense—All write functions are inhibited when
VCC is 3V typically.
• Write Inhibit—Holding either OE LOW, WE HIGH, or CE
HIGH will prevent an inadvertent write cycle during power-
up and power-down, maintaining data integrity.
LOAD ACCUM
FROM ADDR N
Software Data Protection
The X28HC64 offers a software controlled data protection
feature. The X28HC64 is shipped from Intersil with the software
data protection NOT ENABLED; that is, the device will be in the
standard operating mode. In this mode data should be
protected during power-up/-down operations through the use of
external circuits. The host would then have open read and write
access of the device once VCC was stable.
COMPARE
ACCUM WITH
ADDR N
NO
COMPARE
OK?
YES
The X28HC64 can be automatically protected during power-
up and power-down without the need for external circuits by
employing the software data protection feature. The internal
software data protection circuit is enabled after the first write
operation utilizing the software algorithm. This circuit is
nonvolatile and will remain set for the life of the device,
unless the reset command is issued.
READY
FIGURE 5. TOGGLE BIT SOFTWARE FLOW
The Toggle Bit can eliminate the chore of saving and
fetching the last address and data in order to implement
DATA Polling. This can be especially helpful in an array
comprised of multiple X28HC64 memories that is frequently
updated. Toggle Bit Polling can also provide a method for
status checking in multiprocessor applications. The timing
diagram in Figure 4 illustrates the sequence of events on the
bus. The software flow diagram in Figure 5 illustrates a
method for polling the Toggle Bit.
Once the software protection is enabled, the X28HC64 is
also protected from inadvertent and accidental writes in the
powered-up state. That is, the software algorithm must be
issued prior to writing additional data to the device.
Software Algorithm
Selecting the software data protection mode requires the
host system to precede data write operations by a series of
three write operations to three specific addresses. Refer to
Figure 6 and 7 for the sequence. The three-byte sequence
opens the page write window, enabling the host to write from
one to sixty-four bytes of data. Once the page load cycle has
been completed, the device will automatically be returned to
the data protected state.
FN8109.2
August 28, 2009
5
X28HC64
Software Data Protection
V
CC
(V
)
CC
0V
DATA
ADDR
AAA
1555
55
0AAA
A0
1555
WRITES
OK
WRITE
PROTECTED
t
WC
CE
BYTE
OR
≤t
BLC MAX
WE
PAGE
FIGURE 6. TIMING SEQUENCE—BYTE OR PAGE WRITE
Regardless of whether the device has previously been
protected or not, once the software data protection algorithm
is used, the X28HC64 will automatically disable further
writes unless another command is issued to deactivate it. If
no further commands are issued the X28HC64 will be write
protected during power-down and after any subsequent
power-up.
WRITE DATA AA
TO ADDRESS
1555
WRITE DATA 55
TO ADDRESS
0AAA
Note: Once initiated, the sequence of write operations
should not be interrupted.
WRITE DATA A0
TO ADDRESS
1555
BYTE/PAGE
LOAD ENABLED
WRITE DATA XX
TO ANY
ADDRESS
OPTIONAL
BYTE/PAGE
LOAD OPERATION
WRITE LAST
BYTE TO
LAST ADDRESS
AFTER T
WC
RE-ENTERS DATA
PROTECTED STATE
FIGURE 7. WRITE SEQUENCE FOR SOFTWARE DATA
PROTECTION
FN8109.2
August 28, 2009
6
X28HC64
Resetting Software Data Protection
V
CC
AAA
1555
55
0AAA
80
1555
AA
1555
55
0AAA
20
1555
STANDARD
OPERATING
MODE
DATA
ADDR
≥t
WC
CE
WE
FIGURE 8. RESET SOFTWARE DATA PROTECTION TIMING SEQUENCE
In the event the user wants to deactivate the software data
protection feature for testing or reprogramming in an
EEPROM programmer, the following six step algorithm will
reset the internal protection circuit. After tWC, the X28HC64
will be in standard operating mode.
WRITE DATA AA
TO ADDRESS
1555
Note: Once initiated, the sequence of write operations
should not be interrupted.
WRITE DATA 55
TO ADDRESS
0AAA
WRITE DATA 80
TO ADDRESS
1555
WRITE DATA AA
ADDRESS
1555
WRITE DATA 55
TO ADDRESS
0AAA
WRITE DATA 20
TO ADDRESS
1555
FIGURE 9. SOFTWARE SEQUENCE TO DEACTIVATE
SOFTWARE
FN8109.2
August 28, 2009
7
X28HC64
Because the X28HC64 has two power modes, standby and
System Considerations
active, proper decoupling of the memory array is of prime
concern. Enabling CE will cause transient current spikes.
The magnitude of these spikes is dependent on the output
capacitive loading of the I/Os. Therefore, the larger the array
sharing a common bus, the larger the transient spikes. The
voltage peaks associated with the current transients can be
suppressed by the proper selection and placement of
decoupling capacitors. As a minimum, it is recommended
that a 0.1µF high frequency ceramic capacitor be used
between VCC and VSS at each device. Depending on the
size of the array, the value of the capacitor may have to be
larger.
Because the X28HC64 is frequently used in large memory
arrays, it is provided with a two-line control architecture for
both read and write operations. Proper usage can provide
the lowest possible power dissipation, and eliminate the
possibility of contention where multiple I/O pins share the
same bus.
To gain the most benefit, it is recommended that CE be
decoded from the address bus, and be used as the primary
device selection input. Both OE and WE would then be
common among all devices in the array. For a read
operation, this assures that all deselected devices are in
their standby mode, and that only the selected device(s)
is/are outputting data on the bus.
In addition, it is recommended that a 4.7µF electrolytic bulk
capacitor be placed between VCC and VSS for each eight
devices employed in the array. This bulk capacitor is
employed to overcome the voltage droop caused by the
inductive effects of the PC board traces.
1.4
1.4
5.5V
CC
5.5V
CC
1.2
1.0
0.8
0.6
0.4
0.2
1.2
1.0
0.8
0.6
0.4
0.2
- 55°C
+ 25°C
5.0V
CC
+ 125°C
4.5V
CC
0M
10M
FREQUENCY (Hz)
20M
0M
10M
FREQUENCY (Hz)
20M
FIGURE 11. NORMALIZED ICC(RD) @ 25% OVER THE VCC
RANGE AND FREQUENCY
FIGURE 10. NORMALIZED ICC(RD) BY TEMPERATURE
OVER FREQUENCY DATA PROTECTION
FN8109.2
August 28, 2009
8
X28HC64
Absolute Maximum Ratings
Thermal Information
Temperature Under Bias
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
X28HC64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +85°C
X28HC64I. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on any Pin with Respect to Vss . . . . . . . . . . . . . . -1V to +7V
DC Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Recommended Operating Conditions
Commercial Temperature Range. . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial Temperature Range . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage Range
X28HC64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V ±10%
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
DC Electrical Specifications Over recommended operating conditions, unless otherwise specified. Parameters with MIN and/or MAX
limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
TYP
PARAMETER
SYMBOL
TEST CONDITIONS
MIN (Note 3)
MAX
UNIT
VCC Current (active) (TTL Inputs)
ICC
CE = OE = VIL, WE = VIH, All I/O’s = open, address
inputs = TTL levels @ f = 10 MHz
15
40
mA
V
V
CC Current (Standby) (TTL Inputs)
CC Current (Standby) (CMOS Inputs)
ISB1
ISB2
CE = VIH, OE = VIL All I/O’s = open, other inputs = VIH
1
2
mA
µA
CE = VCC - 0.3V, OE = GND, All I/O’s = open, other
inputs = VCC - 0.3V
100
200
Input Leakage Current
Output Leakage Current
Input LOW Voltage (Note 4)
Input HIGH Voltage (Note 4)
Output LOW Voltage
Output HIGH Voltage
NOTES:
ILI
ILO
VIN = VSS to VCC
±10
±10
µA
µA
V
VOUT = VSS to VCC, CE = VIH
VlL
-1
2
0.8
VIH
VOL
VOH
VCC + 1
0.4
V
IOL = 5mA
V
IOH = -5mA
2.4
V
3. Typical values are for TA = +25°C and nominal supply voltage
4. VIL min. and VIH max. are for reference only and are not tested.
Endurance and Data Retention
Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified.
Temperature limits established by characterization and are not production tested.
PARAMETER
Minimum Endurance
Data Retention
MIN
100,000
100
MAX
UNIT
Cycles
Years
FN8109.2
August 28, 2009
9
X28HC64
Power-up Timing
Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits
established by characterization and are not production tested.
TYP
PARAMETER
SYMBOL
tPUR
(Note 3)
UNIT
µs
Power-up to Read Operation (Note 5)
Power-up to Write Operation (Note 5)
100
5
tPUW
ms
Capacitance
TA = +25°C, f = 1MHz, VCC = 5V
PARAMETER
SYMBOL
CI/O
TEST CONDITIONS
MAX
10
UNIT
Input/output Capacitance (Note 5)
Input Capacitance (Note 5)
NOTE:
VI/O = 0V
VIN = 0V
pF
pF
CIN
6
5. This parameter is periodically sampled and not 100% tested.
Symbol Table
TABLE 2. AC CONDITIONS OF TEST
Input Pulse Levels
0V to 3V
5ns
WAVEFORM
INPUTS
OUTPUTS
Input Rise and Fall Times
Input and Output Timing Levels
Must be
steady
Will be
steady
1.5V
Ma y change
from LO W
to HIGH
Will change
from LO W
to HIGH
TABLE 3. MODE SELECTION
Ma y change
from HIGH
to LO W
Will change
from HIGH
to LO W
CE
L
OE
L
WE
H
MODE
Read
Write
I/O
POWER
Active
DOUT
DIN
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
L
H
L
Active
H
X
X
Standby and write
inhibit
High Z
Standby
N/A
Center Line
is High
Impedance
X
X
L
X
H
Write inhibit
Write inhibit
—
—
—
—
X
Equivalent AC Load Circuits
5V
1.92kΩ
OUTPUT
1.37kΩ
30pF
FN8109.2
August 28, 2009
10
X28HC64
AC Electrical Specifications
Read Cycle Limits Over the recommended operating conditions unless otherwise specified. Parameters with MIN and/or MAX limits are
100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not
production tested.
X28HC64-70
X28HC64-90
X28HC64-12
-55°C TO +125°C
-55°C TO +125°C
-55°C TO +125°C
PARAMETER
Read Cycle Time
SYMBOL
tRC
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
ns
70
90
120
Chip Enable Access Time
Address Access Time
tCE
70
70
35
90
90
40
120
120
50
ns
tAA
ns
Output Enable Access Time
CE LOW to Active Output (Note 6)
OE LOW to Active Output (Note 6)
CE HIGH to High Z Output (Note 6)
OE HIGH to High Z Output (Note 6)
Output Hold from Address Change
NOTE:
tOE
ns
tLZ
0
0
0
0
0
0
ns
tOLZ
tHZ
tOHZ
tOH
ns
30
30
30
30
30
30
ns
ns
0
0
0
ns
6. tLZ min., tHZ, tOLZ min., and tOHZ are periodically sampled and not 100% tested. tHZ max. and tOHZ max. are measured from the point when CE
or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven.
Read Cycle
t
RC
ADDRESS
t
CE
CE
t
OE
OE
V
IH
WE
t
t
OHZ
OLZ
t
t
t
t
HZ
LZ
OH
AA
HIGH Z
DATA I/O
DATA VALID
DATA VALID
FN8109.2
August 28, 2009
11
X28HC64
Write Cycle Limits Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits
established by characterization and are not production tested.
TYP
PARAMETER
Write Cycle Time (Note 7)
SYMBOL
tWC
MIN
(Note 3)
MAX
UNIT
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
µs
µs
2
5
Address Setup Time
Address Hold Time
Write Setup Time
Write Hold Time
tAS
0
50
0
tAH
tCS
tCH
0
CE Pulse Width
tCW
50
0
OE High Setup Time
OE High Hold Time
WE Pulse Width
WE HIGH Recovery (Note 8)
Data Valid (Note 8)
Data Setup
tOES
tOEH
tWP
0
50
50
tWPH
tDV
1
tDS
50
0
Data Hold
tDH
Delay to Next Write (Note 8)
Byte Load Cycle
NOTES:
tDW
10
tBLC
0.15
100
7. tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device
requires to automatically complete the internal write operation.
8. tWPH and tDW are periodically sampled and not 100% tested.
WE Controlled Write Cycle
t
WC
ADDRESS
t
t
AH
AS
t
t
CS
CH
CE
OE
t
t
OEH
OES
t
WP
WE
t
DV
DATA IN
DATA OUT
DATA VALID
HIGH Z
t
t
DH
DS
FN8109.2
August 28, 2009
12
X28HC64
CE Controlled Write Cycle
t
WC
ADDRESS
t
t
AS
AH
t
CW
CE
OE
t
OES
t
OEH
t
t
t
CS
CH
WE
t
DV
DATA VALID
DATA IN
t
DS
DH
HIGH Z
DATA OUT
Page Write Cycle
OE
(NOTE 9)
CE
t
t
BLC
WP
WE
t
WPH
Address
(NOTE 10)
Last Byte
Byte n+2
I/O
Byte 0
Byte 1
Byte 2
Byte n
Byte n+1
t
WC
*For each successive write within the page write operation, A –A should be the same or
6
12
writes to an unknown address could occur.
NOTES:
9. Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch
data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation.
10. The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the
CE or WE controlled write cycle timing.
FN8109.2
August 28, 2009
13
X28HC64
DATA Polling Timing Diagram (Note 11)
ADDRESS
CE
A
A
A
n
n
n
WE
t
t
OEH
OES
OE
t
DW
D
= X
D
= X
OUT
I/O
7
D
= X
IN
OUT
t
WC
Toggle Bit Timing Diagram (Note 11)
CE
WE
t
OES
t
OEH
OE
t
DW
HIGH Z
I/O*
*
6
*
t
WC
* I/O beginning and ending state will vary, depending upon actual t
.
WC
6
NOTE:
11. Polling operations are by definition read cycles and are therefore subject to read cycle timings.
FN8109.2
August 28, 2009
14
X28HC64
Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07)
0.056 (1.42)
N32.45x55 (JEDEC MS-016AE ISSUE A)
PIN (1)
IDENTIFIER
0.004 (0.10)
C
32 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
0.042 (1.07)
0.048 (1.22)
0.050 (1.27) TP
ND
0.025 (0.64)
0.045 (1.14)
INCHES
MILLIMETERS
R
C
L
SYMBOL
MIN
MAX
MIN
3.18
MAX
3.55
NOTES
A
A1
D
0.125
0.060
0.485
0.447
0.188
0.585
0.547
0.238
0.140
0.095
0.495
0.453
0.223
0.595
0.553
0.273
-
1.53
2.41
-
D2/E2
D2/E2
12.32
11.36
4.78
12.57
11.50
5.66
-
D1
D2
E
3
C
L
E1
E
4, 5
14.86
13.90
6.05
15.11
14.04
6.93
-
NE
E1
E2
N
3
VIEW “A”
4, 5
28
7
28
7
6
0.015 (0.38)
MIN
ND
NE
7
7
A1
A
D1
D
9
9
SEATING
PLANE
Rev. 0 7/98
0.020 (0.51) MAX
3 PLCS
-C-
NOTES:
0.026 (0.66)
0.032 (0.81)
1. Controlling dimension: INCH. Converted millimeter dimen-
sions are not necessarily exact.
0.050 (1.27)
MIN
2. Dimensions and tolerancing per ANSI Y14.5M-1982.
3. Dimensions D1 and E1 do not include mold protrusions. Al-
lowable mold protrusion is 0.010 inch (0.25mm) per side.
Dimensions D1 and E1 include mold mismatch and are mea-
sured at the extreme material condition at the body parting
line.
0.013 (0.33)
0.021 (0.53)
0.025 (0.64)
MIN
(0.12)
0.005
M
A S - B S D S
-C-
4. To be measured at seating plane
contact point.
5. Centerline to be determined where center leads exit plastic
body.
VIEW “A” TYP.
6. “N” is the number of terminal positions.
7. ND denotes the number of leads on the two shorts sides of the
package, one of which contains pin #1. NE denotes the num-
ber of leads on the two long sides of the package.
FN8109.2
August 28, 2009
15
X28HC64
Small Outline Plastic Packages (SOIC)
M28.3 (JEDEC MS-013-AE ISSUE C)
N
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
0.25(0.010)
M
B M
H
AREA
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
MAX
2.65
0.30
0.51
0.32
18.10
7.60
NOTES
-B-
A
A1
B
C
D
E
e
0.0926
0.0040
0.013
0.1043
0.0118
0.0200
0.0125
-
-
1
2
3
L
9
SEATING PLANE
A
0.0091
0.6969
0.2914
-
0.7125 17.70
3
-A-
o
h x 45
D
0.2992
7.40
4
0.05 BSC
1.27 BSC
-
-C-
α
H
h
0.394
0.01
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
5
B
0.10(0.004)
L
0.016
6
0.25(0.010) M
C
A M B S
N
α
28
28
7
0o
8o
0o
8o
-
NOTES:
Rev. 0 12/93
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
FN8109.2
August 28, 2009
16
X28HC64
Dual-In-Line Plastic Packages (PDIP)
E28.6 (JEDEC MS-011-AB ISSUE B)
N
28 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INCHES
MILLIMETERS
INDEX
1
2
3
N/2
AREA
SYMBOL
MIN
MAX
0.250
-
MIN
-
MAX
6.35
-
NOTES
-B-
-C-
A
A1
A2
B
-
4
-A-
0.015
0.125
0.014
0.030
0.008
1.380
0.005
0.600
0.485
0.39
3.18
0.356
0.77
0.204
4
D
E
0.195
0.022
0.070
0.015
1.565
-
4.95
0.558
1.77
0.381
39.7
-
-
BASE
PLANE
A2
A
-
SEATING
PLANE
B1
C
8
L
C
L
-
D1
B1
eA
A1
A
D1
e
D
35.1
5
eC
C
B
D1
E
0.13
15.24
12.32
5
eB
0.010 (0.25) M
C
B S
0.625
0.580
15.87
14.73
6
NOTES:
E1
e
5
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
0.100 BSC
0.600 BSC
2.54 BSC
15.24 BSC
-
eA
eB
L
6
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
-
0.700
0.200
-
17.78
5.08
7
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
0.115
2.93
4
9
4. Dimensions A, A1 and L are measured with the package seated in
N
28
28
JEDEC seating plane gauge GS-3.
Rev. 1 12/00
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
eA
6. E and
ular to datum
7. eB and eC are measured at the lead tips with the leads unconstrained.
C must be zero or greater.
are measured with the leads constrained to be perpendic-
-C-
.
e
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8109.2
August 28, 2009
17
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