X3100V_技术文档

X3100, X3101

®

4 Cell/3 Cell

Data Sheet

January 3, 2008

FN8110.1

3 or 4 Cell Li-ion Battery Protection and

Monitor IC

Features

• Software Selectable Protection Levels and Variable

Protect Detection/Release Times

The X3100 is a protection and monitor IC for use in battery

packs consisting of 4 series Lithium-Ion battery cells. The

X3101 is designed to work in 3-cell applications. Both devices

provide internal over-charge, over-discharge, and over-

current protection circuitry, internal EEPROM memory, an

internal voltage regulator, and internal drive circuitry for

external FET devices that control cell charge, discharge, and

cell voltage balancing.

• Integrated FET Drive Circuitry

• Cell Voltage and Current Monitoring

• 0.5% Accurate Voltage Regulator

• Integrated 4k-bit EEPROM

• Flexible Power Management with 1µA Sleep Mode

• Cell Balancing Control

Over-charge, over-discharge, and over-current thresholds

reside in an internal EEPROM memory register and are

selected independently via software using a 3MHz SPI serial

interface. Detection and time-out delays can also be individually

varied using external capacitors.

• Pb-Free Available (RoHS Compliant)

Benefit

• Optimize protection for chosen cells to allow maximum

use of pack capacity

Using an internal analog multiplexer, the X3100 or X3101

allow battery parameters such as cell voltage and current

(using a sense resistor) to be monitored externally by a

separate microcontroller with A/D converter. Software on this

microcontroller implements gas gauge and cell balancing

functionality in software.

• Reduce component count and cost

• Simplify implementation of gas gauge

• Accurate voltage and current measurements

• Record battery history to optimize gas gauge, track pack

failures and monitor system use

The X3100 and X3101 contain a current sense amplifier.

Selectable gains of 10, 25, 80 and 160 allow an external

10-bit A/D converter to achieve better resolution than a more

expensive 14-bit converter.

• Reduce power to extend battery life

• Increase battery capacity and improve cycle life battery life

An internal 4k-bit EEPROM memory featuring IDLock^™

allows the designer to partition and “lock in” written battery

cell/pack data.

The X3100 and X3101 are each housed in a 28 Ld TSSOP

package.

Functional Diagram

RGC RGO

RGP

VCC

UVP/OCP

OVP/LMON

AS0

AS1

AS2

FET CONTROL

CIRCUITRY

5VDC

REGULATOR

VCELL1

CB1

ANALOG-

MUX

AO

VCELL2

CB2

OVERCHARGE

PROTECTION

SAMPLE RATE

TIMER

INTERNAL VOLTAGE

REGULATOR

POWER-ON RESET AND STATUS

OVERDISCHARGE

PROTECTION

SENSE

REGISTER

S0

4k-BIT

EEPROM

VCELL3

CB3

CIRCUITS

SPI

I/F

SCK

CS

SI

PROTECTION

CIRCUIT

TIMING CONTROL

AND

CONFIGURATION

REGISTER

CONTROL

REGISTER

OVERCURRENT

PROTECTION

AND

CURRENT

SENSE

VCELL4/VSS

CB4

CONFIGURATION

VSS

VCS1 VCS2

OVT UVT OCT

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

1

All other trademarks mentioned are the property of their respective owners.

X3100, X3101

Pinout

X3100, X3101

(28 LD TSSOP)

TOP VIEW

VCELL1

CB1

1

2

3

4

5

6

7

8

9

28 VCC

27 RGP

VCELL2

CB2

26

RGC

25 RGO

VCELL3

CB3

24 UVP/OCP

23 OVP/LMON

22 CS

VCELL4/VSS*

CB4

21 SCK

VSS

20

SO

VCS1 10

VCS2 11

OVT 12

UVT 13

OCT 14

19 SI

18 AS2

17 AS1

16 AS0

15 AO

*For X3101, Connect to GND

Ordering Information

PART

NUMBER*

PART

MARKING

V_CCLIMITS

TEMP. RANGE

PKG.

DWG. #

(V)

(°C)

PACKAGE

28 Ld TSSOP

X3100V28*

X3100V

6 to 24

-20 to +70

M28.173

X3100V28I

X3100V I

X3100VZ

28 Ld TSSOP

M28.173

X3100V28Z

(Note)

28 Ld TSSOP

(Pb-free)

X3101V28*

X3101V

6 to 24

-20 to +70

28 Ld TSSOP

M28.173

X3101V28Z

(Note)

X3101VZ

28 Ld TSSOP

(Pb-free)

**Add “-T1” or “T2” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin

plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are

MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

Pin Descriptions

NUMBER PIN NAME

BRIEF DESCRIPTION

1

2

VCELL1 Battery cell 1 voltage input. This pin is used to monitor the voltage of this battery cell internally.

The voltage of an individual cell can also be monitored externally at pin AO.

The X3100 monitors 4 battery cells. The X3101 monitors 3 battery cells.

CB1

Cell balancing FET control output 1. This output is used to switch an external FET in order to

perform cell voltage balancing control. This function can be used to adjust an individual cell voltage

(e.g. during cell charging). CB1 can be driven high (Vcc) or low (Vss) to switch the external FET

ON/OFF.

3

VCELL2 Battery cell 2 voltage. This pin is used to monitor the voltage of this battery cell internally. The voltage of an individual cell

can also be monitored externally at pin AO.

The X3100 monitors 4 battery cells. The X3101 monitors 3 battery cells.

FN8110.1

January 3, 2008

2

X3100, X3101

Pin Descriptions (Continued)

NUMBER PIN NAME

BRIEF DESCRIPTION

4

5

6

7

CB2

Cell balancing FET control output 2. These outputs are used to switch an external FETs in order to perform cell voltage

balancing control. This function can be used to adjust individual cell voltages (e.g. during cell charging). CB2 can be driven

high (Vcc) or low (Vss) to switch the external FET ON/OFF.

VCELL3 Battery cell 3 voltage. This pin is used to monitor the voltage of each battery cell internally. The

voltage of an individual cell can also be monitored externally at pin AO.

The X3100 monitors 4 battery cells. The X3101 monitors 3 battery cells.

CB3

Cell balancing FET control output 3. This output is used to switch an external FET in order to

perform cell voltage balancing control. This function can be used to adjust an individual cell voltage (e.g. during cell charging).

CB3 can be driven high (Vcc) or low (Vss) to switch the external FET ON/OFF.

VCELL4/ Battery cell 4 voltage (X3100) Ground (X3101). This pin is used to monitor the voltage of this battery cell internally. The

VSS

voltage of an individual cell can also be monitored externally at pin AO.

The X3100 monitors 4 battery cells. The X3101 monitors 3 battery cells. For the X3101 device connect the VCELL4/VSS pin

to ground.

8

CB4

Cell balancing FET control output 4. This output is used to switch an external FET in order to

perform cell voltage balancing control. This function can be used to adjust individual cell voltages

(e.g. during cell charging). CB4 can be driven high (Vcc) or low (Vss) to switch the external FET ON/OFF.

When using the X3101, the CB4 pin can be left unconnected, or the FET control can be used for other purposes.

9

VSS

Ground.

10

VCS1

Current sense voltage pin 1. A sense resistor (R_SENSE) is connected between VCS1 and VCS2 (Figure 1). R_SENSEhas a

resistance in the order of 20mΩ to 100mΩ, and is used to monitor current flowing through the battery terminals, and protect

against over-current conditions. The voltage at each end of R_SENSEcan also be monitored at pin AO.

11

VCS2

Current sense voltage pin 2. A sense resistor (R_SENSE) is connected between VCS1 and VCS2 (Figure 1). R_SENSEhas a

resistance in the order of 20mΩ to 100mΩ, and is used to monitor current flowing through the battery terminals, and protect

against over-current conditions. The voltage at each end of R_SENSEcan also be monitored at pin AO.

12

13

14

15

OVT

UVT

OCT

AO

Over-charge detect/release time input. This pin is used to control the delay time (T_OV) associated with the detection of an

over-charge condition (see section “Over-charge Protection” on page 14).

Over-discharge detect/release time input. This pin is used to control the delay times associated with the detection (T_UV

)

and release (T_UVR) of an over-discharge (under-voltage) condition (see section “Over-discharge Protection” on page 16).

Over-current detect/release time input. This pin is used to control the delay times associated with the detection (T_OC) and

release (T_OCR) of an over-current condition (see section “Over-Current Protection” on page 19).

Analog multiplexer output. The analog output pin is used to externally monitor various battery parameter voltages. The

voltages which can be monitored at AO (see section “Analog Multiplexer Selection” on page 21) are:

– Individual cell voltages

– Voltage across the current sense resistor (R_SENSE)^.This voltage is amplified with a gain set by the user in the control register

(see section “Current Monitor Function” on page 21.)

The analog select pins pins AS0 - AS2 select the desired voltage to be monitored on the AO pin.

16

17

18

19

20

AS0

AS1

AS2

SI

Analog output select pin 0. These pins select which voltage is to be multiplexed to the output AO (see section “Sleep Control

(SLP)” on page 11 and section “Current Monitor Function” on page 21)

Analog output select pin 1. These pins select which voltage is to be multiplexed to the output AO (see section “Sleep Control

(SLP)” on page 11 and section “Current Monitor Function” on page 21)

Analog output select pin 2. These pins select which voltage is to be multiplexed to the output AO (see section “Sleep Control

(SLP)” on page 11 and section “Current Monitor Function” on page 21)

Serial data input. SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the device are input

on this pin.

SO

Serial data output. SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked

out by the falling edge of the serial clock. While CS is HIGH, SO will be in a High Impedance state.

Note: SI and SO may be tied together to form one line (SI/SO). In this case, all serial data communication with the X3100 or

X3101 is undertaken over one I/O line. This is permitted ONLY if no simultaneous read/write operations occur.

21

22

SCK

CS

Serial data clock input. The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or

data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin change after the falling

edge of the clock input.

Chip select input pin. When CS is HIGH, the device is deselected and the SO output pin is at high impedance. CS LOW

enables the SPI serial bus.

FN8110.1

January 3, 2008

3

X3100, X3101

Pin Descriptions (Continued)

NUMBER PIN NAME

BRIEF DESCRIPTION

23

24

25

OVP/

LMON

Over-charge Voltage Protection output/Load Monitor output. This one pin performs two functions depending upon the

present mode of operation of the X3100 or X3101.

Over-charge Voltage Protection (OVP)

This pin controls the switching of the battery pack charge FET. This power FET is a P-channel device. As such, cell charge is

possible when OVP/LMON=V_SS, and cell charge is prohibited when OVP/LMO = V_CC. In this configuration the X3100 and

X3101 turn off the charge voltage when the cells reach the over-charge limit. This prevents damage to the battery cells due to

the application of charging voltage for an extended period of time (see section “Over-charge Protection” on page 14).

Load Monitor (LMON)

In Over-current Protection mode, a small test current (7.5µA typ.) is passed out of this pin to sense the load resistance. The

measured load resistance determines whether or not the X3100 or X3101 returns from an over-current protection mode (see

section “Over-Current Protection” on page 19).

UVP/

OCP

Over-discharge protection output/Over-current protection output. Pin UVP/OCP controls the battery cell discharge via

an external power FET. This P-channel FET allows cell discharge when UVP/OCP=Vss, and prevents cell discharge when

UVP/OCP=Vcc. The X3100 and X3101 turn the external power FET off when the X3100 or X3101 detects either:

Over-discharge Protection (UVP)

In this case, pin 24 is referred to as “Over-discharge (Under-Voltage) protection (UVP)” (see section “Over-discharge

Protection” on page 16). UVP/OCP turns off the FET to prevent damage to the battery cells by being discharged to

excessively low voltages.

Over-current protection (OCP)

In this case, pin 24 is referred to as “Over-current protection (OCP)” (see section “Over-Current Protection” on page 19).

UVP/OCP turns off the FET to prevent damage to the battery pack caused by excessive current drain (e.g. as in the case of

a surge current resulting from a stalled disk drive).

RGO

Voltage regulator output pin. This pin is an input that connects to the collector of an external PNP transistor. The voltage

at this pin is the regulated output voltage, but it also provides the feedback voltage for the regulator and the operating voltage

for the device.

26

27

RGC

RGP

Voltage regulator control pin. This pin connects to the base of an external PNP transistor and controls the transistor turn on.

Voltage regulator protection pin. This pin is an input that connects to the emitter of an external PNP transistor and an

external current limit resistor and provides a current limit voltage.

28

VCC

Power supply. This pin is provides the voltage for FET control, regulator operation, and wake-up

circuits.

In a typical application, the microcontroller is also

principles of operation

The X3100 and X3101 provide two distinct levels of

functionality and battery cell protection:

programmed to provide an SMBus interface along with the

Smart Battery System interface protocols. These additions

allow an X3100 or X3101 based module to adhere to the

latest industry battery pack standards.

First, in Normal mode, the device periodically checks each

cell for an overcharge and overdischarge state, while

continuously watching for a pack over-current condition. A

protection mode violation results from an over-charge, over-

discharge, or overcurrent state. The thresholds for these

states are selected by the user through software. When one

of these conditions occur, a Discharge FET or a Charge FET

or both FETs are turned off to protect the battery pack. In an

over-discharge condition, the X3100 and X3101 devices go

into a low power sleep mode to conserve battery power.

During sleep, the voltage regulator turns off, removing power

from the microcontroller to further reduce pack current.

Typical Application Circuit

The X3100 and X3101 have been designed to operate

correctly when used as connected in the Typical Application

Circuit (see Figure 1 on page 5).

The power MOSFET’s Q1 and Q2 are referred to as the

“Discharge FET” and “Charge FET,” respectively. Since

these FETs are p-channel devices, they will be ON when the

gates are at V_SS, and OFF when the gates are at V_CC. As

their names imply, the discharge FET is used to control cell

discharge, while the charge FET is used to control cell

charge. Diode D₁allows the battery cells to receive charge

even if the Discharge FET is OFF, while diode D₂allows the

cells to discharge even if the charge FET is OFF. D₁and D₂

are integral to the Power FETs. It should be noted that the

cells can neither charge nor discharge if both the charge FET

and discharge FET are OFF.

Second, in Monitor mode, a microcontroller with A/D converter

measures battery cell voltage and pack current via pin AO and

the X3100 or X3101 on-board MUX. The user can thus

implement protection, charge/discharge, cell balancing or gas

gauge software algorithms to suit the specific application and

characteristics of the cells used. While monitoring these

voltages, all protection circuits are on continuously.

FN8110.1

January 3, 2008

4

X3100, X3101

Power to the X3100 or X3101 is applied to pin VCC via

diodes D6 and D7. These diodes allow the device to be

powered by the Li-Ion battery cells in normal operating

conditions, and allow the device to be powered by an

external source (such as a charger) via pin P+ when the

battery cells are being charged. These diodes should have

sufficient current and voltage ratings to handle both cases of

battery cell charge and discharge.

The capacitors on the V_CELL1to V_CELL4inputs are used in a

first order low pass filter configuration, at the battery cell

voltage monitoring inputs (VCELL1 - VCELL4) of the X3100

or X3101. This filter is used to block any unwanted

interference signals from being inadvertently injected into

the monitor inputs. These interference signals may result

from:

• Transients created at battery contacts when the battery

pack is being connected/disconnected from the charger or

the host.

The operation of the voltage regulator is described in section

“Voltage Regulator” on page 22. This regulator provides a

5VDC±0.5% output. The capacitor (C1) connected from

RGO to ground provides some noise filtering on the RGO

output. The recommended value is 0.1µF or less. The value

chosen must allow V_RGOto decay to 0.1V in 170ms or less

when the X3100 or X3101 enter the sleep mode. If the decay

is slower than this, a resistor (R1) can be placed in parallel

with the capacitor.

• Electrostatic discharge (ESD) from something/someone

touching the battery contacts.

• Unfiltered noise that exists in the host device.

• RF signals which are induced into the battery pack from

the surrounding environment.

Such interference can cause the X3100 or X3101 to operate

in an unpredictable manner, or in extreme cases, damage

the device. As a guide, the capacitor should be in the order

of 0.01µF and the resistor, should be in the order of 10kΩ.

The capacitors should be of the ceramic type. In order to

minimize interference, PCB tracks should be made as short

and as wide as possible to reduce their impedance. The

battery cells should also be placed as close to the X3100 or

X3101 monitor inputs as possible.

During an initial turn-on period (T_PUR+ T_OC), V_RGOhas a

stable, regulated output in the range of 5VDC ± 10% (see

Figure ). The selection of the microcontroller should take this

into consideration. At the end of this turn on period, the

X3100 and X3101 “self-tunes” the output of the voltage

regulator to 5V+/-0.5%. As such, V_RGOcan be used as a

reference voltage for the A/D converter in the

microcontroller. Repeated power-up operations, consistently

re-apply the same “tuned” value for V_RGO

.

Resistors R_CBand the associated n-channel MOSFET’s (Q₆-

Q₉) are used for battery cell voltage balancing. The X3100

and X3101 provide internal drive circuitry which allows the

user to switch FETs Q₆- Q₉ON or OFF via the

Figure 1 shows a battery pack temperature sensor

implemented as a simple resistive voltage divider, utilizing a

thermistor (R_T) and resistor (R_T’). The voltage V_Tcan be fed

to the A/D input of a microcontroller and used to measure

and monitor the temperature of the battery cells. R_T’ should

be chosen with consideration of the dynamic resistance

range of R_Tas well as the input voltage range of the

microcontroller A/D input. An output of the microcontroller

can be used to turn on the thermistor divider to allow

periodic turn-on of the sensor. This reduces power

consumption since the resistor string is not always drawing

current.

microcontroller and SPI port (see section “Cell Voltage

Balance Control (CBC1-CBC4)” on page 12). When any of

the these FETs are switched ON, a current, limited by

resistor R_CB, flows across the particular battery cell. In doing

so, the user can control the voltage across each individual

battery cell. This is important when using Li-Ion battery cells

since imbalances in cell voltages can, in time, greatly reduce

the usable capacity of the battery pack. Cell voltage

balancing may be implemented in various ways, but is

usually performed towards the end of cell charging (“Top-of-

charge method”). Values for R_CBwill vary according to the

specific application.

Diode D3 is included to facilitate load monitoring in an Over-

current protection mode (see section “Over-Current

Protection” on page 19), while preventing the flow of current

into pin OVP/LMON during normal operation. The N-

Channel transistor turns off this function during the sleep

mode.

The internal 4kbit EEPROM memory can be used to store

the cell characteristics for implementing such functions as

gas gauging, battery pack history, charge/discharge cycles,

and minimum/maximum conditions. Battery pack

Resistor R_PUis connected across the gate and drain of the

charge FET (Q2). The discharge FET Q1 is turned off by the

X3100 or X3101, and hence the voltage at pin OVP/LMON

will be (at maximum) equal to the voltage of the battery

manufacturing data as well as serial number information can

also be stored in the EEPROM array. An SPI serial bus

provides the communication link to the EEPROM.

A current sense resistor (R_SENSE) is used to measure and

monitor the current flowing into/out of the battery terminals,

and is used to protect the pack from over-current conditions

(see section “Over-Current Protection” on page 19). R_SENSE

is also used to externally monitor current via a

terminal, minus one forward biased diode voltage drop (V_P+

-

V_D7). Since the drain of Q2 is connected to a higher potential

(V_P+) a pull-up resistor (R_PU) in the order of 1MΩ should be

used to ensure that the charge FET is completely turned

OFF when OVP/LMON = V_CC

.

FN8110.1

January 3, 2008

5

X3100, X3101

microcontroller (see section “Current Monitor Function” on

page 21).

FETs Q4 and Q5 may be required on general purpose I/Os

of the microcontroller that connect outside of the package. In

some cases, without FETs, pull-up resistors external to the

pack force a voltage on the V_CCpin of the microcontroller

during a pack sleep condition. This voltage can affect the

proper tuned voltage of the X3100/X3101 regulator. These

FETs should be turned-on by the microcontroller. (See

Figure 1.)

Power-on Sequence

Initial connection of the Li-Ion cells in the battery pack will

not normally power-up the battery pack. Instead, the X3100

or X3101 enters and remains in the SLEEP mode. To exit

the SLEEP mode, after the initial power-up sequence, or

following any other SLEEP MODE, a minimum of 16V

(X3100 V_SLR) or 12V (X3101 V_SLR) is applied to the VCC

pin, as would be the case during a battery charge condition.

(See Figure .)

When V_SLRis applied to VCC, the analog select pins (AS2 -

AS0) and the SPI communication pins (CS, CLK, SI, SO)

must be low, so the X3100 and X3101 power-up correctly

into the normal operating mode. This can be done by using a

power-on reset circuit.

When entering the normal operating mode, either from initial

power-up or following the SLEEP MODE, all bits in the

control register are zero. With UVPC and OVPC bits at zero,

the charge and discharge FETs are off. The microcontroller

must turn these on to activate the pack. The microcontroller

would typically check the voltage and current levels prior to

turning on the FETs via the SPI port. The software should

prevent turning on the FETs throughout an initial

measurement/calibration period. The duration of this period

is T_OV+ 200ms or T_UV+ 200ms, whichever is longer.

FN8110.1

January 3, 2008

6

X3100, X3101

Typical Application Circuit

FN8110.1

January 3, 2008

7

X3100, X3101

Power-up Timing (Initial Power-up or after

Sleep Mode)

T

PUR

V

SLR

VCC

0V

5V ±10% (STABLE AND REPEATABLE)

TUNED TO 5V ±0.5%

V

RGO

5V

V

RGO

0V

2ms (Typ.)

1

VOLTAGE REGULATOR OUTPUT STATUS

(INTERNAL SIGNAL)

VRGS

0

T

OC

1

1 = X3100/1 in Overcurrent Protection Mode

OVERCURRENT DETECTION STATUS

(INTERNAL SIGNAL)

0 = X3100/1 NOT in Overcurrent Protection Mode

OCDS

0

1

1 = X3100/1 in Overcurrent Protection Mode OR VRGO Not Yet Tuned

0 = X3100/1 NOT in Overcurrent Protection Mode AND VRGO Tuned

STATUS REGISTER BIT 0

VRGS+OCDS

0

T

+200ms

OV

1

STATUS REGISTER BIT 2

0

(SWCEN = 0)

CCES+OVDS

1 = V

0 = V

< V OR X3100/1 in Overcharge Protection Mode

CE

CELL

> V OR X3100/1 NOT in Overcharge Protection Mode

CE

CELL

1

STATUS REGISTER BIT 2

0

(SWCEN = 1)

OVDS

1 = X3100/1 in Overcharge Protection Mode

0 = X3100/1 NOT in Overcharge Protection Mode

AS2_AS0

SPI PORT

T

+ 200ms OR T + 200ms (WHICHEVER IS LONGER)

UV

OV

Charge, Discharge FETs can be

turned on here.

Any Read or Write Operation, except

turn-on of FETs can start here.

FN8110.1

January 3, 2008

8

X3100, X3101

Overdischarge Settings

Configuration Register

VUV1 and VUV0 control the cell over-discharge (under

voltage threshold) level. See section “Over-discharge

Protection” on page 16.

The X3100 and X3101 can be configured for specific user

requirements using the Configuration Register.

TABLE 1. CONFIGURATION REGISTER FUNCTIONALITY

TABLE 5. OVERDISCHARGE THRESHOLD SELECTION.

BIT(s)

0 to 5

6

NAME

–

FUNCTION

CONFIGURATION

REGISTER BITS

(don’t care)

OPERATION

SWCEN

Switch Cell Charge Enable threshold

function ON/OFF

VUV1

VUV0

X3100

X3101

0

V

_UV= 1.95V

V_UV= 2.25V

7

CELLN

Set the number of Li-ion battery cells

used (3 or 4)

(X3101 default)

0

1

0

1

_UV= 2.05V

V_UV= 2.35V

V_UV= 2.45V

V_UV= 2.55V

8 to 9

10 to11

12 to 13

VCE1-VCE0

VOC1-VOC0

VUV1-VUV0

Select Cell Charge Enable threshold

Select overcurrent threshold

V_UV= 2.15V

V_UV= 2.25V

Select overdischarge (under voltage)

threshold

(X3100 default)

14 to 15

VOV1-VOV0

Select overcharge voltage threshold

Overcurrent Settings

VOC1 and VOC0 control the pack over-current level. See

section “Over-Current Protection” on page 19.

TABLE 2. CONFIGURATION REGISTER—UPPER BYTE

15 14 13 12 11 10

9

8

TABLE 6. OVERCURRENT THRESHOLD VOLTAGE SELECTION

VOV1 VOV0 VUV1 VUV0 VOC1 VOC0 VCE1 VCE0

X3100 Default = 33H; X3101 Default = 03H.

CONFIGURATION REGISTER

BITS

VOC1

VOC0

OPERATION

TABLE 3. CONFIGURATION REGISTER—LOWER BYTE

0

1

0

1

0

1

V

_OC= 0.075V (Default)

7

6

5

4

3

2

1

0

V_OC= 0.100V

V_OC= 0.125V

V_OC= 0.150V

CELLN

SWCEN

x

X3100 Default = C0H; X3101 Default = 40H.

Overcharge Voltage Settings

Cell Charge Enable Settings

VOV1 and VOV0 control the cell over-charge level. See

section “Over-charge Protection” on page 14.

VCE1, VCE0 and SWCEN control the pack charge enable

function. SWCEN enables or disables a circuit that prevents

charging if the cells are at too low a voltage. VCE1 and VCE0

select the voltage that is recognized as too low. See section

“Sleep Mode” on page 16.

TABLE 4. OVERCHARGE VOLTAGE THRESHOLD SELECTION

CONFIGURATION REGISTER

BITS

TABLE 7. CELL CHARGE ENABLE FUNCTION

VOV1

VOV0

OPERATION (V)

CONFIGURATION

REGISTER BITS

0

1

0

1

0

1

V_OV= 4.20 (Default)

V

_OV= 4.25

SWCEN

OPERATION

Charge enable function: ON

Charge enable function: OFF

V_OV= 4.30

V_OV= 4.35

0

1

TABLE 8. CELL CHARGING THRESHOLD VOLTAGE

SELECTION

CONFIGURATION REGISTER

BITS

VCE1

VCE0

OPERATION

V_CE= 0.5V

V_CE= 0.80V

_CE= 1.10V

V_CE= 1.40V (Default)

0

1

0

1

0

1

V

FN8110.1

January 3, 2008

9

X3100, X3101

Cell Number Selection

Figure 1. Power-up of Configuration Register

The X3100 is designed to operate with four (4) Li-Ion battery

cells. The X3101 is designed to operate with three (3) Li-ion

battery cells. The CELLN bit of the configuration register

(Table 9) sets the number of cells recognized. For the

X3101, the value for CELLN should always be zero.

Configuration Register (SRAM)

Upper Byte

Lower Byte

Recall

Shadow EEPROM

1

Table 9. Selection of Number of Battery Cells

The configuration register is designed for unlimited

write operations to SRAM, and a minimum of

1,000,000 store operations to the EEPROM. Data

retention is specified to be greater than 100 years.

Configuration

Register Bit

CELLN

Operation

1

0

4 Li-Ion battery cells (X3100 default)

3 Li-Ion battery cells (X3100 or X3101)

It should be noted that the bits of the shadow

EEPROM are for the dedicated use of the configura-

tion register, and are NOT part of the general purpose

4kbit EEPROM array.

The configuration register consists of 16 bits of

NOVRAM memory (Table 2, Table 3). This memory

features a high-speed static RAM (SRAM) overlaid bit-

for-bit with non-volatile “Shadow” EEPROM. An auto-

matic array recall operation reloads the contents of the

shadow EEPROM into the SRAM configuration regis-

ter upon power-up (Figure 1).

The WCFIG command writes to the configuration reg-

ister, see Table 30 and section “X3100/X3101 SPI Serial

Communication” on page 23.

After writing to this register using a WCFIG instruction,

data will be stored only in the SRAM of the configura-

tion register. In order to store data in shadow

EEPROM,

a WREN instruction, followed by a

EEWRITE to any address of the 4kbit EEPROM mem-

ory array must occur, see Figure 2. This sequence ini-

tiates an internal nonvolatile write cycle which permits

data to be stored in the shadow EEPROM cells. It

must be noted that even though a EEWRITE is made

to the general purpose 4kbit EEPROM array, the value

and address to which it is written, is unimportant. If this

procedure is not followed, the configuration register

will power-up to the last previously stored values fol-

lowing a power-down sequence.

1. In the case that the X3100 or X3101 is configured for use with

only three Li-Ion battery cells (i.e. CELLN = 0), then VCELL4

(pin 7) MUST be tied to Vss (pin 9) to ensure correct operation.

FN8110.1

January 3, 2008

10

X3100, X3101

Figure 2. Writing to Configuration Register

Since the control register is volatile, data will be lost

following a power-down and power-up sequence.

The default value of the control register on initial

power-up or when exiting the SLEEP MODE is 00h

(for both upper and lower bytes respectively). The

functions that can be manipulated by the Control

Register are shown in Table 12.

Power-up

Data Recalled

from Shadow

EEPROM to SRAM

Configuration Register

(SRAM = Old Value)

Table 12. Control Register Functionality

WCFIG (New Value)

Bit(s) Name

Function

Configuration Register

(Sram = New Value)

0-4

5,6

7

–

(don’t care)

Reserved—write 0 to these locations.

0, 0

SLP Select sleep mode.

Store

(New Value)

in Shadow

EEPROM

8,9 CSG1, Select current sense voltage gain

CSG0

NO

YES

10

11

12

13

14

15

OVPC OVP control: switch pin OVP = V_CC/V_SS

UVPC UVP control: switch pin UVP = V_CC/V_SS

CBC1 CB1 control: switch pin CB1 = V_CC/V_SS

CBC2 CB2 control: switch pin CB2 = V_CC/V_SS

CBC3 CB3 control: switch pin CB3 = V_CC/V_SS

CBC4 CB4 control: switch pin CB4 = V_CC/V_SS

WREN

Write

Enable

Power-down-

power-on

Data Recalled

from Shadow

EEPROM to SRAM

EEWRITE

Write to

4kbit EEPROM

Configuration Register

(SRAM = old value)

Sleep Control (SLP)

Power-down

Power-up

Setting the SLP bit to ‘1’ forces the X3100 or X3101

into the sleep mode, if V < V

. See section “Sleep

CC

SLP

Data Recalled

from Shadow

Mode” on page 16.

EEPROM to SRAM

Table 13. Sleep Mode Selection

Configuration Register

(SRAM = New Value)

Control Register Bits

SLP

Operation

CONTROL REGISTER

0

1

Normal operation mode

The Control Register is realized as two bytes of vola-

tile RAM (Table 10, Table 11). This register is written

using the WCNTR instruction, see Table 30 and section

“X3100/X3101 SPI Serial Communication” on page 23.

Device enters Sleep mode

Table 10. Control Register—Upper Byte

15

14

13

12

11

10

9

8

CBC4 CBC3 CBC2 CBC1 UVPC OVPC CSG1 CSG0

Table 11. Control Register—Lower Byte

7

6

5

4

3

2

1

0

SLP

0

x

FN8110.1

January 3, 2008

11

X3100, X3101

Current Sense Gain (CSG1, CSG0)

Table 16. CB1—CB4 Control

These bits set the gain of the current sense amplifier.

These are x10, x25, x80 and x160. For more detail,

see section “Current Monitor Function” on page 21.

Control Register Bits

CBC4 CBC3 CBC2 CBC1

Operation

x

1

0

x

1

0

x

1

0

x

1

0

x

Set CB1 = V_CC(ON)

Set CB1=V_SS(OFF)

Set CB2 = V_CC(ON)

Set CB2 = V_SS(OFF)

Set CB3 = V_CC(ON)

Set CB3 = V_SS(OFF)

Set CB4 = V_CC(ON)

Set CB4 = V_SS(OFF)

Table 14. Current Sense Gain Control

Control Register Bits

CSG1

CSG0

Operation

0

1

0

1

0

1

Set current sense gain = x10

Set current sense gain = x25

Set current sense gain = x80

Set current sense gain = x160

CB1 - CB4 can be controlled by using the WCNTR In-

struction to set bits CBC1 - CBC4 in the control register

(Table 16).

Charge/Discharge Control (OVPC, UVPC)

The OVPC and UVPC bits allow control of cell charge

and discharge externally, via the SPI port. These bits

control the OVP/LMON and UVP/OCP pins, which in turn

control the external power FETs.

STATUS REGISTER

The status of the X3100 or X3101 can be verified by

using the RDSTAT command to read the contents of

the Status Register (Table 17).

Using P-channel power FETs ensures that the FET is

on when the pin voltage is low (Vss), and off when the

pin voltage is high (Vcc).

OVP/LMON and UVP/OCP can be controlled by using

the WCNTR Instruction to set bits OVPC and UVPC in

the Control register (See page 11).

Table 17. Status Register.

7

6

5

4

3

2

1

0

CCES+ UVDS VRGS+

OVDS OCDS

Table 15. UVP/OVP Control

Control Register Bits

The function of each bit in the status register is shown

in Table 18.

OVPC

UVPC

Operation

1

0

x

1

0

Pin OVP = V_SS(FET ON)

Pin OVP = V_CC(FET OFF)

Pin UVP = V_SS(FET ON)

Pin UVP = V_CC(FET OFF)

Bit 0 of the status register (VRGS+OCDS) actually

indicates the status of two conditions of the X3100 or

X3101. Voltage Regulator Status (VRGS) is an inter-

nally generated signal which indicates that the output

of the Voltage Regulator (VRGO) has reached an out-

put of 5VDC ± 0.5%. In this case, the voltage regulator

is said to be “tuned”. Before the signal VRGS goes low

(i.e. before the voltage regulator is tuned), the voltage

at the output of the regulator is nominally 5VDC ± 10%

(See section “Voltage Regulator” on page 22.) Over-

current Detection Status (OCDS) is another internally

generated signal which indicates whether or not the

X3100 or X3101 is in over-current protection mode.

It is possible to set/change the values of OVPC and

UVPC during a protection mode. A change in the state

of the pins OVP/LMON and UVP/OCP, however, will

not take place until the device has returned from the

protection mode.

Cell Voltage Balance Control (CBC1-CBC4)

This function can be used to adjust individual battery

cell voltage during charging. Pins CB1 - CB4 are used

to control external power switching devices. Cell volt-

age balancing is achieved via the SPI port.

Signals VRGS and OCDS are logically OR’ed together

(VRGS + OCDS) and written to bit 0 of the status reg-

ister (See Table 18, Table 17 and Figure ).

FN8110.1

January 3, 2008

12

X3100, X3101

Bit 1 of the status register simply indicates whether or

not the X3100 or X3101 is in over-discharge protec-

tion mode.

When the cell charge enable function is switched ON

(configuration bit SWCEN=0), the signals CCES and

OVDS are logically OR’ed (CCES+OVDS) and written

to bit 2 of the status register. If the cell charge enable

function is switched OFF (configuration bit

SWCEN=1), then bit 2 of the status register effectively

only represents information about the over-charge sta-

tus (OVDS) of the X3100 or X3101 (See Table 18,

Table 17 and Figure ).

Bit 2 of the status register (CCES+OVDS) indicates

the status of two conditions of the X3100 or X3101.

Cell Charge Enable Status (CCES) is an internally

generated signal which indicates the status of any cell

voltage (V

) with respect to the Cell Charge Enable

CELL

Voltage (V ). Over-charge Voltage Detection Status

CE

(OVDS) is an internally generated signal which indi-

cates whether or not the X3100 or X3101 is in over-

charge protection mode.

Table 18. Status Register Functionality.

Bit(s)

Name

Description

Case

Status

Interpretation

0

VRGS+OCDS Voltageregulator

status

-

1

V_RGOnot yet tuned (V_RGO= 5V ± 10%) OR

X3100/X3101 in over-current protection mode.

+

0

V_RGOtuned (V_RGO= 5V ± 0.5%) AND

X3100/X3101 NOT in over-current protection mode.

Over-current

detection status

1

2

UVDS

Over-discharge

detection status

-

1

0

1

X3100/X3101 in over-discharge protection mode

X3100/X3101 NOT in over-discharge protection mode

CCES+OVDS

Cell charge

enable status

SWCEN =0^†

V_CELL< V_CEOR

X3100/X3101 in over-charge protection mode

+

0

V_CELL> V_CEAND

X3100/X3101 NOT in over-charge protection mode

Over-charge

detection status

SWCEN =1^†

-

1

0

X3100/X3101 in over-charge protection mode

X3100/X3101 NOT in over-charge protection mode

Not used (always return zero)

3 - 7

-

†

Notes: This bit is set in the configuration register.

X3100/X3101 INTERNAL PROTECTION FUNCTIONS

Delay times for the detection of, and release from protec-

tion modes (T , T /T

can be individually varied by setting the values of

external capacitors connected to pins OVT, UVT, OCT.

, and T /T

respectively)

OV UV UVR

OC OCR

The X3100 and the X3101 provide periodic monitoring

(see section “Periodic Protection Monitoring” on page

13) for over-charge and over-discharge states and

continuous monitoring for an over-current state. It has

automatic shutdown when a protection mode is

encountered, as well as automatic return after the

device is released from a protection mode. When sam-

pling voltages through the analog port (Monitor Mode),

over-charge and over-discharge protection monitoring

is also performed on a continuous basis.

Periodic Protection Monitoring

In normal operation, the analog select pins are set

such that AS2 = L, AS1 = L, AS0 = L. In this mode the

X3100 and X3101 conserve power by sampling the

cells for over or over-discharge conditions.

In this state over-charge and over-discharge protec-

tion circuitry are usually off, but are periodically

switched on by the internal Protection Sample Rate

Timer (PSRT). The over-charge and over-discharge

protection circuitry is on for approximately 2ms in each

125ms period. Over-current monitoring is continuous.

In monitor mode (see page 21) over-charge and over-

discharge monitoring is also continuous.

Voltage thresholds for each of these protection modes

(V , V , and V respectively) can be individually

OV

UV

OC

selected via software and stored in an internal non-vol-

atile register. This feature allows the user to avoid the

restrictions of mask programmed voltage thresholds, and

is especially useful during prototype/evaluation design

stages or when cells with slightly different characteris-

tics are used in an existing design.

FN8110.1

January 3, 2008

13

X3100, X3101

Over-charge Protection

delay T

that results from a particular capacitance

OV

C

, can be approximated by the following linear

OV

The X3100 and X3101 monitor the voltage on each

equation:

battery cell (V

). If for any cell, V

> V

for a

CELL

OV

time exceeding T , then the Charge FET will be

OV

T

(s) ≈ 10 x C (µF).

OV

switched OFF (OVP/LMON = V ). The device has

CC

now entered Over-charge protection mode (Figure 3).

The status of the discharge FET (via pin UVP) will

remain unaffected.

Table 19. Typical over-charge detection time

Symbol

C

Delay

OV

T_OV

0.1µF

1.0s (Typ)

While in over-charge protection mode, it is possible to

change the state of the OVPC bit in the control register

such that OVP/LMON = Vss (Charge FET = ON).

Although the OVPC bit in the control register can be

changed, the change will not be seen at pin OVP until

the X3100 or X3101 returns from over-charge protec-

tion mode.

The device further continues to monitor the battery cell

voltages, and is released from over-charge protection

mode when V

X3100 or X3101 is released from over-charge protec-

tion mode, the charge FET is automatically switched

ON (OVP/LMON = V ). When the device returns from

< V

, for all cells. When the

CELL

OVR

SS

The over-charge detection delay T , is varied using a

over-charge protection mode, the status of the dis-

charge FET (pin UVP/OCP) remains unaffected.

OV

capacitor (C ) connected between pin OVT and

OV

GND. A typical delay time is shown in Table 10. The

The value of V

can be selected from the values

OV

shown in Table 4 by setting bits VOV1, VOV0. These

bits are set by using the WCFIG instruction to write to

the configuration register.

Figure 3. Over-charge Protection Mode—Event Diagram

Normal Operation Mode

Over-charge

Normal Operation Mode

Protection

Mode

V_OV

V_OVR

V_CELL

T_OV

V_CC

V_SS

OVP/LMON

Event

3

2

0

1

FN8110.1

January 3, 2008

14

X3100, X3101

Table 20. Over-charge Protection Mode—Event Diagram Description

Event

Event Description

[0,1)

—Discharge FET is ON (UVP/OCP = V_SS).

—Charge FET is ON (OVP/LMON = V_SS), and hence battery cells are permitted to receive charge.

—All cell voltages (V_CELL- V_CELL4) are below the over-charge voltage threshold (V_OV).

—The device is in normal operation mode (i.e. not in a protection mode).

[1]

—The voltage of one or more of the battery cells (V_CELL), exceeds V_OV

.

—The internal over-charge detection delay timer begins counting down.

—The device is still in normal operation mode

(1,2)

[2]

The internal over-charge detection delay timer continues counting for T_OVseconds.

The internal over-charge detection delay timer times out

AND

V_CELLstill exceeds V_OV.

—Therefore, the internal over-charge sense circuitry switches the charge FET OFF (OVP/LMON=Vcc).

—The device has now entered over-charge protection mode.

(2,3)

[3]

While in over-charge protection mode:

—The battery cells are permitted to discharge via the discharge FET, and diode D₂across the charge FET

—The X3100 or X3101 monitors the voltages V_CELL1- V_CELL4to determine whether or not they have all fallen

below the “Return from over-charge threshold” (V_OVR).

—(It is possible to change the status of UVP/OCP or OVP/LMON using the control register)

—All cell voltages fall below V_OVR—The device is now in normal operation mode.

—The X3100/X3101 automatically switches charge FET = ON (OVP/LMON = Vss)

—The status of the discharge FET remains unaffected.

—Charging of the battery cells can now resume.

FN8110.1

January 3, 2008

15

X3100, X3101

Over-discharge Protection

If V < V , for a time exceeding T , the cells are

said to be in a over-discharge state (Figure 4). In this

instance, the X3100 and X3101 automatically switch

the discharge FET OFF (UVP/OCP = Vcc), and then

enter sleep mode.

A sleep mode can be induced by the user, by setting

the SLP bit in the control register (Table 13) using the

WCNTR Instruction.

CELL

UV

In sleep mode, power to all internal circuitry is

switched off, minimizing the current drawn by the

device to 1µA (max). In this state, the discharge FET

and the charge FET are switched OFF

The over-discharge (under-voltage) value, V , can be

UV

(OVP/LMON=V and UVP/OCP=V ), and the 5VDC

CC

selected from the values shown in Table 5 by setting

bits VUV1, VUV0 in the configuration register. These

bits are set using the WCFIG command. Once in the

sleep mode, the following steps must occur before the

X3100 or X3101 allows the battery cells to discharge:

regulated output (V

) is 0V. Control of UVP/OCP

RGO

and OVP/LMON via bits UVPC and OVPC in the con-

trol register is also prohibited.

The device returns from sleep mode when V ≥ V

.

CC

SLR

(e.g. when the battery terminals are connected to a

battery charger). In this case, the X3100 or the X3101

restores the 5VDC regulated output (section “Voltage

Regulator” on page 22), and communication via the

SPI port resumes.

– The X3100 and X3101 must wake from sleep mode

(see section “Voltage Regulator” on page 22).

– The charge FET must be switched ON by the micro-

controller (OVP/LMON=V ), via the control register

SS

(see section “Control Register Functionality” on

page 11).

If the Cell Charge Enable function is enabled when

V

rises above V

, the X3100 and X3101 internally

CC

SLR

– All battery cells must satisfy the condition: V

>

CELL

verifies that the individual battery cell voltages (V

are larger than the cell charge enable voltage (^CV^E_C^L_E^L

before allowing the FETs to be turned on. The value

of V is selected by using the WCFIG command to

set bits VCE1–VCE0 in the configuration register.

)

V

for a time exceeding T

.

UVR

– The discharge FET must be switched ON by the

microcontroller (UVP/OCP=V ), via the control reg-

SS

CE

ister (see section “Control Register Functionality” on

page 11)

Only if the condition “V > V_CE” is satisfied can

CELL

The times T /T

are varied using a capacitor (C

)

UV UVR

UV

the state of charge and discharge FETs be changed

via the control register. Otherwise, if V < V for

connected between pin UVT and GND (Table 13). The

delay T that results from a particular capacitance C

CELL

CE

,

UV

any battery cell then both the Charge FET and the dis-

charge FET are OFF (OVP/LMON=Vcc and

can be approximated by the following linear equation:

T

(s) ≈ 10 x C (µF)

UVP/OCP=V ). Thus both charge and discharge of

the battery cells via terminals P+ / P- is prohibited .

UV

CC

1

T

(ms) ≈ 70 x C (µF)

UV

UVR

The cell charging threshold function can be switched

ON or OFF by the user, by setting bit SWCEN in the

configuration register (Table 7) using the WCFIG com-

mand. In the case that this cell charge enable function

Table 21. Typical Over-discharge Delay Times

Symbol

Description

C

Delay

UV

T_UV

Over-discharge

detection delay

0.1µF

1.0s (Typ)

is switched OFF, then V is effectively set to 0V.

CE

Neither the X3100 nor the X3101 enter sleep mode

(automatically or manually, by setting the SLP bit) if

T_UVR

Over-discharge

release time

0.1µF

7ms (Typ)

V

≥ V

. This is to ensure that the device does not

CC

SLR

go into a sleep mode while the battery cells are at a

high voltage (e.g. during cell charging).

Sleep Mode

The X3100 or X3101 can enter sleep mode in two

ways:

i) The device enters the over-discharge protection

mode.

ii) The user sends the device into sleep mode using the

control register.

1. In this case, charging of the battery may resume ONLY if the

cell charge enable function is switched OFF by setting bit

SWCEN

= 1 in the configuration register (See Above,

“CONFIGURATION REGISTER FUNCTIONALITY” on

page 9).

FN8110.1

January 3, 2008

16

X3100, X3101

Figure 4. Over-discharge Protection Mode—Event Diagram

V_SLR

VCC

Cell Charge Prohibited if SWCEN=0

AND V_CELL< V_CE

VCELL

0.7V

V_UVR

V_UV

T_UVR

V_CE

T_UV

V_CC

Note 3

Over-discharge Protection Mode

UVP/OCP

V_SS

The Longer of TOV+200ms OR TUV+200ms

V_CC

Note 1, 2

V_SS

5V

OVP/LMON

RGO

Sleep Mode

0V

Event

2

3

4

5

1

0

Note 1: If SWEN = 0 and V

< V , then OVP/LMON stays high and charging is prohibited.

CE

CELL

Note 2: OVP/LMON stays high until the microcontroller writes a “1” to the OVPC bit in the control register. This sets the signal low, which turns on the

charge FET. It cannot be turned on prior to this time.

Note 3: UVP/OCP stays high until the microcontroller writes a “1” to the UVPC bit in the control register. This sets the signal low, which turns on the

discharge FET. The FET cannot be turned on prior to this time.

Table 22. Over-discharge Protection Mode—Event Diagram Description

Event

Event Description

[0,1)

—Charge FET is ON (OVP/LMON = V_SS)

—Discharge FET is ON (UVP/OCP = V_SS), and hence battery cells are permitted to discharge.

—All cell voltages (VCELL₁- VCELL₄) are above the Over-discharge threshold voltage (V_UV).

—The device is in normal operation mode (i.e. not in a protection mode).

[1]

—The voltage of one or more of the battery cells (V_CELL), falls below V_UV.

—The internal over-discharge detection delay timer begins counting down.

—The device is still in normal operation mode

(1,2)

[2]

The internal over-discharge detection delay timer continues counting for T_UVseconds.

—The internal over-discharge detection delay timer times out, AND V_CELLis still below V_UV.

—The internal over-discharge sense circuitry switches the discharge FET OFF (UVP/OCP = Vcc).

—The charge FET is switched OFF (OVP/LMON = V_CC).

—The device has now entered over-discharge protection mode.

—At the same time, the device enters sleep mode (See section “Voltage Regulator” on page 22).

(2,3)

While device is in sleep (in over-discharge protection) mode:

—The power to ALL internal circuits is switched OFF limiting power consumption to less than 1µA.

—The output of the 5VDC voltage regulator (RGO) is 0V.

—Access to the X3100/X3101 via the SPI port is NOT possible.

FN8110.1

January 3, 2008

17

X3100, X3101

Table 22. Over-discharge Protection Mode—Event Diagram Description (Continued)

Event

Event Description

[3]

Return from sleep mode (but still in over-discharge protection mode):

—Vcc rises above the “Return from Sleep mode threshold Voltage” (V_SLR)—This would normally occur in the

case that the battery pack was connected to a charger. The X3100/X3101 is now powered via P+/P-, and

not the battery pack cells.

—Power is returned to ALL internal circuitry

—5VDC output is returned to the regulator output (RGO).

—Access is enabled to the X3100/X3101 via the SPI port.

—The status of the discharge FET remains OFF (It is possible to change the status of UVPC in the control

register, although it will have no effect at this time).

(3,4)

If the cell charge enable

function is switched ON

—The X3100/X3101 initiates a reset operation that takes the longer of

_{OV +}200ms or T_UV+ 200ms to complete. Do not write to the FET control

T

AND V_CELL> V_CE

bits during this time.

—The charge FET is switched On (OVP/LMON = Vss) by the microcontroller by

writing a “1” to the OVPC bit in the control register.

—The battery cells now receive charge via the charge FET and diode D1

across the discharge FET (which is OFF).

OR

Charge enable function is

switched OFF

—The X3100/X3101 monitors the V_CELLvoltage to determine whether or not it

has risen above V_UVR

.

If the cell charge enable

function is switched ON

—Charge/discharge of the battery cells via P+ is no longer permitted (Charge

FET and discharge FET are held OFF).

—(Charging may re-commence only when the Cell Charge Enable function is

switched OFF - See Sections: “Configuration Register” page 4, and “Sleep

mode” page 17.)

AND

V_CELL< V_CE

[4]

(4,5)

[5]

—The voltage of all of the battery cells (V_CELL), have risen above V_UVR

—The internal Over-discharge release timer begins counting down.

—The X3100/X3101 is still in over-discharge protection mode.

.

—The internal over-discharge release timer continues counting for t_UVRseconds.

—The X3100/X3101 should be in monitor mode (AS2:AS0 not all low) for recovery time based on t_UVR. Other-

wise recovery is based on two successive samples about 120ms apart.

—The internal over-discharge release timer times out, AND V_CELLis still above V_UVR.

—The device returns from over-discharge protection mode, and is now in normal operation mode.

—The Charger voltage can now drop below VSLR and the X3100/X3101 will not go back to sleep.

—The discharge FET is can now be switched ON (UVP/OCP = V_SS) by the microcontroller by writing a “1” to

the UVPC bit of the control register.

—The status of the charge FET remains unaffected (ON)

—The battery cells continue to receive charge via the charge FET and discharge FET (both ON).

FN8110.1

January 3, 2008

18

X3100, X3101

Over-Current Protection

If the load resistance > R_OCR(I

= 0µA) for a time

LMON

exceeding T

, then the X3100 or X3101 is released

OCR

In addition to monitoring the battery cell voltages, the

X3100 and X3101 continually monitor the voltage

from over-current protection mode. The discharge FET

is then automatically switched ON (UVP/OCP = Vss)

by the X3100 or X3101, unless the status of UVP/OCP

has been changed in control register (by manipulating

bit UVPC) during the over-current protection mode.

VCS (VCS - VCS ) across the current sense resis-

21

2

1

tor (R

). If VCS > V

for a time exceeding

SENSE

21

OC

T

, then the device enters over-current protection

OC

mode (Figure 7). In this mode, the X3100 and X3101

automatically switch the discharge FET OFF

(UVP/OCP = Vcc) and hence prevent current from

flowing through the terminals P+ and P-.

T

/T

are varied using a capacitor (C ) con-

OC OCR OC

nected between pin OCT and VSS. A list of typical

delay times is shown in Table 23. Note that the value

C

should be larger than 1nF.

OC

Figure 5. Over-Current Protection

The delay T

and T

that results from a particular

OCR

OC

capacitance C

ing equations:

can be approximated by the follow-

OC

P+

I_LMON

Q2

D1

T

(ms) ≈ 10,000 x C (µF)

OC

V_RGO

R_OCR

Q10

T

(ms) ≈ 10,000 x C (µF)

OC

OCR

(Load)

OVP/LMON

Table 23. Typical Over-Current Delay Times

X3100/X3101

Symbol

Description

C

Delay

OC

FET Control

Circuitry

T_OC

Over-current

detection delay

0.001µF

10ms (Typ)

T_OCR

Over-current

release time

0.001µF

10ms (Typ)

VSS

VCS1

VCS2

P-

The value of V

can be selected from the values

OC

R_SENSE

shown in Table 6, by setting bits VOC1, VOC0 in the

configuration register using the WCFIG command.

The 5VDC voltage regulator output (V

active during an over-current protection mode.

) is always

RGO

Note: If the Charge FET is turned off, due to an over-

charge condition or by direct command from the micro-

controller, the cells are not in an undervoltage

condition and the pack has a load, then excessive cur-

rent may flow through Q10 and diode D1. To eliminate

this effect, the gate of Q10 can be turned off by the

microcontroller through an unused X3101 cell balance

output, or directly from a microcontroller port instead of

Once the device enters over-current protection mode,

the X3100 and X3101 begin a load monitor state. In

the load monitor state, a small current (I

typ.) is passed out of pin OVP/LMON in order to deter-

mine the load resistance. The load resistance is the

impedance seen looking out of pin OVP/LMON,

between terminal P+ and pin VSS (See Figure 5.)

= 7.5µA

LMON

connecting to V

.

RGO

FN8110.1

January 3, 2008

19

X3100, X3101

Figure 6. Over-Current Protection Mode—Event Diagram

Over-Current Protection Mode

Normal Operation Mode

B+

P+

P+ = (RLOAD+RSENSE) x ILMON

V_OC

Voc

V_SS

VCS₂

T_OCR

T_OC

V_CC

V_SS

UVP/OCP

Event

4

0

3

1

2

Table 24. Over-Current Protection Mode—Event Diagram Description

Event

Event Description

[0,1)

—Discharge FET is ON (OCP = Vss). Battery cells are permitted to discharge.

—VCS₂₁(VCS₂- VCS₁) is less than the over-current threshold voltage (V_OC).

—The device is in normal operation mode (i.e. not in a protection mode).

[1]

—Excessive current flows through the battery terminals P+, dropping the voltage. (See Figure 6.).

—The positive battery terminal voltage (P+) falls, and VCS₂₁exceeds V_OC

—The internal over-current detection delay timer begins counting down.

—The device is still in Normal Operation Mode

.

(1,2)

[2]

The internal Over-current detection delay timer continues counting for T_OCseconds.

—The internal over-current detection delay timer times out, AND VCS₂₁is still above V_OC.

—The internal over-current sense circuitry switches the discharge FET OFF (UVP/OCP = Vcc).

—The device now begins a load monitor state by passing a small test current (I_LMON= 7.5µA) out of pin

OVP/LMON. This senses if an over-current condition (i.e. if the load resistance < R_OCR) still exists across

P+/P-.

—The device has now entered over-current protection mode.

—It is possible to change the status of UVPC and OVPC in the control register, although the status of pins

UVP/OCP and OVP/LMON will not change until the device has returned from over-current protection mode.

(2,3)

—The X3100/X3101 now continuously monitors the load resistance to detect whether or not an over-

current condition is still present across the battery terminals P+/P-.

FN8110.1

January 3, 2008

20

X3100, X3101

Table 24. Over-Current Protection Mode—Event Diagram Description (Continued)

Event

Event Description

[3]

—The device detects the load resistance has risen above R_OCR

—Voltages P+ and VCS₂₁return to their normal levels.

.

—The test current from pin OVP/LMON is stopped (I_LMON= 0µA)

—The device has now returned from the load monitor state

—The internal over-current release time timer begins counting down.

—Device is still in over-current protection mode.

(3,4)

[4]

The internal over-current release timer continues counting for T_OCRseconds.

—The internal over-current release timer times out, and VCS₂₁is still below V_OC.

—The device returns from over-current protection mode, and is now in normal operation mode.

—The discharge FET is automatically switched ON (UVP/OCP = Vss)—unless the status of UVPC has been

changed in the control register during the over-current protection mode.

—The status of the charge FET remains unaffected.

—Discharge of the battery cells is once again possible.

MONITOR MODE

Since the value of the sense resistor (R

) is small

SENSE

(typically in the order of tens of mΩ), and since the

Analog Multiplexer Selection

resolution of various A/D converters may vary, the

voltage across R

internally with a gain of between 10 and 160, and out-

put to pin AO (Figure 7).

(VCS and VCS ) is amplified

SENSE

1 2

The X3100 and X3101 can be used to externally monitor

individual battery cell voltages, and battery current. Each

quantity can be monitored at the analog output pin (AO),

and is selected using the analog select (AS0 - AS2) pins

(Table 25). Also, see Figure 7.

Figure 7. X3100/X3101 Monitor Circuit

Table 25. AO Selection Map

Cell 1 Voltage

Cell 2 Voltage

AS2 AS1 AS0

AO output

Voltage

Level

(1)

L

H

L

V_SS

Cell 3 Voltage

Shifters

AS0

AS1

AS2

Cell 4 Voltage

VCELL₁- VCELL₂(VCELL₁₂

VCELL₂- VCELL₃(VCELL₂₃

VCELL₃- VCELL₄(VCELL₃₄

)

L

H

L

AO

L

H

L

2.5V

OP1

+

R2

H

VCELL₄- Vss (VCELL₄)

(2)

L

H

L

VCS₁- VCS₂(VCS₁₂)

-

R2

R1

(2)

H

VCS2 - VCS₁(VCS₂₁

V_SS

)

S0

R1

H

SCL

CS

SI

Config

Register

Gain

Setting

SPI

I/F

Notes: (1) This is the normal state of the X3100 or X3101. While

in this state Over-charge and Over-discharge Protec-

tion conditions are periodically monitored (See “Peri-

odic Protection Monitoring” on page 13.)

CSG1CSG0

(2) VCS₁, VCS₂are read at AO with respect to a DC bias

voltage of 2.5V (See section “Current Monitor Func-

tion” on page 21).

Cross-Bar

Switch

Over-Current

Protection

X3100/X3101

Current Monitor Function

VCS₂

R_SENSE

VCS₁

The voltages monitored at pins VCS and VCS can be

used to calculate current flowing through the battery

terminals, using an off-board microcontroller with an A/D.

1

2

P-

FN8110.1

January 3, 2008

21

X3100, X3101

The internal gain of the X3100 or X3101 current sense

The maximum current that can flow from the voltage

regulator (I ) is controlled by the current limiting

voltage amplifier can be selected by using the WCNTR

Instruction to set bits CSG1 and CSG0 in the control

register (Table 14). The CSG1 and CSG0 bits select

one of four input resistors to Op Amp OP1. The feed-

back resistors remain constant. This ratio of input to

feedback resistors determines the gain. Putting exter-

nal resistors in series with the inputs reduces the gain of

the amplifier.

LMT

resistor (R

) connected between RGP and VCC.

LMT

When the voltage across VCC and RGP reaches a

nominal 2.5V (i.e. the threshold voltage for the FET), Q2

switches ON, shorting VCC to the base of Q1. Since

the base voltage of Q1 is now higher than the emitter

voltage, Q1 switches OFF, and hence the supply current

goes to zero.

VCS1 and VCS2 are read at AO with respect to a DC

bias voltage of 2.5V. Therefore, the voltage range of

Typical values for R

27. In order to protect the voltage regulator circuitry

and I

are shown in Table

LMT

VCS and VCS changes depending upon the direc-

tion of current flow (i.e. battery cells are in Charge or

Discharge—Table 21).

from damage in case of a short-circuit, R

should always be used.

≥ 10Ω

12

21

LMT

Table 27. Typical Values for R

and I

LMT

Table 26. AO Voltage Range for VCS₁₂and VCS₂₁

R

Voltage Regulator Current Limit (I

250mA ± 50% (Typical)

)

LMT

AO

Cell State

Charge

AO Voltage Range

2.5V ≤ AO ≤ 5.0V

0V ≤ AO ≤ 2.5V

2.5V ≤ AO ≤ 5.0V

10Ω

25Ω

50Ω

VCS₁₂

VCS₂₁

100mA ± 50% (Typical)

Discharge

Charge

50mA ± 50% (Typical)

When choosing the value of R

, the drive limitations

Discharge

LMT

of the PNP transistor used should also be taken into

consideration. The transistor should have a gain of at

least 100 to support an output current of 250mA.

By calculating the difference of VCS and VCS the

12

21

offset voltage of the internal op-amp circuitry is can-

celled. This allows for the accurate calculation of cur-

rent flow into and out of the battery cells.

Figure 8. Voltage Regulator Operation

Pack current is calculated using the following formula:

VCC

Un-Regulated

To Internal Voltage

Regulating Circuitry

Voltage

(VCS – VCS

)

21

12

Input

R_LMT

Pack Current = ---------------------------------------------------------------------------------------------------------

(2)(gain setting)(current sense resistor)

X3100/X3101

RGP

RGC

Tuning

VOLTAGE REGULATOR

Q2

I_LMT

The X3100 and X3101 are able to supply peripheral

devices with a regulated 5VDC±0.5% output at pin

RGO. The voltage regulator should be configured

externally as shown in Figure 8.

5VDC

Precision

+

Voltage

_

Q1

Reference

OP1

The non-inverting input of OP1 is fed with a high preci-

sion 5VDC supply. The voltage at the output of the

Regulated

5VDC Output

voltage regulator (V

) is compared to this 5V refer-

RGO

ence via the inverting input of OP1. The output of OP1

in turn drives the regulator pnp transistor (Q1). The

negative feedback at the regulator output maintains

the voltage at 5VDC±0.5% (including ripple) despite

changes in load, and differences in regulator transistors.

V_RGO

0.1

µF

4KBIT EEPROM MEMORY

The X3100 and X3101 contain a CMOS 4k-bit serial

EEPROM, internally organized as 512 x 8 bits. This

memory is accessible via the SPI port, and features

the IDLock function.

When power is applied to pin VCC of the X3100 or

X3101, V

is regulated to 5VDC±10% for a nominal

RGO

time of T +2ms. During this time period, V

is

OC

RGO

“tuned” to attain a final value of 5VDC±0.5% (Figure ).

FN8110.1

January 3, 2008

22

X3100, X3101

The 4kbit EEPROM array can be accessed by the SPI

The IDLock protection byte contains the IDLock bits

IDL2-IDL0, which defines the particular partition to be

locked (Table 28). The rest of the bits [7:3] are unused

and must be written as zeroes. Bringing CS HIGH

after the two byte IDLock instruction initiates a nonvola-

tile write to the status register. Writing more than one

byte to the status register will overwrite the previously

written IDLock byte.

port at any time, even during a protection mode, except

during sleep mode. After power is applied to VCC of the

X3100 or X3101, EEREAD and EEWRITE Instructions

can be executed only after times t

(power-up to

PUR

read time) and t

tively.

(power-up to write time) respec-

PUW

IDLock is a programmable locking mechanism which

allows the user to lock data in different portions of the

EEPROM memory space, ranging from as little as one

page to as much as 1/2 of the total array. This is useful

for storing information such as battery pack serial

number, manufacturing codes, battery cell chemistry

data, or cell characteristics.

Once an IDLock instruction has been completed, that

IDLock setup is held in a nonvolatile IDLock Register

(Table 29) until the next IDLock instruction is issued. The

sections of the memory array that are IDLocked can be

read but not written until IDLock is removed or changed.

Table 29. IDLock Register

EEPROM Write Enable Latch

7

6

5

4

3

2

1

0

The X3100 and X3101 contain an EEPROM “Write

Enable” latch. This latch must be SET before a write to

EEPROM operation is initiated. The WREN instruction

will set the latch and the WRDI instruction will reset the

latch (Figure 9). This latch is automatically reset upon a

power-up condition and after the completion of a byte or

page write cycle.

0

IDL2 IDL1 IDL0

Note: Bits [7:3] specified to be “0’s”

X3100/X3101 SPI SERIAL COMMUNICATION

The X3100 and X3101 are designed to interface

directly with the synchronous Serial Peripheral Inter-

face (SPI) of many popular microcontroller families.

This interface uses four signals, CS, SCK, SI and SO.

The signal CS when low, enables communications

with the device. The SI pin carries the input signal and

SO provides the output signal. SCK clocks data in or

out. The X3100 and X3101 operate in SPI mode 0

which requires SCK to be normally low when not

transferring data. It also specifies that the rising edge

of SCK clocks data into the device, while the falling

edge of SCK clocks data out.

IDLock Memory

Intersil’s IDLock memory provides a flexible mecha-

nism to store and lock battery cell/pack information.

There are seven distinct IDLock memory areas within

the array which vary in size from one page to as much

as half of the entire array.

Prior to any attempt to perform an IDLock operation,

the WREN instruction must first be issued. This

instruction sets the “Write Enable” latch and allows the

part to respond to an IDLock sequence. The EEPROM

memory may then be IDLocked by writing the SET IDL

instruction (Table 30 and Figure 17), followed by the

IDLock protection byte.

This SPI port is used to set the various internal regis-

ters, write to the EEPROM array, and select various

device functions.

The X3100 and X3101 contain an 8-bit instruction

register. It is accessed by clocking data into the SI

input. CS must be LOW during the entire operation.

Table 30 contains a list of the instructions and their

opcodes. All instructions, addresses and data are

transferred MSB first.

Table 28. IDLock Partition Byte Definition

IDLock Protection EEPROM Memory Address

Bytes

IDLocked

0000 0000

0000 0001

0000 0010

0000 0011

0000 0100

0000 0101

0000 0110

0000 0111

None

000h - 07Fh

080h - 0FFh

100h - 17Fh

180h - 1FFh

000h - 0FFh

000h - 00Fh

1F0h - 1FFh

Data input is sampled on the first rising edge of SCK

after CS goes LOW. SCK is static, allowing the user to

stop the clock, and then start it again to resume opera-

tions where left off.

FN8110.1

January 3, 2008

23

X3100, X3101

Table 30. X3100/X3101 Instruction Set

Instruction

Name

Instruction

Format*

Description

WREN

WRDI

0000 0110

0000 0100

0000 0010

0000 0101

0000 0011

0000 1001

Set the write enable latch (write enable operation)—Figure 9

Reset the write enable latch (write disable operation)—Figure 9

EEWRITE

EEREAD STAT

EEREAD

WCFIG

Write command followed by address/data (4kbit EEPROM)—Figure 10, Figure 11

Reads IDLock settings & status of EEPROM EEWRITE instruction—Figure 12

Read operation followed by address (for 4kbit EEPROM)—Figure 13

Write to configuration register followed by two bytes of data—Figure 2, Figure 14.

Data stored in SRAM only and will power-up to previous settings—Figure 1

WCNTR

RDSTAT

SET IDL

0000 1010

0000 1011

0000 0001

Write to control register, followed by two bytes of data—Figure 15

Read contents of status register—Figure 16

Set EEPROM ID lock partition followed by partition byte—Figure 17

*Instructions have the MSB in leftmost position and are transferred MSB first.

Write Enable/Write Disable (WREN/WRDI)

the write operation to proceed. The WRDI command

resets the internal latch if the system decides to abort

a write operation. See Figure 9.

Any write to a nonvolatile array or register, requires

the WREN command be sent prior to the write com-

mand. This command sets an internal latch allowing

Figure 9. EEPROM Write Enable Latch (WREN/WRDI) Operation Sequence

CS

0

1

2

3

4

5

6

7

WREN

SCK

Instruction

(1 Byte)

SI

High Impedance

WRDI

SO

FN8110.1

January 3, 2008

24

X3100, X3101

EEPROM Write Sequence (EEWRITE)

For a byte or page write operation to be completed,

CS can only be brought HIGH after bit 0 of the last

data byte to be written is clocked in. If it is brought

HIGH at any other time, the write operation will not be

completed. Refer to Figure 10 and Figure 11 for

detailed illustration of the write sequences and time

frames in which CS going HIGH are valid.

Prior to any attempt to write data into the EEPROM of

the X3100 or X3101, the “Write Enable” latch must first

be set by issuing the WREN instruction (See Table 30

and Figure 9). CS is first taken LOW. Then the WREN

instruction is clocked into the X3100 or X3101. After all

eight bits of the instruction are transmitted, CS must

then be taken HIGH. If the user continues the write

operation without taking CS HIGH after issuing the

WREN instruction, the write operation will be ignored.

EEPROM Read Status Operation (EEREAD STAT)

If there is not a nonvolatile write in progress, the

EEREAD STAT instruction returns the IDLock byte

from the IDLock register which contains the IDLock

bits IDL2-IDL0 (Table 29). The IDLock bits define the

IDLock condition (Table 28). The other bits are

reserved and will return ‘0’ when read.

To write data to the EEPROM memory array, the user

issues the EEWRITE instruction, followed by the 16 bit

address and the data to be written. Only the last 9 bits

of the address are used and bits [15:9] are specified to

be zeroes. This is minimally a thirty-two clock opera-

tion. CS must go LOW and remain LOW for the dura-

tion of the operation. The host may continue to write

up to 16 bytes of data to the X3100 or X3101. The only

restriction is the 16 bytes must reside on the same

page. If the address counter reaches the end of the

page and the clock continues, the counter will “roll

over” to the first address of the page and overwrite any

data that may have been previously written.

If a nonvolatile write to the EEPROM (i.e. EEWRITE

instruction) is in progress, the EEREAD STAT returns

a HIGH on SO. When the nonvolatile write cycle in

the EEPROM is completed, the status register data is

read out.

Clocking SCK is valid during a nonvolatile write in

progress, but is not necessary. If the SCK line is

clocked, the pointer to the status register is also

clocked, even though the SO pin shows the status of

the nonvolatile write operation (See Figure 12).

Figure 10. EEPROM Byte Write (EEWRITE) Operation Sequence

CS

20 21 22 23 24 25 26 27 28 29 30 31

0

1

2

3

4

5

6

7

8

9

SCK

SI

EEWRITE Instruction

(1 Byte)

Byte Address (2 Byte)

15 14

Data Byte

3

2

1

0

7

6

5

4

3

2

1

0

High Impedance

SO

FN8110.1

January 3, 2008

25

X3100, X3101

Figure 11. EEPROM Page Write (EEWRITE) Operation Sequence

CS

20 21 22 23 24 25 26 27 28 29 30 31

0

1

2

3

4

5

6

7

8

9

10

SCK

SI

EEWRITE

Instruction

Byte Address

(2 Byte)

Data Byte 1

15 14 13

3

2

1

0

7

6

5

4

3

2

1

0

CS

SCK

SI

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

Data Byte 2

Data Byte 3

Data Byte 16

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

6

5

4

3

2

1

0

Figure 12. EEPROM Read Status (EEREAD STAT) Operation Sequence

CS

0

1

2

3

4

5

6

7

...

SCK

SI

EEREAD STAT

Instruction

Nonvolatile EEWRITE in Progress

I

D

L

1

D

L

0

SO

L

2

SO High During

Nonvolatile

EEWRITE Cycle

SO=Status Reg Bit

When No Nonvolatile

EEWRITE Cycle

FN8110.1

January 3, 2008

26

X3100, X3101

EEPROM Read Sequence (EEREAD)

memory at the next address can be read sequentially

by continuing to provide clock pulses. The address is

automatically incremented to the next higher address

after each byte of data is shifted out. When the highest

address is reached (01FFh), the address counter rolls

over to address 0000h, allowing the read cycle to be

continued indefinitely. The read operation is terminated

by taking CS HIGH. Refer to the EEPROM Read

(EEREAD) operation sequence illustrated in Figure 13.

When reading from the X3100 or X3101 EEPROM

memory, CS is first pulled LOW to select the device.

The 8-bit EEREAD instruction is transmitted to the

X3100 or X3101, followed by the 16-bit address, of

which the last 9 bits are used (bits [15:9] specified to be

zeroes). After the EEREAD opcode and address are

sent, the data stored in the memory at the selected

address is shifted out on the SO line. The data stored in

Figure 13. EEPROM (EEREAD) Read Operation Sequence

CS

20 21 22 23 24 25 26 27 28 29 30 31

0

1

2

3

4

5

6

7

8

9

SCK

SI

EEREAD Instruction

(1 Byte)

Byte Address (2 Byte)

Data Out

3

2

1

0

15 14

High Impedance

7

6

5

4

3

2

1

0

SO

FN8110.1

January 3, 2008

27

X3100, X3101

Write Configuration Register (WCFIG)

Write Control Register (WCNTRL)

The Write Configuration Register (WCFIG) instruc-

tion updates the static part of the Configuration Reg-

ister. These new values take effect immediately, for

example writing a new Over-discharge voltage limit.

However, to make these changes permanent, so they

remain if the cell voltages are removed, an EEWRITE

operation to the EEPROM array is required following

the WCFIG command. This command is shown in

Figure 14.

The Write Control Register (WCNTRL) instruction

updates the contents of the volatile Control Register.

This command sets the status of the FET control

pins, the cell balancing outputs, the current sense

gain and external entry to the sleep mode. Since this

instruction controls a volatile register, no other

commands are required and there is no delay time

needed after the instruction, before subsequent

commands. The operation of the WCNTRL command

is shown in Figure 15.

Figure 14. Write Configuration Register (WCFIG) Operation Sequence

CS

20 21 22 23

0

1

2

3

4

5

6

7

8

9

SCK

SI

Configuration

Register Data

WCFIG Instruction

(1 BYTE)

3

2

1

0

15 14

(2 BYTE)

High Impedance

SO

Figure 15. Write Control Register (WCNTR) Operation Sequence

CS

18 19 20 21 22 23

0

1

2

3

4

5

6

7

8

9

SCK

SI

Control

Register Data

WCNTR Instruction

(1 Byte)

1

0

5

4

3

2

15 14

(2 Byte)

High Impedance

SO

Control

Bits

Old Control Bits

New Control Bits

FN8110.1

January 3, 2008

28

X3100, X3101

Read Status Register (RDSTAT)

Set ID Lock (SET IDL)

The Read Status Register (RDSTAT) command

returns the status of the X3100 or X3101. The Status

Register contains three bits that indicate whether the

voltage regulator is stabilized, and if there are any pro-

tection failure conditions. The operation of the

RDSTAT instruction is shown in Figure 16.

The contents of the EEPROM memory array in the

X3100 or X3101 can be locked in one of eight configu-

rations using the SET ID lock command. When a sec-

tion of the EEPROM array is locked, the contents

cannot be changed, even when a valid write operation

attempts a write to that area. The SET IDL command

operation is shown in Figure 17.

Figure 16. Read Status Register (RDSTAT) Operation Sequence

CS

9

10 11 12 13 14 15

0

1

2

3

4

5

6

7

8

SCK

SI

RDSTAT

Instruction

(1 Byte)

High Impedance

2

1

0

SO

Status Register Output

Figure 17. EEPROM IDLock (SET IDL) Operation Sequence

CS

10 11 12 13 14 15

0

1

2

3

4

5

6

7

8

9

SCK

IDLock

Byte

Set IDL

Instruction

I

D

L

2

D

L

1

D

L

0

SI

High Impedance

SO

FN8110.1

January 3, 2008

29

X3100, X3101

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Min.

-55

Max.

125

Unit

°C

mA

°C

V

Storage temperature

Operating temperature

DC output current

-40

85

5

Lead temperature (soldering 10 seconds)

Power supply voltage

300

VCC

V

_SS-0.5

V_SS+27.0

6.75

VCELL

Cell voltage

-0.5

V

Terminal voltage (Pins: SCK, SI, SO, CS, AS0, AS1, AS2, VCS1,

VCS2, OVT, UVT, OCT, AO)

V_SS-0.5

V_RGO+ 0.5

V

TERM1

V

Terminal voltage (VCELL1)

V_SS-0.5

V_CC+ 1.0

V_CC+ 0.5

V

TERM2

Terminal voltage (all other pins)

TERM3

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is

a stress rating only; the functional operation of the device (at these or any other conditions above those indicated in

the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

Temperature

Min.

Max.

Supply Voltage

Limits

Commercial

-20°C

+70°C

X3100/X3101

6V to 24V

D.C. OPERATING CHARACTERISTICS

(Over the recommended operating conditions, unless otherwise specified.)

Limits

Symbol

Parameter

Min.

Max.

Units

Test Conditions

I_LI

Input leakage current (SCK, SI, CS,

ASO, AS1, AS2)

±10

µA

I_LO

Output leakage current (SO)

±10

µA

V

(1)

V_IL

Input LOW voltage

(SCK, SI, CS, AS0, AS1, AS2)

- 0.3

V

_RGOx 0.3

(1)

V_IH

Input HIGH voltage

(SCK, SI, CS, AS0, AS1, AS2)

V

_RGOx 0.7 V_RGO+ 0.3

0.4

V

VOL1

VOH1

VOL2

Output LOW voltage (SO)

Output HIGH voltage (SO)

V

I_OL= 1.0mA

I_OH= -0.4mA

_OL= 100uA

V_RGO- 0.8

Output LOW voltage

0.4

I

(UVP/OCP, OVP/LMON, CB1-CB4)

VOH2

VOL3

VOH3

Output HIGH voltage

(UVP/OCP, OVP/LMON, CB1-CB4)

V_CC-0.4

V

I_OH= -20uA

Output LOW voltage (RGC)

Output HIGH voltage (RGC)

0.4

I_OL= 2mA, RGP = V_CC

RGO = 5V

,

V

_CC-4.0

I_OH= -20µA, RGP = V_CC- 4V,

RGO = 5V

Note: (1) V_ILmin. and V_IHmax. are for reference only and are not 100% tested.

FN8110.1

January 3, 2008

30

X3100, X3101

OPERATING CHARACTERISTICS X3100

(Over the recommended operating conditions unless otherwise specified)

(2)

Description

Sym

Condition

Min

4.5

Typ

Max

5.5

Unit

5V regulated voltage

V_RGOOn power-up or at wake-up

V

After self-tuning

4.98

4.99

5.00

(@10mA V_RGOcurrent; 25^oC)

After self-tuning

4.95

4.90

5.02

5.00

(@10mA V_RGOcurrent; 0 - 50^oC)⁽⁵⁾

After self-tuning

V

(@50mA V_RGOcurrent)⁽⁵⁾

(3)

5VDC voltage regulator current

limit

I_LMT

R_LMT= 10Ω

250

mA

V_CCsupply current (1)

Icc1

Normal operation

85

1.3

0.9

250

2.5

1.2

µA

mA

V_CCsupply current (2)

_CCsupply current (3)

Icc2

Icc3

during nonvolatile EEPROM write

V

During EEPROM read

SCK=3.3MHz

V

_CCsupply current (4)

_CCsupply current (5)

Icc4

Icc5

Sleep mode

1

µA

V

Monitor mode

AN2, AN1, AN0 not equal to 0.

365

600

(4)

Cell over-charge protection mode

voltage threshold

(Default in Boldface)

V_OV

V_OV= 4.20V (VOV1, VOV0 = 0,0)

4.10

4.15

4.275

4.25

V

0^oC to 50^oC

V

_OV= 4.25V (VOV1, VOV0 = 0,1)

4.15

4.20

4.325

4.30

V

0^oC to 50^oC

_OV= 4.30V (VOV1, VOV0 = 1,0)

0^oC to 50^oC

4.2

4.25

4.375

4.35

V

_OV= 4.35V (VOV1, VOV0 = 1,1)

0^oC to 50^oC

4.25

4.30

4.425

4.40

Cell over-charge protection mode

release voltage threshold

V_OVR

T_OV

V_OV-

0.20

Cell over-charge detection time

C_OV= 0.1uF

1

s

(4)

Cell over-discharge protection

mode (SLEEP) threshold.

(Default in Boldface)

V_UV

V_UV= 1.95V (VUV1, VUV0 = 0,0)

1.85

1.95

2.05

2.15

2.05

2.15

2.25

2.35

V

_UV= 2.05V (VUV1, VUV0 = 0,1)

_UV= 2.15V (VUV1, VUV0 = 1,0)

V

V_UV= 2.25V (VUV1, VUV0 = 1,1)

Cell over-discharge protection

mode release threshold

V_UVR

T_UV

V_UV

0.7

+

Cell over-discharge detection time

C_UV= 0.1µF

C_UV= 200pF

1

2

s

ms

Cell over-discharge release time

T_UVRC_UV= 0.1µF

C_UV= 200pF

7

100

ms

µs

FN8110.1

January 3, 2008

31

X3100, X3101

(2)

Description

Sym

Condition

Min

Typ

Max

Unit

V

(4)

Over-current mode detection

voltage

(Default in Boldface)

V_OC

V_OC= 0.075V (VOC1, VOC0 = 0,0)

0.050

0.060

0.100

0.090

0^oC to 50^oC

V

_OC= 0.100V (VOC1, VOC0 = 0,1)

0^oC to 50^oC

0.075

0.085

0.125

0.115

V

_OC= 0.125V (VOC1, VOC0 = 1,0)

0^oC to 50^oC

0.100

0.110

0.150

0.140

V_OC= 0.150V (VOC1, VOC0 = 1,1)

0^oC to 50^oC

0.125

0.135

0.175

0.165

Over-current mode detection time

Over-current mode release time

T_OC

C_OC= 0.001µF

C_OC= 200pF

10

2

ms

kΩ

T_OCRC_OC= 0.001µF

C_OC= 200pF

10

2

Loadresistanceover-currentmode R_OCRReleases when OVP/LMON pin >

release condition

250

2.5V

(4)

Cell charge threshold voltage

V_CE

V_CE= 0.5V (Vce1, Vce0 = 0,0)

0.4

0.7

1

0.5

0.8

1.1

1.4

0.6

0.9

V

V_CE= 0.8V (Vce1, Vce0 = 0,1)

V_CE= 1.1V (Vce1, Vce0 = 1,0)

V_CE= 1.4V (Vce1, Vce0 = 1,1)

1.2

1.3

12.5

1.5

X3100 wake-up voltage

(For Vcc above this voltage, the

device wakes up)

V_SLRSee Wake-up test circuit

15.5

X3100 sleep voltage

V_SLPSee Sleep test circuit

11.5

14.5

V

(For Vcc above this voltage, the

device cannot go to sleep)

Notes: (2) Typical at 25°C.

(3) See Figure 10 on page 22.

(4) The default setting is set at the time of shipping, but may be changed by the user via changes in the configuration register.

(5) For reference only, this parameter is not 100% tested.

Wake-up test circuit (X3100)

Vcc

Sleep test circuit (X3100)

Vcc

Vcc RGP

VCELL1

VCELL2

VCELL3

VCELL4

VCELL1

RGC

RGO

RGC

RGO

1V

VCELL2

V_RGO

1V

VCELL3

VCELL4

1V

Vss

Increase Vcc until V_RGOturns on

Decrease Vcc until V_RGOturns off

FN8110.1

January 3, 2008

32

X3100, X3101

OPERATING CHARACTERISTICS X3101

(Over the recommended operating conditions unless otherwise specified)

(2)

Description Sym Condition

5V regulated voltage

Min

4.5

Typ

Max

5.5

Unit

V_RGOOn power-up or at wake-up

V

After self-tuning

4.98

4.99

5.00

(@10mA V_RGOcurrent; 25^oC)

After self-tuning

4.95

4.90

5.02

5.00

(@10mA V_RGOcurrent; 0 - 50^oC)⁽⁵⁾

After self-tuning

V

(@50mA V_RGOcurrent)⁽⁵⁾

(3)

5VDC voltage regulator current limit I_LMT

V_CCsupply current (1)

R_LMT= 10Ω

250

85

mA

µA

Icc1

Normal operation

250

2.5

1.2

V_CCsupply current (2)

_CCsupply current (3)

Icc2

Icc3

during nonvolatile EEPROM write

1.3

0.9

mA

V

During EEPROM read

SCK = 3.3MHz

V

_CCsupply current (4)

_CCsupply current (5)

Icc4

Icc5

Sleep mode

1

µA

V

Monitor mode

AN2, AN1, AN0 not equal to 0.

365

600

(4)

Cell over-charge protection mode

voltage threshold

(Default in Boldface)

V_OV

V_OV= 4.20V (VOV1, VOV0 = 0,0)

4.10

4.15

4.275

4.25

V

0^oC to 50^oC

V

_OV= 4.25V (VOV1, VOV0 = 0,1)

0^oC to 50^oC

4.15

4.20

4.325

4.30

V

_OV= 4.30V (VOV1, VOV0 = 1,0)

0^oC to 50^oC

4.2

4.25

4.375

4.35

V

V_OV= 4.35V (VOV1, VOV0 = 1,1)

0^oC to 50^oC

4.25

4.30

4.425

4.40

Cell over-charge protection mode

release voltage threshold

V_OVR

T_OV

V_OV

-

0.20

Cell over-charge detection time

C_OV= 0.1uF

1

s

(4)

Cell over-discharge protection

mode (SLEEP) threshold.

(Default in Boldface)

V_UV

V_UV= 2.25V (VUV1, VUV0 = 0,0)

2.15

2.25

2.35

2.45

2.35

2.45

2.55

2.65

V

_UV= 2.35V (VUV1, VUV0 = 0,1)

_UV= 2.45V (VUV1, VUV0 = 1,0)

_UV= 2.55V (VUV1, VUV0 = 1,1)

Cell over-discharge protection

mode release threshold

V_UVR

T_UV

V_UV

0.7

+

Cell over-discharge detection time

C_UV= 0.1µF

C_UV= 200pF

1

2

s

ms

Cell over-discharge release time

T_UVRC_UV= 0.1µF

C_UV= 200pF

7

100

ms

µs

FN8110.1

January 3, 2008

33

X3100, X3101

(2)

Description

Sym

Condition

Min

Typ

Max

Unit

V

(4)

Over-current mode detection

voltage

(Default in Boldface)

V_OC

V_OC= 0.075V (VOC1, VOC0 = 0,0)

0.050

0.060

0.100

0.090

0^oC to 50^oC

V

_OC= 0.100V (VOC1, VOC0 = 0,1)

0^oC to 50^oC

0.075

0.085

0.125

0.115

V

_OC= 0.125V (VOC1, VOC0 = 1,0)

0^oC to 50^oC

0.100

0.110

0.150

0.140

V_OC= 0.150V (VOC1, VOC0 = 1,1)

0^oC to 50^oC

0.125

0.135

0.175

0.165

Over-current mode detection time

Over-current mode release time

T_OC

C_OC= 0.001µF

C_OC= 200pF

10

2

ms

kΩ

T_OCRC_OC= 0.001µF

C_OC= 200pF

10

2

Load resistance over-current mode

release condition

R_OCRReleases when OVP/LMON pin >

2.5V

250

Cell charge threshold voltage

V_CE

V_CE= 0.5V (Vce1, Vce0 = 0,0)

0.4

0.7

1

0.5

0.8

1.1

1.4

0.6

0.9

V

_CE= 0.8V (Vce1, Vce0 = 0,1)

_CE= 1.1V (Vce1, Vce0 = 1,0)

_CE= 1.4V (Vce1, Vce0 = 1,1)

1.2

1.3

10.5

1.5

X3101 wake-up voltage

(For Vcc above this voltage, the device

wakes up)

V_SLRSee Wake-up test circuit

12.5

X3101 sleep voltage

V_SLPSee Sleep test circuit

9.5

11.5

V

(For Vcc above this voltage, the device

cannot go to sleep)

Notes: (2) Typical at 25°C.

(3) See Figure 10 on page 22.

(4) The default setting is set at the time of shipping, but may be changed by the user via changes in the configuration register.

(5) For reference only, this parameter is not 100% tested.

Wake-up test circuit (X3101)

Vcc

Sleep test circuit (X3101)

Vcc

Vcc RGP

VCELL1

VCELL2

VCELL3

VCELL4

VCELL1

VCELL2

VCELL3

VCELL4

RGC

RGO

RGC

RGO

1V

V_RGO

Vss

Decrease Vcc until V_RGOturns off

Increase Vcc until V_RGOturns on

FN8110.1

January 3, 2008

34

X3100, X3101

POWER-UP TIMING

Symbol

Parameter

Min.

Max.

(6)

t_PUR

t_PUW1

t_PUW2

Power-up to SPI read operation (RDSTAT, EEREAD STAT)

T_OC+ 2ms

(6)

Power-up to SPI write operation (WREN, WRDI, EEWRITE, WCFIG, SET IDL, WCNTR)

Power-up to SPI write operation (WCNTR - bits 10 and 11)

T_OV+ 200ms

or

T_UV+ 200ms⁽⁷⁾

Notes: (6) t_PUR, t_PUW1and t_PUW2are the delays required from the time V_CCis stable until a read or write can be initiated. These parameters are

not 100% tested.

(7) Whichever is longer.

CAPACITANCE T = +25°C, f = 1 MHz, V

= 5V

A

RGO

Symbol

Parameter

Output capacitance (SO)

Input capacitance (SCK, SI, CS)

Max.

Units

pF

Conditions

= 0V

(8)

C

8

6

V

OUT

(8)

C

pF

V

= 0V

IN

Notes: (8) This parameter is not 100% tested.

Equivalent A.C. Load Circuit

5V

A.C. TEST CONDITIONS

Input pulse levels

0.5 - 4.5V

10ns

Input rise and fall times

Input and output timing level

2061Ω

2.5V

SO

30pF

3025Ω

FN8110.1

January 3, 2008

35

X3100, X3101

A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)

SERIAL INPUT TIMING

Symbol

Parameter

Clock frequency

Voltage

Min.

0

Max.

Units

MHz

ns

f

3.3

SCK

CYC

t

Cycle time

300

150

130

20

t

CS lead time

ns

LEAD

t

CS lag time

ns

LAG

t_WH

t_WL

t_SU

t_H

Clock HIGH time

Clock LOW time

Data setup time

Data hold time

Data in rise time

Data in fall time

CS deselect time

Write cycle time

ns

20

ns

(9)

t_RI

2

µs

(9)

t_FI

µs

t_CS

100

ns

(10)

t_WC

5

ms

Notes: (9) This parameter is not 100% tested

(10)t_WCis the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile

write cycle.

Serial Input Timing

t_CS

CS

SCK

SI

t_LEAD

t_LAG

t_H

t_SU

t_RI

t_FI

MSB IN

LSB IN

SO

FN8110.1

January 3, 2008

36

X3100, X3101

Serial Output Timing

Symbol

Parameter

Voltage

Min.

Max.

3.3

Units

MHz

ns

f_SCK

t_DIS

t_V

Clock Frequency

0

Output Disable Time

Output Valid from Clock LOW

Output Hold Time

150

130

ns

t_HO

0

ns

(11)

t_RO

Output Rise Time

50

ns

(11)

t_FO

Output Fall Time

ns

Notes: (11)This parameter is not 100% tested.

Serial Output Timing

CS

t_CYC

t_WH

t_LAG

SCK

t_HO

t_WL

t_V

MSB Out

t_DIS

SO

SI

MSB–1 Out

LSB Out

ADDR

LSB In

SYMBOL TABLE

WAVEFORM

INPUTS

OUTPUTS

Must be

steady

Will be

steady

May change

from LOW

to HIGH

Will change

from LOW

to HIGH

May change

from HIGH

to LOW

Will change

from HIGH

to LOW

Don’t Care:

Changes

Allowed

Changing:

State Not

Known

N/A

Center Line

is High

Impedance

FN8110.1

January 3, 2008

37

X3100, X3101

Analog Output Response Time

Symbol

Parameter

Min.

Typ.

Max.

Units

t_VSC

t_CSGO

t_CO

AO Output Stabilization Time (Voltage Source Change)

AO Output Stabilization Time (Current Sense Gain Change)

1.0

ms

1.0

ms

µs

Control Outputs Response Time (UVP/OCP, OVP/MON, CB4,

CB3, CB2, CB1, RGC)

ANALOG OUTPUT RESPONSE TIME

Change in Voltage Source

AS2:AS0

AO

t_VSC

Change in Current Sense Gain Amplification and Control Bits

C S

SCK

DI

0

OVPC

Bit10

CSG1 CSG0 SLP

Bit9 Bit8 Bit7

x

Control Reg

Bit6

Bit5

AO

Old Gain

Current Sense

Gain Change

New Gain

t_CSGO

UVP/OCP

OVP/LMON

CB4:CB1

RGC

On

Control

Outputs

Off

t_CO

FN8110.1

January 3, 2008

38

X3100, X3101

TYPICAL OPERATING CHARACTERISTICS

Norm al Ope r ating Cur r ent

Monitor Mode Current

450

150

125

100

75

400

350

300

50

-20

25

80

-20

25

80

Temperature

X3100 Over Discharge Trip Voltage (Typical)

X3100/X3101 Over Charge Trip Voltage (Typical)

2.30

4.40

4.35

4.30

4.25

4.20

4.15

2.25

2.20

2.15

2.10

2.05

2.00

1.95

-25

25

75

-25

25

75

Temperature (Deg C)

4.2V Setting

4.3V Setting

4.25V Setting

4.35V Setting

1.95V Setting

2.15V Setting

2.05V Setting

2.25V Setting

X3101 Over Discharge Trip Voltage (Typical)

Voltage Regulator Output (Typical)

Vcc = 10.8V to 16V R_lim= 15 Ohm (I_lim= 200mA)

2.60

2.55

2.50

2.45

2.40

2.35

2.30

2.25

5.020

5.000

4.980

4.960

4.940

4.920

4.900

4.880

-25

25

75

Temperature (Deg C)

1

10

50

100

2.25V Setting

2.45V Setting

2.35V Setting

2.55V Setting

Load (mA)

-25 degC

25 degC

75 degC

Voltage Regulator Output (Typical)

Vcc = 10.8V to 16V R_lim= 15 Ohm (I_lim= 200mA)

5.020

5.000

4.980

4.960

4.940

4.920

4.900

4.880

-25

25

75

Temperature

1mA Load

10mA Load

50mA Load

100 mA Load

For typical performance of current and voltage monitoring circuits, please refer to Application Note AN142 and AN143

FN8110.1

January 3, 2008

39

X3100, X3101

FN8110.1

January 3, 2008

40

X3100, X3101

Thin Shrink Small Outline Plastic Packages (TSSOP)

N

M28.173

INDEX

AREA

0.25(0.010)

M

B M

E

28 LEAD THIN SHRINK SMALL OUTLINE PLASTIC

PACKAGE

E1

-B-

GAUGE

PLANE

INCHES

MIN

MILLIMETERS

SYMBOL

MAX

0.047

0.006

0.051

0.0118

0.0079

0.386

0.177

MIN

-

MAX

1.20

0.15

1.05

0.30

0.20

9.80

4.50

NOTES

1

2

3

A

A1

A2

b

-

L

0.002

0.031

0.0075

0.0035

0.378

0.169

0.05

0.80

0.19

0.09

9.60

4.30

-

0.25

0.010

0.05(0.002)

SEATING PLANE

A

-

-A-

D

9

c

-

-C-

D

3

α

A2

e

A1

E1

e

4

c

b

0.026 BSC

0.65 BSC

-

0.10(0.004)

E

0.246

0.256

6.25

0.45

6.50

0.75

-

0.10(0.004) M

C

A M B S

L

0.0177

0.0295

6

NOTES:

N

28

7

1. These package dimensions are within allowable dimensions of

JEDEC MO-153-AE, Issue E.

0^o

8^o

0^o

8^o

-

α

Rev. 0 6/98

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm

(0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per

side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable dambar

protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-

sion at maximum material condition. Minimum space between protru-

sion and adjacent lead is 0.07mm (0.0027 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact. (Angles in degrees)

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8110.1

January 3, 2008

41


型号：	X3100V
厂家：	Intersil
描述：	Cell Balancing Control 光电二极管
文件：	总41页 (文件大小：563K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

X3100V [INTERSIL]

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