X40035SB [INTERSIL]
Triple Voltage Monitor with Integrated CPU Supervisor; 三重电压监控器，集成了CPU监控
| 型号： | X40035SB |
| 厂家： | 
Intersil |
| 描述： | Triple Voltage Monitor with Integrated CPU Supervisor |
| 文件： | 总23页 (文件大小：344K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X40030, X40031, X40034, X40035
®
Data Sheet
August 25, 2008
FN8114.2
Triple Voltage Monitor with Integrated
CPU Supervisor
Features
• Triple voltage detection and reset assertion
The X40030, X40031, X40034, X40035 combine power-on
reset control, watchdog timer, supply voltage supervision,
second and third voltage supervision, and manual reset, in one
package. This combination lowers system cost, reduces board
space requirements, and increases reliability.
- Standard reset threshold settings; see Table 1 on
page 5.
- Adjust low voltage reset threshold voltages using
special programming sequence
- Reset signal valid to VCC = 1V
- Monitor three separate voltages
Applying voltage to VCC activates the power-on reset circuit,
which holds RESET/RESET active for a period of time. This
allows the power supply and system oscillator to stabilize
before the processor can execute code.
• Fault detection register
• Selectable power-on reset time-out (0.05s, 0.2s, 0.4s,
0.8s)
Low VCC detection circuitry protects the user’s system from
low voltage conditions, resetting the system when VCC falls
below the minimum VTRIP1 point. RESET/RESET is active
until VCC returns to proper operating level and stabilizes. A
second and third voltage monitor circuit tracks the unregulated
supply to provide a power fail warning or monitors different
power supply voltage. Three common low voltage
combinations are available, however, Intersil’s unique circuits
allows the threshold for either voltage monitor to be
reprogrammed to meet specific system level requirements or to
fine-tune the threshold for applications requiring higher
precision.
• Selectable watchdog timer interval (25ms, 200ms, 1.4s or
off)
• Debounced manual reset input
• Low power CMOS
- 25µA typical standby current, watchdog on
- 6µA typical standby current, watchdog off
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available in 14 Ld SOIC and 14 Ld TSSOP packages
• Monitor voltages: 5V to 0.9V
• Independent core voltage monitor
• Pb-free available (RoHS compliant)
Applications
• Communication equipment
- Routers, hubs, switches
- Disk arrays, network storage
• Industrial systems
- Process control
- Intelligent instrumentation
• Computer systems
- Computers
- Network servers
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X40030, X40031, X40034, X40035
Block Diagram
+
V3FAIL
V2FAIL
V3MON
V
TRIP3
V3 MONITOR
LOGIC
-
V
OR
CC
V2MON*
V2MON
+
-
V2 MONITOR
LOGIC
V
TRIP2
WATCHDOG
AND
RESET LOGIC
FAULT DETECTION
REGISTER
WDO
MR
DATA
SDA
WP
REGISTER
STATUS
REGISTER
COMMAND
DECODE TEST
AND CONTROL
LOGIC
SCL
RESET
X40030/34
POWER-ON,
MANUAL RESET
LOW VOLTAGE
RESET
RESET
+
V
X40031/35
CC
V
TRIP1
GENERATION
(V1MON)
V
MONITOR
LOGIC
CC
-
LOWLINE
FN8114.2
August 25, 2008
2
X40030, X40031, X40034, X40035
Ordering Information
PART NUMBER
(Note 1)
PART
MARKING
MONITORED
VTRIP1
RANGE
VTRIP2
RANGE
VTRIP3
RANGE
TEMP.
RANGE (°C)
PKG.
DWG. #
V
CC RANGE
PACKAGE
PART NUMBER WITH RESET
X40034S14-A
X40034S14-B
X40034S14-C
X40034S14I-A
X40034S14I-B
X40034S14I-C
X40034V14-A
X40034V14-B
X40034V14-C
X40034V14I-A
X40034V14I-B
X40034V14I-C
X40030S14-C
X40030S14I-C
X40030V14-C
X40030V14I-C
X40030S14-B
X40034S A
X40034S B
X40034S C
X40034S IA
X40034S IB
X40034S IC
X4003 4VA
X4003 4VB
X4003 4VC
X4003 4VIA
X4003 4VIB
X4003 4VIC
X40030S C
X40030S IC
X4003 0VC
X4003 0VIC
X40030S B
X40030S ZB
1.3 to 5.5
4.6V ±50mV 1.3V ±50mV 3.1V ±50mV
2.9V ±50mV
0 to +70
0 to +70
0 to +70
14 Ld SOIC (150 mil) MDP0027
14 Ld SOIC (150 mil) MDP0027
14 Ld SOIC (150 mil) MDP0027
1.0 to 3.6
1.3 to 5.5
1.0V ±50mV
1.3V ±50mV 3.1V ±50mV
2.9V ±50mV
-40 to +85 14 Ld SOIC (150 mil) MDP0027
-40 to +85 14 Ld SOIC (150 mil) MDP0027
-40 to +85 14 Ld SOIC (150 mil) MDP0027
1.0 to 3.6
1.3 to 5.5
1.0V ±50mV
1.3V ±50mV 3.1V ±50mV
2.9V ±50mV
0 to +70
0 to +70
0 to +70
14 Ld TSSOP (4.4mm) MDP0044
14 Ld TSSOP (4.4mm) MDP0044
14 Ld TSSOP (4.4mm) MDP0044
1.0 to 3.6
1.3 to 5.5
1.0V ±50mV
1.3V ±50mV 3.1V ±50mV
2.9V ±50mV
-40 to +85 14 Ld TSSOP (4.4mm) MDP0044
-40 to +85 14 Ld TSSOP (4.4mm) MDP0044
-40 to +85 14 Ld TSSOP (4.4mm) MDP0044
1.0 to 3.6
1.7 to 3.6
1.0V ±50mV
2.9V ±50mV 2.2V ±50mV 2.6V ±50mV
0 to +70
-40 to +85 14 Ld SOIC (150 mil) MDP0027
0 to +70 14 Ld TSSOP (4.4mm) MDP0044
-40 to +85 14 Ld TSSOP (4.4mm) MDP0044
14 Ld SOIC (150 mil) MDP0027
1.7 to 5.5
4.4V ±50mV 2.6V ±50mV 1.8V ±50mV
0 to +70
0 to +70
14 Ld SOIC (150 mil) MDP0027
X40030S14Z-B
(Note 2)
14 Ld SOIC (150 mil) MDP0027
(Pb-free)
X40030S14I-B
X40030S IB
-40 to +85 14 Ld SOIC (150 mil) MDP0027
X40030S14IZ-B X40030S ZIB
(Note 2)
-40 to +85 14 Ld SOIC (150 mil) MDP0027
(Pb-free)
X40030V14-B
X40030V14I-B
X40030S14-A
X4003 0VB
X4003 0VIB
X40030S A
X40030S ZA
0 to +70
14 Ld TSSOP (4.4mm) MDP0044
-40 to +85 14 Ld TSSOP (4.4mm) MDP0044
4.6V ±50mV 2.9V ±50mV
0 to +70
0 to +70
14 Ld SOIC (150 mil) MDP0027
X40030S14Z-A
(Note 2)
14 Ld SOIC (150 mil) MDP0027
(Pb-free)
X40030S14I-A
X40030S IA
-40 to +85 14 Ld SOIC (150 mil) MDP0027
X40030S14IZ-A X40030S ZIA
(Note 2)
-40 to +85 14 Ld SOIC (150 mil) MDP0027
(Pb-free)
X40030V14-A
X40030V14I-A
X4003 0VA
X4003 0VIA
0 to +70
14 Ld TSSOP (4.4mm) MDP0044
-40 to +85 14 Ld TSSOP (4.4mm) MDP0044
PART NUMBER WITH RESET
X40035S14-A
X40035S14-B
X40035S14-C
X40035S14I-A
X40035S14I-B
X40035S14I-C
X40035V14-A
X40035V14-B
X40035S A
X40035S B
X40035S C
X40035S IA
X40035S IB
X40035S IC
X4003 5VA
X4003 5VB
1.3 to 5.5
4.6V ±50mV 1.3V ±50mV 3.1V ±50mV
2.9V ±50mV
0 to +70
0 to +70
0 to +70
14 Ld SOIC (150 mil) MDP0027
14 Ld SOIC (150 mil) MDP0027
14 Ld SOIC (150 mil) MDP0027
1.0 to 3.6
1.3 to 5.5
1.0V ±50mV
1.3V ±50mV 3.1V ±50mV
2.9V ±50mV
-40 to +85 14 Ld SOIC (150 mil) MDP0027
-40 to +85 14 Ld SOIC (150 mil) MDP0027
-40 to +85 14 Ld SOIC (150 mil) MDP0027
1.0 to 3.6
1.3 to 5.5
1.0V ±50mV
1.3V ±50mV 3.1V ±50mV
2.9V ±50mV
0 to +70
0 to +70
14 Ld TSSOP (4.4mm) MDP0044
14 Ld TSSOP (4.4mm) MDP0044
FN8114.2
August 25, 2008
3
X40030, X40031, X40034, X40035
Ordering Information (Continued)
PART NUMBER
(Note 1)
PART
MARKING
MONITORED
VCC RANGE
VTRIP1
RANGE
VTRIP2
RANGE
VTRIP3
RANGE
TEMP.
RANGE (°C)
PKG.
DWG. #
PACKAGE
X40035V14-C
X40035V14I-A
X40035V14I-B
X40035V14I-C
X40031S14-C
X40031S14I-C
X40031V14-C
X40031V14I-C
X40031S14-B
X4003 5VC
X4003 5VIA
X4003 5VIB
X4003 5VIC
X40031S C
X40031S IC
X4003 1VC
X4003 1VIC
X40031S B
X40031S ZB
1.0 to 3.6
1.3 to 5.5
4.6V ±50mV 1.0V ±50mV 2.9V ±50mV
1.3V ±50mV 3.1V ±50mV
2.9V ±50mV
0 to +70
14 Ld TSSOP (4.4mm) MDP0044
-40 to +85 14 Ld TSSOP (4.4mm) MDP0044
-40 to +85 14 Ld TSSOP (4.4mm) MDP0044
-40 to +85 14 Ld TSSOP (4.4mm) MDP0044
1.0 to 3.6
1.7 to 3.6
1.0V ±50mV
2.9V ±50mV 2.2V ±50mV 2.6V ±50mV
0 to +70
-40 to +85 14 Ld SOIC (150 mil) MDP0027
0 to +70 14 Ld TSSOP (4.4mm) MDP0044
-40 to +85 14 Ld TSSOP (4.4mm) MDP0044
14 Ld SOIC (150 mil) MDP0027
1.7 to 5.5
4.4V ±50mV 2.6V ±50mV 1.8V ±50mV
0 to +70
0 to +70
14 Ld SOIC (150 mil) MDP0027
X40031S14Z-B
(Note 2)
14 Ld SOIC (150 mil) MDP0027
(Pb-free)
X40031S14I-B
X40031S IB
-40 to +85 14 Ld SOIC (150 mil) MDP0027
X40031S14IZ-B X40031S ZIB
(Note 2)
-40 to +85 14 Ld SOIC (150 mil) MDP0027
(Pb-free)
X40031V14-B
X40031V14I-B
X40031S14-A
X4003 1VB
X4003 1VIB
X40031S A
X40031S ZA
0 to +70
14 Ld TSSOP (4.4mm) MDP0044
-40 to +85 14 Ld TSSOP (4.4mm) MDP0044
4.6V ±50mV 2.9V ±50mV
0 to +70
0 to +70
14 Ld SOIC (150 mil) MDP0027
X40031S14Z-A
(Note 2)
14 Ld SOIC (150 mil) MDP0027
(Pb-free)
X40031S14I-A
X40031S IA
-40 to +85 14 Ld SOIC (150 mil) MDP0027
X40031S14IZ-A X40031S ZIA
(Note 2)
-40 to +85 14 Ld SOIC (150 mil) MDP0027
(Pb-free)
X40031V14-A
X40031V14I-A
NOTES:
X4003 1VA
X4003 1VIA
0 to +70
14 Ld TSSOP (4.4mm) MDP0044
-40 to +85 14 Ld TSSOP (4.4mm) MDP0044
1. Add “T1” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-
020.
FN8114.2
August 25, 2008
4
X40030, X40031, X40034, X40035
A manual reset input provides debounce circuitry for
minimum reset component count.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcontroller
fails to restart a timer within a selectable time out interval,
the device activates the WDO signal. The user selects the
interval from three preset values. Once selected, the interval
does not change, even after cycling the power.
TABLE 1. SELECTION TABLE
EXPECTED SYSTEM
VOLTAGES
VTRIP1
(V)
VTRIP2
(V)
VTRIP3
(V)
POR
(SYSTEM)
DEVICE
X40030, X40031
2.0 to 4.75*
4.55 to 4.65*
4.35 to 4.45*
2.95 to 3.05*
2.0 to 4.75*
4.55 to 4.65*
4.55 to 4.65*
4.55 to 4.65*
1.70 to 4.75
2.85 to 2.95
2.55 to 2.65
2.15 to 2.25
0.90 to 3.50
1.25 to 1.35
1.25 to 1.35
0.95 to 1.05
1.70 to 4.75
1.65 to 1.75
1.65 to 1.75
1.65 to 1.75
1.70 to 4.75
3.05 to 3.15
2.85 to 2.95
2.85 to 2.95
X40030A, X40031A
X40030B, X40031B
X40030C, X40031C
X40034, X40035
5V; 3V or 3.3V; 1.8V
5V; 3V; 1.8V
RESET = X40030
RESET = X40031
3.3V; 2.5V; 1.8V
X40034A, X40035A
X40034B, X40035B
X40034C, X40035C
5V; 3.3V; 1.5V
RESET = X40030
RESET = X40031
5V; 3V or 3.3V; 1.5V
5V; 3V or 3.3V; 1.2V
*Voltage monitor requires VCC to operate. Others are independent of VCC
FN8114.2
August 25, 2008
5
X40030, X40031, X40034, X40035
Pinouts
X40030, X40034
(14 LD SOIC, TSSOP)
TOP VIEW
X40031, X40035
(14 LD SOIC, TSSOP)
TOP VIEW
V
V2FAIL
V2MON
V
1
2
3
4
14
13
12
11
V2FAIL
CC
1
2
3
4
14
13
12
11
CC
WDO
V2MON
LOWLINE
NC
WDO
V3FAIL
V3MON
WP
LOWLINE
NC
V3FAIL
V3MON
WP
MR
5
6
7
10
9
MR
5
6
7
10
9
SCL
RESET
RESET
SCL
V
SDA
V
8
SS
SDA
8
SS
Pin Descriptions
PIN
NAME
FUNCTION
1
V2FAIL
V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than VTRIP2 and goes HIGH when
V2MON exceeds VTRIP2. There is no power-up reset delay circuitry on this pin.
2
V2MON
V2 Voltage Monitor Input. When the V2MON input is less than the VTRIP2 voltage, V2FAIL goes LOW. This input can
monitor an unregulated power supply with an external resistor divider or can monitor a second power supply with no external
components. Connect V2MON to VSS or VCC when not used. The V2MON comparator is supplied by V2MON (X40030,
X40031) or by the VCC input (X40034, X40035).
3
4
5
LOWLINE
NC
Early Low VCC Detect. This CMOS output signal goes LOW when V
< VTRIP1 and goes high when V
> VTRIP1.
CC
CC
No connect.
MR
Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will remain HIGH/LOW
until the pin is released and for the tPURST thereafter.
6
RESET/
RESET
RESET Output. (X40030, X40034) This pin is an active HIGH CMOS output which goes HIGH whenever VCC falls below
VTRIP1 voltage or if manual reset is asserted. This output stays active for the programmed time period (tPURST) on power-up. It
will also stay active until manual reset is released and for tPURST thereafter.
RESET Output. (X40031, X40035) This open drain pin is an active LOW output ,which goes LOW whenever VCC falls
below VTRIP1 voltage or if manual reset is asserted. This output stays active for the programmed time period (tPURST) on
power-up. It will also stay active until manual reset is released and for tPURST thereafter.
7
8
VSS
Ground
SDA
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and
may be wire ORed with other open drain or open collector outputs. This pin requires a pull-up resistor and the input buffer
is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to LOW and followed by a stop
condition) restarts the Watchdog timer. The absence of this transition within the watchdog time out period results in WDO
going active.
9
SCL
WP
Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
10
Write Protect. WP HIGH prevents writes to any location in the device (including all the registers). It has an internal
pull-down resistor (>10MΩ typical).
11
12
V3MON
V3FAIL
V3 Voltage Monitor Input. When the V3MON input is less than the VTRIP3 voltage, V3FAIL goes LOW. This input can
monitor an unregulated power supply with an external resistor divider or can monitor a third power supply with no external
components. Connect V3MON to VSS or V
when not used. The V3MON comparator is supplied by the V3MON input.
CC
V3 Voltage Fail Output. This open drain output goes LOW when V3MON is less than VTRIP3 and goes HIGH when
V3MON exceeds VTRIP3. There is no power-up reset delay circuitry on this pin.
13
14
WDO
VCC
WDO Output. WDO is an active LOW, open drain output, which goes active whenever the watchdog timer goes active.
Supply Voltage.
FN8114.2
August 25, 2008
6
X40030, X40031, X40034, X40035
For the X40030 and X40031 the V2FAIL signal remains
active until the V2MON drops below 1V (V2MON falling). It
also remains active until V2MON returns and exceeds
Principles of Operation
Power-on Reset
Applying power to the X40030, X40031, X40034, X40035
activates a Power-on Reset Circuit that pulls the
RESET/RESET pins active. This signal provides several
benefits.
V
TRIP2.This voltage sense circuitry monitors the power
supply connected to V2MON pin. If VCC = 0, V2MON can still
be monitored.
For the X40034 and X40035, the V2FAIL signal remains
active until VCC drops below 1V and remains active until
V2MON returns and exceeds VTRIP2.This sense circuitry is
powered by VCC. If VCC = 0, V2MON cannot be monitored.
• It prevents the system microprocessor from starting to
operate with insufficient voltage.
• It prevents the processor from operating prior to
stabilization of the oscillator.
Low Voltage V3 Monitoring
• It allows time for an FPGA to download its configuration
prior to initialization of the circuit.
The X40030, X40031, X40034, X40035 also monitors a third
voltage level and asserts V3FAIL if the voltage falls below a
preset minimum VTRIP3. The V3FAIL signal is either ORed
with RESET to prevent the microprocessor from operating in
a power fail or brownout condition or used to interrupt the
microprocessor with notification of an impending power
failure. The V3FAIL signal remains active until the V3MON
drops below 1V (V3MON falling). It also remains active until
• It prevents communication to the EEPROM, greatly reducing
the likelihood of data corruption on power-up.
When VCC exceeds the device VTRIP1 threshold value for
tPURST (selectable), the circuit releases the RESET (X40031,
X40035) and RESET (X40030, X40034) pin allowing the
system to begin operation.
V3MON returns and exceeds VTRIP3
.
V
CC
X40030, X40034
This voltage sense circuitry monitors the power supply
connected to V3MON pin. If VCC = 0, V3MON can still be
monitored.
SYSTEM
RESET
RESET
Early Low V Detection (LOWLINE)
MR
CC
This CMOS output goes LOW earlier than RESET/RESET
whenever VCC falls below the VTRIP1 voltage and returns
high when VCC exceeds the VTRIP1 voltage. There is no
power-up delay circuitry (tPURST) on this pin.
MANUAL
RESET
FIGURE 1. CONNECTING A MANUAL RESET PUSH-BUTTON
V
CC
X40031-A
RESET
Manual Reset
6V TO 10V
1M
By connecting a push-button directly from MR to ground, the
designer adds manual system reset capability. The MR pin is
LOW while the push-button is closed and RESET/RESET
pin remains HIGH/LOW until the push-button is released and
for tPURST thereafter.
5V
V
CC
SYSTEM
RESET
V2FAIL
V3FAIL
V2MON
3.3V
V3MON
(1.7V)
POWER
FAIL
INTERRUPT
390k
Low Voltage V (V1 Monitoring)
CC
During operation, the X40030, X40031, X40034, X40035
monitors the VCC level and asserts RESET/RESET if the
supply voltage falls below a preset minimum VTRIP1. The
RESET signal prevents the microprocessor from operating in
a power fail or brownout condition. The RESET/RESET
signal remains active until the voltage drops below 1V. It also
remains active until VCC returns and exceeds VTRIP1 for
V
CC
X40031-B
UNREG.
SUPPLY
5V
V
REG
CC
SYSTEM
RESET
RESET
3.0V
REG
V2MON
tPURST
.
V2FAIL
V3FAIL
1.8V
REG
Low Voltage V2 Monitoring
V3MON
The X40030 also monitors a second voltage level and
asserts V2FAIL if the voltage falls below a preset minimum
NOTICE: NO EXTERNAL COMPONENTS REQUIRED TO MONITOR
THREE VOLTAGES.
VTRIP2. The V2FAIL signal is either ORed with RESET to
prevent the microprocessor from operating in a power fail or
brownout condition or used to interrupt the microprocessor
with notification of an impending power failure.
FIGURE 2. TWO USES OF MULTIPLE VOLTAGE MONITORING
FN8114.2
August 25, 2008
7
X40030, X40031, X40034, X40035
V
(X = 1, 2, 3)
TRIPX
V
/V2MON/V3MON
CC
V
P
WDO
SCL
0
7
0
7
0
7
SDA
t
WC
A0h
00h
FIGURE 3. VTRIPX SET/RESET CONDITIONS
Setting a V
Voltage (x = 1, 2, 3)
Watchdog Timer
TRIPx
There are two procedures used to set the threshold voltages
(VTRIPx), depending upon if the threshold voltage to be stored
is higher or lower than the present value. For example, if the
present VTRIPx is 2.9V and the new VTRIPx is 3.2V, the new
voltage can be stored directly into the VTRIPx cell. If however,
the new setting is to be lower than the present setting, then it
is necessary to “reset” the VTRIPx voltage before setting the
new value.
The Watchdog Timer circuit monitors the microprocessor
activity by monitoring the SDA and SCL pins. A standard
read or write sequence to any slave address byte restarts
the watchdog timer and prevents the WDO signal from going
active. A minimum sequence to reset the watchdog timer
requires four microprocessor instructions namely, a Start,
Clock Low, Clock High and Stop. The state of two nonvolatile
control bits in the Status Register determine the watchdog
timer period. The microprocessor can change these
watchdog bits by writing to the X40030, X40031, X40034,
X40035 control register (also refer to page 21).
Setting a Higher V
Voltage (x = 1, 2, 3)
TRIPx
To set a VTRIPx threshold to a new voltage which is higher
than the present threshold, the user must apply the desired
0.6µs
1.3µs
VTRIPx threshold voltage to the corresponding input pin
SCL
SDA
(Vcc(V1MON), V2MON or V3MON). Then, a programming
voltage (Vp) must be applied to the WDO pin before a START
condition is set up on SDA. Next, issue on the SDA pin the
Slave Address A0h, followed by the Byte Address 01h for
V
TRIP1, 09h for VTRIP2, and 0Dh for VTRIP3, and a 00h Data
START
WDT RESET STOP
Byte in order to program VTRIPx. The STOP bit following a
valid write operation initiates the programming sequence. Pin
WDO must then be brought LOW to complete the operation.
To check if the VTRIPX has been set, set VXMON to a value
slightly greater than VTRIPX (that was previously set). Slowly
ramp down VXMON and observe when the corresponding
outputs (LOWLINE, V2FAIL and V3FAIL) switch. The voltage
at which this occurs is the VTRIPX (actual).
FIGURE 4. WATCHDOG RESTART
V1, V2 and V3 Threshold Program
Procedure (Optional)
The X40030 is shipped with standard V1, V2 and V3
threshold (VTRIP1, VTRIP2, VTRIP3) voltages. These values
will not change over normal operating and storage
conditions. However, in applications where the standard
thresholds are not exactly right, or if higher precision is
needed in the threshold value, the X40030, X40031, X40034,
X40035 trip points may be adjusted. The procedure is
described in the following and uses the application of a high
voltage control signal.
CASE A
If the desired VTRIPX is greater than the VTRIPX (actual), then
add the difference between VTRIPX (desired) – VTRIPX
(actual) to the original VTRIPX desired. This is your new
VTRIPX that should be applied to VXMON and the whole
sequence should be repeated again (see Figure 5).
CASE B
If the VTRIPX (actual), is higher than the VTRIPX (desired),
perform the reset sequence as described in the next section.
FN8114.2
August 25, 2008
8
X40030, X40031, X40034, X40035
The new VTRIPX voltage to be applied to VXMON will now
be: VTRIPX (desired) – (VTRIPX (actual) – VTRIPX (desired)).
The Control Register is accessed with a special preamble in
the slave byte (1011) and is located at address 1FFh. It can
only be modified by performing a byte write operation directly
to the address of the register and only one data byte is
allowed for each register write operation. Prior to writing to the
Control Register, the WEL and RWEL bits must be set using a
two step process, with the whole sequence requiring 3 steps.
See “Writing to the Control Registers” on page 11.
Note: This operation does not corrupt the memory array.
Setting a Lower V
Voltage (x=1, 2, 3)
TRIPx
In order to set VTRIPx to a lower voltage than the present
value, then VTRIPx must first be “reset” according to the
procedure described in the following. Once VTRIPx has been
“reset”, then VTRIPx can be set to the desired voltage using
the procedure described in “Setting a Higher VTRIPx
Voltage (x = 1, 2, 3)” on page 8.
The user must issue a stop, after sending this byte to the
register, to initiate the nonvolatile cycle that stores WD1,
WD0, PUP1, PUP0 and BP. The X40030, X40031, X40034,
X40035 will not acknowledge any data bytes written after the
first byte is entered.
Resetting the V
Voltage
TRIPx
To reset a VTRIPx voltage, apply the programming voltage
(Vp) to the WDO pin before a START condition is set up on
SDA. Next, issue on the SDA pin the Slave Address A0h
followed by the Byte Address 03h for VTRIP1, 0Bh for VTRIP2
and 0Fh for VTRIP3, followed by 00h for the Data Byte in
order to reset VTRIPx. The STOP bit following a valid write
operation initiates the programming sequence. Pin WDO
must then be brought LOW to complete the operation.
The state of the Control Register can be read at any time by
performing a random read at address 1FFh, using the
special preamble. Only one byte is read by each register
read operation. The master should supply a stop condition to
be consistent with the bus protocol.
,
7
6
5
4
3
2
1
0
PUP1 WD1 WD0
BP
0
RWEL WEL PUP0
After being reset, the value of VTRIPx becomes a nominal
value of 1.7V or lesser.
RWEL: Register Write Enable Latch (Volatile)
Note: This operation does not corrupt the memory array.
Set VCC ≅ 1.5(V2MON or V3MON), when setting VTRIP2 or
The RWEL bit must be set to “1” prior to a write to the
Control Register.
VTRIP3 respectively.
Control Register
The Control Register provides the user a mechanism for
changing the Block Lock and Watchdog Timer settings. The
Block Lock and Watchdog Timer bits are nonvolatile and do
not change when power is removed.
V
P
ADJUST
RUN
V2FAIL
RESET
µC
1
6
2
7
14
13
9
X40030
V
TRIP1
8
ADJ.
SCL
SDA
V
TRIP2
ADJ.
FIGURE 5. SAMPLE VTRIP RESET CIRCUIT
FN8114.2
August 25, 2008
9
X40030, X40031, X40034, X40035
VX = V , VXMON
CC
V
PROGRAMMING
TRIPX
NOTE: X = 1, 2, 3
LET: MDE = MAXIMUM DESIRED ERROR
DESIRED
NO
V
<
TRIPX
+
MDE
PRESENT VALUE
ACCEPTABLE
DESIRED VALUE
YES
ERROR RANGE
–
EXECUTE
MDE
V
RESET SEQUENCE
TRIPX
ERROR = ACTUAL - DESIRED
SET V = DESIRED V
X
TRIPX
NEW V APPLIED =
X
EXECUTE
NEW V APPLIED =
X
SET HIGHER V SEQUENCE
OLD V APPLIED - | ERROR |
X
OLD V APPLIED + | ERROR |
X
X
APPLY V AND VOLTAGE
CC
EXECUTE RESET V
SEQUENCE
TRIPX
> DESIRED V
TO
V
TRIPX
X
NO
DECREASE
V
X
OUTPUT SWITCHES?
YES
–
+
ERROR < MDE
V
ERROR > MDE
ACTUAL
DESIRED
TRIPX -
V
TRIPX
| ERROR | < | MDE |
DONE
FIGURE 6. VTRIPX SET/RESET SEQUENCE (X = 1, 2, 3)
FN8114.2
August 25, 2008
10
X40030, X40031, X40034, X40035
bits. This operation proceeded by a start and ended with a
WEL: Write Enable Latch (Volatile)
stop bit. Since this is a nonvolatile write cycle it will take up
to 10ms (max.) to complete. The RWEL bit is reset by this
cycle and the sequence must be repeated to change the
nonvolatile bits again. If bit 2 is set to ‘1’ in this third step
(qxys 011r) then the RWEL bit is set, but the WD1, WD0,
PUP1, PUP0, and BP bits remain unchanged. Writing a
second byte to the control register is not allowed. Doing so
aborts the write operation and returns a NACK.
The WEL bit controls the access to the memory and to the
Register during a write operation. This bit is a volatile latch
that powers up in the LOW (disabled) state. While the WEL
bit is LOW, writes to any address, including any control
registers will be ignored (no acknowledge will be issued after
the Data Byte). The WEL bit is set by writing a “1” to the
WEL bit and zeroes to the other bits of the control register.
Once set, WEL remains set until either it is reset to 0 (by
writing a “0” to the WEL bit and zeroes to the other bits of the
control register) or until the part powers up again. Writes to
the WEL bit do not cause a high voltage write cycle, so the
device is ready for the next operation immediately after the
stop condition.
• A read operation occurring between any of the previous
operations will not interrupt the register write operation.
• The RWEL bit cannot be reset without writing to the
nonvolatile control bits in the control register, or power
cycling the device or attempting a write to a write
protected block.
To illustrate, a sequence of writes to the device consisting of
[02H, 06H, 02H] will reset all of the nonvolatile bits in the
Control Register to 0. A sequence of [02H, 06H, 06H] will
leave the nonvolatile bits unchanged and the RWEL bit
remains set.
PUP1, PUP0: Power-Up Bits (Nonvolatile)
The Power-up bits, PUP1 and PUP0, determine the tPURST
time delay. The nominal power-up times are shown in Table 2.
TABLE 2. NOMINAL POWER-UP TIMES
PUP1
PUP0
POWER-ON RESET DELAY (tPURST)
Note: tPURST is set to 200ms as factory default. Watchdog
Timer bits are shipped disabled.
0
0
1
1
0
1
0
1
50ms
200ms (factory setting)
400ms
Fault Detection Register (FDR)
The Fault Detection Register provides the user the status of
what causes the system reset active. The Manual Reset
Fail, Watchdog Timer Fail and Three Low Voltage Fail bits
are volatile.
800ms
WD1, WD0: Watchdog Timer Bits (Nonvolatile)
The bits WD1 and WD0 control the period of the Watchdog
Timer. The options are shown in Table 3.
7
6
5
4
3
2
1
0
LV1F
LV2F
LV3F
WDF
MRF
0
0
0
TABLE 3. WATCHDOG TIMER OPTIONS
WD1
WD0
WATCHDOG TIME OUT PERIOD
The FDR is accessed with a special preamble in the slave
byte (1011) and is located at address 0FFh. It can only be
modified by performing a byte write operation directly to the
address of the register and only one data byte is allowed for
each register write operation.
0
0
1
1
0
1
0
1
1.4s
200ms
25ms
Disabled (factory setting)
There is no need to set the WEL or RWEL in the control
register to access this FDR.
Writing to the Control Registers
At power-up, the FDR is defaulted to all “0”. The system
needs to initialize this register to all “1” before the actual
monitoring can take place. In the event of any one of the
monitored sources fail, the corresponding bit in the register
will change from a “1” to a “0” to indicate the failure. At this
moment, the system should perform a read to the register
and note the cause of the reset. After reading the register,
the system should reset the register back to all “1” again.
The state of the FDR can be read at any time by performing
a random read at address 0FFh, using the special preamble.
Changing any of the nonvolatile bits of the control and trickle
registers requires the following steps:
• Write a 02H to the Control Register to set the Write Enable
Latch (WEL). This is a volatile operation, so there is no
delay after the write (operation preceded by a start and
ended with a stop).
• Write a 06H to the Control Register to set the Register
Write Enable Latch (RWEL) and the WEL bit. This is also
a volatile cycle. The zeros in the data byte are required
(operation proceeded by a start and ended with a stop).
The FDR can be read by performing a random read at 0FFh
address of the register at any time. Only one byte of data is
read by the register read operation.
• Write one byte value to the Control Register that has all
the control bits set to the desired state. The Control
register can be represented as qxys 001r in binary, where
xy are the WD bits, s is the BP bit and qr are the power-up
FN8114.2
August 25, 2008
11
X40030, X40031, X40034, X40035
MRF: Manual Reset Fail Bit (Volatile)
Serial Start Condition
The MRF bit will be set to “0” when Manual Reset input goes
active.
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The
device continuously monitors the SDA and SCL lines for the
start condition and will not respond to any command until
this condition has been met. See Figure 8.
WDF: Watchdog Timer Fail Bit (Volatile)
The WDF bit will be set to “0” when the WDO goes active.
LV1F: Low V Reset Fail Bit (Volatile)
CC
Serial Stop Condition
The LV1F bit will be set to “0” when VCC (V1MON) falls
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA when SCL is
HIGH. The stop condition is also used to place the device
into the Standby power mode after a read sequence. A stop
condition can only be issued after the transmitting device
has released the bus. See Figure 8.
below VTRIP1
.
LV2F: Low V2MON Reset Fail Bit (Volatile)
The LV2F bit will be set to “0” when V2MON falls below
VTRIP2
.
LV3F: Low V3MON Reset Fail Bit (Volatile)
Serial Acknowledge
The LV3F bit will be set to “0” when the V3MON falls below
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting 8-bits.
During the ninth clock cycle, the receiver will pull the SDA
line LOW to acknowledge that it received the 8-bits of data.
See Figure 9.
VTRIP3
.
Serial Interface
Interface Conventions
The device supports a bidirectional bus oriented protocol. The
protocol defines any device that sends data onto the bus as a
transmitter, and the receiving device as the receiver. The
device controlling the transfer is called the master and the
device being controlled is called the slave. The master always
initiates data transfers, and provides the clock for both
transmit and receive operations. Therefore, the devices in this
family operate as slaves in all applications.
The device will respond with an acknowledge after
recognition of a start condition and if the correct Device
Identifier and Select bits are contained in the Slave Address
Byte. If a write operation is selected, the device will respond
with an acknowledge after the receipt of each subsequent
8-bit word. The device will acknowledge all incoming data
and address bytes, except for the Slave Address Byte when
the Device Identifier and/or Select bits are incorrect.
Serial Clock and Data
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are reserved for
indicating start and stop conditions. See Figure 7.
.
SCL
SDA
DATA STABLE
DATA CHANGE
DATA STABLE
FIGURE 7. VALID DATA CHANGES ON THE SDA BUS
SCL
SDA
START
STOP
FIGURE 8. VALID START AND STOP CONDITIONS
FN8114.2
August 25, 2008
12
X40030, X40031, X40034, X40035
SCL FROM
MASTER
1
8
9
DATA OUTPUT FROM
TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
FIGURE 9. ACKNOWLEDGE RESPONSE FROM RECEIVER
In the read mode, the device will transmit 8-bits of data,
release the SDA line, then monitor the line for an
operation. If the device is still busy with the high voltage
cycle then no ACK will be returned. If the device has
completed the write operation, an ACK will be returned and
the host can then proceed with the read or write operation.
See Figure 10.
acknowledge. If an acknowledge is detected and no stop
condition is generated by the master, the device will continue
to transmit data. The device will terminate further data
transmissions if an acknowledge is not detected. The master
must then issue a stop condition to return the device to
Standby mode and place the device into a known state.
BYTE LOAD
COMPLETED BY
ISSUING STOP.
ENTER ACK POLLING
Serial Write Operations
Byte Write
ISSUE START
For a write operation, the device requires the Slave Address
Byte and a Word Address Byte. This gives the master access
to any one of the words in the array. After receipt of the Word
Address Byte, the device responds with an acknowledge, and
awaits the next eight bits of data. After receiving the 8 bits of
the Data Byte, the device again responds with an
acknowledge. The master then terminates the transfer by
generating a stop condition, at which time the device begins
the internal write cycle to the nonvolatile memory. During this
internal write cycle, the device inputs are disabled, so the
device will not respond to any requests from the master. The
SDA output is at high impedance. See Figure 10.
ISSUE SLAVE
ADDRESS BYTE
ISSUE STOP
(READ OR WRITE)
NO
ACK
RETURNED?
YES
HIGH VOLTAGE CYCLE
COMPLETE. CONTINUE
COMMAND SEQUENCE?
ISSUE STOP
A write to a protected block of memory will suppress the
acknowledge bit.
NO
YES
Stops and Write Modes
Stop conditions that terminate write operations must be sent
by the master after sending at least 1 full data byte plus the
subsequent ACK signal. If a stop is issued in the middle of a
data byte, or before 1 full data byte plus its associated ACK
is sent, then the device will reset itself without performing the
write. The contents of the array will not be effected.
CONTINUE NORMAL
READ OR WRITE
COMMANDSEQUENCE
PROCEED
Acknowledge Polling
FIGURE 10. ACKNOWLEDGE POLLING SEQUENCE
The disabling of the inputs during high voltage cycles can be
used to take advantage of the typical 5ms write cycle time.
Once the stop condition is issued to indicate the end of the
master’s byte load operation, the device initiates the internal
high voltage cycle. Acknowledge polling can be initiated
immediately. To do this, the master issues a start condition
followed by the Slave Address Byte for a write or read
Serial Read Operations
Read operations are initiated in the same manner as write
operations with the exception that the R/W bit of the Slave
Address Byte is set to one. There are three basic read
operations: Current Address Reads, Random Reads, and
Sequential Reads.
FN8114.2
August 25, 2008
13
X40030, X40031, X40034, X40035
S
T
A
R
T
S
S
T
O
P
SLAVE
ADDRESS
BYTE
ADDRESS
T
A
R
T
SLAVE
ADDRESS
SIGNALS
FROM THE
MASTER
SDA BUS
1
1 0 1 1 0
0
0
1
1 1 1 1 1 1 1
A
C
K
A
C
K
A
C
K
SIGNALS
FROM THE
SLAVE
DATA
FIGURE 11. RANDOM ADDRESS READ SEQUENCE
Read Operation
Data Protection
Random read operation allows the master to access any
memory location in the array. Prior to issuing the Slave
Address Byte with the R/W bit set to one, the master must
first perform a “dummy” write operation. The master issues
the start condition and the Slave Address Byte, receives an
acknowledge, then issues the Word Address Bytes. After
acknowledging receipts of the Word Address Bytes, the
master immediately issues another start condition and the
Slave Address Byte with the R/W bit set to one. This is
followed by an acknowledge from the device and then by the
8-bit word. The master terminates the read operation by not
responding with an acknowledge and then issuing a stop
condition. See Figure 11 for the address, acknowledge, and
data transfer sequence.
The following circuitry has been included to prevent
inadvertent writes:
• The WEL bit must be set to allow write operations.
• The proper clock count and bit sequence is required prior
to the stop bit in order to start a nonvolatile write cycle.
• A three step sequence is required before writing into the
Control Register to change Watchdog Timer or Block Lock
settings.
• The WP pin, when held HIGH, prevents all writes to the
array and all the Register.
SLAVE BYTE
CONTROL REGISTER
1
1
0
0
1
1
1
1
0
0
0
0
1
0
R/W
R/W
FAULT DETECTION
REGISTER
Serial Device Addressing
Slave Address Byte
WORD ADDRESS
Following a start condition, the master must output a Slave
Address Byte. This byte consists of several parts:
CONTROL REGISTER
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
FAULT DETECTION
REGISTER
• a device type identifier that is always ‘1011’.
• 1-bit (AS) that provides the device select bit. AS bit is set to
“0” as factory default.
FIGURE 12. X40030, X40031, X40034, X40035 ADDRESSING
• next bit is ‘0’.
• last bit of the slave command byte is a R/W bit. The R/W
bit of the Slave Address Byte defines the operation to be
performed. When the R/W bit is a one, then a read
operation is selected. A zero selects a write operation.
Word Address
The word address is either supplied by the master or
obtained from an internal counter. The internal counter is
undefined on a power-up condition.
Operational Notes
The device powers-up in the following state:
• The device is in the low power standby state.
• The WEL bit is set to ‘0’. In this state it is not possible to
write to the device.
• SDA pin is the input mode.
• RESET/RESET Signal is active for tPURST
.
FN8114.2
August 25, 2008
14
X40030, X40031, X40034, X40035
Absolute Maximum Ratings
Thermal Information
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on any Pin with respect to VSS . . . . . . . . . . . . .-1.0V to +7V
DC Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Chip Supply Voltage
X40030, X40031. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
X40034, X40035. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Monitored Voltage
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Commercial Temperature Range. . . . . . . . . . . . . . . . . 0°C to +75°C
Industrial Temperature Range . . . . . . . . . . . . . . . . . .-40°C to +85°C
X40030, X40031. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7V to 5.5V
X40034, X40035. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0V to 5.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
3. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested.
DC Operating Characteristics Over the recommended operating conditions, unless otherwise specified.
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 3)
(Note 7) (Note 3) UNIT
ICC1
(Note 4)
Active Supply Current (VCC) Read
VIL = VCC x 0.1, VIH = VCC x 0.9,
fSCL = 400kHz
1.5
3.0
10
mA
mA
µA
ICC2
(Note 4)
Active Supply Current (VCC) Write
Standby Current (VCC) AC (WDT off)
ISB1
(Note 4)
VIL = VCC x 0.1
IH = VCC x 0.9
SCL, fSDA = 400kHz
6
V
f
ISB2
(Note 5)
Standby Current (VCC) DC (WDT on)
Input Leakage Current (SCL, MR, WP)
VSDA = VSCL = VCC
Others = GND or VCC
25
30
µA
ILI
VIL = GND to VCC
10
10
µA
µA
ILO
Output Leakage Current (SDA, V2FAIL, V3FAIL, WDO, VSDA = GND to VCC
RESET)
Device is in Standby (Note 5)
VIL
(Note 6)
Input LOW Voltage (SDA, SCL, MR, WP)
-0.5
VCC x 0.3
VCC + 0.5
V
V
VIH
Input HIGH Voltage (SDA, SCL, MR, WP)
VCC x 0.7
(Note 6)
VHYS
Schmitt Trigger Input Hysteresis
(Note 9)
Fixed Input Level
0.2
V
V
V
VCC Related Level
0.05 x VCC
VOL
Output LOW Voltage (SDA, RESET/RESET, LOWLINE, IOL = 3.0mA (2.7V to 5.5V)
0.4
V2FAIL, V3FAIL, WDO)
I
OL = 1.8mA (2.7V to 3.6V)
IOH = -1.0mA (2.7V to 5.5V)
OH = -0.4mA (2.7V to 3.6V)
VOH
Output (RESET, LOWLINE) HIGH Voltage
VCC – 0.8
VCC – 0.4
V
I
VCC SUPPLY
VTRIP1
(Note 8)
VCC Trip Point Voltage Range
2.0
4.75
4.65
V
V
X40030, X40031-A, X40034,
X40035
4.55
4.6
X40030, X40031-B
X40030, X40031-C
4.35
2.85
4.4
2.9
4.45
2.95
V
V
SECOND SUPPLY MONITOR
IV2 V2MON Current
15
µA
FN8114.2
August 25, 2008
15
X40030, X40031, X40034, X40035
DC Operating Characteristics Over the recommended operating conditions, unless otherwise specified. (Continued)
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
X40030, X40031
(Note 3)
(Note 7) (Note 3) UNIT
VTRIP2
(Note 8)
V2MON Trip Point Voltage Range
1.7
0.9
4.75
3.5
V
V
X40034, X40035
X40030, X40031-A
X40030, X40031-B
X40030, X40031-C
X40034, X40035-A and B
X40034, X40035-C
2.85
2.55
2.15
1.25
0.95
2.9
2.6
2.2
1.3
1.0
2.95
2.65
2.25
1.35
1.05
5
V
V
V
V
V
tRPD2
VTRIP2 to V2FAIL
µs
(Note 9)
THIRD SUPPLY MONITOR
IV3
V3MON Current
15
4.75
1.75
3.15
2.95
5
µA
V
VTRIP3
(Note 8)
V3MON Trip Point Voltage Range
1.7
X40030, X40031
1.65
3.05
2.85
1.7
3.1
2.9
V
X40034, X40035-A
X40034, X40035-B and C
V
V
tRPD3
VTRIP3 to V3FAIL
µs
(Note 9)
NOTES:
4. The device enters the Active state after any start, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave Address
Byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation.
5. The device goes into Standby: 200ns after any stop, except those that initiate a high voltage write cycle; tWC after a stop that initiates a high
voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte.
6. VIL Min. and VIH Max. are for reference only and are not tested.
7. At +25°C, VCC = 3V
8. See ordering information for standard programming levels. For custom programmed levels, contact factory.
9. Based on characterization data.
Equivalent Input Circuit for VxMON (x = 1, 2, 3)
R
ΔV = 100mV
VxMON
ΔV
V
ref
+
–
OUTPUT PIN
V
REF
C
t
= 5µs WORST CASE
RPDX
Capacitance
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 3)
UNIT
pF
COUT
CIN
Output Capacitance (SDA, RESET/RESET, LOWLINE, V2FAIL,V3FAIL, WDO)
Input Capacitance (SCL, WP, MR)
VOUT = 0V
VIN = 0V
8
6
pF
FN8114.2
August 25, 2008
16
X40030, X40031, X40034, X40035
Equivalent AC Output Load Circuit For
Symbol Table
V = 5V
cc
WAVEFORM
INPUTS
OUTPUTS
V
5V
V2MON, V3MON
CC
Must be
steady
Will be
steady
4.6kΩ
4.6kΩ
2.06kΩ
Ma y change
from LO W
to HIGH
Will change
from LO W
to HIGH
RESET
WDO
V2FAIL,
V3FAIL
SDA
Ma y change
from HIGH
to LOW
Will change
from HIGH
to LOW
30pF
30pF
30pF
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
AC Test Conditions
N/A
Center Line
is High
Impedance
Input pulse levels
VCC x 0.1 to VCC x 0.9
10ns
Input rise and fall times
Input and output timing levels
Output load
V
CC x 0.5
Standard output load
AC Characteristics
MIN
MAX
SYMBOL
PARAMETER
(Note 3)
(Note 3)
UNIT
kHz
ns
fSCL
tIN
SCL Clock Frequency
400
0.9
Pulse Width Suppression Time at Inputs
SCL LOW to SDA Data Out Valid
Time the Bus Free Before Start of New Transmission
Clock LOW Time
50
0.1
1.3
1.3
0.6
0.6
0.6
100
0
tAA
µs
tBUF
µs
tLOW
tHIGH
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tDH
µs
Clock HIGH Time
µs
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
µs
µs
ns
Data In Hold Time
µs
Stop Condition Setup Time
Data Output Hold Time
0.6
50
µs
ns
tR
SDA and SCL Rise Time
20 + 0.1Cb
(Note 10)
300
300
ns
tF
SDA and SCL Fall Time
20 + 0.1Cb
(Note 10)
ns
tSU:WP
tHD:WP
Cb
WP Setup Time
0.6
0
µs
µs
pF
WP Hold Time
Capacitive Load for Each Bus Line
400
NOTE:
10. Cb = total capacitance of one bus line in pF
FN8114.2
August 25, 2008
17
X40030, X40031, X40034, X40035
Timing Diagrams
Bus Timing
t
t
LOW
tHIGH
tR
F
SCL
t
SU:DAT
t
t
t
SU:STO
SU:STA
HD:DAT
t
HD:STA
SDA IN
t
t
DH
t
AA
BUF
SDA OUT
WP Pin Timing
START
SCL
CLK 1
CLK 9
SLAVE ADDRESS BYTE
SDA IN
WP
t
t
HD:WP
SU:WP
Write Cycle Timing
SCL
TH
ACK
SDA
8
BIT OF LAST BYTE
t
WC
STOP
START
CONDITION
CONDITION
Nonvolatile Write Cycle Timing
MIN
MAX
SYMBOL
PARAMETER
(Note 3)
TYP
(Note 3)
UNIT
tWC
Write Cycle Time
5
10
ms
(Note 11)
NOTE:
11. tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the
minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
FN8114.2
August 25, 2008
18
X40030, X40031, X40034, X40035
Power Fail Timings
V
TRIPX
t
t
RPDL
RPDL
V
CC
[
[
t
RPDX
t
V2MON OR
RPDX
t
RPDL
[
V3MON
t
RPDX
t
F
LOWLINE OR
V2FAIL OR
t
R
V
RVALID
[
V3FAIL
X = 2, 3
RESET/RESET/MR Timings
V
TRIP1
V
CC
t
t
PURST
PURST
t
RPD1
t
F
t
R
RESET
V
RVALID
RESET
MR
t
MD
t
IN1
Low Voltage and Watchdog Timings Parameters (@ +25°C, V = 5V)
CC
MIN
TYP
MAX
SYMBOL
PARAMETERS
(Note 3) (Note 12)
(Note 3)
UNIT
,
tRPD1 tRPDL VTRIP1 to RESET/RESET (Power-down only), VTRIP1 to LOWLINE
(Note 13)
5
µs
t LR
LOWLINE to RESET/RESET Delay (Power-down Only) [= tRPD1 - tRPDL
VTRIP2 to V2FAIL, or VTRIP3 to V3FAIL (x = 2, 3)
]
500
ns
µs
tRPDX
5
(Note 13)
tPURST
Power-on Reset Delay
PUP1 = 0, PUP0 = 0
50
ms
(Note 13)
PUP1 = 0, PUP0 = 1 (Factory Setting)
PUP1 = 1, PUP0 = 0
200
ms
ms
400
(Note 13)
PUP1 = 1, PUP0 = 1
800
ms
(Note 13)
FN8114.2
August 25, 2008
19
X40030, X40031, X40034, X40035
Low Voltage and Watchdog Timings Parameters (@ +25°C, V
= 5V) (Continued)
CC
MIN
TYP
MAX
SYMBOL
tF
PARAMETERS
VCC,V2MON, V3MON, Fall Time
(Note 3) (Note 12)
(Note 3)
UNIT
mV/µs
mV/µs
V
20
20
1
tR
VCC, V2MON, V3MON, Rise Time
Reset Valid VCC
VRVALID
tMD
MR to RESET/RESET Delay (activation only)
Pulse Width for MR
500
5
ns
tin1
µs
tWDO
Watchdog Timer Period
WD1 = 0, WD0 = 0
1.4
200
25
s
WD1 = 0, WD0 = 1
ms
ms
WD1 = 1, WD0 = 0
WD1 = 1, WD0 = 1 (Factory Setting)
Watchdog Reset Time Out Delay
WD1 = 0, WD0 = 0
OFF
tRST1
100
200
300
ms
WD1 = 0, WD0 = 1
tRST2
tRSP
NOTES:
Watchdog Reset Time Out Delay WD1 = 1, WD0 = 0
Watchdog Timer Restart Pulse Width
12.5
1
25
37.5
ms
µs
12. VCC = 5V at +25°C.
13. Values based on characterization data only.
Watchdog Time Out for 2-Wire Interface
START
START
CLOCKIN (0 OR 1)
t
RSP
< t
WDO
SCL
SDA
t
t
t
RST
RST
WDO
WDO
WDT
RESTART
START
MINIMUM SEQUENCE TO RESET WDT
SCL
SDA
FN8114.2
August 25, 2008
20
X40030, X40031, X40034, X40035
V
Set/Reset Conditions
TRIPX
(V
)
V
/V2MON/V3MON
TRIPX
CC
t
THD
V
t
P
TSU
WDO
t
VPS
t
VPO
t
VPH
7
SCL
SDA
0
0
7
0
7
*
t
WC
A0h
START
00h
RESETS V
01H*
09H*
0DH*
03H*
0BH*
0FH*
TRIP1
SETS V
SETS V
SETS V
TRIP1
RESETS V
RESETS V
TRIP2
TRIP2
TRIP3
TRIP3
* ALL OTHERS RESERVED
VTRIP1, VTRIP2, VTRIP3 Programming Specifications VCC = 2.0V to 5.5V; Temperature = +25°C
MIN
MAX
PARAMETER
tVPS
DESCRIPTION
(Note 3) (Note 3) UNIT
WDO Program Voltage Setup Time
WDO Program Voltage Hold Time
VTRIPx Level Setup Time
10
10
10
10
10
1
µs
µs
µs
µs
ms
ms
V
tVPH
tTSU
tTHD
VTRIPx Level Hold (stable) Time
VTRIPx Program Cycle
tWC
tVPO
Program Voltage Off Time Before Next Cycle
Programming Voltage
VP
15
2.0
1.7
0.9
1.7
-25
10
18
VTRAN1
VTRAN2
VTRAN2A
VTRAN3
Vtv
VTRIP1 Set Voltage Range
4.75
4.75
3.5
V
VTRIP2 Set Voltage Range - X40030, X40031
VTRIP2 Set Voltage Range - X40034, X40035
VTRIP3 Set Voltage Range
V
V
4.75
+25
V
VTRIPx Set Voltage Variation After Programming (-40 to +85°C).
WDO Program Voltage Setup Time
mV
µs
tVPS
FN8114.2
August 25, 2008
21
X40030, X40031, X40034, X40035
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M
C A B
e
H
C
A2
A1
GAUGE
PLANE
SEATING
PLANE
0.010
L
4° ±4°
0.004 C
b
0.010 M
C
A
B
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
SO24
(SOL-24)
SO28
(SOL-28)
SYMBOL
SO-8
0.068
0.006
0.057
0.017
0.009
0.193
0.236
0.154
0.050
0.025
0.041
0.013
8
SO-14
0.068
0.006
0.057
0.017
0.009
0.341
0.236
0.154
0.050
0.025
0.041
0.013
14
(SOL-20)
0.104
0.007
0.092
0.017
0.011
0.504
0.406
0.295
0.050
0.030
0.056
0.020
20
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.068
0.006
0.057
0.017
0.009
0.390
0.236
0.154
0.050
0.025
0.041
0.013
16
0.104
0.007
0.092
0.017
0.011
0.406
0.406
0.295
0.050
0.030
0.056
0.020
16
0.104
0.007
0.092
0.017
0.011
0.606
0.406
0.295
0.050
0.030
0.056
0.020
24
0.104
0.007
0.092
0.017
0.011
0.704
0.406
0.295
0.050
0.030
0.056
0.020
28
-
±0.003
±0.002
±0.003
±0.001
±0.004
±0.008
±0.004
Basic
-
-
-
c
-
D
1, 3
E
-
E1
e
2, 3
-
L
±0.009
Basic
-
L1
h
-
Reference
Reference
-
N
-
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
FN8114.2
August 25, 2008
22
X40030, X40031, X40034, X40035
Thin Shrink Small Outline Package Family (TSSOP)
0.25 M C A B
MDP0044
THIN SHRINK SMALL OUTLINE PACKAGE FAMILY
D
A
(N/2)+1
N
MILLIMETERS
SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE
PIN #1 I.D.
A
A1
A2
b
1.20
0.10
0.90
0.25
0.15
5.00
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
5.00
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
6.50
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
7.80
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
9.70
6.40
4.40
0.65
0.60
1.00
Max
±0.05
E
E1
±0.05
0.20 C B A
+0.05/-0.06
+0.05/-0.06
±0.10
2X
1
(N/2)
N/2 LEAD TIPS
B
c
TOP VIEW
D
E
Basic
E1
e
±0.10
0.05
H
Basic
e
C
L
±0.15
L1
Reference
Rev. F 2/07
SEATING
PLANE
0.10 M C A B
b
NOTES:
0.10 C
N LEADS
1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
SIDE VIEW
2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.
SEE DETAIL “X”
3. Dimensions “D” and “E1” are measured at dAtum Plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
END VIEW
L1
A2
A
GAUGE
PLANE
0.25
L
A1
0° - 8°
DETAIL X
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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FN8114.2
August 25, 2008
23
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