X4003M8Z-27A [INTERSIL]
Selectable watchdog timer;
| 型号： | X4003M8Z-27A |
| 厂家： | 
Intersil |
| 描述： | Selectable watchdog timer |
| 文件： | 总16页 (文件大小：332K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X4003, X4005
June 30, 2008
FN8113.2
CPU Supervisor
Features
These devices combine three popular functions; Power-on
Reset Control, Watchdog Timer and Supply Voltage
Supervision. This combination lowers system cost, reduces
board space requirements and increases reliability.
• Selectable watchdog timer
- Select 200ms, 600ms, 1.4s, off
• Low VCC detection and reset assertion
- Five standard reset threshold voltages nominal 4.62V,
4.38V, 2.92V, 2.68V, 1.75V
Applying power to the device activates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and oscillator to stabilize
before the processor can execute code.
- Adjust low VCC reset threshold voltage using special
programming sequence
- Reset signal valid to VCC = 1V
• Low power CMOS
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcontroller
fails to restart a timer within a selectable time out interval,
the device activates the RESET/RESET signal. The user
selects the interval from three preset values. Once selected,
the interval does not change, even after cycling the power.
- 12µA typical standby current, watchdog on
- 800nA typical standby current watchdog off
- 3mA active current
• 400kHz I2C interface
• 1.8V to 5.5V power supply operation
The device’s low VCC detection circuitry protects the user’s
system from low voltage conditions, resetting the system
when VCC falls below the minimum VCC trip point.
RESET/RESET is asserted until VCC returns to proper
operating level and stabilizes. Five industry standard VTRIP
thresholds are available; however, Intersil’s unique circuits
allow the threshold to be reprogrammed to meet custom
requirements, or to fine-tune the threshold for applications
requiring higher precision.
• Available packages
- 8 Ld SOIC
- 8 Ld MSOP
• Pb-free available (RoHS compliant)
Pinout
X4003, X4005
(8 LD SOIC, MSOP)
TOP VIEW
V
1
2
3
4
8
7
6
5
NC
NC
CC
WP
SCL
RESET/RESET*
V
SDA
SS
*RESET APPLIES TO X4003
RESET APPLIES TO X4005
Block Diagram
WATCHDOG TRANSITION
DETECTOR
WATCHDOG
TIMER RESET
WP
RESET (X4003)
RESET (X4005)
DATA
SDA
CONTROL
REGISTER
REGISTER
COMMAND
DECODE AND
CONTROL
LOGIC
RESET AND
WATCHDOG
TIMEBASE
SCL
V
THRESHOLD
CC
RESET LOGIC
POWER-ON AND
LOW VOLTAGE
V
RESET
GENERATION
+
-
CC
V
TRIP
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2006, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X4003, X4005
Ordering Information
PART NUMBER
PART NUMBER
RESET
RESET
PART
PART
VCC RANGE VTRIP RANGE TEMP. RANGE
(ACTIVE LOW) MARKING (ACTIVE HIGH) MARKING
(V)
(V)
(°C)
PACKAGE
8 Ld MSOP
PKG. DWG. #
X4003M8-4.5A ACH X4005M8-4.5A ACQ
4.5 to 5.5
4.5 to 4.75
0 to +70
M8.118
(3.0mm)
X4003M8Z-4.5A DAH
(Note)
X4005M8Z-4.5A DAP
(Note)
0 to +70
0 to +70
0 to +70
-40 to +85
-40 to +85
-40 to +85
-40 to +85
0 to +70
0 to +70
0 to +70
0 to +70
-40 to +85
-40 to +85
-40 to +85
-40 to +85
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
8 Ld MSOP
(3.0mm) (Pb-free)
M8.118
X4003S8-4.5A
X4003 AL X4005S8-4.5A
X4005 AL
8 Ld SOIC
(150 mil)
MDP0027
MDP0027
M8.118
X4003S8Z-4.5A
(Note)
X4003 ZAL X4005S8Z-4.5A X4005 ZAL
(Note)
8 Ld SOIC
(150 mil) (Pb-free)
X4003M8I-4.5A
ACI
X4005M8I-4.5A ACR
8 Ld MSOP
(3.0mm)
X4003M8IZ-4.5A DAD
(Note)
X4005M8IZ-4.5A DAM
(Note)
8 Ld MSOP
(3.0mm) (Pb-free)
M8.118
X4003S8I-4.5A
X4003 AM X4005S8I-4.5A
X4005 AM
8 Ld SOIC
(150 mil)
MDP0027
MDP0027
M8.118
X4003S8IZ-4.5A X4003 ZAM X4005S8IZ-4.5A X4005 ZAM
(Note)
8 Ld SOIC
(150 mil) (Pb-free)
(Note)
X4003M8
ACJ
X4005M8
ACS
4.25 to 4.5
8 Ld MSOP
(3.0mm)
X4003M8Z (Note) DAE
X4005M8Z (Note) DER
8 Ld MSOP
(3.0mm) (Pb-free)
M8.118
X4003S8
X4003
X4005S8
X4005
8 Ld SOIC
(150 mil)
MDP0027
MDP0027
M8.118
X4003S8Z (Note) X4003 Z
X4005S8Z (Note) X4005 Z
8 Ld SOIC
(150 mil) (Pb-free)
X4003M8I
ACK
X4005M8I
ACT
8 Ld MSOP
(3.0mm)
X4003M8IZ (Note) DAA
X4005M8IZ
(Note)
DAJ
8 Ld MSOP
(3.0mm) (Pb-free)
M8.118
X4003S8I
X4003 I
X4005S8I
X4005 I
X4005 ZI
ACU
8 Ld SOIC
(150 mil)
MDP0027
MDP0027
M8.118
X4003S8IZ (Note) X4003 ZI
X4005S8IZ
(Note)
8 Ld SOIC
(150 mil) (Pb-free)
X4003M8-2.7A
ACL
X4005M8-2.7A
2.7 to 5.5
2.85 to 3.0
8 Ld MSOP
(3.0mm)
X4003M8Z-2.7A DAG
(Note)
X4005M8Z-2.7A DAO
(Note)
8 Ld MSOP
(3.0mm) (Pb-free)
M8.118
X4003S8-2.7A
X4003 AN X4005S8-2.7A
X4005 AN
8 Ld SOIC
(150 mil)
MDP0027
MDP0027
M8.118
X4003S8Z-2.7A
(Note)
X4003 ZAN X4005S8Z-2.7A X4005 ZAN
(Note)
8 Ld SOIC
(150 mil) (Pb-free)
X4003M8-2.7
ACN
X4005M8-2.7
ACW
2.55 to 2.7
8 Ld MSOP
(3.0mm)
X4003M8Z-2.7
(Note)
DAF
X4005M8Z-2.7
(Note)
DAN
8 Ld MSOP
(3.0mm) (Pb-free)
M8.118
X4003S8-2.7
X4003 F
X4005S8-2.7
X4005 F
X4005 ZF
8 Ld SOIC
(150 mil)
MDP0027
MDP0027
X4003S8Z-2.7
(Note)
X4003 ZF X4005S8Z-2.7
(Note)
8 Ld SOIC
(150 mil) (Pb-free)
FN8113.2
June 30, 2008
2
X4003, X4005
Ordering Information (Continued)
PART NUMBER
RESET
PART NUMBER
RESET
PART
PART
VCC RANGE VTRIP RANGE TEMP. RANGE
(ACTIVE LOW) MARKING (ACTIVE HIGH) MARKING
(V)
(V)
(°C)
PACKAGE
8 Ld SOIC
PKG. DWG. #
X4003S8I-2.7A X4003 AP X4005S8I-2.7A X4005 AP
2.7 to 3.6
2.85 to 3.0
-40 to +85
MDP0027
(150 mil)
X4003S8IZ-2.7A X4003 ZAP X4005S8IZ-2.7A X4005 ZAP
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
8 Ld SOIC
(150 mil) (Pb-free)
MDP0027
M8.118
(Note)
(Note)
X4003M8I-2.7A
ACM
X4005M8I-2.7A ACV
8 Ld MSOP
(3.0mm)
X4003M8IZ-2.7A DAC
(Note)
X4005M8IZ-2.7A DAL
(Note)
8 Ld MSOP
(3.0mm) (Pb-free)
M8.118
X4003S8I-2.7
X4003 G
X4005S8I-2.7
X4005 G
2.55 to 2.7
8 Ld SOIC
(150 mil)
MDP0027
MDP0027
M8.118
X4003S8IZ-2.7
(Note)
X4003 ZG X4005S8IZ-2.7
(Note)
X4005 ZG
ACX
8 Ld SOIC
(150 mil) (Pb-free)
X4003M8I-2.7
ACO
X4005M8I-2.7
8 Ld MSOP
(3.0mm)
X4003M8IZ-2.7
(Note)
DAB
X4005M8IZ-2.7 DAK
(Note)
8 Ld MSOP
(3.0mm) (Pb-free)
M8.118
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-
020.
Pin Descriptions
PIN
NUMBER
(MSOP)
NAME
NC
FUNCTION
1
2
3
No internal connections
No internal connections
NC
RESET/RESET Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active whenever VCC falls below
the minimum VCC sense level. It will remain active until VCC rises above the minimum VCC sense level for 250ms.
RESET/RESET goes active if the watchdog timer is enabled and SDA remains either HIGH or LOW longer than the
selectable Watchdog time out period. A falling edge of SDA, while SCL also toggles from HIGH to LOW followed by a
stop condition resets the watchdog timer. RESET/RESET goes active on power-up and remains active for 250ms after
the power supply stabilizes.
4
5
VSS
Ground
SDA
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and
may be wire ORed with other open drain or open collector outputs. This pin requires a pull-up resistor and the input buffer
is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA while SCL also toggles from HIGH to LOW follow by a stop
condition resets the watchdog timer. The absence of this procedure within the watchdog time-out period results in
RESET/RESET going active.
6
7
8
SCL
WP
Serial Clock. The serial clock controls the serial bus timing for data input and output.
Write Protect. WP HIGH prevents changes to the watchdog timer setting.
Supply voltage
VCC
FN8113.2
June 30, 2008
3
X4003, X4005
Principles of Operation
0.6µs
0.6µs
Power-on Reset
SCL
Application of power to the X4003/X4005 activates a power-on
reset circuit that pulls the RESET/RESET pin active. This signal
provides several benefits:
SDA
• It prevents the system microprocessor from starting to
operate with insufficient voltage.
START
CONDITION
STOP
CONDITION
RESTART
• It prevents the processor from operating prior to
stabilization of the oscillator.
FIGURE 1. WATCHDOG RESTART
V
Threshold Reset Procedure
CC
• It allows time for an FPGA to download its configuration
prior to initialization of the circuit.
The X4003/X4005 is shipped with a standard VCC threshold
(VTRIP) voltage. This value will not change over normal
operating and storage conditions. However, in applications
where the standard VTRIP is not exactly right, or if higher
precision is needed in the VTRIP value, the X4003/X4005
threshold may be adjusted. The procedure is described in
the following and uses the application of a nonvolatile control
signal.
When VCC exceeds the device VTRIP threshold value for
200ms (nominal) the circuit releases RESET/RESET, allowing
the system to begin operation.
Low Voltage Monitoring
During operation, the X4003/X4005 monitors the VCC level
and asserts RESET/RESET if supply voltage falls below a
preset minimum VTRIP. The RESET/RESET signal prevents
the microprocessor from operating in a power fail or
brownout condition. The RESET/RESET signal remains
active until the voltage drops below 1V. It also remains active
until VCC returns and exceeds VTRIP for 200ms.
Setting the V
Voltage
TRIP
This procedure is used to set the VTRIP to a higher voltage
value. For example, if the current VTRIP is 4.4V and the new
VTRIP is 4.6V, this procedure will directly make the change. If
the new setting is to be lower than the current setting, then it
is necessary to reset the trip point before setting the new
value.
Watchdog Timer
The watchdog timer circuit monitors the microprocessor
activity by monitoring the SDA and SCL pins. The
To set the new VTRIP voltage, apply the desired VTRIP
threshold voltage to the VCC pin and tie the WP pin to the
programming voltage VP. Then write data 00hto address
01h. The stop bit following a valid write operation initiates the
microprocessor must toggle the SDA pin HIGH to LOW
periodically, while SCL also toggles from HIGH to LOW (this
is a start bit) followed by a stop condition prior to the
expiration of the watchdog time-out period to prevent a
RESET/RESET signal. The state of two nonvolatile control
bits in the control register determine the watchdog timer
period. The microprocessor can change these watchdog
bits, or they may be “locked” by tying the WP pin HIGH.
VTRIP programing sequence. Bring WP LOW to complete the
operation.
V
3
= 15V TO 18V
P
WP
0
1
2
3
4
5
6
7
0
1
2
4
5
6
7
3
0
1
2
4
5
6
7
SCL
SDA
A0h
01h
00h
FIGURE 2. SET VTRIP LEVEL SEQUENCE (VCC = DESIRED VTRIP VALUE)
FN8113.2
June 30, 2008
4
X4003, X4005
V
3
= 15V TO 18V
P
WP
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
4
5
6
7
SCL
SDA
A0h
03h
00h
FIGURE 3. RESET VTRIP LEVEL SEQUENCE (VCC > 3V. WP = 15V TO 18V)
V
P
ADJUST
RUN
4.7k
µC
1
2
3
4
8
7
6
5
RESET/RESET
X4003
X4005
V
TRIP
ADJ.
SCL
SDA
FIGURE 4. SAMPLE VTRIP RESET CIRCUIT
Resetting the V
Voltage
TRIP
This procedure is used to set the VTRIP to a “native” voltage
level. For example, if the current VTRIP is 4.4V and the new
V
V
TRIP must be 4.0V, then the VTRIP must be reset. When
TRIP is reset, the new VTRIP is something less than 1.7V.
This procedure must be used to set the voltage to a lower
value.
To reset the new VTRIP voltage, apply the desired VTRIP
threshold voltage to the VCC pin and tie the WP pin to the
programming voltage VP. Then write 00h to address 03h.
The stop bit of a valid write operation initiates the VTRIP
programming sequence. Bring WP LOW to complete the
operation.
FN8113.2
June 30, 2008
5
X4003, X4005
V
PROGRAMMING
TRIP
EXECUTE
RESET V
TRIP
SEQUENCE
SET V = V APPLIED =
CC
CC
DESIRED V
TRIP
EXECUTE
SET V
SEQUENCE
NEW V APPLIED =
CC
OLD V APPLIED + ERROR
CC
NEW V APPLIED =
CC
TRIP
OLD V APPLIED - ERROR
CC
EXECUTE
APPLY 5V TO V
CC
CC
RESET V
TRIP
SEQUENCE
DECREMENT V
(V = V - 50MV)
CC
CC
NO
RESET PIN
GOES ACTIVE?
YES
ERROR EMAX
ERROR –EMAX
MEASURED V
DESIRED V
-
TRIP
TRIP
-EMAX < ERROR < EMAX
EMAX = MAXIMUM ALLOWABLE V
ERROR
DONE
TRIP
FIGURE 5. VTRIP PROGRAMMING SEQUENCE
and WD0. The X4003/X4005 will not acknowledge any data
bytes written after the first byte is entered.
Control Register
The control register provides the user a mechanism for
changing the watchdog timer settings. Watchdog timer bits
are nonvolatile and do not change when power is removed.
The state of the control register can be read at any time by
performing a serial read operation. Only one byte is read by
each register read operation. The X4003/X4005 resets itself
after the first byte is read. The master should supply a stop
condition to be consistent with the bus protocol, but a stop is
not required to end this operation.
The control register is accessed with a special preamble in the
slave byte (1011) and is located at address 1FFh. It can only be
modified by performing a control register write operation. Only
one data byte is allowed for each register write operation. Prior
to writing to the control register, the WEL and RWEL bits must
be set using a two step process, with the whole sequence
requiring 3 steps. See "Writing to the Control Register" on
page 7.
7
6
5
4
3
2
1
0
0
WD1
WD0
0
0
RWEL
WEL
0
RWEL: Register Write Enable Latch (Volatile)
The user must issue a stop after sending the control byte to
the register to initiate the nonvolatile cycle that stores WD1
The RWEL bit must be set to “1” prior to a write to the control
register.
FN8113.2
June 30, 2008
6
X4003, X4005
0xy0 0010 in binary, where xy are the WD bits. (Operation
WEL: Write Enable Latch (Volatile)
preceeded by a start and ended with a stop.) Since this is
a nonvolatile write cycle it will take up to 10ms to
complete. The RWEL bit is reset by this cycle and the
sequence must be repeated to change the nonvolatile bits
again. If bit 2 is set to ‘1’ in this third step (0xy0 0110) then
the RWEL bit is set, but the WD1 and WD0 bits remain
unchanged. Writing a second byte to the control register is
not allowed. Doing so aborts the write operation and
returns a NACK.
The WEL bit controls the access to the control register
during a write operation. This bit is a volatile latch that
powers up in the LOW (disabled) state. While the WEL bit is
LOW, writes the control register will be ignored (no
acknowledge will be issued after the data byte). The WEL bit
is set by writing a “1” to the WEL bit and zeroes to the other
bits of the control register. Once set, WEL remains set until
either it is reset to 0 (by writing a “0” to the WEL bit and
zeroes to the other bits of the control register) or until the
part powers up again. Writes to the WEL bit do not cause a
nonvolatile write cycle, so the device is ready for the next
operation immediately after the stop condition.
• A read operation occurring between any of the previous
operations will not interrupt the register write operation.
• The RWEL bit cannot be reset without writing to the
nonvolatile control bits in the control register, power
cycling the device or attempting a write to a write
protected block.
WD1, WD0: Watchdog Timer Bits
The bits WD1 and WD0 control the period of the watchdog
timer. The options are shown in the following:
To illustrate, a sequence of writes to the device consisting of
[02H, 06H, 02H] will reset all of the nonvolatile bits in the
control register to 0. A sequence of [02H, 06H, 06H] will
leave the nonvolatile bits unchanged and the RWEL bit
remains set.
WD1
WD0
WATCHDOG TIME-OUT PERIOD
0
0
1
1
0
1
0
1
1.4s
600ms
200ms
Serial Interface
Disabled (factory setting)
Serial Interface Conventions
The device supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter, and the receiving device as the
receiver. The device controlling the transfer is called the
master and the device being controlled is called the slave.
The master always initiates data transfers, and provides the
clock for both transmit and receive operations. Therefore,
the devices in this family operate as slaves in all
applications.
Writing to the Control Register
Changing any of the nonvolatile bits of the control register
requires the following steps:
• Write a 02H to the control register to set the write enable
latch (WEL). This is a volatile operation, so there is no
delay after the write. (Operation preceeded by a start and
ended with a stop.)
• Write a 06H to the control register to set both the register
write enable latch (RWEL) and the WEL bit. This is also a
volatile cycle. The zeros in the data byte are required.
(Operation preceeded by a start and ended with a stop.)
Serial Clock and Data
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are reserved for
indicating start and stop conditions. See Figure 6.
• Write a value to the control register that has all the control
bits set to the desired state. This can be represented as
SCL
SDA
DATA STABLE
DATA CHANGE
DATA STABLE
FIGURE 6. VALID DATA CHANGES ON THE SDA BUS
FN8113.2
June 30, 2008
7
X4003, X4005
SCL
SDA
START
STOP
FIGURE 7. VALID START AND STOP CONDITIONS
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM
TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
FIGURE 8. ACKNOWLEDGE RESPONSE FROM RECEIVER
SIGNALS
FROM THE
MASTER
BYTE
ADDRESS
SLAVE
ADDRESS
DATA
SDA BUS
1 0 1 1 0 0 1 0
1 1 1 1 1 1 1 1
A
C
K
A
C
K
A
C
K
SIGNALS
FROM THE
SLAVE
FIGURE 9. WRITE CONTROL REGISTER SEQUENCE
SDA line LOW to acknowledge that it received the eight bits
of data. Refer to Figure 8.
Serial Start Condition
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The
device continuously monitors the SDA and SCL lines for the
start condition and will not respond to any command until
this condition has been met. See Figure 7.
The device will respond with an acknowledge after
recognition of a start condition and the correct contents of
the slave address byte. Acknowledge bits are also provided
by the X4003/4005 after correct reception of the control
register address byte, after receiving the byte written to the
control register and after the second slave address in a read
question (see Figures 9 and 10).
Serial Stop Condition
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA when SCL is
HIGH. The stop condition is also used to place the device
into the Standby power mode after a read sequence. A stop
condition can only be issued after the transmitting device
has released the bus. See Figure 7.
Serial Write Operations
Slave Address Byte
Following a start condition, the master must output a slave
address byte. This byte consists of several parts:
Serial Acknowledge
• a device type identifier that is always ‘1011’.
• two bits of ‘0’.
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting eight
bits. During the ninth clock cycle, the receiver will pull the
• one bit of the slave command byte is a R/W bit. The R/W
bit of the slave address byte defines the operation to be
FN8113.2
June 30, 2008
8
X4003, X4005
performed. When the R/W bit is a one, then a read
operation is selected. A zero selects a write operation.
Refer to Figure 9.
condition. Refer to Figure 10 for the address, acknowledge,
and data transfer sequences.
Operational Notes
• After loading the entire slave address byte from the SDA
bus, the device compares the input slave byte data to the
proper slave byte. Upon a correct compare, the device
outputs an acknowledge on the SDA line.
The device powers-up in the following state:
• The device is in the low power standby state.
• The WEL bit is set to ‘0’. In this state it is not possible to
write to the device.
Write Control Register
To write to the control register, the device requires the slave
address byte and a byte address. This gives the master
access to register. After receipt of the address byte, the
device responds with an acknowledge, and awaits the data.
After receiving the 8 bits of the data byte, the device again
responds with an acknowledge. The master then terminates
the transfer by generating a stop condition, at which time the
device begins the internal write cycle to the nonvolatile memory.
During this internal write cycle, the device inputs are disabled,
so the device will not respond to any requests from the master.
If WP is HIGH, the control register cannot be changed. A write
to the control register will suppress the acknowledge bit and no
data in the control register will change. With WP low, a second
byte written to the control register terminates the operation and
no write occurs.
• SDA pin is the input mode.
RESET/RESET signal is active for tPURST
.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
• The WEL bit must be set to allow a write operation.
• The proper clock count and bit sequence is required prior
to the stop bit in order to start a nonvolatile write cycle.
• A three step sequence is required before writing into the
control register to change watchdog timer or block lock
settings.
• The WP pin, when held HIGH, prevents all writes to the
control register.
Stops and Write Modes
• Communication to the device is inhibited below the VTRIP
voltage.
Stop conditions that terminate write operations must be sent by
the master after sending 1 full data byte plus the subsequent
ACK signal. If a stop is issued in the middle of a data byte, or
before 1 full data byte plus its associated ACK is sent, then the
device will reset itself without performing the write.
• Command to change the control register are terminated if
in-progress when RESET/RESET go active.
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Serial Read Operations
Must be
steady
Will be
steady
The read operation allows the master to access the control
register. To conform to the I2C standard, prior to issuing the
slave address byte with the R/W bit set to one, the master
must first perform a “dummy” write operation. The master
issues the start condition and the slave address byte,
receives an acknowledge, then issues the byte address.
After acknowledging receipt of the byte address, the master
immediately issues another start condition and the slave
address byte with the R/W bit set to one. This is followed by
an acknowledge from the device and then by the eight bit
control register. The master terminates the read operation by
not responding with an acknowledge and then issuing a stop
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
S
S
S
T
O
P
T
T
A
R
T
SLAVE
ADDRESS
BYTE
ADDRESS
SLAVE
A
SIGNALS
FROM THE
MASTER
ADDRESS
R
T
SDA BUS
1 0 1 1 0 0 1 0
1 1 1 1 1 1 1 1
1 0 1 1 0 0 1 1
A
C
K
A
C
K
A
C
K
SIGNALS
FROM THE
SLAVE
DATA
FIGURE 10. CONTROL REGISTER READ SEQUENCE
FN8113.2
June 30, 2008
9
X4003, X4005
Absolute Maximum Ratings
Thermal Information
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Voltage on any Pin with Respect to VSS . . . . . . . . . . . .-1.0V to +7V
DC Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Commerical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
DC Operating Characteristics Over the recommended operating conditions unless otherwise specified.
CC = 1.8 TO 3.6V
V
VCC = 2.7 TO 5.5V
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
MIN
MAX
UNIT
ICC
Active Supply Current Read Control
fSCL = 400kHz nonvolatile,
SDA = Open
0.5
1.0
mA
(Note 1) Register
ICC2
Active Supply Current Write Control
fSCL = 400kHz nonvolatile,
SDA = Open
1.5
1
3.0
1
mA
µA
µA
µA
(Note 1) Register
ICC3
(Note 2)
Operating Current AC (WDT Off)
fSCL = 400kHz nonvolatile,
SDA = Open
ICC4
(Note 2)
Operating Current DC (WDT Off)
Operating Current DC (WDT On)
VSDA = VSCL = VCC
Others = GND or VSB
1
1
ICC5
VSDA = VSCL = VCC
10
20
(Note 2)
Others = GND or VSB
ILI
Input Leakage Current
Output Leakage Current
VIN = GND to VCC
10
10
10
10
µA
µA
ILO
VSDA = GND to VCC
Device is in Standby (Note 2)
VIL
(Note 3)
Input LOW Voltage
Input HIGH Voltage
-0.5
VCC x 0.3
VCC + 0.5
-0.5
VCC x 0.3
VCC + 0.5
V
V
VIH
VCC x 0.7
VCC x 0.7
(Note 3)
VHYS
Schmitt Trigger Input Hysteresis
Fixed Input Level
0.2
0.2
V
V
V
V
CC Related Level
0.05 x VCC
0.05 x VCC
VOL
Output LOW Voltage
IOL = 3.0mA (2.7V to 5.5V)
0.4
0.4
I
OL = 1.8mA (1.8V to 3.6V)
NOTES:
1. The device enters the active state after any start, and remains active until: 9 clock cycles later if the device select bits in the slave address byte
are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation.
2. The device goes into standby: 200ns after any stop, except those that initiate a nonvolatile write cycle; tWC after a stop that initiates a nonvolatile
cycle; or 9 clock cycles after any start that is not followed by the correct device select bits in the slave address byte.
3. VIL min. and VIH max. are for reference only and are not tested.
Capacitance
SYMBOL
COUT
(TA = +25°C, f = 1.0 MHz, VCC = 5V)
PARAMETER
TYP
8
UNIT
pF
TEST CONDITIONS
VOUT = 0V
Output Capacitance (SDA, RESET/RESET)
Input Capacitance (SCL, WP)
CIN
6
pF
VIN = 0V
FN8113.2
June 30, 2008
10
X4003, X4005
AC Test Conditions
Equivalent AC Load Circuit
5V
Input pulse levels
0.1VCC to 0.9VCC
10ns
5V
Input rise and fall times
Input and output timing levels
Output load
For V = 0.4V
OL
4.6k
1533
0.5VCC
and I = 3mA
OL
Standard output load
SDA
RESET
RESET
100pF
100pF
AC Electrical Specifications Over recommended operating conditions, unless otherwise specified.
100kHz
400kHz
SYMBOL
fSCL
PARAMETER
MIN
0
MAX
100
n/a
MIN
MAX
UNIT
kHz
ns
SCL Clock Frequency
0
400
tIN
Pulse Width Suppression Time at Inputs
SCL LOW to SDA Data Out Valid
Time the Bus Free Before Start of New Transmission
Clock LOW Time
n/a
0.1
4.7
4.7
4.0
4.7
4.0
250
5.0
0.6
50
50
tAA
0.9
0.1
1.3
1.3
0.6
0.6
0.6
100
0
0.9
µs
tBUF
µs
tLOW
µs
tHIGH
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tDH
Clock HIGH Time
µs
Start Condition Set-up Time
Start Condition Hold Time
Data in Setup Time
µs
µs
ns
Data in Hold Time
µs
Stop Condition Set-up Time
Data Output Hold Time
0.6
50
µs
ns
tR
SDA and SCL Rise Time
1000
300
20 + 0.1Cb
(Note 5)
300
300
ns
tF
SDA and SCL Fall Time
20 + 0.1Cb
(Note 5)
ns
tSU:WP
tHD:WP
Cb
WP Set-up Time
0.4
0
0.6
0
µs
µs
pF
WP Hold Time
Capacitive Load for Each Bus Line
400
400
NOTES:
4. Typical values are for TA = +25°C and VCC = 5.0V
5. Cb = total capacitance of one bus line in pF
FN8113.2
June 30, 2008
11
X4003, X4005
Timing Diagrams
Bus Timing
t
t
t
t
R
F
HIGH
LOW
SCL
t
SU:DAT
t
SU:STO
t
t
HD:DAT
SU:STA
t
HD:STA
SDA IN
t
t
t
BUF
A
DH
SDA OUT
WP Pin Timing
START
SCL
SDA IN
WP
CLK 1
CLK 9
SLAVE ADDRESS BYTE
t
t
HD:WP
SU:WP
Write Cycle Timing
SCL
TH
SDA
8
BIT OF LAST BYTE
ACK
t
WC
STOP
START
CONDITION
CONDITION
Nonvolatile Write Cycle Timing
TYP
SYMBOL
PARAMETER
MIN
(Note 1)
MAX
UNIT
t
WC (Note 6)
Write Cycle Time
5
10
ms
NOTE:
6. tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the
minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
FN8113.2
June 30, 2008
12
X4003, X4005
Power-Up and Power-Down Timing
V
TRIP
V
CC
t
0V
PURST
t
PURST
t
F
t
R
t
RPD
V
RVALID
RESET
RESET
V
RVALID
RESET/RESET Output Timing
SYMBOL
PARAMETER
MIN
4.5
TYP
4.62
4.38
2.92
2.62
1.75
200
500
10
MAX
4.75
4.5
UNIT
V
VTRIP
Reset Trip Point Voltage, X4003-4.5A, X4005-4.5A
Reset Trip Point Voltage, X4003, X4005
Reset Trip Point Voltage, X4003-2.7A, X4005-2.7A
Reset Trip Point Voltage, X4003-2.7, X4005-2.7
Reset Trip Point Voltage, X4003-1.8, X4005-1.8
Power-up Reset Time-out
4.25
2.85
2.55
1.7
V
3.0
V
2.7
V
1.8
V
tPURST
tRPD
tF
100
400
ms
ns
ms
ns
V
VCC Detect to Reset Output
VCC Fall Time
tR
VCC Rise Time
0.1
VRVALID
Reset Valid VCC
1
SDA vs RESET/RESET Timing
SCL
SDA
t
CST
RESET
t
t
RST
t
t
RST
WDO
WDO
RESET
RESET/RESET Output Timing
SYMBOL
PARAMETER
Watchdog Time-out Period
MIN
TYP
MAX
UNIT
tWDO
WD1 = 1, WD0 = 1 (factory setting)
WD1 = 1, WD0 = 0
OFF
200
600
1.4
100
450
1
300
800
2
ms
ms
sec
ns
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0
tCST
tRST
CS Pulse Width to Reset the Watchdog
Reset Time-out
400
100
200
400
ms
FN8113.2
June 30, 2008
13
X4003, X4005
V
Programming Timing Diagram
TRIP
V
CC
V
TRIP
(V
)
TRIP
t
t
THD
TSU
V
P
WP
t
t
t
VPH
VPS
VPO
SCL
SDA
t
RP
01h OR 03h
00h
A0h
VTRIP Programming Parameters
PARAMETER
DESCRIPTION
MIN
1
MAX
UNIT
µs
tVPS
tVPH
tTSU
tTHD
tWC
VTRIP Program Enable Voltage Set-up Time
VTRIP Program Enable Voltage Hold Time
VTRIP Set-up Time
1
µs
1
µs
VTRIP Hold (Stable) Time
10
ms
ms
µs
VTRIP Write Cycle Time
10
tVPO
tRP
VTRIP Program Enable Voltage Off Time (Between Successive Adjustments)
VTRIP Program Recovery Period (Between Successive Adjustments)
Programming Voltage
0
10
ms
V
VP
15
18
5.0
VTRAN
Vta1
Vta2
Vtr
VTRIP Programmed Voltage Range
1.7
-0.1
-25
-25
-25
V
Initial VTRIP Program Voltage Accuracy (VCC Applied - VTRIP) (Programmed At +25°C.)
+0.4
+25
+25
+25
V
Subsequent VTRIP Program Voltage Accuracy [(VCC Applied - Vta1) - VTRIP. programmed at +25°C.)
VTRIP Program Voltage Repeatability (Successive Program Operations. Programmed at +25°C.)
VTRIP Program Variation After Programming (0°C to +75°C). (Programmed at +25°C)
mV
mV
mV
Vtv
FN8113.2
June 30, 2008
14
X4003, X4005
Mini Small Outline Plastic Packages (MSOP)
N
M8.118 (JEDEC MO-187AA)
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
INCHES
MILLIMETERS
E1
E
SYMBOL
MIN
MAX
MIN
0.94
0.05
0.75
0.25
0.09
2.95
2.95
MAX
1.10
0.15
0.95
0.36
0.20
3.05
3.05
NOTES
A
A1
A2
b
0.037
0.002
0.030
0.010
0.004
0.116
0.116
0.043
0.006
0.037
0.014
0.008
0.120
0.120
-
-B-
0.20 (0.008)
INDEX
AREA
1 2
A
B
C
-
-
TOP VIEW
4X
9
0.25
(0.010)
R1
c
-
R
GAUGE
PLANE
D
3
E1
e
4
SEATING
PLANE
L
0.026 BSC
0.65 BSC
-
-C-
4X
L1
A
A2
E
0.187
0.016
0.199
0.028
4.75
0.40
5.05
0.70
-
L
6
SEATING
PLANE
L1
N
0.037 REF
0.95 REF
-
0.10 (0.004)
-A-
C
C
b
8
8
7
-H-
A1
e
R
0.003
0.003
5o
-
-
0.07
0.07
5o
-
-
-
D
0.20 (0.008)
C
R1
0
-
15o
6o
15o
6o
-
a
SIDE VIEW
C
L
0o
0o
-
E
1
-B-
Rev. 2 01/03
0.20 (0.008)
C
D
END VIEW
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
- H -
and are measured at Datum Plane.
Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (0.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
- B -
to be determined at Datum plane
-A -
10. Datums
and
.
- H -
11. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8113.2
June 30, 2008
15
X4003, X4005
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M
C A B
e
H
C
A2
A1
GAUGE
PLANE
SEATING
PLANE
0.010
L
4° ±4°
0.004 C
b
0.010 M
C
A
B
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
SYMBOL
SO-8
0.068
0.006
0.057
0.017
0.009
0.193
0.236
0.154
0.050
0.025
0.041
0.013
8
SO-14
0.068
0.006
0.057
0.017
0.009
0.341
0.236
0.154
0.050
0.025
0.041
0.013
14
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.068
0.006
0.057
0.017
0.009
0.390
0.236
0.154
0.050
0.025
0.041
0.013
16
0.104
0.007
0.092
0.017
0.011
0.406
0.406
0.295
0.050
0.030
0.056
0.020
16
0.104
0.007
0.092
0.017
0.011
0.504
0.406
0.295
0.050
0.030
0.056
0.020
20
0.104
0.007
0.092
0.017
0.011
0.606
0.406
0.295
0.050
0.030
0.056
0.020
24
0.104
0.007
0.092
0.017
0.011
0.704
0.406
0.295
0.050
0.030
0.056
0.020
28
-
0.003
0.002
0.003
0.001
0.004
0.008
0.004
Basic
-
-
-
c
-
D
1, 3
E
-
E1
e
2, 3
-
L
0.009
Basic
-
L1
h
-
Reference
Reference
-
N
-
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
FN8113.2
June 30, 2008
16
相关型号：
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