X4003M8 [INTERSIL]
CPU Supervisor; CPU监控器
Intersil 
X4003, X4005
®
Data Sheet
May 11, 2006
FN8113.1
DESCRIPTION
CPU Supervisor
These devices combine three popular functions,
Power-on Reset Control, Watchdog Timer, and Supply
Voltage Supervision. This combination lowers system
cost, reduces board space requirements, and
increases reliability.
FEATURES
• Selectable watchdog timer
—Select 200ms, 600ms, 1.4s, off
• Low V detection and reset assertion
CC
—Five standard reset threshold voltages
nominal 4.62V, 4.38V, 2.92V, 2.68V, 1.75V
Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
—Adjust low V reset threshold voltage using
CC
special programming sequence
—Reset signal valid to V = 1V
CC
• Low power CMOS
The Watchdog Timer provides an independent
protection mechanism for microcontrollers. When the
microcontroller fails to restart a timer within a select-
able time out interval, the device activates the
RESET/RESET signal. The user selects the interval
from three preset values. Once selected, the interval
does not change, even after cycling the power.
—12µA typical standby current, watchdog on
—800nA typical standby current watchdog off
—3mA active current
2
• 400kHz I C interface
• 1.8V to 5.5V power supply operation
• Available packages
—8 Ld SOIC
—8 Ld MSOP
• Pb-free plus anneal available (RoHS compliant)
The device’s low V
detection circuitry protects the
CC
user’s system from low voltage conditions, resetting the
system when V falls below the minimum V trip
CC
CC
point. RESET/RESET is asserted until V
returns to
CC
proper operating level and stabilizes. Five industry stan-
dard V thresholds are available; however, Intersil’s
TRIP
unique circuits allow the threshold to be reprogrammed
to meet custom requirements, or to fine-tune the thresh-
old for applications requiring higher precision.
BLOCK DIAGRAM
Watchdog Transition
Detector
Watchdog
Timer Reset
WP
RESET (X4003)
RESET (X4005)
Data
Register
SDA
Control
Register
Command
Decode &
Control
Reset &
Watchdog
Timebase
SCL
Logic
V
Threshold
CC
Reset logic
Power-on and
Low Voltage
V
Reset
Generation
+
-
CC
V
TRIP
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
X4003, X4005
Ordering Information
PART NUMBER
PART NUMBER
RESET
RESET
PART
PART
VCC RANGE VTRIP RANGE TEMP. RANGE
(ACTIVE LOW) MARKING (ACTIVE HIGH) MARKING
(V)
(V)
(°C)
PACKAGE
8 Ld MSOP
PKG. DWG. #
X4003M8-4.5A ACH X4005M8-4.5A ACQ
4.5 to 5.5
4.5 to 4.75
0 to 70
M8.118
(3.0mm)
X4003M8Z-4.5A DAH
(Note)
X4005M8Z-4.5A DAP
(Note)
0 to 70
-40 to 85
-40 to 85
0 to 70
8 Ld MSOP
(3.0mm) (Pb-free)
M8.118
X4003M8I-4.5A
ACI
X4005M8I-4.5A ACR
8 Ld MSOP
(3.0mm)
M8.118
X4003M8IZ-4.5A DAD
(Note)
X4005M8IZ-4.5A DAM
(Note)
8 Ld MSOP
(3.0mm) (Pb-free)
M8.118
X4003S8-4.5A
X4003 AL X4005S8-4.5A
X4005 AL
8 Ld SOIC
(150 mil)
MDP0027
MDP0027
MDP0027
MDP0027
M8.118
X4003S8Z-4.5A
(Note)
X4003 ZAL X4005S8Z-4.5A X4005 ZAL
(Note)
0 to 70
8 Ld SOIC
(150 mil) (Pb-free)
X4003S8I-4.5A
X4003 AM X4005S8I-4.5A
X4005 AM
-40 to 85
-40 to 85
0 to 70
8 Ld SOIC
(150 mil)
X4003S8IZ-4.5A X4003 ZAM X4005S8IZ-4.5A X4005 ZAM
(Note)
8 Ld SOIC
(150 mil) (Pb-free)
(Note)
X4003M8
ACJ
X4005M8
ACS
4.25 to 4.5
8 Ld MSOP
(3.0mm)
X4003M8Z (Note) DAE
X4005M8Z (Note) DER
0 to 70
8 Ld MSOP
M8.118
(3.0mm) (Pb-free)
X4003M8I
ACK
X4005M8I
ACT
-40 to 85
-40 to 85
0 to 70
8 Ld MSOP
(3.0mm)
M8.118
X4003M8IZ (Note) DAA
X4005M8IZ
(Note)
DAJ
8 Ld MSOP
(3.0mm) (Pb-free)
M8.118
X4003S8
X4003
X4005S8
X4005
8 Ld SOIC
(150 mil)
MDP0027
MDP0027
MDP0027
MDP0027
M8.118
X4003S8Z (Note) X4003 Z
X4005S8Z (Note) X4005 Z
0 to 70
8 Ld SOIC
(150 mil) (Pb-free)
X4003S8I
X4003 I
X4005S8I
X4005 I
X4005 ZI
ACU
-40 to 85
-40 to 85
0 to 70
8 Ld SOIC
(150 mil)
X4003S8IZ (Note) X4003 ZI
X4005S8IZ
(Note)
8 Ld SOIC
(150 mil) (Pb-free)
X4003M8-2.7A
ACL
X4005M8-2.7A
2.7 to 5.5
2.85 to 3.0
8 Ld MSOP
(3.0mm)
X4003M8Z-2.7A DAG
(Note)
X4005M8Z-2.7A DAO
(Note)
0 to 70
8 Ld MSOP
(3.0mm) (Pb-free)
M8.118
X4003M8I-2.7A
ACM
X4005M8I-2.7A ACV
-40 to 85
-40 to 85
0 to 70
8 Ld MSOP
(3.0mm)
M8.118
X4003M8IZ-2.7A DAC
(Note)
X4005M8IZ-2.7A DAL
(Note)
8 Ld MSOP
(3.0mm) (Pb-free)
M8.118
X4003S8-2.7A
X4003 AN X4005S8-2.7A
X4005 AN
8 Ld SOIC
(150 mil)
MDP0027
MDP0027
MDP0027
X4003S8Z-2.7A
(Note)
X4003 ZAN X4005S8Z-2.7A X4005 ZAN
(Note)
0 to 70
8 Ld SOIC
(150 mil) (Pb-free)
X4003S8I-2.7A
X4003 AP X4005S8I-2.7A
X4005 AP
-40 to 85
8 Ld SOIC
(150 mil)
FN8113.1
May 11, 2006
2
X4003, X4005
Ordering Information (Continued)
PART NUMBER
RESET
PART NUMBER
RESET
PART
PART
VCC RANGE VTRIP RANGE TEMP. RANGE
(ACTIVE LOW) MARKING (ACTIVE HIGH) MARKING
(V)
(V)
(°C)
PACKAGE
8 Ld SOIC
PKG. DWG. #
X4003S8IZ-2.7A X4003 ZAP X4005S8IZ-2.7A X4005 ZAP
2.7 to 5.5
2.85 to 3.0
-40 to 85
MDP0027
(Note)
(Note)
(150 mil) (Pb-free)
X4003M8-2.7
ACN
X4005M8-2.7
ACW
DAN
ACX
2.55 to 2.7
0 to 70
0 to 70
8 Ld MSOP
(3.0mm)
M8.118
X4003M8Z-2.7
(Note)
DAF
X4005M8Z-2.7
(Note)
8 Ld MSOP
(3.0mm) (Pb-free)
M8.118
X4003M8I-2.7
ACO
X4005M8I-2.7
-40 to 85
-40 to 85
0 to 70
8 Ld MSOP
(3.0mm)
M8.118
X4003M8IZ-2.7
(Note)
DAB
X4005M8IZ-2.7 DAK
(Note)
8 Ld MSOP
(3.0mm) (Pb-free)
M8.118
X4003S8-2.7
X4003 F
X4005S8-2.7
X4005 F
8 Ld SOIC
(150 mil)
MDP0027
MDP0027
MDP0027
MDP0027
X4003S8Z-2.7
(Note)
X4003 ZF X4005S8Z-2.7
(Note)
X4005 ZF
X4005 G
X4005 ZG
0 to 70
8 Ld SOIC
(150 mil) (Pb-free)
X4003S8I-2.7
X4003 G
X4005S8I-2.7
-40 to 85
-40 to 85
8 Ld SOIC
(150 mil)
X4003S8IZ-2.7
(Note)
X4003 ZG X4005S8IZ-2.7
(Note)
8 Ld SOIC
(150 mil) (Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN8113.1
May 11, 2006
3
X4003, X4005
PIN CONFIGURATION
8-Pin JEDEC SOIC, MSOP
VCC
1
2
3
4
8
7
6
5
NC
NC
WP
SCL
SDA
RESET
VSS
PIN DESCRIPTION
Pin
(SOIC/DIP)
Pin
TSSOP
Pin
(MSOP)
Name
Function
1
2
3
3
4
5
NC
NC
No internal connections
No internal connections
2
RESET/
RESET
Reset Output. RESET/RESET is an active LOW/HIGH, open
drain output which goes active whenever VCC falls below the min-
imum VCC sense level. It will remain active until VCC rises above
the minimum VCC sense level for 250ms. RESET/
RESET goes active if the watchdog timer is enabled and SDA re-
mains either HIGH or LOW longer than the selectable Watchdog
time out period. A falling edge of SDA, while SCL also toggles from
HIGH to LOW followed by a stop condition
resets the watchdog timer. RESET/RESET goes active on power-
up and remains active for 250ms after the power supply stabilizes.
4
5
6
7
3
4
VSS
Ground
SDA
Serial Data. SDA is a bidirectional pin used to transfer data into
and out of the device. It has an open drain output and may be wire
ORed with other open drain or open collector outputs. This pin re-
quires a pull up resistor and the input buffer is
always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA while
SCL also toggles from HIGH to LOW follow by a stop condition re-
sets the watchdog timer. The absence of this procedure within the
watchdog time out period results in RESET/RESET going active.
6
7
8
8
1
2
5
6
1
SCL
WP
Serial Clock. The serial clock controls the serial bus timing for
data input and output.
Write Protect. WP HIGH prevents changes to the watchdog
timer setting.
VCC
Supply voltage
FN8113.1
May 11, 2006
4
X4003, X4005
PRINCIPLES OF OPERATION
Power-on Reset
signal remains active until the voltage drops below 1V.
It also remains active until V returns and exceeds
CC
V
for 200ms.
TRIP
Application of power to the X4003/X4005 activates a
power-on reset circuit that pulls the RESET/RESET
pin active. This signal provides several benefits.
Watchdog Timer
The watchdog timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. The
microprocessor must toggle the SDA pin HIGH to
LOW periodically, while SCL also toggles from HIGH
to LOW (this is a start bit) followed by a stop condition
prior to the expiration of the watchdog time out period
to prevent a RESET/RESET signal. The state of two
nonvolatile control bits in the control register deter-
mine the watchdog timer period. The microprocessor
can change these watchdog bits, or they may be
“locked” by tying the WP pin HIGH.
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
– It prevents the processor from operating prior to
stabilization of the oscillator.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
When V exceeds the device V
threshold value for
CC
TRIP
200ms (nominal) the circuit releases RESET/RESET,
allowing the system to begin operation.
Figure 1. Watchdog Restart
Low Voltage Monitoring
.6µs
.6µs
During operation, the X4003/X4005 monitors the V
CC
SCL
SDA
level and asserts RESET/RESET if supply voltage falls
below a preset minimum V . The RESET/RESET
signal prevents the microprocessor from operating in a
power fail or brownout condition. The RESET/RESET
TRIP
Start
Condition
Stop
Condition
Restart
Set V
Level Sequence (V = desired V
value)
TRIP
TRIP
CC
V
3
P = 15-18V
WP
0
1 2 3 4 5 6 7
0
1
2
4 5 6 7
3
0
1
2
4 5 6 7
SCL
SDA
A0h
01h
00h
V
THRESHOLD RESET PROCEDURE
Setting the V
Voltage
CC
TRIP
This procedure is used to set the V
voltage value. For example, if the current V
to a higher
TRIP
The X4003/X4005 is shipped with a standard V
CC
is 4.4V
TRIP
threshold (V
) voltage. This value will not change
TRIP
and the new V
is 4.6V, this procedure will directly
TRIP
over normal operating and storage conditions. How-
ever, in applications where the standard V is not
make the change. If the new setting is to be lower than
the current setting, then it is necessary to reset the trip
point before setting the new value.
TRIP
exactly right, or if higher precision is needed in the
value, the X4003/X4005 threshold may be
V
TRIP
adjusted. The procedure is described below, and uses
the application of a nonvolatile control signal.
FN8113.1
May 11, 2006
5
X4003, X4005
To set the new V
voltage, apply the desired V
be reset. When V
is reset, the new V
is some-
TRIP
TRIP
TRIP
TRIP
threshold voltage to the V
the programming voltage V . Then write data 00hto
pin and tie the WP pin to
thing less than 1.7V. This procedure must be used to
set the voltage to a lower value.
CC
P
address 01h. The stop bit following a valid write opera-
To reset the new V
voltage, apply the desired
TRIP
tion initiates the V
programing sequence. Bring WP
TRIP
V
threshold voltage to the V pin and tie the WP
TRIP
CC
LOW to complete the operation.
pin to the programming voltage V . Then write 00h to
P
address 03h. The stop bit of a valid write operation ini-
Resetting the V Voltage
TRIP
tiates the V
programming sequence. Bring WP
TRIP
This procedure is used to set the V
voltage level. For example, if the current V
to a “native”
TRIP
LOW to complete the operation.
is 4.4V
TRIP
and the new V
must be 4.0V, then the V
must
TRIP
TRIP
Figure 2. Reset V
Level Sequence (V > 3V. WP = 15-18V)
TRIP
CC
VP = 15 - 18V
WP
0
1 2 3 4 5 6 7
0
1
2
3 4 5 6 7
0
1
2
3 4 5 6 7
SCL
SDA
A0h
03h
00h
Figure 3. Sample V
Reset Circuit
TRIP
VP
Adjust
Run
4.7K
µC
1
2
3
4
8
RESET/
RESET
7
6
5
X4003/05
VTRIP
Adj.
SCL
SDA
FN8113.1
May 11, 2006
6
X4003, X4005
Figure 4. V
Programming Sequence
TRIP
VTRIP Programming
Execute
Reset VTRIP
Sequence
Set VCC = VCC Applied =
Desired VTRIP
Execute
Set VTRIP
Sequence
New VCC Applied =
Old VCC applied + Error
New VCC Applied =
Old VCC Applied - Error
Execute
Reset VTRIP
Sequence
Apply 5V to VCC
Decrement VCC
(VCC = VCC - 50mV)
NO
RESET pin
goes active?
YES
Error ≥ Emax
Error ≤ –Emax
Measured VTRIP
Desired VTRIP
-
-Emax < Error < Emax
DONE
Emax = Maximum Allowable VTRIP Error
Control Register
The user must issue a stop after sending the control
byte to the register to initiate the nonvolatile cycle that
stores WD1 and WD0. The X4003/X4005 will not
acknowledge any data bytes written after the first byte
is entered.
The control register provides the user a mechanism
for changing the watchdog timer settings. watchdog
timer bits are nonvolatile and do not change when
power is removed.
The state of the control register can be read at any
time by performing a serial read operation. Only one
byte is read by each register read operation. The
X4003/X4005 resets itself after the first byte is read.
The master should supply a stop condition to be con-
sistent with the bus protocol, but a stop is not required
to end this operation.
The control register is accessed with a special preamble
in the slave byte (1011) and is located at address 1FFh.
It can only be modified by performing a control register
write operation. Only one data byte is allowed for each
register write operation. Prior to writing to the control reg-
ister, the WEL and RWEL bits must be set using a two
step process, with the whole sequence requiring 3 steps.
See "Writing to the Control Register" below.
7
6
5
4
3
2
1
0
0
WD1 WD0
0
0
RWEL WEL
0
FN8113.1
May 11, 2006
7
X4003, X4005
RWEL: Register Write Enable Latch (Volatile)
– Write a value to the control register that has all the
control bits set to the desired state. This can be rep-
resented as 0xy0 0010 in binary, where xy are the
WD bits. (Operation preceeded by a start and ended
with a stop.) Since this is a nonvolatile write cycle it
will take up to 10ms to complete. The RWEL bit is
reset by this cycle and the sequence must be
repeated to change the nonvolatile bits again. If bit 2
is set to ‘1’ in this third step (0xy0 0110) then the
RWEL bit is set, but the WD1 and WD0 bits remain
unchanged. Writing a second byte to the control reg-
ister is not allowed. Doing so aborts the write opera-
tion and returns a NACK.
The RWEL bit must be set to “1” prior to a write to the
control register.
WEL: Write Enable Latch (Volatile)
The WEL bit controls the access to the control register
during a write operation. This bit is a volatile latch that
powers up in the LOW (disabled) state. While the WEL
bit is LOW, writes the control register will be ignored
(no acknowledge will be issued after the data byte).
The WEL bit is set by writing a “1” to the WEL bit and
zeroes to the other bits of the control register. Once
set, WEL remains set until either it is reset to 0 (by
writing a “0” to the WEL bit and zeroes to the other bits
of the control register) or until the part powers up
again. Writes to the WEL bit do not cause a nonvolatile
write cycle, so the device is ready for the next opera-
tion immediately after the stop condition.
– A read operation occurring between any of the previ-
ous operations will not interrupt the register write
operation.
– The RWEL bit cannot be reset without writing to the
nonvolatile control bits in the control register, power
cycling the device or attempting a write to a write
protected block.
WD1, WD0: Watchdog Timer Bits
The bits WD1 and WD0 control the period of the
watchdog timer. The options are shown below.
To illustrate, a sequence of writes to the device con-
sisting of [02H, 06H, 02H] will reset all of the nonvola-
tile bits in the control register to 0. A sequence of [02H,
06H, 06H] will leave the nonvolatile bits unchanged
and the RWEL bit remains set.
WD1
WD0
Watchdog Time Out Period
1.4 seconds
0
0
1
1
0
1
0
1
600 milliseconds
SERIAL INTERFACE
200 milliseconds
Disabled (factory setting)
Serial Interface Conventions
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data
transfers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this fam-
ily operate as slaves in all applications.
Writing to the Control Register
Changing any of the nonvolatile bits of the control regis-
ter requires the following steps:
– Write a 02H to the control register to set the write
enable latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation pre-
ceeded by a start and ended with a stop.)
– Write a 06H to the control register to set both the
register write enable latch (RWEL) and the WEL bit.
This is also a volatile cycle. The zeros in the data
byte are required. (Operation preceeded by a start
and ended with a stop.)
Serial Clock and Data
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 5.
FN8113.1
May 11, 2006
8
X4003, X4005
Figure 5. Valid Data Changes on the SDA Bus
SCL
SDA
Data Stable
Data Change
Data Stable
Serial Start Condition
Serial Stop Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL
is HIGH. The device continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition has been
met. See Figure 6.
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the Standby power mode after a read
sequence. A stop condition can only be issued after the
transmitting device has released the bus. See Figure 6.
Figure 6. Valid Start and Stop Conditions
SCL
SDA
Start
Stop
Serial Acknowledge
The device will respond with an acknowledge after
recognition of a start condition and the correct con-
tents of the slave address byte. Acknowledge bits are
also provided by the X4003/4005 after correct recep-
tion of the control register address byte, after receiving
the byte written to the control register and after the
second slave address in a read question (See Figure 8
and See Figure 9.)
Acknowledge is a software convention used to indi-
cate successful data transfer. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to Figure 7.
FN8113.1
May 11, 2006
9
X4003, X4005
Figure 7. Acknowledge Response From Receiver
SCL from
Master
1
8
9
Data Output
from
Data Output
from Receiver
Start
Acknowledge
SERIAL WRITE OPERATIONS
Slave Address Byte
byte, the device responds with an acknowledge, and
awaits the data. After receiving the 8 bits of the data byte,
the device again responds with an acknowledge. The
master then terminates the transfer by generating a stop
condition, at which time the device begins the internal
write cycle to the nonvolatile memory. During this internal
write cycle, the device inputs are disabled, so the device
will not respond to any requests from the master. If WP is
HIGH, the control register cannot be changed. A write to
the control register will suppress the acknowledge bit and
no data in the control register will change. With WP low,
a second byte written to the control register terminates
the operation and no write occurs.
Following a start condition, the master must output a
slave address byte. This byte consists of several parts:
– a device type identifier that is always ‘1011’.
– two bits of ‘0’.
– one bit of the slave command byte is a R/W bit. The
R/W bit of the slave address byte defines the opera-
tion to be performed. When the R/W bit is a one,
then a read operation is selected. A zero selects a
write operation. Refer to Figure 8.
– After loading the entire slave address byte from the
SDA bus, the device compares the input slave byte
data to the proper slave byte. Upon a correct com-
pare, the device outputs an acknowledge on the
SDA line.
Stops and Write Modes
Stop conditions that terminate write operations must
be sent by the master after sending 1 full data byte
plus the subsequent ACK signal. If a stop is issued in
the middle of a data byte, or before 1 full data byte
plus its associated ACK is sent, then the device will
reset itself without performing the write.
Write Control Register
To write to the control register, the device requires the
slave address byte and a byte address. This gives the
master access to register. After receipt of the address
Figure 8. Write Control Register Sequence
Byte
Address
Slave
Address
Signals from
the Master
Data
SDA Bus
1 0 1 1 0 0 1 0
1 1 1 1 1 1 1 1
A
C
K
A
C
K
A
C
K
Signals from
the Slave
FN8113.1
May 11, 2006
10
X4003, X4005
Serial Read Operations
not responding with an acknowledge and then issuing
a stop condition. Refer to Figure 9 for the address,
acknowledge, and data transfer sequences.
The read operation allows the master to access the control
register. To conform to the I C standard, prior to issu-
2
ing the slave address byte with the R/W bit set to one,
the master must first perform a “dummy” write opera-
tion. The master issues the start condition and the
slave address byte, receives an acknowledge, then
issues the byte address. After acknowledging receipt
of the byte address, the master immediately issues
another start condition and the slave address byte with
the R/W bit set to one. This is followed by an acknowl-
edge from the device and then by the eight bit control
register. The master terminates the read operation by
Operational Notes
The device powers-up in the following state:
– The device is in the low power standby state.
– The WEL bit is set to ‘0’. In this state it is not possi-
ble to write to the device.
– SDA pin is the input mode.
RESET/RESET signal is active for t
.
PURST
Figure 9. Control Register Read Sequence
S
S
S
t
o
p
t
t
a
r
Slave
Address
Byte
Address
Slave
Address
Signals from
the Master
a
r
t
t
SDA Bus
1 0 1 1 0 0 1 0
1 1 1 1 1 1 1 1
1 0 1 1 0 0 1 1
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Data
Data Protection
Symbol Table
The following circuitry has been included to prevent
inadvertent writes:
WAVEFORM
INPUTS
OUTPUTS
– The WEL bit must be set to allow a write operation.
Must be
steady
Will be
steady
– The proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile
write cycle.
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
– A three step sequence is required before writing into
the control register to change watchdog timer or
block lock settings.
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
– The WP pin, when held HIGH, prevents all writes to
the control register.
N/A
Center Line
is High
Impedance
– Communication to the device is inhibited below the
V
voltage.
TRIP
– Command to change the control register are termi-
nated if in-progress when RESET/RESET go active.
FN8113.1
May 11, 2006
11
X4003, X4005
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias ................... -65°C to+135°C
Storage temperature ........................ -65°C to+150°C
Voltage on any pin with
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
respect to V ...................................... -1.0V to +7V
SS
D.C. output current...............................................5mA
Lead temperature (soldering, 10s) .................... 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
Max.
70°C
Option
-1.8
Supply Voltage Limits
1.8V to 3.6V
-40°C
+85°C
-2.7 and -2.7A
Blank and -4.5A
2.7V to 5.5V
4.5V to 5.5V
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
= 1.8 to 3.6V = 2.7 to 5.5V
V
V
CC
CC
Symbol
Parameter
Min
Max
Min
Max
Unit
Test Conditions
(1)
ICC
Active supply current
read control register
0.5
1.0
mA fSCL = 400kHz nonvolatile,
SDA = Open
(1)
ICC2
Active supply current
write control register
1.5
1
3.0
1
mA
(2)
ICC3
Operating current AC
(WDT off)
µA
(2)
ICC4
Operating current DC
(WDT off)
1
1
µA
µA
VSDA = VSCL = VCC
Others = GND or VSB
(2)
ICC5
Operating current DC
(WDT on)
10
20
ILI
Input leakage current
Output leakage current
10
10
10
10
µA
µA
VIN = GND to VCC
ILO
VSDA = GND to VCC
Device is in Standby(2)
(3)
VIL
Input LOW voltage
Input HIGH voltage
-0.5
VCC x 0.3
-0.5
VCC x 0.3
V
V
V
(3)
VIH
VCC x 0.7 VCC + 0.5 VCC x 0.7 VCC + 0.5
VHYS
Schmitt trigger input
hysteresis fixed input level
0.2
0.2
VCC related level
.05 x VCC
.05 x VCC
VOL
Output LOW voltage
0.4
0.4
V
IOL = 3.0mA (2.7-5.5V)
IOL = 1.8mA (1.8-3.6V)
Notes: (1) The device enters the active state after any start, and remains active until: 9 clock cycles later if the device select bits in the slave
address byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation.
(2) The device goes into standby: 200ns after any stop, except those that initiate a nonvolatile write cycle; tWC after a stop that initiates a
nonvolatile cycle; or 9 clock cycles after any start that is not followed by the correct device select bits in the slave address byte.
(3) VIL min. and VIH max. are for reference only and are not tested.
FN8113.1
May 11, 2006
12
X4003, X4005
CAPACITANCE (T = 25°C, f = 1.0 MHz, V = 5V)
A
CC
Symbol
Parameter
Max.
Unit
pF
Test Conditions
VOUT = 0V
(4)
COUT
Output capacitance (SDA, RESET/RESET)
Input capacitance (SCL, WP)
8
6
(4)
CIN
pF
VIN = 0V
Note: (4) This parameter is periodically sampled and not 100% tested.
EQUIVALENT A.C. LOAD CIRCUIT
A.C. TEST CONDITIONS
Input pulse levels
0.1VCC to 0.9VCC
10ns
5V
5V
4.6kΩ
Input rise and fall times
Input and output timing levels
Output load
For VOL = 0.4V
and IOL = 3 mA
0.5VCC
1533Ω
Standard output load
SDA
RESET
RESET
100pF
100pF
A.C. CHARACTERISTICS (Continued)(Over recommended operating conditions, unless otherwise specified)
100kHz
400kHz
Min.
Symbol
fSCL
Parameter
Min. Max.
Max.
Unit
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
µs
ns
ns
ns
µs
µs
pF
SCL clock frequency
0
100
n/a
0.9
0
400
tIN
Pulse width suppression time at inputs
SCL LOW to SDA data out valid
Time the bus free before start of new transmission
Clock LOW time
n/a
0.1
4.7
4.7
4.0
4.7
4.0
250
5.0
0.6
50
50
tAA
0.1
1.3
1.3
0.6
0.6
0.6
100
0
0.9
tBUF
tLOW
tHIGH
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tDH
Clock HIGH time
Start condition setup time
Start condition hold time
Data in setup time
Data in hold time
Stop condition setup time
Data output hold time
0.6
50
tR
SDA and SCL rise time
SDA and SCL fall time
WP setup time
1000 20 +.1Cb(6)
300
300
tF
300
20 +.1Cb(6)
tSU:WP
tHD:WP
Cb
0.4
0
0.6
0
WP hold time
Capacitive load for each bus line
400
400
Notes: (5) Typical values are for TA = 25°C and VCC = 5.0V
(6) Cb = total capacitance of one bus line in pF.
FN8113.1
May 11, 2006
13
X4003, X4005
TIMING DIAGRAMS
Bus Timing
tF
tHIGH
tLOW
tR
SCL
tSU:STA
SDA IN
tSU:DAT
tSU:STO
tHD:DAT
tHD:STA
tBUF
tA
tDH
SDA OUT
WP Pin Timing
Start
SCL
SDA IN
WP
Clk 1
Clk 9
Slave Address Byte
tSU:WP
tHD:WP
Write Cycle Timing
SCL
SDA
8th Bit of Last Byte
ACK
tWC
Stop
Start
Condition
Condition
Nonvolatile Write Cycle Timing
(1)
Symbol
Parameter
Min.
Typ.
Max.
Unit
(7)
tWC
Write cycle time
5
10
ms
Note: (7) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
FN8113.1
May 11, 2006
14
X4003, X4005
Power-Up and Power-Down Timing
VTRIP
VCC
0 Volts
tPURST
tPURST
tF
tR
tRPD
VRVALID
RESET
VRVALID
RESET
RESET/RESET Output Timing
Symbol
Parameter
Min.
Typ.
Max.
Unit
VTRIP
Reset trip point voltage, X4003-4.5A, X4005-4.5A
Reset trip point voltage, X4003, X4005
Reset trip point voltage, X4003-2.7A, X4005-2.7A
Reset trip point voltage, X4003-2.7, X4005-2.7
Reset trip point voltage, X4003-1.8, X4005-1.8
4.5
4.25
2.85
2.55
1.7
4.62
4.38
2.92
2.62
1.75
4.75
4.5
3.0
2.7
1.8
V
V
V
tPURST
Power-up reset time out
VCC detect to reset/output
VCC fall time
100
200
400
500
ms
ns
ms
ns
V
(8)
tRPD
(8)
tF
10
0.1
1
(8)
tR
VCC rise time
VRVALID
Reset valid VCC
Note: (8) This parameter is periodically sampled and not 100% tested.
SDA vs. RESET/RESET Timing
SCL
SDA
tCST
RESET
tWDO
tRST
tWDO
tRST
RESET
FN8113.1
May 11, 2006
15
X4003, X4005
RESET/RESET Output Timing
Symbol
Parameter
Min.
Typ.
Max.
Unit
tWDO
Watchdog time out period,
WD1 = 1, WD0 = 1 (factory setting)
WD1 = 1, WD0 = 0
WD1 = 0, WD0 = 1
OFF
200
600
1.4
100
450
1
300
800
2
ms
ms
sec
WD1 = 0, WD0 = 0
tCST
tRST
CS pulse width to reset the watchdog
Reset time out
400
100
ns
200
400
ms
V
Programming Timing Diagram
TRIP
VCC
(VTRIP
VTRIP
)
tTHD
tTSU
VP
WP
tVPH
tVPS
tVPO
SCL
SDA
tRP
01h or 03h
00h
A0h
V
Programming Parameters
TRIP
Parameter
tVPS
Description
Min. Max. Unit
VTRIP program enable voltage setup time
VTRIP program enable voltage hold time
VTRIP setup time
1
1
µs
µs
µs
ms
ms
µs
ms
V
tVPH
tTSU
tTHD
tWC
tVPO
tRP
1
VTRIP hold (stable) time
10
VTRIP write cycle time
10
VTRIP program enable voltage off time (between successive adjustments)
VTRIP program recovery period (between successive adjustments)
Programming voltage
0
10
15
1.7
VP
18
VTRAN
Vta1
VTRIP programmed voltage range
5.0
V
Initial VTRIP program voltage accuracy (VCC applied - VTRIP) (Programmed at 25°C.)
-0.1 +0.4
V
Vta2
Subsequent VTRIP program voltage accuracy [(VCC applied - Vta1) - VTRIP
Programmed at 25°C.)
.
-25
-25
-25
+25
+25
+25
mV
Vtr
VTRIP program voltage repeatability (Successive program operations. Programmed
at 25°C.)
mV
mV
Vtv
VTRIP program variation after programming (0-75°C). (programmed at 25°C)
VTRIP programming parameters are periodically sampled and are not 100% tested.
FN8113.1
May 11, 2006
16
X4003, X4005
Mini Small Outline Plastic Packages (MSOP)
N
M8.118 (JEDEC MO-187AA)
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
INCHES
MILLIMETERS
E1
E
SYMBOL
MIN
MAX
MIN
0.94
0.05
0.75
0.25
0.09
2.95
2.95
MAX
1.10
0.15
0.95
0.36
0.20
3.05
3.05
NOTES
A
A1
A2
b
0.037
0.002
0.030
0.010
0.004
0.116
0.116
0.043
0.006
0.037
0.014
0.008
0.120
0.120
-
-B-
0.20 (0.008)
INDEX
AREA
1 2
A
B
C
-
-
TOP VIEW
4X θ
9
0.25
(0.010)
R1
c
-
R
GAUGE
PLANE
D
3
E1
e
4
SEATING
PLANE
L
0.026 BSC
0.65 BSC
-
-C-
4X θ
L1
A
A2
E
0.187
0.016
0.199
0.028
4.75
0.40
5.05
0.70
-
L
6
SEATING
PLANE
L1
N
0.037 REF
0.95 REF
-
0.10 (0.004)
-A-
C
C
b
8
8
7
-H-
A1
e
R
0.003
0.003
5o
-
-
0.07
0.07
5o
-
-
-
D
0.20 (0.008)
C
R1
0
-
15o
6o
15o
6o
-
a
SIDE VIEW
C
L
0o
0o
-
α
E
1
-B-
Rev. 2 01/03
0.20 (0.008)
C
D
END VIEW
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
- H -
and are measured at Datum Plane.
Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (0.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
- B -
to be determined at Datum plane
-A -
10. Datums
and
.
- H -
11. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only.
FN8113.1
May 11, 2006
17
X4003, X4005
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M
C A B
e
H
C
A2
A1
GAUGE
PLANE
SEATING
PLANE
0.010
L
4° ±4°
0.004 C
b
0.010 M
C
A
B
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
SYMBOL
SO-8
0.068
0.006
0.057
0.017
0.009
0.193
0.236
0.154
0.050
0.025
0.041
0.013
8
SO-14
0.068
0.006
0.057
0.017
0.009
0.341
0.236
0.154
0.050
0.025
0.041
0.013
14
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.068
0.006
0.057
0.017
0.009
0.390
0.236
0.154
0.050
0.025
0.041
0.013
16
0.104
0.007
0.092
0.017
0.011
0.406
0.406
0.295
0.050
0.030
0.056
0.020
16
0.104
0.007
0.092
0.017
0.011
0.504
0.406
0.295
0.050
0.030
0.056
0.020
20
0.104
0.007
0.092
0.017
0.011
0.606
0.406
0.295
0.050
0.030
0.056
0.020
24
0.104
0.007
0.092
0.017
0.011
0.704
0.406
0.295
0.050
0.030
0.056
0.020
28
-
±0.003
±0.002
±0.003
±0.001
±0.004
±0.008
±0.004
Basic
-
-
-
c
-
D
1, 3
E
-
E1
e
2, 3
-
L
±0.009
Basic
-
L1
h
-
Reference
Reference
-
N
-
Rev. L 2/01
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8113.1
May 11, 2006
18
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