X9268 [INTERSIL]
Dual Supply/Low Power/256-Tap/2-Wire Bus; 双电源/低功耗/ 256点击/ 2 - Wire总线
| 型号： | X9268 |
| 厂家： | 
Intersil |
| 描述： | Dual Supply/Low Power/256-Tap/2-Wire Bus |
| 文件： | 总24页 (文件大小：367K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X9268
®
Dual Supply/Low Power/256-Tap/2-Wire Bus
Data Sheet
June 21, 2005
FN8172.1
DESCRIPTION
Dual Digitally-Controlled (XDCP™)
Potentiometers
The X9268 integrates
potentiometer (XDCP) on
integrated circuit.
2
digitally controlled
monolithic CMOS
a
FEATURES
• Dual–Two separate potentiometers
• 256 resistor taps/pot–0.4% resolution
• 2-Wire Serial Interface for write, read, and
transfer operations of the potentiometer
• Wiper Resistance, 100Ω typical @ V+ = 5V,
V- = -5V
• 16 Nonvolatile Data Registers for Each
Potentiometer
• Nonvolatile Storage of Multiple Wiper Positions
• Power-on Recall. Loads Saved Wiper Position
on Power-up.
The digital controlled potentiometer is implemented
using 255 resistive elements in a series array.
Between each element are tap points connected to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
2-Wire bus interface. Each potentiometer has
associated with it a volatile Wiper Counter Register
(WCR) and a four nonvolatile Data Registers that can
be directly written to and read by the user. The
contents of the WCR controls the position of the wiper
on the resistor array though the switches. Powerup
recalls the contents of the default Data Register (DR0)
to the WCR.
• Standby Current < 5µA Max
• V : ±2.7V to ±5.5V Operation
CC
• 50kΩ, 100kΩ versions of End to End Pot
Resistance
The XDCP can be used as
a three-terminal
• Endurance: 100,000 Data Changes per Bit per
Register
• 100 yr. Data Retention
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
• 24-Lead SOIC, 24-Lead TSSOP
• Low Power CMOS
• Power Supply V
= ±2.7V to ±5.5V
CC
V+ = 2.7V to 5.5V
V- = -2.7V to -5.5V
FUNCTIONAL DIAGRAM
V
R
R
H1
V
CC
H0
+
Write
Read
Transfer
Inc/Dec
Address
Data
Status
Power-on Recall
Bus
2-Wire
Bus
Interface
Wiper Counter
Registers (WCR)
Interface
and Control
Data Registers
(DR0–DR3)
Control
V
R
R
R
R
V-
SS
W0
L0
W1
L1
50kΩ
or 100kΩ versions
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1
X9268
DETAILED FUNCTIONAL DIAGRAM
R
R
R
H0
L0 W0
V
V
CC
+
Power-on
Recall
Pot 0
R
R
0
1
Wiper
Counter
Register
(WCR)
R
R
2
3
SCL
SDA
INTERFACE
AND
50k
Ω and 100kΩ
A3
A2
A1
CONTROL
CIRCUITRY
256-taps
8
Power-on
Recall
A0
Data
WP
R
R
0
1
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 1
R
R
2
3
R
R
R
V
V-
L1 H1 W1
SS
CIRCUIT LEVEL APPLICATIONS
SYSTEM LEVEL APPLICATIONS
• Vary the gain of a voltage amplifier
• Adjust the contrast in LCD displays
• Provide programmable dc reference voltages for
comparators and detectors
• Control the power level of LED transmitters in
communication systems
• Control the volume in audio circuits
• Set and regulate the DC biasing point in an RF
power amplifier in wireless systems
• Trim out the offset voltage error in a voltage ampli-
fier circuit
• Control the gain in audio and home entertainment
systems
• Set the output voltage of a voltage regulator
• Provide the variable DC bias for tuners in RF wire-
less systems
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and
Q-factor in filter circuits
• Set the operating points in temperature control
systems
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Control the operating point for sensors in industrial
systems
• Vary the frequency and duty cycle of timer ICs
• Trim offset and gain errors in artificial intelligent
systems
• Vary the dc biasing of a pin diode attenuator in RF
circuits
• Provide a control variable (I, V, or R) in feedback
circuits
FN8172.1
June 21, 2005
2
X9268
PIN CONFIGURATION
SOIC, TSSOP
A3
NC
1
2
24
23
22
21
20
19
18
17
16
SCL
NC
NC
NC
V-
A0
NC
3
NC
NC
V+
4
5
6
X9268
V
V
7
CC
SS
R
R
8
W1
L0
R
R
H0
9
H1
R
R
W0
10
15
14
L1
A2
A1
11
12
WP
13
SDA
PIN ASSIGNMENTS
Pin
(SOIC,
TSSOP)
Symbol
Function
1
NC
A0
No Connect
2
Device Address for 2-Wire bus.
No Connect
3
NC
NC
NC
V+
4
No Connect
5
No Connect
6
Analog Suppy Pin (Positive)
System Supply Voltage
Low Terminal for Potentiometer 0.
High Terminal for Potentiometer 0.
Wiper Terminal for Potentiometer 0.
Device Address for 2-Wire bus.
Hardware Write Protect
7
V
CC
8
R
L0
H0
W0
9
R
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
R
A2
WP
SDA
A1
Serial Data Input/Output for 2-Wire bus.
Device Address for 2-Wire bus.
Low Terminal for Potentiometer 1.
High Terminal for Potentiometer 1.
Wiper Terminal for Potentiometer 1.
System Ground
R
L1
H1
W1
R
R
V
SS
V-
NC
NC
NC
SCL
A3
Analog Supply Pin (Negative)
No Connect
No Connect
No Connect
Serial Clock for 2-Wire bus.
Device Address for 2-Wire bus.
FN8172.1
3
June 21, 2005
X9268
PIN DESCRIPTIONS
R
W
The wiper pin are equivalent to the wiper terminal of a
Bus Interface Pins
mechanical potentiometer. Since there are
4
potentiometers, there are 2 sets of R such that R
is the terminal of POT 0 and so on.
W
W0
SERIAL DATA INPUT/OUTPUT (SDA)
The SDA is a bidirectional serial data input/output pin
for a 2-Wire slave device and is used to transfer data
into and out of the device. It receives device address,
opcode, wiper register address and data sent from an
2-Wire master at the rising edge of the serial clock
SCL, and it shifts out data after each falling edge of
the serial clock SCL.
Bias Supply Pins
SYSTEM SUPPLY VOLTAGE (V ) AND SUPPLY
CC
GROUND (V
)
SS
The V
pin is the system ground.
pin is the system supply voltage. The V
CC
SS
It is an open drain output and may be wire-ORed with
any number of open drain or open collector outputs.
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the
guidelines for calculating typical values on the bus
pull-up resistors graph.
Analog Supply Voltages (V+ and V-)
These supplies are the analog voltage supplies for the
potentiometer. The V+ supply is tied to the wiper
switches while the V- supply is used to bias the
switches and the internal P+ substrate of the
integrated circuit. Both of these supplies set the
voltage limits of the potentiometer.
SERIAL CLOCK (SCL)
This input is used by 2-Wire master to supply 2-Wire
serial clock to the X9268.
Other Pins
NO CONNECT
DEVICE ADDRESS (A3 - A0)
No connect pins should be left open. This pins are
used for Intersil manufacturing and testing purposes.
The address inputs are used to set the least significant
3 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
Address input in order to initiate communication with
the X9268. A maximum of 8 devices may occupy the
2-Wire serial bus.
HARDWARE WRITE PROTECT INPUT (WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
Potentiometer Pins
R , R
H
L
The R and R pins are equivalent to the terminal
H
L
connections on a mechanical potentiometer. Since
there are 2 potentiometers, there are 2 sets of R and
H
R such that R and R are the terminals of POT 0
L
H0
L0
and so on.
FN8172.1
4
June 21, 2005
X9268
PRINCIPLES OF OPERATION
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
The X9268 is a integrated microcircuit incorporating
four resistor arrays and their associated registers and
counters and the serial interface logic providing direct
communication between the host and the digitally
controlled potentiometers. This section provides detail
description of the following:
(R ) output. Within each individual array only one
W
switch may be turned on at a time.
These switches are controlled by a Wiper Counter
Register (WCR). The 8-bits of the WCR (WCR[7:0])
are decoded to select, and enable, one of 256
switches (See Table 1).
– Resistor Array Description
The WCR may be written directly. These Data
Registers can the WCR can be read and written by the
host system.
– Serial Interface Description
– Instruction and Register Description.
Array Description
Power-up and Down Requirements.
The X9268 is comprised of a resistor array (See
Figure 1). Each array contains 255 discrete resistive
segments that are connected in series. The physical
ends of each array are equivalent to the fixed
At all times, the voltages on the potentiometer pins
must be less than V+ and more than V-. During power-
up and power-down, V , V+, and V- must reach their
CC
final values within 1msecs of each other. The V
ramp rate spec is always in effect.
CC
terminals of a mechanical potentiometer (R and R
H
L
inputs).
Figure 1. Detailed Potentiometer Block Diagram
One of Two Potentiometers
SERIAL DATA PATH
SERIAL
BUS
INPUT
R
H
FROM INTERFACE
CIRCUITRY
C
O
U
N
T
REGISTER 0
(DR0)
REGISTER 1
(DR1)
8
8
PARALLEL
BUS
INPUT
E
R
REGISTER 2
(DR2)
REGISTER 3
(DR3)
D
E
C
O
D
E
WIPER
COUNTER
REGISTER
(WCR)
INC/DEC
LOGIC
IF WCR = 00[H] THEN R = R
W
L
UP/DN
UP/DN
CLK
IF WCR = FF[H] THEN R = R
W
H
R
R
MODIFIED SCL
L
W
FN8172.1
5
June 21, 2005
X9268
SERIAL INTERFACE DESCRIPTION
Serial Interface
the SDA and SCL lines for the start condition and will
not respond to any command until this condition is
met. See Figure 2.
The X9268 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9268 will be considered a
slave device in all applications.
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH. See Figure 2.
Acknowledge
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW periods. SDA state changes during SCL
HIGH are reserved for indicating start and stop
conditions. See Figure 2.
Start Condition
The X9268 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9268 will respond with a final acknowledge.
See Figure 2.
All commands to the X9268 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH. The X9268 continuously monitors
Figure 2. Acknowledge Response from Receiver
SCL FROM
MASTER
1
8
9
DATA
OUTPUT
FROM
TRANSMITTER
DATA
OUTPUT
FROM
RECEIVER
START
ACKNOWLEDGE
FN8172.1
6
June 21, 2005
X9268
Acknowledge Polling
INSTRUCTION AND REGISTER DESCRIPTION
Instructions
The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms nonvolatile write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9268
initiates the internal write cycle. ACK polling, Flow 1,
can be initiated immediately. This involves issuing the
start condition followed by the device slave address. If
the X9268 is still busy with the write operation no ACK
will be returned. If the X9268 has completed the write
operation an ACK will be returned and the master can
then proceed with the next operation.
DEVICE ADDRESSING: IDENTIFICATION BYTE (ID AND A)
The first byte sent to the X9268 from the host is called
the Identification Byte. The most significant four bits of
the slave address are a device type identifier. The
ID[3:0] bits is the device id for the X9268; this is fixed
as 0101[B] (refer to Table 1).
The A[3:0] bits in the ID byte is the internal slave
address. The physical device address is defined by
the state of the A3 - A0 input pins. The slave address
is externally specified by the user. The X9268
compares the serial data stream with the address
input state; a successful compare of both address
bits is required for the X9268 to successfully continue
the command sequence. Only the device which slave
address matches the incoming device address sent
by the master executes the instruction. The A3 - A0
inputs can be actively driven by CMOS input signals
FLOW 1: ACK Polling Sequence
Nonvolatile Write
Command Completed
EnterACK Polling
Issue
START
or tied to V
or V
.
CC
SS
INSTRUCTION BYTE (I)
Issue Slave
Issue STOP
Address
The next byte sent to the X9268 contains the
instruction and register pointer information. The three
most significant bits are used provide the instruction
opcode I [3:0]. The RB and RA bits point to one of the
four Data Registers of each associated XDCP. The
least significant bit points to one of two Wiper Counter
Registers or Pots. The format is shown in Table 2.
ACK
Returned?
No
Yes
No
Further
Operation?
Register Selection
Yes
Register Selected
RB
0
RA
0
Issue
Instruction
DR0
DR1
DR2
DR3
Issue STOP
Proceed
0
1
1
0
Proceed
1
1
FN8172.1
June 21, 2005
7
X9268
Table 1. Identification Byte Format
Device Type
Identifier
Slave Address
ID3
0
ID2
1
ID1
0
ID0
1
A3
A2
A1
A0
(MSB)
(LSB)
Table 2. Instruction Byte Format
Data
Register
Selection
Instruction
Opcode
Pot Selection
(WCR Selection)
I3
I2
I1
I0
RB
RA
0
P0
(MSB)
(LSB)
Table 3. Instruction Set
Instruction
Instruction Set
I3 I2 I1 I0 RB RA
0
P0
Operation
Read Wiper Counter
Register
1
1
1
1
1
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
0
0
0
0
0
0
1/0 Read the contents of the Wiper Counter
Register pointed to by P0
Write Wiper Counter Register
0
0
1/0 Write new value to the Wiper Counter
Register pointed to by P0
Read Data Register
1/0 1/0
1/0 1/0
1/0 1/0
1/0 Read the contents of the Data Register
pointed to by P0 and RB - RA
Write Data Register
1/0 Write new value to the Data Register
pointed to by P0 and RB - RA
XFR Data Register to Wiper
Counter Register
1/0 Transfer the contents of the Data Register
pointed to by P0 and RB - RA to its
associated Wiper Counter Register
XFR Wiper Counter Register
to Data Register
1
0
1
0
1
0
0
0
1
0
0
1
0
1
0
0
1/0 1/0
1/0 1/0
1/0 1/0
0
0
0
0
1/0 Transfer the contents of the Wiper Counter
Register pointed to by P0 to the Data
Register pointed to by RB - RA
Global XFR Data Registers to
Wiper Counter Registers
0
Transfer the contents of the Data Registers
pointed to by RB - RA of all four pots to their
respective Wiper Counter Registers
Global XFR Wiper Counter
Registers to Data Register
0
Transfer the contents of both Wiper Counter
Registers to their respective data Registers
pointed to by RB - RA of all four pots
Increment/Decrement Wiper
Counter Register
0
0
1/0 Enable Increment/decrement of the Control
Latch pointed to by P0
Note: 1/0 = data is one or zero
FN8172.1
June 21, 2005
8
X9268
DEVICE DESCRIPTION
with the value in DR0 upon power-up, this may be
different from the value present at power-down.
Power-up guidelines are recommended to ensure
proper loadings of the DR0 value into the WCR (See
Design Considerations Section).
Wiper Counter Register (WCR)
The X9268 contains two Wiper Counter Registers, one
for each DCP potentiometer. The Wiper Counter
Register can be envisioned as a 8-bit parallel and
serial load counter with its outputs decoded to select
one of 256 switches along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of
four associated data registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/Decrement
instruction (See Instruction section for more details).
Finally, it is loaded with the contents of its Data
Register zero (DR0) upon power-up.
Data Registers (DR)
Each potentiometer has four 8-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the
data registers is a nonvolatile operation and will take a
maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9268 is powered-
down. Although the register is automatically loaded
Bit [7:0] are used to store one of the 256 wiper
positions (0~255).
Table 4. Wiper counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile, V).
WCR7
V
WCR6
V
WCR5
V
WCR4
V
WCR3
V
WCR2
V
WCR1
V
WCR0
V
(MSB)
(LSB)
Table 5. Data Register, DR (8-bit), Bit [7:0]: Used to store wiper positions or data (Nonvolatile, NV).
Bit 7
NV
Bit 6
NV
Bit 5
NV
Bit 4
NV
Bit 3
NV
Bit 2
NV
Bit 1
NV
Bit 0
NV
MSB
LSB
FN8172.1
June 21, 2005
9
X9268
DEVICE DESCRIPTION
Instructions
– XFR Data Register to Wiper Counter Register –
This transfers the contents of one specified Data
Register to the associated Wiper Counter Register.
Four of the nine instructions are three bytes in length.
These instructions are:
– XFR Wiper Counter Register to Data Register –
This transfers the contents of the specified Wiper
Counter Register to the specified associated Data
Register.
– Read Wiper Counter Register – read the current
wiper position of the selected potentiometer,
– Global XFR Data Register to Wiper Counter
Register – This transfers the contents of all speci-
fied Data Registers to the associated Wiper Counter
Registers.
– Write Wiper Counter Register – change current
wiper position of the selected potentiometer,
– Read Data Register – read the contents of the
selected Data Register;
– Global XFR Wiper Counter Register to Data
Register – This transfers the contents of all Wiper
Counter Registers to the specified associated Data
Registers.
– Write Data Register – write a new value to the
selected Data Register.
The basic sequence of the three byte instructions is
illustrated in Figure 4. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
INCREMENT/DECREMENT COMMAND
The final command is Increment/Decrement (Figure 5
and 6). The Increment/Decrement command is
different from the other commands. Once the
command is issued and the X9268 has responded
with an acknowledge, the master can clock the
selected wiper up and/or down in one segment steps;
thereby, providing a fine tuning capability to the host.
wiper to this action will be delayed by t
. A transfer
WRL
from the WCR (current wiper position), to a Data
Register is a write to nonvolatile memory and takes a
minimum of t
to complete. The transfer can occur
WR
between one of the four potentiometers and one of its
associated registers; or it may occur globally, where
the transfer occurs between all potentiometers and
one associated register
For each SCL clock pulse (t
) while SDA is HIGH,
HIGH
the selected wiper will move one resistor segment
towards the R terminal. Similarly, for each SCL clock
H
pulse while SDA is LOW, the selected wiper will move
one resistor segment towards the R terminal.
Four instructions require a two-byte sequence to
complete. These instructions transfer data between the
host and the X9268; either between the host and one of
the data registers or directly between the host and the
Wiper Counter Register. These instructions are:
L
See Instruction format for more details.
FN8172.1
10
June 21, 2005
X9268
Figure 3. Two-Byte Instruction Sequence
SCL
SDA
0
1
0
1
ID3 ID2 ID1 ID0
S
A2 A1 A0
S
T
A
R
T
A3
A I3 I2 I1
P0
I0
RB RA 0
A
C
K
C
K
T
O
P
Internal
Address
Instruction
Opcode
Register
Address
Pot/WCR
Address
Device ID
Figure 4. Three-Byte Instruction Sequence
SCL
SDA
0
1
0
1
0
0
S
T
A
R
T
I3
A
C
K
I1
P0
A
C
K
D7 D6 D5 D4 D3 D2 D1 D0
A
C
K
S
T
O
P
ID3 ID2
ID0
I2
I0 RB RA
ID1
A3 A2 A1 A0
Internal
Address
Device ID
WCR[7:0]
or
Data Register D[7:0]
Instruction
Opcode
Register
Address
Pot/WCR
Address
Figure 5. Increment/Decrement Instruction Sequence
SCL
0
1
0
1
SDA
0
ID3 ID2 ID1 ID0
Device ID
I1
A3 A2 A1 A0
I3
I2
I0
RB RA 0
P0
S
T
A
R
T
A
C
K
A
C
K
I
I
D
E
C
1
S
T
O
P
I
D
N
C
1
N
C
2
N
C
n
E
C
n
Internal
Address
Instruction
Opcode
Pot/WCR
Address
Register
Address
Figure 6. Increment/Decrement Timing Limits
INC/DEC
CMD
Issued
t
WRID
SCL
SDA
Voltage Out
R
W
FN8172.1
June 21, 2005
11
X9268
INSTRUCTION FORMAT
Read Wiper Counter Register (WCR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/WCR
Addresses
Wiper Position
(Sent by X9268 on SDA)
S
T
A
R
T
S
A
C
K
S
A
C
K
M S
A T
C O
K P
W
C
R
W
C
R
7
W W W W W W
C C C C C C
R R R R R R
0
1
0
1 A3 A2 A1 A0
1
0
0
1
0
0
0
P0
5
4 3 2 1 0
6
Write Wiper Counter Register (WCR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/WCR
Addresses
Wiper Position
(Sent by Master on SDA)
S
T
A
R
T
S
A
C
K
S
A
C
K
S S
A T
C O
K P
W
C
W
C
R
7
W W W W W W
C C C C C C
R R R R R R
0
1
0
1 A3 A2 A1 A0
1
0
1
0
0
0
0
P0
R
5
4 3 2 1 0
6
Read Data Register (DR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/WCR
Addresses
Wiper Position
(Sent by X9268 on SDA)
S
T
A
R
T
S
A
C
K
S
A
C
K
M S
A T
C O
K P
W
C
W
C
R
7
W W W W W W
C C C C C C
R R R R R R
0
1
0
1 A3 A2 A1 A0
1
0
1
1 RB RA
0
P0
R
5
4 3 2 1 0
6
Write Data Register (DR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/WCR
Addresses
Wiper Position
(Sent by Master on SDA)
S
T
A
R
T
S
A
C
K
S
S S
A T
C O
K P
A
C
K
W
C
W
C
R
7
W W W W W W
C C C C C C
R R R R R R
5 4 3 2 1 0
0
1
0
1 A3 A2 A1 A0
1 1 0 0 RB RA
0
P0
R
6
Global XFR Data Register (DR) to Wiper Counter Register (WCR)
S
T
A
R
T
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/WCR
Addresses
S
A
C
K
S S
A T
C O
K P
0
1
0
1
A3 A2 A1 A0
0
0
0
1
RB RA
0
0
FN8172.1
12
June 21, 2005
X9268
Global XFR Wiper Counter Register (WCR) to Data Register (DR)
S
T
A
R
T
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/WCR
Addresses
S
A
C
K
S S
A T
C O
K P
HIGH-VOLTAGE
WRITE CYCLE
0
1
0
1 A3 A2 A1 A0
1 0 0 0 RB RA 0
0
Transfer Wiper Counter Register (WCR) to Data Register (DR)
S
T
A
R
T
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/WCR
Addresses
S
A
C
K
S S
A T HIGH-VOLTAGE
C O WRITE CYCLE
P0
K P
0
1
0
1 A3 A2 A1 A0
1
1
1
0 RB RA
0
Transfer Data Register (DR) to Wiper Counter Register (WCR)
S
T
A
R
T
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/WCR
Addresses
S
A
C
K
S S
A T
C O
K P
0
1
0
1
A3 A2 A1 A0
1 1 0 1 RB RA
0
P0
Increment/Decrement Wiper Counter Register (WCR)
S Device Type
Device
Addresses
Instruction
Opcode
DR/WCR
Addresses
Increment/Decrement
(Sent by Master on SDA)
S
A
C
K
S
A
C
K
S
T
O
P
T
A
R
T
Identifier
0
1
0
1 A3 A2 A1 A0
0
0
1
0
0
0
0
P0
I/D I/D
.
.
.
.
I/D I/D
Notes: (1) “MACK”/”SACK”: stands for the acknowledge sent by the master/slave.
(2) “A3 ~ A0”: stands for the device addresses sent by the master.
(3) “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
(4) “I”: stands for the increment operation, SDA held high during active SCL phase (high).
(5) “D”: stands for the decrement operation, SDA held low during active SCL phase (high).
FN8172.1
13
June 21, 2005
X9268
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias.................... -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
Voltage on SDA, SCL or any address input
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this
specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
with respect to V ................................. -1V to +7V
SS
Voltage on V+ (referenced to V )........................10V
SS
Voltage on V- (referenced to V )........................-10V
SS
(V+) - (V-) ..............................................................12V
Any V /R ..............................................................V+
H
H
Any V /R .................................................................V-
L
L
Lead temperature (soldering, 10 seconds)........ 300°C
(10 seconds)..................................................±6mA
I
W
RECOMMENDED OPERATING CONDITIONS
(4)
Temp
Min.
0°C
Max.
+70°C
+85°C
Device
X9268
Supply Voltage (V
CC
)
Limits
Commercial
Industrial
5V ± 10%
-40°C
X9268-2.7
2.7V to 5.5V
V+
V-
2.7V to 5.5V
-2.7V to -5.5V
FN8172.1
June 21, 2005
14
X9268
POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
Parameter
End to End Resistance
End to EndResistance
End to end resistance tolerance
Power rating
Min.
Typ.
100
50
Max.
Unit
kΩ
kΩ
%
Test Conditions
T version
R
TOTAL
R
U version
TOTAL
±20
50
mW
mA
Ω
25°C, each pot
I
Wiper current
±3
W
R
R
Wiper resistance
250
150
+5.5
+5.5
-4.5
-2.7
V+
I
I
= ± 1mA, V+ = 3V; V- = -3V
= ± 1mA, V+ = 5V; V- = -5V
W
W
W
W
Wiper resistance
Ω
V+
Voltage on V+ Pin
Voltage on V- Pin
X9268
+4.5
+2.7
-5.5
-5.5
V-
V
X9268-2.7
X9268
V-
V
X9268 -2.7
V
Voltage on any V /R or V /R pin
V
dBV
%
TERM
H
H
L
L
Noise
-120
0.4
Ref: 1kHz
(4)
Resolution
(1)
(3)
Absolute linearity
Relative linearity
±1
MI
V
V
- V
w(n)(expected)
w(n)(actual)
- [V
(2)
(3)
MI
±0.6
]
w(n) + MI
w(n + 1)
Temperaturecoefficientofresistance
Ratiometric Temperature Coefficient
C /C /C Potentiometer Capacitance
W
±300
ppm/°C
ppm/°C
pF
±20
10/10/25
See Circuit #3
H
L
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(3) MI = RTOT / 255 or (R - R ) / 255, single pot
H
L
(4) During power-up V
> V , V , and V .
CC
H L W
(5) n = 0, 1, 2, …,255; m =0, 1, 2, …, 254.
FN8172.1
15
June 21, 2005
X9268
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
= 400kHz; V = +6V;
SDA = Open; (for 2-Wire, Active, Read and
Volatile Write States only)
I
I
I
V
supply current
(active)
3
mA
f
SCL
CC1
CC2
SB
CC
CC
V
supply current
5
5
mA
f
= 400kHz; V
= +6V;
CC
CC
(nonvolatile write)
SCL
SDA = Open; (for 2-Wire, Active,
Nonvolatile Write State only)
V
current (standby)
µA
VCC = +6V; VIN = VSS or VCC;
SDA = VCC; (for 2-Wire, Standby State only)
CC
I
I
Input leakage current
Output leakage current
Input HIGH voltage
Input LOW voltage
10
10
µA
µA
V
V
V
= V to V
SS CC
LI
IN
= V to V
SS CC
LO
OUT
V
V
V
V
V
x 0.7
V
+ 1
IH
CC
-1
CC
x 0.3
V
V
IL
CC
0.4
Output LOW voltage
Output HIGH voltage
V
I
= 3mA
OL
OL
OH
ENDURANCE AND DATA RETENTION
Parameter
Minimum endurance
Data retention
Min.
Units
100,000
100
Data changes per bit per register
years
CAPACITANCE
Symbol
Test
Input / Output capacitance (SDA)
Input capacitance (SCL, WP, A3, A2, A1 and A0)
Max.
Units
pF
Test Conditions
= 0V
(6)
C
C
8
6
V
IN/OUT
(6)
OUT
V = 0V
IN
pF
IN
POWER-UP TIMING
Symbol
Parameter
Power-up rate
Min.
Max.
50
Units
V/ms
ms
(6)
V
0.2
CC
Power-up to initiation of read operation
t V
CC
r
(7)
PUR
1
t
POWER-UP AND DOWN REQUIREMENTS
The are no restrictions on the sequencing of the bias supplies V , V+, and V- provided that all three supplies reach
CC
their final values within 1msec of each other. At all times, the voltages on the potentiometer pins must be less than V+
and more than V-. The recall of the wiper position from nonvolatile memory is not in effect until all supplies reach their
final value. The V
ramp rate spec is always in effect.
CC
A.C. TEST CONDITIONS
V
x 0.1 to V x 0.9
CC
Input Pulse Levels
CC
Input rise and fall times
Input and output timing level
10ns
V
x 0.5
CC
Notes: (6) This parameter is not 100% tested
(7) t and t are the delays required from the time the (last) power supply (V -) is stable until the specific instruction can be issued.
PUR
PUW
CC
These parameters are periodically sampled and not 100% tested.
FN8172.1
16
June 21, 2005
X9268
EQUIVALENT A.C. LOAD CIRCUIT
5V
3V
SPICE Macromodel
1533
Ω
867
Ω
R
TOTAL
R
R
L
H
SDA pin
SDA pin
C
C
W
C
L
L
10pF
100pF
100pF
25pF
10pF
R
W
AC TIMING
Symbol
Parameter
Min.
Max.
Units
kHz
ns
f
t
t
t
t
t
t
t
t
t
t
t
t
Clock Frequency
400
SCL
Clock Cycle Time
2500
600
1300
600
600
600
100
30
CYC
Clock High Time
ns
HIGH
LOW
SU:STA
HD:STA
SU:STO
SU:DAT
HD:DAT
R
Clock Low Time
ns
Start Setup Time
ns
Start Hold Time
ns
Stop Setup Time
ns
SDA Data Input Setup Time
SDA Data Input Hold Time
SCL and SDA Rise Time
SCL and SDA Fall Time
ns
ns
300
300
0.9
ns
ns
F
SCL Low to SDA Data Output Valid Time
SDA Data Output Hold Time
µs
ns
AA
0
50
1200
0
DH
T
Noise Suppression Time Constant at SCL and SDA inputs
Bus Free Time (Prior to Any Transmission)
A0, A1 Setup Time
ns
I
t
t
t
ns
BUF
ns
SU:WPA
HD:WPA
A0, A1 Hold Time
0
ns
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
Parameter
Typ.
Max.
Units
t
High-voltage write cycle time (store instructions)
5
10
ms
WR
XDCP TIMING
Symbol
Parameter
Min. Max. Units
t
t
Wiper response time after the third (last) power supply is stable
5
5
10
10
µs
µs
WRPO
WRL
Wiper response time after instruction issued (all load instructions)
FN8172.1
17
June 21, 2005
X9268
TIMING DIAGRAMS
Start and Stop Timing
(START)
(STOP)
t
t
F
R
SCL
t
t
t
SU:STO
SU:STA
HD:STA
t
t
F
R
SDA
Input Timing
t
t
CYC
HIGH
SCL
SDA
t
LOW
t
t
t
BUF
SU:DAT
HD:DAT
Output Timing
SCL
SDA
t
t
DH
AA
FN8172.1
18
June 21, 2005
X9268
XDCP Timing (for All Load Instructions)
(STOP)
SCL
SDA
VWx
LSB
t
WRL
Write Protect and Device Address Pins Timing
(START)
(STOP)
SCL
...
(Any Instruction)
...
SDA
...
t
t
SU:WPA
HD:WPA
WP
A0, A1
FN8172.1
19
June 21, 2005
X9268
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
+V
R
V
R
RW
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Application Circuits
Noninverting Amplifier
Voltage Regulator
V
+
–
S
V
V
V (REG)
O
317
O
IN
R
1
R
2
I
adj
R
R
1
2
V
= (1+R /R )V
V
(REG) = 1.25V (1+R /R )+I
R
adj 2
O
2
1
S
O
2
1
Offset Voltage Adjustment
Comparator with Hysterisis
R
R
2
1
V
–
+
S
V
V
S
O
100kΩ
–
+
V
O
TL072
R
R
1
2
10kΩ
10kΩ
+12V
V
V
= {R /(R +R )} V (max)
1 1 2 O
UL
LL
10kΩ
-12V
= {R /(R +R )} V (min)
1 1 2 O
FN8172.1
20
June 21, 2005
X9268
Application Circuits (continued)
Attenuator
Filter
C
V
+
–
S
R
V
R
2
O
1
3
–
+
R
V
O
V
S
R
R
2
R
4
R = R = R = R = 10kΩ
1
2
3
4
R
1
G
= 1 + R /R
2 1
V
= G V
S
O
O
fc = 1/(2πRC)
-1/2 ≤ G ≤ +1/2
Inverting Amplifier
Equivalent L-R Circuit
R
R
2
1
V
S
R
2
C
1
–
+
V
+
–
S
V
O
R
R
1
Z
IN
V
= G V
S
O
G = - R /R
2
1
3
Z
= R + s R (R + R ) C = R + s Leq
2 2 1 3 1 2
IN
(R + R ) >> R
1
3
2
Function Generator
C
R
R
1
2
–
+
–
+
R
R
}
A
}
B
frequency ∝ R , R , C
1
2
amplitude ∝ R , R
A
B
FN8172.1
21
June 21, 2005
X9268
PACKAGING INFORMATION
24-Lead Plastic, TSSOP, Package Code V24
.026 (.65) BSC
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.303 (7.70)
.311 (7.90)
.041 (1.05)
.0075 (.19)
.0118 (.30)
0.002 (0.05)
0.005 (0.15)
.010 (.25)
Gage Plane
(7.72)
(4.16)
0°–8°
Seating Plane
.020 (.50)
.030 (.75)
(1.78)
(0.42)
Detail A (20X)
(0.65)
ALL MEASUREMENTS ARE TYPICAL
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
FN8172.1
22
June 21, 2005
X9268
PACKAGING INFORMATION
24-Lead Plastic Small Outline Gull Wing Package Type S
0.393 (10.00)
0.290 (7.37)
0.299 (7.60)
0.420 (10.65)
Pin 1 Index
Pin 1
0.014 (0.35)
0.020 (0.50)
0.598 (15.20)
0.610 (15.49)
(4X) 7°
0.092 (2.35)
0.105 (2.65)
0.003 (0.10)
0.012 (0.30)
0.050 (1.27)
0.050"Typical
0.010 (0.25)
0.020 (0.50)
X 45°
0.050"
Typical
0° - 8°
0.009 (0.22)
0.013 (0.33)
0.420"
0.015 (0.40)
0.050 (1.27)
0.030" Typical
24 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
FN8172.1
23
June 21, 2005
X9268
ORDERING INFORMATION
X9268
Y
P
T
V
V
Limits
CC
Device
Blank = 5V ± 10%
-2.7 = 2.7 to 5.5V
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Package
S24 = 24-Lead SOIC
T24= 24-Lead TSSOP
Potentiometer Organization
Pot
U =
T =
50kΩ
100kΩ
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8172.1
24
June 21, 2005
相关型号：
X9268TB24
DUAL 100K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PBGA24, XBGA-24
XICOR
X9268TB24I
Digital Potentiometer, 2 Func, 100000ohm, 2-wire Serial Control Interface, 256 Positions, CMOS, PBGA24, XBGA-24
XICOR
X9268TS24
Digital Potentiometer, 2 Func, 100000ohm, 2-wire Serial Control Interface, 256 Positions, CMOS, PDSO24, PLASTIC, SOIC-24
XICOR
X9268TS24-2.7T1
Digital Potentiometer, 2 Func, 100000ohm, 2-wire Serial Control Interface, 256 Positions, CMOS, PDSO24, PLASTIC, SOIC-24
XICOR
X9268TS24I-2.7
Digital Potentiometer, 2 Func, 100000ohm, 2-wire Serial Control Interface, 256 Positions, CMOS, PDSO24, PLASTIC, SOIC-24
XICOR
X9268TS24I-2.7T1
Digital Potentiometer, 2 Func, 100000ohm, 2-wire Serial Control Interface, 256 Positions, CMOS, PDSO24, PLASTIC, SOIC-24
XICOR
©2020 ICPDF网 联系我们和版权申明