X9271UV14Z-2.7 [INTERSIL]
Single, Digitally Controlled (XDCPâ¢) Potentiometer;
| 型号： | X9271UV14Z-2.7 |
| 厂家： | 
Intersil |
| 描述： | Single, Digitally Controlled (XDCPâ¢) Potentiometer |
| 文件： | 总22页 (文件大小：673K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X9271
Single Supply/Low Power/256-Tap/SPI Bus
Data Sheet
June 23, 2011
FN8174.3
DESCRIPTION
Single, Digitally Controlled (XDCP™)
Potentiometer
The X9271 integrates a single, digitally controlled
potentiometer (XDCP™) on a monolithic CMOS
integrated circuit.
FEATURES
• 256 Resistor Taps
• SPI Serial Interface for Write, Read, and Transfer
Operations of Potentiometer
• Wiper Resistance, 100Ω typical @ V
• 16 Nonvolatile Data Registers
• Nonvolatile Storage of Multiple Wiper Positions
• Power-on Recall; Loads Saved Wiper Position
on Power-up
The digitally controlled potentiometer is implemented by
using 255 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI bus
interface. The potentiometer has associated with it a
volatile Wiper Counter Register (WCR) and four
nonvolatile data registers that can be directly written to
and read by the user. The contents of the WCR control
the position of the wiper on the resistor array though the
switches. Power-up recalls the contents of the default
data register (DR0) to the WCR.
= 5V
CC
• Standby Current < 3µA Max
• V
= 2.7V to 5.5V Operation
CC
• 50kΩ, 100kΩ Versions of End-to-End Resistance
• 100-yr Data Retention
• Endurance: 100,000 Data Changes per Bit per
Register
The XDCP can be used as
a three-terminal
• 14-Lead TSSOP
• Low-power CMOS
• Pb-free Plus Anneal Available (RoHS Compliant)
potentiometer or as a two-terminal variable resistor in
a wide variety of applications. including control,
parameter adjustments, and signal processing.
FUNCTIONAL DIAGRAM
V
R
H
CC
Write
Read
Address
Data
Status
50kΩ and 100kΩ
256 Taps
Transfer
Inc/Dec
Power-on Recall
Wiper Counter
Register (WCR)
Bus
Interface
and Control
SPI
Bus
Interface
POT
Data Registers
16 Bytes
Control
R
V
R
W
SS
L
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2005, 2011. All Rights Reserved
XDCP is a trademark of Intersil Americas Inc. Intersil (and design) is a trademark owned by Intersil Corporation
or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners.
1
X9271
Ordering Information
PART NUMBER
PART
V
LIMITS
(V)
POTENTIOMETER TEMP. RANGE
PKG.
DWG. #
CC
(Notes 1, 3)
X9271UV14IZ (Note 2)
X9271UV14Z (Note 2)
X9271TV14 (Note 4)
MARKING
X9271 UVZI
X9271 UVZ
X9271 TV
ORGANIZATION (kΩ)
(°C)
PACKAGE
5 ±10%
50
50
-40 to +85
0 to +70
14 Ld TSSOP (4.4mm) (Pb-free) M14.173
14 Ld TSSOP (4.4mm) (Pb-free) M14.173
5 ±10%
5 ±10%
2.7 to 5.5
5 ±10%
5 ±10%
2.7 to 5.5
100
100
100
100
50
0 to +70
14 Ld TSSOP (4.4mm)
14 Ld TSSOP (4.4mm)
M14.173
M14.173
X9271TV14I-2.7T1 (Note 4) X9271 TVG
-40 to +85
-40 to +85
0 to +70
X9271TV14IZ (Note 2)
X9271TV14Z (Note 2)
X9271UV14I-2.7 (Note 4)
X9271 TVZI
X9271 TVZ
X9271 UVG
14 Ld TSSOP (4.4mm) (Pb-free) M14.173
14 Ld TSSOP (4.4mm) (Pb-free) M14.173
-40 to +85
-40 to +85
0 to +70
14 Ld TSSOP (4.4mm)
M14.173
X9271UV14IZ-2.7 (Note 2) X9271 UVZG 2.7 to 5.5
50
14 Ld TSSOP (4.4mm) (Pb-free) M14.173
14 Ld TSSOP (4.4mm) (Pb-free) M14.173
14 Ld TSSOP (4.4mm) (Pb-free) M14.173
14 Ld TSSOP (4.4mm) (Pb-free) M14.173
X9271UV14Z-2.7 (Note 2) X9271 UVZF
X9271TV14IZ-2.7 (Note 2) X9271 TVZG
X9271TV14Z-2.7 (Note 2) X9271 TVZF
NOTES:
2.7 to 5.5
2.7 to 5.5
2.7 to 5.5
50
50
-40 to +85
0 to +70
100
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for X9271. For more information on MSL please see Tech Brief TB363.
4. Not recommended for new designs.
FN8174.3
June 23, 2011
2
X9271
DETAILED FUNCTIONAL DIAGRAM
V
CC
Power-on Recall
50kΩ and 100kΩ
Bank 0
256 Taps
R
H
R
R
0
1
Wiper
Counter
Register
(WCR)
HOLD
CS
SCK
SO
R
R
L
R
R
2
3
Interface
and
Control
Circuitry
W
SI
A0
A1
Bank 1
Bank 2
Bank 3
DATA
R
R
R
R
R
R
0
1
0
1
0
1
WP
R
R
R
R
R
R
2
3
2
3
2
3
Control
12 Additional Nonvolatile Registers
3 Banks of 4 Registers x 8 Bits
V
SS
CIRCUIT-LEVEL APPLICATIONS
SYSTEM-LEVEL APPLICATIONS
• Vary the gain of a voltage amplifier.
• Adjust the contrast in LCD displays.
• Provide programmable DC reference voltages for
comparators and detectors.
• Control the power level of LED transmitters in
communication systems.
• Control the volume in audio circuits.
• Set and regulate the DC biasing point in an RF
power amplifier in wireless systems.
• Trim out the offset voltage error in a voltage amplifier
circuit.
• Control the gain in audio and home entertainment
systems.
• Set the output voltage of a voltage regulator.
• Provide the variable DC bias for tuners in RF
wireless systems.
• Trim the resistance in Wheatstone bridge circuits.
• Control the gain, characteristic frequency, and
Q-factor in filter circuits.
• Set the operating points in temperature control
systems.
• Set the scale factor and zero point in sensor signal
conditioning circuits.
• Control the operating point for sensors in industrial
systems.
• Vary the frequency and duty cycle of timer ICs.
• Trim offset and gain errors in artificial intelligence
systems.
• Vary the DC biasing of a pin diode attenuator in RF
circuits.
• Provide a control variable (I, V, or R) in feedback
circuits.
FN8174.3
June 23, 2011
3
X9271
PIN CONFIGURATION
TSSOP
X9271
S0
A0
V
CC
1
2
3
4
5
6
7
14
13
12
11
10
9
R
R
R
L
NC
CS
H
W
HOLD
A1
SCK
SI
8
V
WP
SS
PIN ASSIGNMENTS
TSSOP
Symbol
SO
Function
1
2
Serial Data Output
Device Address
No Connect
A0
3
NC
4
CS
Chip Select
5
SCK
SI
Serial Clock
6
Serial Data Input
System Ground
Hardware Write Protect
Device Address
7
V
SS
8
WP
A1
9
10
11
12
13
14
HOLD
Device Select. Pause the serial bus.
Wiper Terminal of Potentiometer
High Terminal of Potentiometer
Low Terminal of Potentiometer
System Supply Voltage
R
W
R
H
R
L
V
CC
FN8174.3
June 23, 2011
4
X9271
PIN DESCRIPTIONS
Potentiometer Pins
R , R
H
L
Bus Interface Pins
The R and R pins are equivalent to the terminal
connections on a mechanical potentiometer.
H
L
SERIAL OUTPUT (SO)
The Serial Output (SO) is the serial data output pin.
During a read cycle, data is shifted out on this pin.
Data is clocked out by the falling edge of the serial
clock.
R
W
The wiper pin (R ) is equivalent to the wiper terminal
W
of a mechanical potentiometer.
SERIAL INPUT (SI)
Supply Pins
The Serial Input (SI) is the serial data input pin. All
operational codes, byte addresses, and data to be
written to the potentiometers and potentiometer
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
SYSTEM SUPPLY VOLTAGE (V ) AND SUPPLY GROUND (V
CC
)
SS
The System Supply Voltage (V ) pin is the system
CC
supply voltage. The Supply Ground (V ) pin is the
SS
system ground.
SERIAL CLOCK (SCK)
Other Pins
The Serial Clock (SCK) input is used to clock data into
and out of the X9271.
HARDWARE WRITE PROTECT INPUT (WP)
The Hardware Write Protect Input (WP) pin, when
LOW, prevents nonvolatile writes to the data registers.
HOLD (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is under way, HOLD may be used to pause the
serial communication with the controller without resetting
the serial sequence. To pause, HOLD must be brought
LOW while SCK is LOW. To resume communication,
HOLD is brought HIGH, again while SCK is LOW. If the
pause feature is not used, HOLD should be held HIGH at
all times. CMOS level input.
NO CONNECT
No Connect pins should be left floating. These pins
are used for Intersil manufacturing and testing
purposes.
DEVICE ADDRESS (A1 - A0)
The Device Address (A1 - A0) inputs are used to set
the 8-bit slave address. A match in the slave address
serial data stream must be made with the address
input in order to initiate communication with the
X9271.
CHIP SELECT (CS)
When Chip Select (CS) is HIGH, the X9271 is
deselected, the SO pin is at high impedance, and
(unless an internal write cycle is under way) the device
is in standby state. CS LOW enables the X9271,
placing it in the active power mode. It should be noted
that after a power-up, a HIGH to LOW transition on CS
is required prior to the start of any operation.
FN8174.3
June 23, 2011
5
X9271
PRINCIPLES OF OPERATION
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (R and R
inputs).
H
L
Device Description
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
SERIAL INTERFACE
The X9271 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.
(R ) output. Within each individual array, only one
W
switch may be turned on at a time.
These switches are controlled by a Wiper Counter
Register (WCR). The eight bits of the WCR
(WCR[7:0]) are decoded to select, and enable, one of
256 switches (Table 1).
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
POWER-UP AND POWER-DOWN RECOMMENDATIONS
There are no restrictions on the power-up or
ARRAY DESCRIPTION
power-down conditions of V
applied to the potentiometer pins, provided that V
CC
always more positive than or equal to V , V , and V ;
and the voltages
is
CC
The X9271 is composed of a resistor array (Figure 1).
The array contains the equivalent of 255 discrete
resistive segments that are connected in series. The
H
L
W
i.e., V
≥ V , V , V . The V
ramp rate
CC
H
L
W
CC
specification is always in effect.
SERIAL DATA PATH
R
SERIAL
BUS
INPUT
C
H
FROM INTERFACE
CIRCUITRY
REGISTER 0
(DR0)
REGISTER 1
(DR1)
O
U
N
T
E
R
PARALLEL
BUS
INPUT
8
8
BANK_0 Only
REGISTER 3
(DR3)
REGISTER 2
(DR2)
D
E
C
O
WIPER
COUNTER
REGISTER
(WCR)
D
E
INC/DEC
LOGIC
IF WCR = 00[H] THEN R = R
W
L
UP/DN
MODIFIED SCK
IF WCR = FF[H] THEN R = R
UP/DN
CLK
W
H
R
R
L
W
FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM
FN8174.3
June 23, 2011
6
X9271
.
DEVICE DESCRIPTION
TABLE 1. WIPER COUNTER REGISTER, WCR (8-bit),
WCR[7:0]: Used to store current wiper position
(Volatile, V)
Wiper Counter Register (WCR)
WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0
The X9271 contains a Wiper Counter Register (WCR)
for the DCP potentiometer. The WCR can be
envisioned as an 8-bit parallel and serial load counter,
with its outputs decoded to select one of 256 switches
along its resistor array (Table 1). The contents of the
WCR can be altered in four ways:
V
V
V
V
V
V
V
V
(MSB)
(LSB)
.
TABLE 2. DATA REGISTER, DR (8-BIT), DR[7:0]: Used to
store wiper positions or data (Nonvolatile, NV)
1. It can be written directly by the host via the Write Wiper
Counter Register instruction (serial load).
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
2. It can be written indirectly by transferring the contents of
one of four associated data registers via the XFR Data
Register instruction (parallel load).
NV
NV
NV
NV
NV
NV
NV
NV
MSB
LSB
3. It can be modified one step at a time by the Increment/
Decrement instruction.
TABLE 3. STATUS REGISTER, SR (WIP is 1-bit)
4. It is loaded with the contents of its Data Register zero
(DR0) upon power-up.
WIP
(LSB)
The WCR is a volatile register; that is, its contents are
lost when the X9271 is powered down. Although the
register is automatically loaded with the value in DR0
upon power-up, this may be different from the value
present at power-down. Power-up guidelines are
recommended to ensure proper loading of the R0
value into the WCR. The DR0 value of Bank 0 is the
default value.
Data Registers (DR3–DR0)
The potentiometer has four 8-bit nonvolatile Data
Registers. These can be read or written directly by the
host (Table 2). Data can also be transferred between
any of the four Data Registers and the associated
WCR. All operations changing data in one of the Data
Registers are nonvolatile operations and take a
maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.
Bits [7:0] are used to store one of the 256 wiper
positions or data (0 ~255).
Status Register (SR)
The 1-bit Status Register is used to store the system
status (Table 3).
WIP: Write In Progress status bit; read only.
– WIP = 1 indicates that a high-voltage write cycle is in
progress.
– WIP = 0 indicates that no high-voltage write cycle is
in progress
FN8174.3
June 23, 2011
7
X9271
DEVICE DESCRIPTION
Banks 1, 2, and 3 are additional banks of registers (12
total) that can be used for SPI write and read
operations. The data registers in Banks 1, 2, and 3
cannot be used for direct read/write operations to the
Wiper Counter Register (Tables 5 and 6).
Instructions
IDENTIFICATION BYTE (ID AND A)
The first byte sent to the X9271 from the host,
following a CS going HIGH to LOW, is called the
Identification byte. The most significant four bits of the
slave address are a device type identifier. The ID[3:0]
bit is the device ID for the X9271; this is fixed as
0101[B] (Table 4).
TABLE 4. IDENTIFICATION BYTE FORMAT
SET TO 0 FOR
PROPER
INTERNAL
SLAVE
DEVICE TYPE IDENTIFIER
OPERATION
ADDRESS
ID3
0
ID2
ID1
ID0
0
0
A1
A0
The A1 - A0 bits in the ID byte are the internal slave
address. The physical device address is defined by
the state of the A1 - A0 input pins. The slave address
is externally specified by the user. The X9271
compares the serial data stream with the address
input state; a successful compare of both address bits
is required for the X9271 to successfully continue the
command sequence. Only the device for which slave
address matches the incoming device address sent by
the master executes the instruction. The A1 - A0
inputs can be actively driven by CMOS input signals or
1
0
1
(MSB)
(LSB)
TABLE 5. REGISTER SELECTION (DR0 TO DR3) TABLE
REGISTER
RB
RA SELECTION
OPERATIONS
0
0
1
0
1
0
1
2
3
Data Register Read and Write; Wiper
Counter Register Operations
0
1
1
Data Register Read and Write; Wiper
Counter Register Operations
tied to V
or V
.
CC
SS
Data Register Read and Write; Wiper
Counter Register Operations
INSTRUCTION BYTE (I[3:0])
Data Register Read and Write; Wiper
Counter Register Operations
The next byte sent to the X9271 contains the
instruction and register pointer information. The three
most significant bits are used to provide the instruction
operation code (I[3:0]). The RB and RA bits point to
one of the four Data Registers. P0 is the POT
selection; since the X9271 is single POT, P0 = 0. The
format is shown in Table 7.
TABLE 6. REGISTER BANK SELECTION (BANK 0 TO BANK 3)
BANK
P1
P0 SELECTION
OPERATIONS
0
0
0
Data Register Read and Write; Wiper
Counter Register Operations
REGISTER BANK SELECTION (R1, R0, P1, P0)
0
1
1
1
0
1
1
2
3
Data Register Read and Write Only
Data Register Read and Write Only
Data Register Read and Write Only
There are 16 registers organized into four banks.
Bank 0 is the default bank of registers. Only Bank 0
registers can be used for the data register to Wiper
Counter Register operations.
TABLE 7. INSTRUCTION BYTE FORMAT
REGISTER BANK SELECTION FOR
SP1 REGISTER WRITE AND READ OPERATIONS)
REGISTER
SELECTION
POTENTIOMETER SELECTION
(WCR SELECTION) (Note 5)
INSTRUCTION OPCODE
I2 I1
I3
P0
RB
RA
P1
P0
(MSB)
(LSB)
NOTE:
5. Set to P0 = 0 for potentiometer operations.
FN8174.3
June 23, 2011
8
X9271
DEVICE DESCRIPTION
Instructions
Two instructions require a 2-byte sequence to
complete (Figure 4). These instructions transfer data
between the host and the X9271; either between the
host and one of the data registers, or directly between
the host and the Wiper Counter Register. These
instructions are:
Five of the eight instructions are three bytes in length.
These instructions are:
– Read Wiper Counter Register: Read the current
wiper position of the potentiometer.
– XFR Data Register to Wiper Counter Register:
Transfers the contents of one specified Data Regis-
ter to the associated Wiper Counter Register.
– Write Wiper Counter Register: Change current
wiper position of the potentiometer.
– XFR Wiper Counter Register to Data Register:
Transfers the contents of the specified Wiper Coun-
ter Register to the associated Data Register.
– Read Data Register: Read the contents of the
selected Data Register.
– Write Data Register: Write a new value to the
selected Data Register.
The final command is Increment/Decrement (Figures 5
and 6). It is different from the other commands,
because its length is indeterminate. Once the
command is issued, the master can clock the selected
wiper up and/or down in one resistor segment step,
thereby providing a fine-tuning capability to the host.
– Read Status: This command returns the contents of
the WIP bit, which indicates if the internal write cycle
is in progress.
See Table 8 for details of the instruction set.
For each SCK clock pulse (t
) while SI is HIGH,
the selected wiper moves one resistor segment
HIGH
The basic sequence of the 3-byte instruction is shown
in Figure 2. These 3-byte instructions exchange data
between the WCR and one of the Data Registers. A
transfer from a Data Register to a WCR is essentially a
write to a static RAM, with the static RAM controlling
the wiper position. The response of the wiper to this
towards the R terminal. Similarly, for each SCK clock
H
pulse while SI is LOW, the selected wiper moves one
resistor segment towards the R terminal.
L
Write-in-Process (WIP) Bit
action is delayed by t
(current wiper position) to a Data Register is a write to
nonvolatile memory and takes a minimum of t to
complete. The transfer can occur between one of the
four potentiometers and one of its associated
registers, or it may occur globally, where the transfer
occurs between all potentiometers and one associated
register. The Read Status Register instruction is the
only unique format (Figure 3).
. A transfer from the WCR
WRL
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW
to HIGH after a complete write sequence is received
by the device. The progress of this internal write
operation can be monitored by the Write-in-Process bit
(WIP). The WIP bit is read with a Read Status
command.
WR
FN8174.3
June 23, 2011
9
X9271
CS
SCL
SI
0
0
0
0
0
1
0
1
ID3 ID2 ID1 ID0
Device ID
A1 A0
RB RA P1 P0
D7 D6 D5 D4 D3 D2 D1 D0
I1
I3 I2
I0
Internal
Address
Instruction
Opcode
Register
Address
Pot/Bank
Address
WCR[7:0] valid only when P1 = P0 = 0;
or
Data Register Bit [7:0] for all values of P1 and P0
FIGURE 2. THREE-BYTE INSTRUCTION SEQUENCE (WRITE)
CS
SCL
SI
0
0
0
0
0
1
0
1
X
X
X
X
X
X
X
X
A1 A0
RB RA P1 P0
I3
I1
I2
I0
ID3 ID2 ID1 ID0
Device ID
Don’t Care
Internal
Address
Pot/Bank
Address
Instruction
Opcode
Register
Address
S0
D7 D6 D5 D4 D3 D2 D1 D0
WCR[7:0] valid only when P1 = P0 = 0;
or
Data Register Bit [7:0] for all values of P1 and P0
FIGURE 3. THREE-BYTE INSTRUCTION SEQUENCE (READ)
CS
SCK
SI
0
0
0
0
0
0
1
0
1
0
A1 A0
I0
ID3 ID2 ID1 ID0
Device ID
I1
RB RA
P0
I3
P1
I2
Internal
Address
Instruction
Opcode
Register
Address
Pot/Bank
Address
These commands only valid when P1 = P0 = 0
FIGURE 4. TWO-BYTE INSTRUCTION SEQUENCE
FN8174.3
June 23, 2011
10
X9271
CS
SCL
0
SI
0
0
0
0
0
0
1
0
1
ID3 ID2 ID1 ID0
Device ID
P1
A1 A0
RA RB
P0
I1
I3 I2
I0
I
I
D
E
C
1
I
D
E
C
n
N
C
1
N
C
2
N
C
n
Internal
Address
Pot/Bank
Address
Instruction
Opcode
Register
Address
FIGURE 5. INCREMENT/DECREMENT INSTRUCTION SEQUENCE
t
WRID
SCK
SI
VOLTAGE OUT
V
W
INC/DEC CMD ISSUED
FIGURE 6. INCREMENT/DECREMENT TIMING LIMITS
TABLE 8. INSTRUCTION SET
INSTRUCTION SET
(1/0 = DATA IS ONE OR ZERO)
INSTRUCTION
I3
1
I2
0
I1
0
I0
1
RB
0
RA
0
P
P
OPERATION
1
0
Read Wiper Counter Register
Write Wiper Counter Register
Read Data Register
0
1/0 Read contents of Wiper Counter Register.
1/0 Write new value to Wiper Counter Register.
1
0
1
0
0
0
0
1
0
1
1
1/0
1/0
1/0
1/0 Read contents of Data Register pointed to by P1 - P0
and RB - RA.
Write Data Register
1
1
1
0
0
1
1
1
0
1
0
0
1
1
0
0
1
0
0
1
1/0
1/0
1/0
0
1/0
1/0
1/0
0
1/0
0
1/0 Write new value to Data Register pointed to by P1 - P0
and RB - RA.
XFR Data Register to
Wiper Counter Register
0
0
0
1
Transfer contents of Data Register pointed to by
RB - RA (Bank 0 only) to Wiper Counter Register.
XFR Wiper Counter
Register to Data Register
0
Transfer contents of Wiper CounterRegister to Register
pointed to by RB-RA (Bank 0 only).
Increment/Decrement
Wiper Counter Register
0
Enable increment/decrement of the Wiper Counter
Register.
Read Status (WIP Bit)
0
0
0
Read status of internal write cycle by checking WIP bit.
FN8174.3
June 23, 2011
11
X9271
INSTRUCTION FORMAT
Read Wiper Counter Register (WCR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/Bank
Addresses
Wiper Position
(Sent by X9271 on SO)
CS
Falling
Edge
CS
Rising
Edge
W
C
R
W
C
R
7
W W W W W W
C C C C C C
R R R R R R
0
1
0
1
0
0 A1 A0 1
0
0
1
0
0
0
0
5
4
3
2
1
0
6
Write Wiper Counter Register (WCR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/Bank
Addresses
Data Byte
(Sent by Host on SI)
CS
Falling
Edge
CS
Rising
Edge
W
C
R
W
C
R
7
W W W W W W
C C C C C C
R R R R R R
0
1
0
1
0
0 A1 A0 1
0
1
0
0
0
0
0
5
4 3 2 1 0
6
Read Data Register (DR)
Device Type
CS
Device
Addresses
0 A1 A0 1 0 1 1 RB RA P1 P0 D7 D 6 D5 D4 D3 D2 D1 D0
Instruction
Opcode
DR/Bank
Addresses
Data Byte
(Sent by X9271 on SO)
CS
Rising
Edge
Identifier
Falling
Edge
0
1
0
1
0
Write Data Register (DR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/Bank
Addresses
Data Byte
(Sent by Host on SI)
CS
CS
Falling
Edge
Rising
Edge
0
1 0 1 0 0 A1 A0 1 1 0 0 RB RA P1 P0 D7 D 6 D5 D4 D3 D2 D1 D0
Transfer Wiper Counter Register (WCR) to Data Register (DR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/Bank
Addresses
CS
Falling
Edge
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
0
1
0
1
0
0 A1 A0 1 1
1
0
RB RA
0
0
FN8174.3
June 23, 2011
12
X9271
Transfer Data Register (DR) to Wiper Counter Register (WCR) (Notes 6, 7)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/Bank
Addresses
CS
Falling
Edge
CS
Rising
Edge
0
1
0
1
0 0 A1 A0 1 1 0 1 RB RA
0
0
Increment/Decrement Wiper Counter Register (WCR) (Notes 6, 7, 8, 9, 10)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/Bank
Addresses
Increment/Decrement
(Sent by Master on SDA)
CS
Falling
Edge
CS
Rising
Edge
0
1
0
1
0
0
A1 A0
0
0
1
0
X X
0
0
I/D I/D
.
.
.
.
I/D I/D
Read Status Register (SR) (Note 6)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/Bank
Addresses
Data Byte
(Sent by X9271 on SO)
0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 WIP
CS
Falling
Edge
CS
Rising
Edge
0
1
0
1
0
0
A1 A0
NOTES:
6. “A1 ~ A0”: stands for the device addresses sent by the master.
7. WCRx refers to wiper position data in the Wiper Counter Register.
8. “I”: stands for the increment operation. SI held HIGH during active SCK phase (high).
9. “D”: stands for the decrement operation. SI held LOW during active SCK phase (high).
10. “X:”: Don’t Care.
FN8174.3
June 23, 2011
13
X9271
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias .................... -65°C to +135°C
Storage temperature.......................... -65°C to +150°C
Voltage on SCK, any address input,
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this
specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
with respect to V ................................. -1V to +7V
SS
ΔV = |(V - V )|.....................................................5.5V
H
L
Lead temperature (soldering, 10 seconds)........ 300°C
(10 seconds)..................................................±6mA
I
W
Pb-Free Reflow Profile ..........................see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
RECOMMENDED OPERATING CONDITIONS
Temp
Commercial
Industrial
Min.
0°C
Max.
+70°C
+85°C
Supply Voltage (V ) Limits
CC
Device
X9271
(Note 14)
5V ± 10%
-40°C
X9271-2.7
2.7V to 5.5V
ANALOG CHARACTERISTICS (Over recommended industrial operating conditions unless otherwise stated.)
Limits
Min.
(Note 18)
Max.
(Note 18)
Symbol
Parameter
End to End Resistance
End to End Resistance
Typ.
100
50
Units
kΩ
Test Conditions
R
R
T version
U version
TOTAL
TOTAL
kΩ
End to End Resistance
Tolerance
±20
%
Power Rating
50
±3
mW
+25°C, each pot
I
Wiper Current
mA
W
R
R
Wiper Resistance
Wiper Resistance
300
150
W
I
I
= ± 3mA @ V
= ± 3mA @ V
= 3V
= 5V
W
W
W
CC
CC
W
W
V
Voltage on any R or R Pin
V
V
V
dBV/√Hz
%
V
= 0V
TERM
H
L
SS
CC
SS
Ref: 1V
Noise
-120
0.4
Resolution
Absolute Linearity (Note 11)
Relative Linearity (Note 12)
Temperature Coefficient of
±1
MI
(Note 13)
R
R
w(n)(actual) - w(n)(expected)
(Note 15)
±0.2
MI
(Note 13)
R
- [R
] (Note 15)
w(n) + MI
w(n + 1)
±300
ppm/°C
ppm/°C
pF
R
TOTAL
Ratiometric Temp.
Coefficient
20
C /C /C
W
Potentiometer
Capacitance
10/10/25
See macro model
H
L
NOTES:
11. Absolute linearity is used to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
12. Relative linearity is used to determine actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
13. MI = RTOT / 255 or (R - R ) / 255, single pot.
H
L
14. During power-up, V
CC
> V , V , and V .
H L W
15. n = 0, 1, 2, …,255; m =0, 1, 2, …., 254.
FN8174.3
June 23, 2011
14
X9271
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Min.
Max.
Symbol
Parameter
(Note 18) Typ. (Note 18) Units
Test Conditions
I
I
I
V
Supply Current
400
5
μA
mA
μA
f
= 2.5 MHz, SO = Open, V
= 6V
= 6V
CC1
CC2
SB
CC
SCK
CC
(Active)
Other Inputs = V
SS
V
Supply Current
1
f
= 2.5MHz, SO = Open, V
CC
(Nonvolatile Write)
SCK
Other Inputs = V
CC
SS
V
Current (Standby)
3
SCK = SI = V , Addr. = V
CS = V
,
SS
CC
SS
= 6V
CC
I
I
Input Leakage Current
Output Leakage Current
Input HIGH Voltage
Input LOW Voltage
10
10
μA
μA
V
V
V
= V to V
SS CC
LI
IN
= V to V
SS CC
LO
OUT
V
V
V
V
V
V
x 0.7
V
+ 1
IH
CC
-1
CC
x 0.3
V
V
IL
CC
0.4
Output LOW Voltage
Output HIGH Voltage
Output HIGH Voltage
V
I
I
I
= 3mA
OL
OH
OH
OL
OH
OH
V
V
- 0.8
- 0.4
V
= -1mA, V
CC
≥ +3V
≤ +3V
CC
V
= -0.4mA, V
CC
CC
ENDURANCE AND DATA RETENTION
Min.
Parameter
Minimum Endurance
Data Retention
(Note 18)
100,000
100
Units
Data changes per bit per register
Years
CAPACITANCE
Max.
Symbol
Test
(Note 18)
Units
pF
Test Conditions
C
C
C
(Note 16)
Input / Output Capacitance (SI)
Output Capacitance (SO)
8
8
6
V
V
= 0V
= 0V
IN/OUT
(Note 16)
OUT
OUT
pF
OUT
(Note 16)
Input Capacitance (A0, CS, WP, HOLD, and
SCK)
pF
V
= 0V
IN
IN
POWER-UP TIMING
Symbol
Min.
Max.
Parameter
(Note 18)
(Note 18)
Units
V/ms
ms
t V
CC
(Note 16)
V
Power-up Rate
0.2
50
1
r
CC
t
t
(Note 17)
(Note 17)
Power-up to Initiation of Read Operation
Power-up to Initiation of Write Operation
PUR
50
ms
PUW
A.C. TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Level
V
x 0.1 to V
x 0.9
CC
CC
10ns
V
x 0.5
CC
NOTES:
16. This parameter is not 100% tested.
17. t
and t
are the delays required from the time the (last) power supply (V -) is stable until the specific instruction can be issued. These
PUW CC
PUR
parameters are periodically sampled and are not 100% tested.
18. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
FN8174.3
June 23, 2011
15
X9271
EQUIVALENT A.C. LOAD CIRCUIT
SPICE Macromodel
5V
1462Ω
3V
1382Ω
R
TOTAL
R
R
L
H
SO pin
SO pin
C
C
W
C
L
L
10pF
2714Ω
100pF
1217Ω
100pF
25pF
10pF
R
W
AC TIMING
Symbol
Parameter
Min.
Max.
Units
MHz
ns
ns
ns
ns
ns
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SSI/SPI Clock Frequency
SSI/SPI Clock Cycle Time
SSI/SPI Clock High Time
SSI/SPI Clock Low Time
Lead Time
2.5
SCK
CYC
WH
WL
LEAD
LAG
SU
500
200
200
250
250
50
Lag Time
SI, SCK, HOLD and CS Input Setup Time
SI, SCK, HOLD and CS Input Hold Time
SI, SCK, HOLD and CS Input Rise Time
SI, SCK, HOLD and CS Input Fall Time
SO Output Disable Time
ns
ns
μs
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
50
H
2
RI
2
FI
0
0
250
200
DIS
V
SO Output Valid Time
SO Output Hold Time
HO
RO
FO
SO Output Rise Time
100
100
SO Output Fall Time
HOLD Time
400
100
100
HOLD
HSU
HH
HZ
HOLD Setup Time
HOLD Hold Time
HOLD Low to Output in High Z
HOLD High to Output in Low Z
100
100
10
LZ
T
Noise Suppression Time Constant at SI, SCK, HOLD and CS Inputs
I
t
t
t
CS Deselect Time
WP, A0 Setup Time
WP, A0 Hold Time
2
0
0
CS
WPASU
WPAH
FN8174.3
June 23, 2011
16
X9271
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol Parameter
Typ.
Max.
Units
t
High-voltage Write Cycle Time (Store Instructions)
5
10
ms
WR
XDCP TIMING
Symbol
Parameter
Min.
Max. Units
t
t
Wiper Response Time After Third (Last) Power Supply is Stable
Wiper Response Time After Instruction Issued (All Load Instructions)
5
5
10
10
μs
μs
WRPO
WRL
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
FN8174.3
June 23, 2011
17
X9271
TIMING DIAGRAMS
Input Timing
t
CS
CS
t
t
t
LAG
LEAD
t
CYC
SCK
...
t
t
t
t
RI
t
FI
WL
SU
H
WH
...
MSB
LSB
SI
High Impedance
SO
Output Timing
CS
SCK
SO
...
...
t
t
t
DIS
V
HO
LSB
MSB
ADDR
SI
Hold Timing
CS
t
t
HH
HSU
SCK
SO
...
t
t
FO
RO
t
t
LZ
HZ
SI
t
HOLD
HOLD
FN8174.3
June 23, 2011
18
X9271
XDCP Timing (for All Load Instructions)
CS
SCK
...
...
t
WRL
MSB
LSB
SI
VWx
High Impedance
SO
Write Protect and Device Address Pins Timing
(Any Instruction)
CS
t
t
WPAH
WPASU
WP
A0
A1
FN8174.3
June 23, 2011
19
X9271
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
+V
R
V
R
RW
I
3-terminal Potentiometer;
Variable Voltage Divider
2-terminal Variable Resistor;
Variable Current
Application Circuits
Noninverting Amplifier
Voltage Regulator
V
+
–
S
V
O
V
V (REG)
O
317
IN
R
1
R
2
I
adj
R
R
1
2
V
= (1+R /R )V
V
(REG) = 1.25V (1+R /R )+I
R
adj
O
2
1
S
O
2
1
2
Offset Voltage Adjustment
Comparator with Hysterisis
R
R
2
1
V
–
+
S
V
V
S
O
100kΩ
–
+
V
O
TL072
R
R
1
2
10kΩ
10kΩ
+12V
V
= {R /(R +R )} V (max)
1 1 2 O
UL
RL = {R /(R +R )} V (min)
10kΩ
-12V
L
1
1
2
O
FN8174.3
June 23, 2011
20
X9271
Application Circuits (continued)
Attenuator
Filter
C
V
+
–
S
R
V
R
2
O
1
3
–
+
R
V
O
V
S
R
R
2
R
4
R = R = R = R = 10kΩ
1
2
3
4
R
1
G
= 1 + R /R
2 1
V
= G V
S
O
O
fc = 1/(2πRC)
-1/2 ≤ G ≤ +1/2
Inverting Amplifier
Equivalent L-R Circuit
R
R
2
1
V
S
R
2
C
1
–
+
V
+
–
S
V
O
R
R
1
Z
IN
V
= G V
S
O
G = - R /R
2
1
3
Z
= R + s R (R + R ) C = R + s Leq
2 2 1 3 1 2
IN
(R + R ) >> R
1
3
2
Function Generator
C
R
R
1
2
–
+
–
+
R
R
}
A
}
B
Frequency ∝ R , R , C
1
2
Amplitude ∝ R , R
A
B
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8174.3
June 23, 2011
21
X9271
Package Outline Drawing
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 3, 10/09
A
1
3
5.00 ±0.10
SEE
DETAIL "X"
14
8
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
3
1
7
0.20 C B A
B
0.65
0.09-0.20
TOP VIEW
END VIEW
1.00 REF
0.05
H
C
0.90 +0.15/-0.10
1.20 MAX
SEATING
PLANE
GAUGE
PLANE
0.25
5
0.25 +0.05/-0.06
0.10 CBA
0°-8°
0.60 ±0.15
0.05 MIN
0.15 MAX
0.10 C
SIDE VIEW
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
(5.65)
3. Dimensions are measured at datum plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.80mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead is 0.07mm.
6. Dimension in ( ) are for reference only.
(0.65 TYP)
(0.35 TYP)
7. Conforms to JEDEC MO-153, variation AB-1.
TYPICAL RECOMMENDED LAND PATTERN
FN8174.3
June 23, 2011
22
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