X9313ZMIZ-3_技术文档

X9313

®

Digitally Controlled Potentiometer (XDCP™)

Data Sheet

April 18, 2007

FN8177.5

Linear, 32 Taps, 3 Wire Interface, Terminal

Voltages ± V

Features

CC

• Solid-state potentiometer

• 3-wire serial interface

• 32 wiper tap points

The Intersil X9313 is a digitally controlled potentiometer

(XDCP). The device consists of a resistor array, wiper

switches, a control section, and nonvolatile memory. The

wiper position is controlled by a 3-wire interface.

- Wiper position stored in nonvolatile memory and

recalled on power-up

The potentiometer is implemented by a resistor array

composed of 31 resistive elements and a wiper switching

network. Between each element and at either end are tap

points accessible to the wiper terminal. The position of the

wiper element is controlled by the CS, U/D, and INC inputs.

The position of the wiper can be stored in nonvolatile

memory and then be recalled upon a subsequent power-up

operation.

• 31 resistive elements

- Temperature compensated

- End to end resistance range ±20%

- Terminal voltages, -V

to +V

CC

• Low power CMOS

- V

CC

= 3V or 5V

- Active current, 3mA max.

- Standby current, 500µA max.

The device can be used as a three-terminal potentiometer or

as a two-terminal variable resistor in a wide variety of

applications including:

• High reliability

- Endurance, 100,000 data changes per bit

- Register data retention, 100 years

• Control

• R

TOTAL

values = 1kΩ, 10kΩ, 50kΩ

• Parameter adjustments

• Signal processing

• Packages

- 8 Ld SOIC, 8 Ld MSOP and 8 Ld PDIP

• Pb-free plus anneal available (RoHS compliant)

Block Diagram

DECODER

31

5-BIT

UP/DOWN

COUNTER

U/D

INC

CS

R /V

H

V

(SUPPLY VOLTAGE)

CC

30

29

28

R /V

H

UP/DOWN

(U/D)

5-BIT

NONVOLATILE

MEMORY

CONTROL

AND

MEMORY

ONE OF

INCREMENT

(INC)

R

/V

W

THIRTY-TWO

OUTPUTS

TRANSFER

GATES

RESISTOR

ARRAY

ACTIVE

AT A

TIME

DEVICE SELECT

(CS)

R /V

L

2

STORE AND

RECALL

CONTROL

CIRCUITRY

V

(GROUND)

SS

1

0

V

CC

SS

GENERAL

R /V

L

/V

R

W

DETAILED

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

1

All other trademarks mentioned are the property of their respective owners.

X9313

Ordering Information

TEMPERATURE

RANGE

PART

MARKING

V

RANGE

(V)

R

PKG.

DWG. #

CC

TOTAL

(kΩ)

PART NUMBER

X9313UMI

(°C)

PACKAGE

8 Ld MSOP

13UI

4.5 to 5.5

50

-40 to +85

0 to +70

M8.118

X9313UMIZ (Note)

X9313UP

DDB

8 Ld MSOP (Pb-free)

8 Ld PDIP

M8.118

X9313UP

X9313U

X9313U Z

X9313U I

X9313U ZI

DDF

MDP0031

MDP0027

M8.15

X9313US*

0 to +70

8 Ld SOIC

X9313USZ* (Note)

X9313USI

0 to +70

8 Ld SOIC (Pb-free)

8 Ld SOIC

-40 to +85

0 to +70

MDP0027

M8.15

X9313USIZ (Note)

X9313WMZ (Note)

X9313WMI*

8 Ld SOIC (Pb-free)

8 Ld MSOP (Pb-free)

8 Ld MSOP

10

M8.118

13WI

-40 to +85

0 to +70

M8.118

X9313WMIZ* (Note)

X9313WP

DDE

8 Ld MSOP (Pb-free)

8 Ld PDIP

M8.118

X9313WP

X9313WP ZD

X9313WP I

X9313WP ZI

X9313WS

X9313W Z

X9313WS I

X9313WS ZI

313Z

MDP0031

MDP0027

M8.15

X9313WPZ-3

X9313WPI

-40 to +85

0 to +70

8 Ld PDIP*** (Pb-free)

8 Ld PDIP

X9313WPIZ

8 Ld PDIP*** (Pb-free)

8 Ld SOIC

,

X9313WS* **

,

X9313WSZ* ** (Note)

0 to +70

8 Ld SOIC (Pb-free)

8 Ld SOIC

X9313WSI*

-40 to +85

0 to +70

MDP0027

M8.15

X9313WSIZ* (Note)

X9313ZM

8 Ld SOIC (Pb-free)

8 Ld MSOP

M8.118

X9313ZMZ (Note)

DDJ

0 to +70

8 Ld MSOP (Pb-free)

8 Ld MSOP

M8.118

,

X9313ZMI* **

13ZI

1

-40 to +85

0 to +70

M8.118

,

X9313ZMIZ* ** (Note)

DDH

8 Ld MSOP (Pb-free)

8 Ld PDIP

M8.118

X9313ZP

X9313ZP I

X9313ZP ZI

X9313ZS

X9313 Z

X9313ZS I

X9313ZS ZI

13UD

MDP0031

MDP0027

M8.15

X9313ZPI

-40 to +85

0 to +70

8 Ld PDIP

X9313ZPIZ (Note)

8 Ld PDIP*** (Pb-free)

8 Ld SOIC

,

X9313ZS* **

,

X9313ZSZ* ** (Note)

0 to +70

8 Ld SOIC (Pb-free)

8 Ld SOIC

X9313ZSI*

-40 to +85

0 to +70

MDP0027

M8.15

X9313ZSIZ* (Note)

X9313UM-3T1

8 Ld SOIC (Pb-free)

3 to 5.5

50

8 Ld MSOP Tape and Reel M8.118

X9313UMZ-3T1 (Note)

DDD

0 to +70

8 Ld MSOP Tape and Reel M8.118

(Pb-free)

X9313UMI-3*

13UE

-40 to +85

0 to +70

8 Ld MSOP

M8.118

MDP0027

M8.15

X9313UMIZ-3* (Note)

13UEZ

X9313U D

X9313U ZD

13WD

8 Ld MSOP (Pb-free)

8 Ld SOIC

,

X9313US-3* **

,

X9313USZ-3* ** (Note)

0 to +70

8 Ld SOIC (Pb-free)

8 Ld MSOP

X9313WM-3*

10

0 to +70

M8.118

X9313WMZ-3* (Note)

X9313WMI-3*

DDG

0 to +70

8 Ld MSOP (Pb-free)

8 Ld MSOP

13WE

-40 to +85

FN8177.5

April 18, 2007

2

X9313

Ordering Information (Continued)

TEMPERATURE

RANGE

PART

MARKING

V

RANGE

(V)

R

PKG.

DWG. #

CC

TOTAL

(kΩ)

PART NUMBER

X9313WMIZ-3* (Note)

X9313WS-3*

(°C)

PACKAGE

8 Ld MSOP (Pb-free)

8 Ld SOIC

13WEZ

-40 to +85

0 to +70

-40 to +85

0 to +70

-40 to +85

M8.118

X9313W D

X9313W ZD

13ZD

MDP0027

M8.15

X9313WSZ-3* (Note)

X9313ZM-3*

8 Ld SOIC (Pb-free)

8 Ld MSOP

3 to 5.5

1

M8.118

X9313ZMZ-3* (Note)

X9313ZMI-3*

DDK

8 Ld MSOP (Pb-free)

8 Ld MSOP

M8.118

13ZE

M8.118

X9313ZMIZ-3* (Note)

X9313ZP-3

13ZEZ

8 Ld MSOP (Pb-free)

8 Ld PDIP

M8.118

X9313ZP D

X9313ZP ZD

X9313Z D

X9313Z ZD

X9313Z E

X9313Z ZE

MDP0031

MDP0027

M8.15

X9313ZPZ-3 (Note)

X9313ZS-3*

8 Ld PDIP (Pb-free)***

8 Ld SOIC

X9313ZSZ-3* (Note)

X9313ZSI-3*

8 Ld SOIC (Pb-free)

8 Ld SOIC

MDP0027

M8.15

X9313ZSIZ-3* (Note)

8 Ld SOIC (Pb-free)

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

*Add "T1" suffix for tape and reel.

**Add "T2" suffix for tape and reel.

***Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.

Chip Select (CS)

Pin Descriptions

The device is selected when the CS input is LOW. The current

RH/VH and RL/VL

counter value is stored in nonvolatile memory when CS is

The high (RH/VH) and low (RL/VL) terminals of the X9313

returned HIGH while the INC input is also HIGH. After the

are equivalent to the fixed terminals of a mechanical

potentiometer. The terminology of RL/VL and RH/VH

references the relative position of the terminal in relation to

store operation is complete the X9313 will be placed in the low

power standby mode until the device is selected once again.

wiper movement direction selected by the U/D input and not

the voltage potential on the terminal.

Pinouts

X9313

8 LD PDIP, 8 LD SOIC

RW/VW

TOP VIEW

RW/VW is the wiper terminal and is equivalent to the

movable terminal of a mechanical potentiometer. The

position of the wiper within the array is determined by the

control inputs. The wiper terminal series resistance is

INC

1

2

3

4

8

7

6

5

VCC

U/D

RH/VH

VSS

CS

X9313

RL/VL

typically 40Ω at V

= 5V.

CC

RW/VW

Up/Down (U/D)

The U/D input controls the direction of the wiper movement

and whether the counter is incremented or decremented.

X9313

8 LD MSOP

TOP VIEW

Increment (INC)

The INC input is negative-edge triggered. Toggling INC will

move the wiper and either increment or decrement the

counter in the direction indicated by the logic level on the

U/D input.

RH/VH

U/D

INC

VCC

1

8

7

6

5

VSS

RW/VW

RL/VL

2

3

4

X9313

CS

FN8177.5

April 18, 2007

3

X9313

TABLE 1. PIN NAMES

DESCRIPTION

The system may select the X9313, move the wiper and

deselect the device without having to store the latest wiper

position in nonvolatile memory. After the wiper movement is

performed as described above and once the new position is

reached, the system must keep INC LOW while taking CS

HIGH. The new wiper position will be maintained until

changed by the system or until a power-up/down cycle

recalled the previously stored data.

SYMBOL

RH/VH

RW/VW

RL/VL

VSS

High terminal

Wiper terminal

Low terminal

Ground

VCC

Supply voltage

This procedure allows the system to always power-up to a

preset value stored in nonvolatile memory; then during

system operation minor adjustments could be made. The

adjustments might be based on user preference, system

parameter changes due to temperature drift, etc.

U/D

Up/Down control input

Increment control input

Chip Select control input

INC

CS

The state of U/D may be changed while CS remains LOW.

This allows the host system to enable the device and then

move the wiper up and down until the proper trim is attained.

Principles of Operation

There are three sections of the X9313: the input control,

counter and decode section; the nonvolatile memory; and

the resistor array. The input control section operates just like

an up/down counter. The output of this counter is decoded to

turn on a single electronic switch connecting a point on the

resistor array to the wiper output. Under the proper

conditions the contents of the counter can be stored in

nonvolatile memory and retained for future use. The resistor

array is comprised of 31 individual resistors connected in

series. At either end of the array and between each resistor

is an electronic switch that transfers the potential at that

point to the wiper.

TABLE 2. MODE SELECTION

CS

INC

U/D

MODE

L

H

Wiper up

L

Wiper down

H

X

Store wiper position

H

X

L

X

Standby current

No store, return to standby

L

H

L

Wiper up (not recommended)

Wiper down (not recommended)

The wiper, when at either fixed terminal, acts like its

mechanical equivalent and does not move beyond the last

position. That is, the counter does not wrap around when

clocked to either extreme.

Symbol Table

The electronic switches on the device operate in a “make

before break” mode when the wiper changes tap positions. If

the wiper is moved several positions, multiple taps are

connected to the wiper for t (INC to V change). The

WAVEFORM

INPUTS

OUTPUTS

Must be

steady

Will be

steady

IW

W

R

value for the device can temporarily be reduced by

TOTAL

a significant amount if the wiper is moved several positions.

May change

from Low to

High

Will change

from Low to

High

When the device is powered-down, the last wiper position

stored will be maintained in the nonvolatile memory. When

power is restored, the contents of the memory are recalled

and the wiper is set to the value last stored.

May change

from High to

Low

Will change

from High to

Low

Don’t Care:

Changes

Allowed

Changing:

State Not

Known

Instructions and Programming

The INC, U/D and CS inputs control the movement of the

wiper along the resistor array. With CS set LOW the device

is selected and enabled to respond to the U/D and INC

inputs. HIGH to LOW transitions on INC will increment or

decrement (depending on the state of the U/D input) a seven

bit counter. The output of this counter is decoded to select

one of thirty-two wiper positions along the resistive array.

N/A

Center Line

is High

Impedance

The value of the counter is stored in nonvolatile memory

whenever CS transitions HIGH while the INC input is also

HIGH.

FN8177.5

April 18, 2007

4

X9313

Absolute Maximum Ratings

Recommended Operating Conditions

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage on CS, INC, U/D, and

Temperature:

Commercial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

Supply Voltage (VCC):

X9313 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V ±10%

X9313-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 5.5V

Max Wiper current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±4.4mA

Power rating:

V

with respect to V . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V

SS

CC

Voltage on V , V , V

W

H

L

with respect to V . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6V to +7V

SS

ΔV = |V - V |:

H

L

X9313Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4V

X9313W, X9313U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10V

Lead Temperature (soldering 10s). . . . . . . . . . . . . . . . . . . . .+300°C

R

≥ 10kΩ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10mW

1kΩ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16mW

TOTAL

I

(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±8.8mA

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Pb-free PDIPs can be used for through hole wave solder processing

only. They are not intended for use in Reflow solder processing

applications

W

ESD Rating

Human Body Model (Per MIL-STD-883 Method 3015.7) . . . 2.0kV

Machine Model (Per EIAJ ED-4701 Method C-111). . . . . . . .200V

CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional

operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

Potentiometer CharacteristicsOver recommended operating conditions unless otherwise stated.

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS/NOTES

MIN

TYP

MAX

UNIT

%

End-to-end resistance tolerance

±20

V

terminal voltage

-V

+V

CC

V

VH

H

L

CC

V

-V

+V

CC

V

VL

CC

R

Wiper resistance

Wiper current

I

= (V - V )/R

, V

= 5V

40

100

Ω

W

H

L

TOTAL CC

I

±4.4

mA

dBV

%

W

Noise (Note 5)

Ref: 1kHz

-120

3

Resolution

Absolute linearity (Note 1)

R

- R

±1

MI

(Note 3)

W(n)(actual)

W(n)(expected)

Relative linearity (Note 2)

- (R

+MI)

±0.2

MI

W(n+1)

W(n)

(Note 3)

R

temperature coefficient (Note 5)

±300

±20

ppm/°C

TOTAL

Ratiometric temperature coefficient

(Note 5)

C /C /C

W

Potentiometer capacitances

See Circuit #3

10/10/25

pF

H

L

(Note 5)

NOTES:

1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = (V

- V

) = ±1 MI maximum.

W(n)(actual)

+ MI) = ±0.2 MI.

W(n)(expected)

2. Relative linearity is a measure of the error in step size between taps = R

W(n+1)

- (R

W(n)

3. 1 MI = minimum increment = R

/31.

TOT

FN8177.5

April 18, 2007

5

X9313

DC Operating Characteristics Over recommended operating conditions unless otherwise stated.

LIMITS

TYP

SYMBOL

PARAMETER

active current

TEST CONDITIONS/NOTES

MIN

(Note 4)

MAX

UNIT

I

V

CS = V , U/D = V or V and

1

3

mA

CC

IL IL IH

INC = 0.42/2.4V @ max t

CYC

I

Standby supply current

CS = V

- 0.3V, U/D and INC = V or

SS

200

500

±10

µA

SB

CC

- 0.3V

V

CC

I

CS, INC, U/D input leakage current

CS, INC, U/D input HIGH current

CS, INC, U/D input LOW current

CS, INC, U/D input capacitance

V

= V to V

SS CC

µA

V

LI

IN

V

2

IH

V

+0.8

V

IL

C

V

= 5V, V = V , T = +25°C,

IN SS

10

pF

IN

CC

A

(Note 5)

f = 1MHz

Endurance and Data Retention

PARAMETER

MIN

UNIT

Minimum endurance

100,000

Data changes per bit

per register

Data retention

100

Years

V

/R

H

R

TOTAL

V

/R

H

TEST POINT

/R

FORCE

CURRENT

R

L

H

C

L

C

W

C

H

10pF

V

S

V

VW

TEST POINT

/R

W

25pF

V

W

10pF

V /R

L

V /R

R

L

W

FIGURE 1. TEST CIRCUIT #1

FIGURE 2. TEST CIRCUIT #2

FIGURE 3. CIRCUIT #3 SPICE MACRO

MODEL

FN8177.5

April 18, 2007

6

X9313

AC Operating Characteristics Over recommended operating conditions unless otherwise stated.

LIMITS

TYP

SYMBOL

PARAMETER

MIN

100

2.9

1

(Note 4)

MAX

UNIT

ns

t

CS to INC setup

CI

ID

DI

INC HIGH to U/D change

U/D to INC setup

INC LOW period

ns

µs

t

µs

IL

IH

IC

t

INC HIGH period

1

µs

INC inactive to CS inactive

CS deselect time (STORE)

CS deselect time (NO STORE)

1

µs

t

20

100

ms

ns

CPH

t

INC to V change

W

5

µs

IW

t

INC cycle time

2

µs

CYC

t , t (Note 5)

INC input rise and fall time

Power-up to wiper stable

500

50

µs

R

F

t

(Note 5)

10

µs

PU

t

V

(Note 5)

V

power-up rate

0.2

V/ms

ms

R

CC

t

(Note 5)

Store cycle

WR

NOTES:

4. Typical values are for T = +25°C and nominal supply voltage.

A

5. This parameter is not 100% tested.

1ms after V

CC

reaches its final value. The V

CC

ramp spec is

Power-Up and Power-Down Requirements

always in effect. In order to prevent unwanted tap position

changes, or an inadvertent store, bring the CS and INC high

before or concurrently with the VCC pin on power-up.

The recommended power-up sequence is to apply V /V

CC SS

first, then the potentiometer voltages. During power-up, the

data sheet parameters for the DCP do not fully apply until

CS

t

CYC

t

CPH

CI

IL

IH

IC

90%

INC

U/D

10%

t

R

ID

DI

F

t

IW

(SEE NOTE)

MI

V

W

NOTE: MI IN THE AC TIMING DIAGRAM REFERS TO THE MINIMUM INCREMENTAL CHANGE IN THE V OUTPUT DUE TO A CHANGE IN THE WIPER

W

POSITION.

FIGURE 4. AC TIMING DIAGRAM

FN8177.5

April 18, 2007

7

X9313

computer-based digital controls, and (3) the retentivity of

nonvolatile memory used for the storage of multiple

potentiometer settings or data.

Applications Information

Electronic digitally controlled potentiometers (XDCP) provide

three powerful application advantages; (1) the variability and

reliability of a solid-state potentiometer, (2) the flexibility of

Basic Configurations of Electronic Potentiometers

V

R

V

R

V

H

L

V

/R

W

V

I

THREE-TERMINAL POTENTIOMETER;

VARIABLE VOLTAGE DIVIDER

TWO-TERMINAL VARIABLE RESISTOR;

VARIABLE CURRENT

Basic Circuits

BUFFERED REFERENCE VOLTAGE

CASCADING TECHNIQUES

NONINVERTING AMPLIFIER

R

+V

+5V

1

LM308A

V

+V

+

–

S

+5V

V

O

VW

OP-07

+

–

V

X

REF

-5V

VW/RW

V

OUT

R

2

+V

-5V

R

1

V

W

V

= V /R

W W

OUT

(a)

(b)

V

= (1 + R R )V

2/ S

O

1

VOLTAGE REGULATOR

OFFSET VOLTAGE ADJUSTMENT

COMPARATOR WITH HYSTERESIS

R

2

1

LT311A

–

V

S

V

S

V

(REG)

V

O

317

IN

O

+

100kΩ

R

1

–

+

V

O

TL072

I

adj

R

2

1

10kΩ

R

2

10kΩ

V

= [R (R + R )] V (max)

1/ 1 2 O

UL

LL

= [R (R + R )] V (min)

1/

1

2

O

V

(REG) = 1.25V (1 + R R ) + I R

2/ ADJ 2

O

1

+12V

-12V

(FOR ADDITIONAL CIRCUITS SEE AN115)

FN8177.5

April 18, 2007

8

X9313

Mini Small Outline Plastic Packages (MSOP)

N

M8.118 (JEDEC MO-187AA)

8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE

INCHES

MILLIMETERS

E1

E

SYMBOL

MIN

MAX

MIN

0.94

0.05

0.75

0.25

0.09

2.95

MAX

1.10

0.15

0.95

0.36

0.20

3.05

NOTES

A

A1

A2

b

0.037

0.002

0.030

0.010

0.004

0.116

0.043

0.006

0.037

0.014

0.008

0.120

-

-B-

0.20 (0.008)

INDEX

AREA

1 2

A

B

C

-

TOP VIEW

4X θ

9

0.25

(0.010)

R1

c

-

R

GAUGE

PLANE

D

3

E1

e

4

SEATING

PLANE

L

0.026 BSC

0.65 BSC

-

-C-

4X θ

L1

A

A2

E

0.187

0.016

0.199

0.028

4.75

0.40

5.05

0.70

-

L

6

SEATING

PLANE

L1

N

0.037 REF

0.95 REF

-

0.10 (0.004)

-A-

C

b

8

7

-H-

A1

e

R

0.003

-

0.07

-

D

0.20 (0.008)

C

R1

0

-

o

5

15

5

15

-

a

SIDE VIEW

C

L

o

0

6

0

6

-

α

E

1

-B-

Rev. 2 01/03

0.20 (0.008)

C

D

END VIEW

NOTES:

1. These package dimensions are within allowable dimensions of

JEDEC MO-187BA.

2. Dimensioning and tolerancing per ANSI Y14.5M-1994.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs and are measured at Datum Plane. Mold flash, protrusion

and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions

- H -

and are measured at Datum Plane.

Interlead flash and

protrusions shall not exceed 0.15mm (0.006 inch) per side.

5. Formed leads shall be planar with respect to one another within

0.10mm (0.004) at seating Plane.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable

dambar protrusion shall be 0.08mm (0.003 inch) total in excess

of “b” dimension at maximum material condition. Minimum space

between protrusion and adjacent lead is 0.07mm (0.0027 inch).

- B -

to be determined at Datum plane

-A -

10. Datums

and

.

- H -

11. Controlling dimension: MILLIMETER. Converted inch dimen-

sions are for reference only.

FN8177.5

April 18, 2007

9

X9313

Small Outline Plastic Packages (SOIC)

M8.15 (JEDEC MS-012-AA ISSUE C)

N

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

INDEX

AREA

0.25(0.010)

M

B M

H

INCHES

MILLIMETERS

E

SYMBOL

MIN

MAX

MIN

1.35

0.10

0.33

0.19

4.80

3.80

MAX

1.75

0.25

0.51

0.25

5.00

4.00

NOTES

-B-

A

A1

B

C

D

E

e

0.0532

0.0040

0.013

0.0688

0.0098

0.020

-

1

2

3

L

9

SEATING PLANE

A

0.0075

0.1890

0.1497

0.0098

0.1968

0.1574

-

-A-

3

h x 45°

D

4

-C-

0.050 BSC

1.27 BSC

-

α

H

h

0.2284

0.0099

0.016

0.2440

0.0196

0.050

5.80

0.25

0.40

6.20

0.50

1.27

-

e

A1

C

5

B

0.10(0.004)

L

6

0.25(0.010) M

C

A M B S

N

α

8

7

NOTES:

0°

8°

0°

8°

-

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

Rev. 1 6/05

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per

side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact.

FN8177.5

April 18, 2007

10

X9313

Small Outline Package Family (SO)

A

D

h X 45°

(N/2)+1

N

A

PIN #1

I.D. MARK

E1

E

c

SEE DETAIL “X”

1

(N/2)

B

L1

0.010 M

C A B

e

H

C

A2

A1

GAUGE

PLANE

SEATING

PLANE

0.010

L

4° ±4°

0.004 C

b

0.010 M

C

A

B

DETAIL X

MDP0027

SMALL OUTLINE PACKAGE FAMILY (SO)

INCHES

SO16

(0.150”)

SO16 (0.300”)

(SOL-16)

SO20

SO24

(SOL-24)

SO28

(SOL-28)

SYMBOL

SO-8

0.068

0.006

0.057

0.017

0.009

0.193

0.236

0.154

0.050

0.025

0.041

0.013

8

SO-14

0.068

0.006

0.057

0.017

0.009

0.341

0.236

0.154

0.050

0.025

0.041

0.013

14

(SOL-20)

0.104

0.007

0.092

0.017

0.011

0.504

0.406

0.295

0.050

0.030

0.056

0.020

20

TOLERANCE

MAX

NOTES

A

A1

A2

b

0.068

0.006

0.057

0.017

0.009

0.390

0.236

0.154

0.050

0.025

0.041

0.013

16

0.104

0.007

0.092

0.017

0.011

0.406

0.295

0.050

0.030

0.056

0.020

16

0.104

0.007

0.092

0.017

0.011

0.606

0.406

0.295

0.050

0.030

0.056

0.020

24

0.104

0.007

0.092

0.017

0.011

0.704

0.406

0.295

0.050

0.030

0.056

0.020

28

-

±0.003

±0.002

±0.003

±0.001

±0.004

±0.008

±0.004

Basic

-

c

-

D

1, 3

E

-

E1

e

2, 3

-

L

±0.009

Basic

-

L1

h

-

Reference

-

N

-

Rev. M 2/07

NOTES:

1. Plastic or metal protrusions of 0.006” maximum per side are not included.

2. Plastic interlead protrusions of 0.010” maximum per side are not included.

3. Dimensions “D” and “E1” are measured at Datum Plane “H”.

4. Dimensioning and tolerancing per ASME Y14.5M-1994

FN8177.5

April 18, 2007

11

X9313

Plastic Dual-In-Line Packages (PDIP)

E

N

1

D

PIN #1

INDEX

A2

A

E1

SEATING

PLANE

L

c

A1

NOTE 5

2

N/2

eA

eB

e

b

b2

MDP0031

PLASTIC DUAL-IN-LINE PACKAGE

INCHES

SYMBOL

PDIP8

0.210

0.015

0.130

0.018

0.060

0.010

0.375

0.310

0.250

0.100

0.300

0.345

0.125

8

PDIP14

0.210

0.015

0.130

0.018

0.060

0.010

0.750

0.310

0.250

0.100

0.300

0.345

0.125

14

PDIP16

0.210

0.015

0.130

0.018

0.060

0.010

0.750

0.310

0.250

0.100

0.300

0.345

0.125

16

PDIP18

PDIP20

0.210

0.015

0.130

0.018

0.060

0.010

1.020

0.310

0.250

0.100

0.300

0.345

0.125

20

TOLERANCE

MAX

NOTES

A

A1

A2

b

0.210

0.015

0.130

0.018

0.060

0.010

0.890

0.310

0.250

0.100

0.300

0.345

0.125

18

MIN

±0.005

±0.002

b2

c

+0.010/-0.015

+0.004/-0.002

±0.010

D

1

2

E

+0.015/-0.010

±0.005

E1

e

Basic

eA

eB

L

Basic

±0.025

±0.010

N

Reference

Rev. C 2/07

NOTES:

1. Plastic or metal protrusions of 0.010” maximum per side are not included.

2. Plastic interlead protrusions of 0.010” maximum per side are not included.

3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.

4. Dimension eB is measured with the lead tips unconstrained.

5. 8 and 16 lead packages have half end-leads as shown.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8177.5

April 18, 2007

12


型号：	X9313ZMIZ-3
厂家：	Intersil
描述：	Digitally Controlled Potentiometer 数字控制电位器电位器
文件：	总12页 (文件大小：277K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

X9313ZMIZ-3 [INTERSIL]

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