X93255_08 [INTERSIL]
Dual Digitally Controlled Potentiometers(XDCPs?); 双数字电位器（ XDCPs ？ ）
| 型号： | X93255_08 |
| 厂家： | 
Intersil |
| 描述： | Dual Digitally Controlled Potentiometers(XDCPs?) |
| 文件： | 总7页 (文件大小：158K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X93255
®
Data Sheet
February 4, 2008
FN8187.1
Dual Digitally Controlled Potentiometers
(XDCPs™)
Features
• Dual solid-state potentiometers
• Independent Up/Down interfaces
• 32 wiper tap points per potentiometer
The Intersil X93255 is a dual digitally controlled
potentiometer (XDCP). The device consists of two resistor
arrays, wiper switches, a control section, and nonvolatile
memory. The wiper positions are controlled by individual
Up/Down interfaces.
- Wiper position stored in nonvolatile memory and
recalled on power-up
• 31 resistive elements per potentiometer
- Temperature compensated
A potentiometer is implemented by a resistor array
composed of 31 resistive elements and a wiper switching
network. The position of each wiper element is controlled by
a set of independent CS, U/D, and INC inputs. The position
of the wiper can be stored in nonvolatile memory and then
be recalled upon a subsequent power-up operation.
- Maximum resistance tolerance ± 25%
- Terminal voltage, 0 to V
CC
• Low power CMOS
- V
CC
= 5V ± 10%
Each potentiometer is connected as a two-terminal variable
resistor and can be used in a wide variety of applications
including:
- Active current, 200µA typ.
- Standby current, 4µA max
• High reliability
• Bias and gain control
- Endurance 200,000 data changes per bit
- Register data retention, 100 years
• LCD Contrast Adjustment
• R
value = 50kΩ
• Package
TOTAL
Pinout
X93255
(14 LD TSSOP)
TOP VIEW
- 14 Ld TSSOP
DNC*
R
H1
14
13
12
1
2
3
R
L1
U/D
1
CS
INC
U/D
R
INC
V
1
2
2
1
CC
11
10
4
5
CS
2
R
9
8
6
7
L2
H2
SS
V
DNC*
*Do not connect.
Ordering Information
TEMP
PART NUMBER
X93255UV14I
X93255UV14IT1*
PART MARKING
X9325 5UVI
V
LIMITS (V)
R
(kΩ)
RANGE (°C)
PACKAGE
14 Ld TSSOP
14 Ld TSSOP
PKG DWG. #
M14.173
M14.173
CC
TOTAL
5 ±10%
5 ±10%
50
-40 to +85
-40 to +85
X9325 5UVI
50
* Please refer to TB347 for details on reel specifications.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1
X93255
Block Diagram
V
(SUPPLY VOLTAGE)
CC
R
H1
30kΩ
30kΩ
UP/DOWN
(U/D )
1
R
L1
CONTROL
INCREMENT
AND
(INC )
1
MEMORY
R
H2
DEVICE SELECT
(CS )
1
UP/DOWN
(U/D )
2
R
L2
CONTROL
AND
MEMORY
INCREMENT
(INC )
2
DEVICE SELECT
(CS )
2
V
(GROUND)
SS
Pin Descriptions
TSSOP
SYMBOL
DESCRIPTION
1
2
DNC
Do Not Connect
Low Terminal 1
Chip Select 1
Increment 2
R
L1
3
CS
1
4
INC
2
2
5
U/D
Up/Down 2
6
R
High Terminal 2
Ground
H2
7
V
SS
8
DNC
Do Not Connect
Low Terminal 2
Chip Select 2
Supply Voltage
Increment 1
9
R
L2
10
11
12
13
14
CS
2
V
CC
INC
U/D
1
1
Up/Down 1
R
High Terminal 1
H1
FN8187.1
February 4, 2008
2
X93255
Absolute Maximum Ratings
Thermal Information
Voltage on CS, INC, U/D, R , R and V
Temperature under bias. . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Lead temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . . +300°C
Maximum reflow temperature (40s). . . . . . . . . . . . . . . . . . . . +240°C
H
L
CC
with respect to V
. . . . . . . . . . . . . . . . . . . . . . . . . .-1V to +6.5V
SS
Maximum resistor current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2mA
Recommended Operating Conditions
Temperature Range
Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V ±10% (Note 6)
CC
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. Absolute linearity is utilized to determine actual wiper resistance vs expected resistance = (R
±1 Ml Maximum. n = 1 .. 29 only
(actual) - R
(expected)) =
H(n)
H(n)
2. Relative linearity is a measure of the error in step size between taps = R
- [R
+ Ml] = ±0.5 Ml, n = 1 .. 29 only.
H(n)
H(n+1)
3. 1 Ml = Minimum Increment = R
/31.
TOT
4. Typical values are for T = +25°C and nominal supply voltage.
A
5. Limits established by characterization and are not production tested.
6. When performing multiple write operations, V
must not decrease by more than 150mV from its initial value.
CC
7. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested.
Potentiometer Characteristics
Over recommended operating conditions, unless otherwise specified.
MIN
TYP
MAX
SYMBOL
PARAMETER
End-to-End Resistance
R , R Terminal Voltages
TEST CONDITIONS/NOTES
(Note 7)
37.5
0
(Note 4)
(Note 7)
UNIT
kΩ
R
50
-120
3
62.5
TOT
V
V
V
R
H
L
CC
Power Rating
R
= 50kΩ (Note 5)
1
mΩ
(Note 6)
TOTAL
Noise
Ref: 1kHz (Note 5)
dBV
(Note 6)
R
Wiper Resistance
Wiper Current
(Note 5)
(Note 5)
1000
0.6
Ω
mA
%
W
I
W
Resolution
Absolute Linearity (Note 1)
R
R
- R
H(n)(expected)
±1
MI
(Note 3)
H(n)(actual)
Relative Linearity (Note 2)
[R
]
±0.5
MI
H(n+1 - H(n)+MI
(Note 3)
R
Temperature Coefficient
(Notes 5)
±35
ppm/°C
pF
TOTAL
C /C /C
W
Potentiometer Capacitances
See “Circuit #2 SPICE Macro Model”
on page 4
10/10/25
H
L
FN8187.1
February 4, 2008
3
X93255
DC Operating Specifications Over recommended operating conditions unless otherwise specified.
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 7)
(Note 4)
(Note 7)
UNIT
I
V
V
Active Current (Increment) per DCP CS = V , U/D = V or V and
200
300
1400
4
µA
CC1
CC
CC
IL IL IH
INC = 0.4V @ max. t
CYC
I
Active Current (Store)
CS = V , U/D = V or V and
IH IL IH
µA
µA
CC2
(EEPROM Store) per DCP
INC = V @ max. t
IH
WR
I
Standby Supply Current
CS = V
- 0.3V, U/D and
SB
CC
INC = V or V
- 0.3V
CC
SS
= V
I
I
I
CS
V
V
V
±1
250
±1
µA
µA
µA
V
LI
LI
LI
CS
CC
= 5V, CS = 0
= V to V
CS
120
200
CC
INC, U/D Input Leakage Current
CS, INC, U/D Input HIGH Voltage
CS, INC, U/D Input LOW Voltage
CS, INC, U/D Input Capacitance
IN
SS
CC
V
V
x 0.7
V
CC
+ 0.5
x 0.1
IH
CC
V
-0.5
V
V
IL
CC
C
V
= 5V, V = V , T = +25°C,
IN SS
10
pF
IN
CC
A
(Note 6)
f = 1MHz (Note 5)
Endurance and Data Retention
AC Conditions of Test
PARAMETER
Minimum endurance
Data retention
MIN
200,000
100
UNIT
Input pulse levels
0V to 5V
Data changes per bit
Years
Input rise and fall times
Input reference levels
10ns
1.5V
Test Circuit #1
Circuit #2 SPICE Macro Model
TEST POINT
R
TOTAL
V /R
H
H
R
R
L
H
C
L
C
W
C
H
10pF
25pF
10pF
AC Operating Characteristics Over recommended operating conditions unless otherwise specified. In the table, CS, INC, U/D, R and
H
R
are used to refer to either CS or CS , etc.
L
1
2
MIN
TYP
MAX
SYMBOL
PARAMETER
(Note 7)
(Note 4)
(Note 7)
UNIT
ns
t
CS to INC Setup
100
100
100
1
Cl
lD
DI
t
INC HIGH to U/D Change
U/D to INC Setup
ns
t
ns
t
INC LOW Period
µs
lL
lH
lC
t
t
INC HIGH Period
1
µs
INC Inactive to CS Inactive
CS Deselect Time (No store)
CS Deselect Time (Store)
INC Cycle Time
1
µs
t
t
t
250
10
2
ns
CPH
CPH
CYC
ms
µs
t
t
INC Input Rise and Fall Time
500
50
µs
R, F
(Note 5)
t
V
V
Power-up Rate
1
V/ms
ms
R
CC
CC
(Note 5)
t
Store cycle
5
10
WR
FN8187.1
February 4, 2008
4
X93255
AC Timing
CS
t
CYC
(STORE)
t
t
t
t
t
CPH
CI
IL
IH
IC
90%
90%
INC
U/D
10%
t
t
t
t
R
ID
DI
F
Note: CS, INC, U/D, R and R are used to refer
H
L
to either CS or CS , etc.
1
2
Power-up and Power-down Requirements
Principles of Operation
There are no restrictions on the power-up or power-down
There are multiple sections for each potentiometer in the
X93255: an input control, a counter and decode section; the
nonvolatile memory; and a resistor array. Each input control
section operates just like an up/down counter. The output of
this counter is decoded to turn on a single electronic switch
connecting a point on the resistor array to the wiper output.
Under the proper conditions, the contents of the counter can
be stored in nonvolatile memory and retained for future use.
Each resistor array is comprised of 31 individual resistors
connected in series. At either end of the array and between
each resistor is an electronic switch that transfers the
conditions of V
and the voltages applied to the
potentiometer pins provided that V is always more
CC
CC
positive than or equal to V and V , i.e., V
≥ V V . The
H, L
H
L
CC
V
ramp rate specification is always in effect.
CC
Pin Descriptions
R and R
H
L
The R and R pins of the X93255 are equivalent to the end
H
L
terminals of a variable resistor. The minimum voltage is V
SS
and the maximum is V . The terminology of R and R
CC
H
L
connection at that point to the wiper. The wiper is connected
references the relative position of the terminal in relation to
wiper movement direction selected by the U/D input per
potentiometer.
to the R terminal, forming a variable resistor from R to R .
L
H
L
Each wiper, when at either fixed terminal, acts like its
mechanical equivalent and does not move beyond the last
position. That is, the counter does not wrap around when
clocked to either extreme.
Up/Down (U/D)
The U/D input controls the direction of a single
potentiometer’s wiper movement and whether the counter is
incremented or decremented.
If the wiper is moved several positions, multiple taps are
connected to the wiper for up to 10µs. The 2-terminal
Increment (INC)
resistance value for the device can temporarily change by a
significant amount if the wiper is moved several positions.
The INC input is negative-edge triggered. Toggling INC will
move the wiper and either increment or decrement the
pertaining potentiometer’s counter in the direction indicated
by the logic level on the pertaining potentiometer’s U/D
input.
When the device is powered-down, the last wiper position
stored will be maintained in the nonvolatile memory for each
potentiometer. When power is restored, the contents of the
memory are recalled and each wiper is set to the value last
stored.
Chip Select (CS)
A potentiometer is selected when the pertaining CS input is
LOW. Its current counter value is stored in nonvolatile
memory when the pertaining CS is returned HIGH while the
pertaining INC input is also HIGH. After the store operation
is complete, the affected potentiometer will be placed in the
low power standby mode until the potentiometer is selected
once again.
FN8187.1
February 4, 2008
5
X93255
Mode Selection
Instructions and Programming
The INC, U/D and CS inputs control the movement of the
pertaining wiper along the resistor array. With CS set LOW,
the pertaining potentiometer is selected and enabled to
respond to the U/D and INC inputs. HIGH to LOW transitions
on INC will increment or decrement (depending on the state
of the U/D input) a 5-bit counter. The output of this counter is
decoded to select one of thirty two wiper positions along the
resistive array.
CS
INC
U/D
H
L
MODE
L
Wiper Up
L
Wiper Down
H
X
L
L
L
X
Store Wiper Position
H
X
Standby Current
X
No Store, Return to Standby
Wiper Up (not recommended)
Wiper Down (not recommended)
H
L
The value of the counter is stored in nonvolatile memory
whenever each CS transitions HIGH while the pertaining
INC input is also HIGH. In order to avoid an accidental store
during power-up, each CS must go HIGH with V
during
Symbol Table
CC
initial power-up. When left open, each CS pin is internally
pulled up to V by an internal 30k resistor.
CC
WAVEFORM
INPUTS
OUTPUTS
The system may select the X93255, move any wiper and
deselect the device without having to store the latest wiper
position in nonvolatile memory. After the wiper movement is
performed as previously described and once the new
position is reached, the system must keep INC LOW while
taking CS HIGH. The new wiper position will be maintained
until changed by the system or until a power-up/down cycle
recalled the previously stored data. In order to recall the
stored position of the wiper on power-up, the CS pin must be
held HIGH.
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
This procedure allows the system to always power-up to a
preset value stored in nonvolatile memory; then during
system operation minor adjustments could be made. The
adjustments might be based on user preference, system
parameter changes due to temperature drift, or other system
trim requirements.
N/A
Center Line
is High
Impedance
The state of U/D may be changed while CS remains LOW.
This allows the host system to enable the device and then
move each wiper up and down until the proper trim is
attained.
FN8187.1
February 4, 2008
6
X93255
Thin Shrink Small Outline Plastic Packages (TSSOP)
M14.173
N
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
E
E1
-B-
INCHES
MIN
MILLIMETERS
GAUGE
PLANE
SYMBOL
MAX
0.047
0.006
0.041
0.0118
0.0079
0.199
0.177
MIN
-
MAX
1.20
0.15
1.05
0.30
0.20
5.05
4.50
NOTES
A
A1
A2
b
-
-
1
2
3
0.002
0.031
0.0075
0.0035
0.195
0.169
0.05
0.80
0.19
0.09
4.95
4.30
-
L
0.25
0.010
-
0.05(0.002)
SEATING PLANE
A
9
-A-
D
c
-
D
3
-C-
α
E1
e
4
A2
e
A1
0.026 BSC
0.65 BSC
-
c
b
0.10(0.004)
E
0.246
0.256
6.25
0.45
6.50
0.75
-
0.10(0.004) M
C
A M B S
L
0.0177
0.0295
6
N
14
14
7
NOTES:
o
o
o
o
0
8
0
8
-
α
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
Rev. 2 4/06
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8187.1
February 4, 2008
7
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