X9400WS24IZ-2.7 [INTERSIL]
Quad Digitally Controlled Potentiometers; 四通道数字电位器
| 型号： | X9400WS24IZ-2.7 |
| 厂家： | 
Intersil |
| 描述： | Quad Digitally Controlled Potentiometers |
| 文件： | 总19页 (文件大小：356K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X9400
®
Low Noise/Low Power/SPI Bus
Data Sheet
July 28, 2006
FN8189.3
DESCRIPTION
Quad Digitally Controlled Potentiometers
(XDCP™)
The X9400 integrates four digitally controlled
potentiometers (XDCPs) on a monolithic CMOS
integrated circuit.
FEATURES
• Four potentiometers per package
• 64 resistor taps
The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI
serial bus interface. Each potentiometer has
associated with it a volatile Wiper Counter Register
(WCR) and four nonvolatile Data Registers (DR0-3)
that can be directly written to and read by the user.
The contents of the WCR controls the position of the
wiper on the resistor array through the switches.
Power-up recalls the contents of DR0 to the WCR.
• SPI serial interface for write, read, and transfer
operations of the potentiometer
• Wiper resistance, 40Ω typical at 5V.
• Four non-volatile data registers for each
potentiometer
• Non-volatile storage of multiple wiper position
• Power-on recall. Loads saved wiper position on
power-up.
• Standby current < 1µA max
• System V : 2.7V to 5.5V operation
CC
+
–
• Analog V /V : -5V to +5V
• 10kΩ, 2.5kΩ end to end resistance
• 100 yr. data retention
• Endurance: 100,000 data changes per bit per
register
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
• Low power CMOS
• 24 Ld SOIC and 24 Ld TSSOP
• Pb-free plus anneal available (RoHS compliant)
BLOCK DIAGRAM
V
V
CC
SS
Pot 0
R0 R1
R2 R3
V
/R
H0 H0
R0 R1
R2 R3
V+
V-
Wiper
Counter
Register
(WCR)
Wiper
Counter
Register
(WCR)
V
/R
H2 H2
Resistor
Array
Pot 2
V
/R
L0 L0
HOLD
V
/R
L2 L2
CS
SCK
SO
SI
V
/R
W0 W0
V
/R
W2 W2
Interface
and
Control
8
Circuitry
A0
A1
V
/R
W1 W1
Data
V
/R
W3 W3
WP
R0 R1
R2 R3
R0 R1
R2 R3
V
/R
Wiper
Counter
Register
(WCR)
H1 H1
V
/R
Resistor
Array
Pot 1
Wiper
Counter
Register
(WCR)
H3 H3
Resistor
Array
Pot 3
V
/R
L1 L1
V
/R
L3 L3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9400
Ordering Information
POTENTIOMETER TEMPERATURE
PART
MARKING
V
LIMITS
(V)
ORGANIZATION
RANGE
(°C)
CC
PART NUMBER
(kΩ)
PACKAGE
PKG. DWG. #
M24.3
X9400WS24*
X9400WS
5 ±10%
10
0 to +70
0 to +70
24 Ld SOIC (300 mil)
X9400WS24ZT1
(Note)
X9400WS Z
24 Ld SOIC (300 mil) (Pb-free)
Tape and Reel
M24.3
X9400WS24I*
X9400WS I
-40 to +85
-40 to +85
24 Ld SOIC (300 mil)
M24.3
M24.3
X9400WS24IZ*
(Note)
X9400WS ZI
24 Ld SOIC (300 mil) (Pb-free)
X9400WV24*
X9400WV24I*
X9400WV
0 to +70
-40 to +85
-40 to +85
24 Ld TSSOP (4.4mm)
MDP0044
MDP0044
MDP0044
X9400WV I
X9400WV ZI
24 Ld TSSOP (4.4mm)
X9400WV24IZ*
(Note)
24 Ld TSSOP (4.4mm) (Pb-free)
X9400WV24Z*
(Note)
X9400WV Z
0 to +70
24 Ld TSSOP (4.4mm) (Pb-free)
MDP0044
X9400YS24*
X9400YS24I*
X9400YV24*
X9400YV24I*
X9400YS
2.5
0 to +70
-40 to +85
0 to +70
24 Ld SOIC (300 mil)
M24.3
X9400YS I
X9400YV
24 Ld SOIC (300 mil)
M24.3
24 Ld TSSOP (4.4mm)
24 Ld TSSOP (4.4mm)
24 Ld TSSOP (4.4mm) (Pb-free)
MDP0044
MDP0044
MDP0044
X9400YV I
X9400YV ZI
-40 to +85
-40 to +85
X9400YV24IZ*
(Note)
X9400YV24Z*
(Note)
X9400YV Z
0 to +70
24 Ld TSSOP (4.4mm) (Pb-free)
MDP0044
X9400WS24-2.7*
X9400WS24I-2.7*
X9400WS F
X9400WS G
2.7 to 5.5
10
0 to +70
-40 to +85
-40 to +85
24 Ld SOIC (300 mil)
M24.3
M24.3
M24.3
24 Ld SOIC (300 mil)
X9400WS24IZ-2.7* X9400WS ZG
(Note)
24 Ld SOIC (300 mil) (Pb-free)
X9400WV24-2.7*
X9400WV24I-2.7*
X9400WV F
X9400WV G
0 to +70
-40 to +85
-40 to +85
24 Ld TSSOP (4.4mm)
MDP0044
MDP0044
MDP0044
24 Ld TSSOP (4.4mm)
X9400WV24IZ-2.7* X9400WV ZG
(Note)
24 Ld TSSOP (4.4mm) (Pb-free)
X9400WV24Z-2.7* X9400WV ZF
(Note)
0 to +70
24 Ld TSSOP (4.4mm) (Pb-free)
MDP0044
X9400YS24-2.7*
X9400YS24I-2.7*
X9400YV24-2.7*
X9400YV24I-2.7*
X9400YS F
X9400YS G
X9400YV F
X9400YV G
2.5
0 to +70
-40 to +85
0 to +70
24 Ld SOIC (300 mil)
M24.3
24 Ld SOIC (300 mil)
M24.3
24 Ld TSSOP (4.4mm)
24 Ld TSSOP (4.4mm)
24 Ld TSSOP (4.4mm) (Pb-free)
MDP0044
MDP0044
MDP0044
-40 to +85
-40 to +85
X9400YV24IZ-2.7* X9400YV ZG
(Note)
X9400YV24Z-2.7*
(Note)
X9400YV ZF
0 to +70
24 Ld TSSOP (4.4mm) (Pb-free)
MDP0044
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN8189.3
July 28, 2006
2
X9400
PIN DESCRIPTIONS
Host Interface Pins
Serial Output (SO)
be brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked
out by the falling edge of the serial clock.
Device Address (A - A )
0
1
The address inputs are used to set the least significant
2 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9400. A maximum of 4 devices may occupy the
SPI serial bus.
Serial Input
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
Potentiometer Pins
Serial Clock (SCK)
V /R (V /R - V /R ), V /R (V /R
H0 H0 H3 H3 L0 L0
L3 L3
-
H
H
L
L
The SCK input is used to clock data into and out of the
X9400.
V
/R )
The V /R and V /R inputs are equivalent to the
H
H
L
L
terminal connections on either end of a mechanical
potentiometer.
Chip Select (CS)
When CS is HIGH, the X9400 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9400, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
V /R (V /R
W0 W0
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.
- V /R )
W3 W3
W
W
Hardware Write Protect Input (WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
Analog Supplies (V+, V-)
The analog Supplies V+, V- are the supply voltages for
the XDCP analog section.
PIN CONFIGURATION
SOIC
TSSOP
V+
V
V
WP
SI
1
2
24
23
22
21
20
19
18
17
16
15
1
2
24
23
22
21
20
19
18
17
16
15
CC
/R
V
/R
CS
V
A
L3 L3
L0 L0
1
/R
V
V
A
/R
V
/R
3
V
/R
W0 W0
H3 H3
3
H0 H0
/R
L1 L1
/R
V
V
V
V
/R
/R
V
4
H1 H1
H0 H0
W3 W3
4
W0 W0
CS
V
/R
W1 W1
/R
5
5
L0 L0
0
V
SO
SS
WP
6
6
CC
X9400
X9400
SI
V-
HOLD
SCK
7
V+
V
7
V
/R
A
1
/R
W2 W2
8
8
L3 L3
V
V
/R
V
/R
H2 H2
V
/R
9
V
V
/R
9
L2 L2
L1 L1
H3 H3
V
/R
/R
/R
10
L2 L2
H2 H2
10
V
/R
W3 W3
H1 H1
V
/R
A
14
13
SCK
14
13
V
/R
W2 W2
11
12
0
11
12
W1 W1
V
HOLD
V-
SS
SO
FN8189.3
July 28, 2006
3
X9400
PIN NAMES
Symbol
Wiper Counter Register (WCR)
The X9400 contains four Wiper Counter Registers,
one for each XDCP potentiometer. The WCR is
equivalent to a serial-in, parallel-out register/counter
with its outputs decoded to select one of sixty-four
switches along its resistor array. The contents of the
WCR can be altered in four ways: it may be written
directly by the host via the write Wiper Counter
Register instruction (serial load); it may be written
indirectly by transferring the contents of one of four
associated data registers via the XFR Data Register or
global XFR data register instructions (parallel load); it
can be modified one step at a time by the
increment/decrement instruction. Finally, it is loaded
with the contents of its Data Register zero (DR0) upon
power-up.
Description
Serial Clock
SCK
SI, SO
Serial Data
A - A
Device Address
0
1
V
/R - V /R
H0 H0 H3 H3
,
Potentiometer Pins (terminal
equivalent)
V /R - V /R
L0 L0 L3 L3
V
/R
- V /R
Potentiometer Pins (wiper
equivalent)
W0 W0 W1 W1
WP
Hardware Write Protection
System Supply Voltage
System Ground
V
V
CC
SS
NC
No Connection
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9400 is powered-
down. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.
DEVICE DESCRIPTION
The X9400 is highly integrated microcircuit
incorporating four resistor arrays and their associated
registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.
a
Data Registers
Each potentiometer has four 6-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the
data registers is a nonvolatile operation and will take a
maximum of 10ms.
Serial Interface
The X9400 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.
Array Description
Data Register Detail
The X9400 is comprised of four resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
(MSB)
D5
(LSB)
D0
D4
NV
D3
NV
D2
NV
D1
NV
NV
NV
potentiometer (V /R and V /R inputs).
H
H
L
L
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(V /R ) output. Within each individual array only one
W
W
switch may be turned on at a time.
These switches are controlled by a wiper counter
register (WCR). The six bits of the WCR are decoded
to select, and enable, one of sixty-four switches.
FN8189.3
July 28, 2006
4
X9400
Figure 1. Detailed Potentiometer Block Diagram
(One of Four Arrays)
Serial Data Path
Serial
Bus
Input
V /R
H H
From Interface
Circuitry
C
o
u
n
t
Register 0
Register 2
Register 1
8
6
Parallel
Bus
Input
e
r
Wiper
D
e
c
o
d
e
Register 3
Counter
Register
(WCR)
INC/DEC
Logic
If WCR = 00[H] then V /R = V /R
W
W
L
L
UP/DN
UP/DN
If WCR = 3F[H] then V /R = V /R
H
W
W
H
V /R
Modified SCL
L
L
CLK
V
/R
W
W
Write in Process
continue the command sequence. The A - A inputs
0 1
can be actively driven by CMOS input signals or tied to
or V
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW
to HIGH after a complete write sequence is received
by the device. The progress of this internal write
operation can be monitored by a write in process bit
(WIP). The WIP bit is read with a read status
command.
V
.
SS
CC
The remaining two bits in the slave byte must be set to 0.
Figure 2. Identification Byte Format
Device Type
Identifier
INSTRUCTIONS
0
1
0
1
0
0
A1
A0
Identification (ID) Byte
The first byte sent to the X9400 from the host,
following a CS going HIGH to LOW, is called the
Identification byte. The most significant four bits of the
slave address are a device type identifier, for the
X9400 this is fixed as 0101[B] (refer to Figure 2).
Device Address
Instruction Byte
The next byte sent to the X9400 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next four
bits point to one of the four pots and, when applicable,
they point to one of four associated registers. The
format is shown below in Figure 3.
The two least significant bits in the ID byte select one
of four devices on the bus. The physical device
address is defined by the state of the A - A input
0
1
pins. The X9400 compares the serial data stream with
the address input state; a successful compare of both
address bits is required for the X9400 to successfully
FN8189.3
July 28, 2006
5
X9400
Figure 3. Instruction Byte Format
Five instructions require a three-byte sequence to
complete. These instructions transfer data between the
host and the X9400; either between the host and one of
the data registers or directly between the host and the
Wiper Counter Register. These instructions are:
Register
Select
I3
I2
I1
I0
R1 R0
P1
P0
– Read Wiper Counter Register—read the current
wiper position of the selected pot,
Pot Select
Instructions
– Write Wiper Counter Register—change current
wiper position of the selected pot,
The four high order bits of the instruction byte specify
the operation. The next two bits (R and R ) select
– Read Data Register—read the contents of the
selected data register;
1
0
one of the four registers that is to be acted upon when
a register oriented instruction is issued. The last two
bits (P and P ) selects which one of the four
– Write Data Register—write a new value to the
selected data register.
1
0
potentiometers is to be affected by the instruction.
– Read Status—This command returns the contents
of the WIP bit which indicates if the internal write
cycle is in progress.
Four of the ten instructions are two bytes in length and
end with the transmission of the instruction byte.
These instructions are:
The sequence of these operations is shown in Figure 5
and Figure 6.
– XFR Data Register to Wiper Counter Register—This
transfers the contents of one specified Data Register
to the associated Wiper Counter Register.
The final command is Increment/Decrement. It is
different from the other commands, because it’s length
is indeterminate. Once the command is issued, the
master can clock the selected wiper up and/or down in
one resistor segment steps; thereby, providing a fine
tuning capability to the host. For each SCK clock pulse
– XFR Wiper Counter Register to Data Register —
This transfers the contents of the specified Wiper
Counter Register to the specified associated Data
Register.
(t
) while SI is HIGH, the selected wiper will move
one resistor segment towards the V /R terminal.
HIGH
– Global XFR Data Register to Wiper Counter Register
—This transfers the contents of all specified Data
Registers to the associated Wiper Counter Registers.
H
H
Similarly, for each SCK clock pulse while SI is LOW, the
selected wiper will move one resistor segment towards
– Global XFR Wiper Counter Register to Data Register
—This transfers the contents of all Wiper Counter
Registers to the specified associated Data Registers.
the V /R terminal. A detailed illustration of the
L
L
sequence and timing for this operation are shown in
Figure 7 and Figure 8.
The basic sequence of the two byte instructions is
illustrated in Figure 4. These two-byte instructions
exchange data between the WCR and one of the data
registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action will be delayed by t
. A transfer
WRL
from the WCR (current wiper position), to a data
register is a write to nonvolatile memory and takes a
minimum of t
to complete. The transfer can occur
WR
between one of the four potentiometers and one of its
associated registers; or it may occur globally, where the
transfer occurs between all potentiometers and one
associated register.
FN8189.3
July 28, 2006
6
X9400
Figure 4. Two-Byte Instruction Sequence
CS
SCK
SI
0
1
0
1
0
0
A1 A0
I3 I2
I1 I0 R1 R0 P1 P0
Figure 5. Three-Byte Instruction Sequence (Write)
CS
SCK
SI
0
0
0
1
0
1
A1 A0
I3 I2
I1 I0 R1 R0 P1 P0
0
0
D5 D4 D3 D2 D1 D0
Figure 6. Three-Byte Instruction Sequence (Read)
CS
SCK
SI
Don’t Care
0
0
0
1
0
1
A1 A0
I3 I2
I1 I0 R1 R0 P1 P0
S0
0
0
D5 D4 D3 D2 D1 D0
Figure 7. Increment/Decrement Instruction Sequence
CS
SCK
SI
P1
0
1
0
1
0
0
A1 A0
I3 I2
I1 I0
0
0
P0
I
I
D
E
C
1
I
D
E
C
n
N
C
1
N
C
2
N
C
n
FN8189.3
July 28, 2006
7
X9400
Figure 8. Increment/Decrement Timing Limits
t
WRID
SCK
SI
Voltage Out
V
/R
W
W
INC/DEC CMD Issued
Table 1. Instruction Set
Instruction Set
Instruction
Read Wiper Counter Register
I
1
I
0
I
I
1
R
0
R
0
P
P
P
Operation
Read the contents of the Wiper Counter Register
pointed to by P - P
3
2
1
0
1
0
1
0
0
1
1
0
0
P
1
0
1
0
Write Wiper Counter Register
Read Data Register
1
1
1
1
0
0
1
1
0
1
0
1
0
0
P
P
P
P
P
P
P
P
Write new value to the Wiper Counter Register
pointed to by P - P
1
1
1
1
0
0
0
0
1
0
R
R
Read the contents of the Data Register pointed to
by P - P and R - R
1
1
1
0
0
0
1
0
1
0
Write Data Register
R
R
R
R
Write new value to the Data Register pointed to by
P - P and R - R
1
0
1
0
XFR Data Register to Wiper
Counter Register
Transfer the contents of the Data Register pointed to
by R - R to the Wiper Counter Register pointed to by
1
0
P - P
1
0
XFR Wiper Counter Register
to Data Register
1
0
1
1
0
0
1
0
0
0
1
0
R
R
R
R
R
R
P
P
Transfer the contents of the Wiper Counter
Register pointed to by P - P to the Register
1
1
1
0
0
0
1
0
1
0
pointed to by R - R
1
0
Global XFR Data Register to
Wiper Counter Register
0
0
Transfer the contents of the Data Registers pointed
to by R - R of all four pots to their respective Wiper
1
0
Counter Register
Global XFR Wiper Counter
Register to Data Register
0
0
Transfer the contents of all Wiper Counter
Registers to their respective data Registers
pointed to by R - R of all four pots
1
0
Increment/Decrement Wiper
Counter Register
0
0
0
1
1
0
0
1
0
0
P
P
Enable Increment/decrement of the Wiper Counter
Register pointed to by P - P
1
0
1
0
Read Status (WIP bit)
0
0
0
1
Read the status of the internal write cycle, by
checking the WIP bit.
FN8189.3
July 28, 2006
8
X9400
Instruction Format
Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master.
(2) WPx refers to wiper position data in the Counter Register
(3) “I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
(4) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
Read Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
WCR
addresses
wiper position
(sent by X9400 on SO)
CS
CS
Falling
Edge
Rising
Edge
W W W W W W
0 P P P P P P
A A
P
1
P
0
0
1
0
1
0
0
1
0
0
1
0
0
0
0
1
0
5
4 3 2 1 0
Write Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
WCR
addresses
Data Byte
(sent by Host on SI)
CS
Falling
Edge
CS
Rising
Edge
W W W W W W
0 P P P P P P
A A
P
1
P
0
0
1
0
1
0
0
1
0
1
0
0
0
1
0
5
4 3 2 1 0
Read Data Register (DR)
device type
identifier
device
addresses
instruction DR and WCR
opcode addresses
Data Byte
(sent by X9400 on SO)
CS
CS
Falling
Edge
Rising
Edge
W W W W W W
0 0 P P P P P P
A A
R
1
R
0
P
1
P
0
0
1
0
1
0
0
1
0
1
1
1
0
5
4 3 2 1 0
Write Data Register (DR)
device type
identifier
device
addresses
instruction DR and WCR
opcode addresses
Data Byte
(sent by host on SI)
CS
Falling
Edge
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
W W W W W W
0 P P P P P P
A A
1
R
1
R
0
P
1
P
0
0
1
0
1
0
0
1
1
0
0
0
0
5
4 3 2 1 0
Transfer Data Register (DR) to Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction DR and WCR
opcode addresses
CS
Falling
Edge
CS
Rising
Edge
A A
1
R
1
R
0
P
1
P
0
0
1
0
1
0
0
1 1 0 1
0
Transfer Wiper Counter Register (WCR) to Data Register (DR)
device type
identifier
device
addresses
instruction DR and WCR
opcode addresses
CS
Falling
Edge
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
A A
1
R
1
R
0
P
1
P
0
0
1
0
1
0
0
1 1 1 0
0
FN8189.3
July 28, 2006
9
X9400
Increment/Decrement Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
WCR
increment/decrement
CS
Falling
Edge
CS
Rising
Edge
addresses (sent by master on SDA)
A A
1
P P I/ I/
1 0 D D
I/ I/
D D
0
1
0
1
0
0
0
0
1
0
X X
.
.
.
.
0
Global Transfer Data Register (DR) to Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
DR
addresses
CS
Falling
Edge
CS
Rising
Edge
A
1
A
0
R R
1 0
0
1
0
1
0
0
0
0
0
1
0 0
Global Transfer Wiper Counter Register (WCR) to Data Register (DR)
device type
identifier
device
addresses
instruction
opcode
DR
addresses
CS
Falling
Edge
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
A A
1
R R
1 0
0
1
0
1
0
0
1
0
0
0
0 0
0
Read Status
device type
identifier
device
addresses
instruction
opcode
wiper
addresses
Data Byte
(sent by X9400 on SO)
CS
CS
Falling
Edge
Rising
Edge
W
I
P
A A
0
1
0
1
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
FN8189.3
July 28, 2006
10
X9400
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias.................... -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
Voltage on SCK, SCL or any address
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification)
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
input with respect to V ......................... -1V to +7V
SS
Voltage on V+ (referenced to V )........................10V
SS
Voltage on V- (referenced to V )........................-10V
SS
(V+) - (V-) ..............................................................12V
Any V ....................................................................V+
H
Any V ......................................................................V-
L
Lead temperature (soldering, 10 seconds)........ 300°C
I
(10 seconds)................................................±12mA
W
RECOMMENDED OPERATING CONDITIONS
Temp
Commercial
Industrial
Min.
0°C
-40°C
Max.
+70°C
+85°C
Device
X9400
Supply Voltage (V ) Limits
CC
5V ± 10%
2.7V to 5.5V
X9400-2.7
ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
R
Parameter
End to end resistance
Power rating
Min.
Typ.
Max.
±20
50
Unit
%
Test Conditions
TOTAL
mW
mA
Ω
25°C, each pot
I
Wiper current
±6
W
R
Wiper resistance
150
40
250
Wiper Current = ± 1mA,
= 3V
W
V
CC
Wiper Current = ± 1mA,
= 5V
100
Ω
V
CC
Vv+
Vv-
Voltage on V+ Pin
Voltage on V- Pin
X9400
+4.5
+2.7
-5.5
-5.5
V-
+5.5
+5.5
-4.5
-2.7
V+
V
X9400-2.7
X9400
V
X9400-2.7
V
Voltage on any V /R or V /R Pin
V
dBV
%
TERM
H
H
L
L
Noise
-120
1.6
Ref: 1kHz
Resolution
(1)
(3)
Absolute linearity
Relative linearity
-1
+1
MI
R
R
- R
w(n)(expected)
w(n)(actual)
(2)
(3)
MI
-0.2
+0.2
- [R
]
w(n + 1)
w(n) + MI
Temperature coefficient of R
Ratiometric temp. coefficient
Potentiometer capacitances
±300
ppm/°C
ppm/°C
pF
TOTAL
±20
10
C /C /C
10/10/25
0.1
See Spice Macromodel
H
L
W
I
R , R , R leakage current
µA
V
= V to V . Device is in
SS CC
AL
H
L
W
IN
stand-by mode.
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when
used as a potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (R - R )/63, single pot
H
L
FN8189.3
July 28, 2006
11
X9400
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
I
V
V
supply current (Active)
400
µA
f = 2MHz, SO = Open,
SCK
CC1
CC
CC
Other Inputs = V
SS
I
supplycurrent(Nonvolatile
1
mA
f
= 2MHz, SO = Open,
CC2
SCK
Other Inputs = V
Write)
SS
I
V
current (standby)
1
µA
µA
µA
V
SCK = SI = V , Addr. = V
SS SS
SB
CC
I
Input leakage current
Output leakage current
Input HIGH voltage
Input LOW voltage
Output LOW voltage
10
10
V
V
= V to V
SS CC
LI
IN
I
= V to V
SS CC
LO
OUT
V
V
x 0.7
V
+ 0.5
CC
IH
CC
V
-0.5
V
x 0.1
V
IL
CC
0.4
V
V
I
= 3mA
OL
OL
ENDURANCE AND DATA RETENTION
Parameter
Minimum endurance
Data retention
Min.
Unit
100,000
100
Data changes per bit per register
years
CAPACITANCE
Symbol
Test
Max.
Unit
pF
Test Conditions
= 0V
(4)
C
Output capacitance (SO)
8
6
V
OUT
OUT
V = 0V
IN
(4)
C
Input capacitance (A0, A1, SI, and SCK)
pF
IN
POWER-UP TIMING
Symbol
Parameter
Min.
Max.
Unit
(5)
t
Power-up to initiation of read operation
Power-up to initiation of write operation
1
5
ms
ms
PUR
(5)
t
PUW
(4)
t
V
V Power-up ramp
CC
0.2
50
V/msec
R
CC
POWER-UP REQUIREMENTS (Power-up sequencing
EQUIVALENT A.C. LOAD CIRCUIT
can affect correct recall of the wiper registers)
5V
The preferred power-on sequence is as follows: First
V
, then the potentiometer pins, R , R , and R .
CC
H
L
W
1533Ω
Voltage should not be applied to the potentiometer
pins before V+ or V- is applied. The V ramp rate
CC
specifi-cation should be met, and any glitches or slope
changes in the V line should be held to <100mV if
SDA Output
CC
powers down, it should be held below
100pF
possible. If V
CC
0.1V for more than 1 second before powering up again
in order for proper wiper register recall. Also, V
CC
should not reverse polarity by more than 0.5V. Recall
of wiper position will not be complete until V , V+
CC
and V-reach their final value.
FN8189.3
July 28, 2006
12
X9400
A.C. TEST CONDITIONS
SYMBOL TABLE
Input pulse levels
V
x 0.1 to V
x 0.5
x 0.9
CC
CC
10ns
WAVEFORM
INPUTS
OUTPUTS
Input rise and fall times
Input and output timing level
V
CC
Must be
steady
Will be
steady
Notes: (4) This parameter is periodically sampled and not 100% tested
(5) t and t are the delays required from the time the
May change
from Low to
High
Will change
from Low to
High
PUR PUW
third (last) power supply (V , V+ or V-) is stable until the
CC
specific instruction can be issued. These parameters are
periodically sampled and not 100% tested.
May change
from High to
Low
Will change
from High to
Low
SPICE Macro Model
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
R
TOTAL
N/A
Center Line
is High
Impedance
R
R
L
H
C
L
C
H
C
W
10pF
10pF
25pF
R
W
AC TIMING
Symbol
Parameter
Min.
Max.
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
f
SSI/SPI clock frequency
SSI/SPI clock cycle time
SSI/SPI clock high time
SSI/SPI clock low time
Lead time
2.0
SCK
t
500
200
200
250
250
50
CYC
t
WH
t
WL
t
LEAD
t
Lag time
LAG
t
SI, SCK, HOLD and CS input setup time
SI, SCK, HOLD and CS input hold time
SI, SCK, HOLD and CS input rise time
SI, SCK, HOLD and CS input fall time
SO output disable time
SU
t
50
H
t
2
RI
t
2
FI
t
0
0
500
100
DIS
t
SO output valid time
V
t
SO output hold time
HO
RO
t
SO output rise time
50
50
t
SO output fall time
FO
t
HOLD time
400
100
100
HOLD
t
HOLD setup time
HSU
t
HOLD hold time
HH
t
HOLD low to output in High Z
HOLD high to output in Low Z
100
100
20
HZ
t
LZ
T
Noise suppression time constant at SI, SCK, HOLD and CS inputs
CS deselect time
I
t
2
0
0
CS
WPASU
t
WP, A0 and A1 setup time
t
WP, A0 and A1 hold time
WPAH
FN8189.3
July 28, 2006
13
X9400
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
Parameter
Typ.
Max.
Unit
t
High-voltage write cycle time (store instructions)
5
10
ms
WR
XDCP TIMING
Symbol
Parameter
Min. Max. Unit
t
Wiper response time after the third (last) power supply is stable
Wiper response time after instruction issued (all load instructions)
10
10
µs
µs
ns
WRPO
t
WRL
t
Wiper response time from an active SCL/SCK edge (increment/decrement instruction)
450
WRID
TIMING DIAGRAMS
Input Timing
t
CS
CS
t
t
t
LAG
LEAD
t
CYC
SCK
...
WH
t
t
FI
t
RI
t
t
WL
SU
H
...
MSB
LSB
SI
High Impedance
SO
Output Timing
CS
SCK
SO
...
...
t
t
t
DIS
V
HO
MSB
LSB
ADDR
SI
FN8189.3
July 28, 2006
14
X9400
Hold Timing
CS
t
t
HH
HSU
SCK
SO
...
t
t
FO
RO
t
t
LZ
HZ
SI
t
HOLD
HOLD
XDCP Timing (for All Load Instructions)
CS
SCK
...
...
t
WRL
MSB
LSB
SI
V
/R
W
W
High Impedance
SO
XDCP Timing (for Increment/Decrement Instruction)
CS
SCK
...
t
WRID
...
V
/R
W
W
...
ADDR
Inc/Dec
SI
Inc/Dec
High Impedance
SO
FN8189.3
July 28, 2006
15
X9400
Write Protect and Device Address Pins Timing
(Any Instruction)
CS
t
t
WPAH
WPASU
WP
A0
A1
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
+V
R
V
R
V
/R
W
W
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Application Circuits
Noninverting Amplifier
Voltage Regulator
V
+
–
S
V
V
V (REG)
O
317
O
IN
R
1
R
2
I
adj
R
R
1
2
V
= (1+R /R )V
V
(REG) = 1.25V (1+R /R )+I
R
adj 2
O
2
1
S
O
2
1
Offset Voltage Adjustment
Comparator with Hysteresis
R
R
2
1
V
–
+
S
V
V
S
O
100kΩ
–
+
V
O
TL072
R
R
1
2
10kΩ
10kΩ
+12V
V
V
= {R /(R +R )} V (max)
1 1 2 O
UL
LL
10kΩ
-12V
= {R /(R +R )} V (min)
1
1
2
O
FN8189.3
July 28, 2006
16
X9400
Application Circuits (continued)
Attenuator
Filter
C
V
+
–
S
R
V
R
1
2
O
–
R
V
O
V
+
S
R
3
R
2
R
4
All R = 10kΩ
S
R
1
G
= 1 + R /R
2 1
V
= G V
S
O
O
fc = 1/(2πRC)
-1/2 ≤ G ≤ +1/2
Inverting Amplifier
Equivalent L-R Circuit
R
R
2
1
V
S
R
2
C
1
–
+
V
+
–
S
V
O
R
R
1
Z
IN
V
= G V
S
O
G = - R /R
2
1
3
Z
= R + s R (R + R ) C = R + s Leq
2 2 1 3 1 2
IN
(R + R ) >> R
1
3
2
Function Generator
C
R
R
1
2
–
+
–
+
R
R
}
}
A
B
frequency ∝ R , R , C
1
2
amplitude ∝ R , R
A
B
FN8189.3
July 28, 2006
17
X9400
Small Outline Plastic Packages (SOIC)
M24.3 (JEDEC MS-013-AD ISSUE C)
N
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
MAX
2.65
NOTES
-B-
A
A1
B
C
D
E
e
0.0926
0.0040
0.013
0.1043
0.0118
0.020
-
0.30
-
1
2
3
L
0.51
9
SEATING PLANE
A
0.0091
0.5985
0.2914
0.0125
0.32
-
-A-
0.6141 15.20
15.60
7.60
3
h x 45°
D
0.2992
7.40
4
-C-
0.05 BSC
1.27 BSC
-
α
H
h
0.394
0.010
0.016
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C
A M B S
N
α
24
24
7
0°
8°
0°
8°
-
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 4/06
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
FN8189.3
July 28, 2006
18
X9400
Thin Shrink Small Outline Package Family (TSSOP)
MDP0044
THIN SHRINK SMALL OUTLINE PACKAGE FAMILY
0.25 M C A B
D
A
(N/2)+1
SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE
N
A
A1
A2
b
1.20
0.10
0.90
0.25
0.15
5.00
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
5.00
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
6.50
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
7.80
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
9.70
6.40
4.40
0.65
0.60
1.00
Max
±0.05
PIN #1 I.D.
E
E1
±0.05
+0.05/-0.06
+0.05/-0.06
±0.10
c
0.20 C B A
2X
1
(N/2)
D
N/2 LEAD TIPS
B
E
Basic
TOP VIEW
E1
e
±0.10
Basic
L
±0.15
0.05
H
e
L1
Reference
Rev. E 12/02
C
NOTES:
SEATING
PLANE
1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
0.10 M C A B
b
0.10 C
N LEADS
SIDE VIEW
2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.
3. Dimensions “D” and “E1” are measured at dAtum Plane H.
SEE DETAIL “X”
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
END VIEW
L1
A2
A
GAUGE
PLANE
0.25
L
A1
0° - 8°
DETAIL X
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8189.3
July 28, 2006
19
相关型号：
X9400WS24IZ-2.7T1
Quad Digitally Controlled Potentiometers (XDCP™); SOIC24, TSSOP24; Temp Range: -40° to 85°C
RENESAS
X9400WS24IZT1
Quad Digitally Controlled Potentiometers (XDCP™); SOIC24, TSSOP24; Temp Range: -40° to 85°C
RENESAS
X9400WS24T1
Digital Potentiometer, 4 Func, 10000ohm, 3-wire Serial Control Interface, 64 Positions, CMOS, PDSO24, PLASTIC, SOIC-24
RENESAS
X9400WS24ZT1
Quad Digitally Controlled Potentiometers (XDCP™); SOIC24, TSSOP24; Temp Range: See Datasheet
RENESAS
X9400WV24
QUAD 10K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO24, PLASTIC, TSSOP-24
RENESAS
X9400WV24-2.7
QUAD 10K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO24, 4.40 MM, TSSOP-24
RENESAS
X9400WV24-2.7T1
Digital Potentiometer, 4 Func, 10000ohm, 3-wire Serial Control Interface, 64 Positions, CMOS, PDSO24, PLASTIC, TSSOP-24
RENESAS
©2020 ICPDF网 联系我们和版权申明