X9409WV24I [INTERSIL]
Low Noise/Low Power/2-Wire Bus; 低噪音/低功耗/ 2 - Wire总线
| 型号： | X9409WV24I |
| 厂家： | 
Intersil |
| 描述： | Low Noise/Low Power/2-Wire Bus |
| 文件： | 总20页 (文件大小：356K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X9409
®
Low Noise/Low Power/2-Wire Bus
Data Sheet
October 19, 2005
FN8192.3
PRELIMINARY
DESCRIPTION
Quad Digitally Controlled Potentiometers
(XDCP™)
The X9409 integrates
potentiometers (XDCP) on a monolithic CMOS
integrated microcircuit.
4
digitally controlled
FEATURES
• Four potentiometers per package
• 64 resistor taps
The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the 2-wire
bus interface. Each potentiometer has associated with
it a volatile Wiper Counter Register (WCR) and 4
nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the
resistor array through the switches. Power-up recalls
the contents of DR0 to the WCR.
• 2-wire serial interface for write, read, and trans-
fer operations of the potentiometer
• 50Ω Wiper resistance, typical at 5V.
• Four non-volatile data registers for each
potentiometer
• Non-volatile storage of multiple wiper position
• Power-on recall. Loads saved wiper position on
power-up.
• Standby current < 1µA typical
• System V : 2.7V to 5.5V operation
CC
• 10kΩ, 2.5kΩ End to end resistance
• 100 yr. data retention
The XDCP can be used as
a three-terminal
• Endurance: 100,000 data changes per bit per
register
• Low power CMOS
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
• 24 Ld SOIC, 24 Ld TSSOP
• Pb-free plus anneal available (RoHS compliant)
BLOCK DIAGRAM
Pot 0
V
CC
R
R
R
R
V
/R
H0 HO
R
R
R
R
V
0
2
1
0
2
1
SS
Wiper
Counter
Register
(WCR)
Wiper
Counter
Register
(WCR)
V
/R
H2 H2
Resistor
Array
Pot 2
V
R
/
L0
3
WP
3
LO
V
/R
L2 L2
V
R
/
W0
SCL
SDA
A0
V
/R
W2 W2
WO
Interface
and
Control
A1
8
Circuitry
A2
V
R
/
A3
W1
Data
V
/R
W3 W3
W1
R
R
R
R
0
2
1
R
R
R
R
V
R
/
Wiper
Counter
Register
(WCR)
0
1
H1
V
/R
Wiper
Counter
Register
(WCR)
H3 H3
Resistor
Array
Pot 1
H1
Resistor
Array
Pot 3
3
V
/R
2
3
L1 L1
V
/R
L3 L3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9409
Ordering Information
POTENTIOMETER
ORGANIZATION
(kΩ)
TEMP RANGE
(°C)
PART NUMBER
X9409YS24
PART MARKING
V
LIMITS (V)
PACKAGE
CC
X9409YS
5 ±10%
2.5
0 to 70
0 to 70
24 Ld SOIC (300 mil)
X9409YS24Z (Note)
X9409WS24*
X9409YS Z
X9409WS
24 Ld SOIC (300 mil) (Pb-free)
24 Ld SOIC (300 mil)
10
0 to 70
X9409WS24Z* (Note)
X9409WS24I*
X9409WS Z
X9409WS I
X9409WS Z I
X9409WV
0 to 70
24 Ld SOIC (300 mil) (Pb-free)
24 Ld SOIC (300 mil)
-40 to 85
-40 to 85
0 to 70
X9409WS24IZ* (Note)
X9409WV24*
24 Ld SOIC (300 mil) (Pb-free)
24 Ld TSSOP (4.4mm)
X9409WV24Z* (Note)
X9409WV24I*
X9409WV Z
X9409WV I
X9409WV Z I
X9409YS G
X9409YS Z G
X9409YV G
X9409YV Z G
X9409WS F
0 to 70
24 Ld TSSOP (4.4mm) (Pb-free)
24 Ld TSSOP (4.4mm)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
0 to 70
X9409WV24IZ* (Note)
X9409YS24I-2.7
24 Ld TSSOP (4.4mm) (Pb-free)
24 Ld SOIC (300 mil)
2.7 to 5.5
2.5
10
X9409YS24IZ-2.7 (Note)
X9409YV24I-2.7
24 Ld SOIC (300 mil) (Pb-free)
24 Ld TSSOP (4.4mm)
X9409YV24IZ-2.7 (Note)
X9409WS24-2.7*
24 Ld TSSOP (4.4mm) (Pb-free)
24 Ld SOIC (300 mil)
X9409WS24Z-2.7* (Note) X9409WS Z F
X9409WS24I-2.7* X9409WS G
X9409WS24IZ-2.7* (Note) X9409WS Z G
X9409WV24-2.7* X9409WV F
X9409WV24Z-2.7* (Note) X9409WV Z F
X9409WV24I-2.7* X9409WV G
0 to 70
24 Ld SOIC (300 mil) (Pb-free)
24 Ld SOIC (300 mil)
-40 to 85
-40 to 85
0 to 70
24 Ld SOIC (300 mil) (Pb-free)
24 Ld TSSOP (4.4mm)
0 to 70
24 Ld TSSOP (4.4mm) (Pb-free)
24 Ld TSSOP (4.4mm)
-40 to 85
-40 to 85
X9409WV24IZ-2.7* (Note) X9409WV Z G
*Add "T1" suffix for tape and reel.
24 Ld TSSOP (4.4mm) (Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN8192.3
2
October 19, 2005
X9409
PIN DESCRIPTIONS
Hos t Interface Pins
Serial Clock (SCL)
V
/R
V
/R
W0 W0 - W3 W3
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.
Hardware Write Protect Input (WP)
The SCL input is used to clock data into and out of the
X9409.
The WP pin when low prevents nonvolatile writes to
the Data Registers.
Serial Data (SDA)
PIN NAMES
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor. For selecting typical
values, refer to the guidelines for calculating typical
values on the bus pull-up resistors graph.
Symbol
Description
Serial Clock
SCL
SDA
A0-A3
Serial Data
Device Address
V
V
/R - V /R
H0 H0 H3 H3
/R - V /R
L0 L0 L3 L3
,
Potentiometer Pin
(terminal equivalent)
V
/R
W0 W0
- V /R
Potentiometer Pin
(wiper equivalent)
W3 W3
Device Address (A - A )
0
3
The address inputs are used to set the least significant
4 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9409. A maximum of 16 devices may occupy the
2-wire serial bus.
WP
V
Hardware Write Protection
System Supply Voltage
System Ground (Digital)
No Connection
CC
V
SS
NC
Potentiometer Pins
V
/R - V /R , V /R - V /R
H0 H0 H3 H3 L0 L0 L3 L3
The V /R and V /R inputs are equivalent to the
H
H
L
L
terminal connections on either end of a mechanical
potentiometer.
PIN CONFIGURATION
SOIC
TSSOP
NC
V
V
WP
SDA
1
2
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
24
CC
/R
V
/R
A
V
A
1
L3 L3
23
22
21
20
19
18
17
16
15
L0 L0
2
/R
V
V
A
/R
V
/R
W0 W0
3
V
/R
H3 H3
H0 H0
L1 L1
V
/R
V
V
V
/R
/R
V
/R
H1 H1
4
H0 H0
W3 W3
W0 W0
V
/R
W1 W1
/R
A
2
5
L0 L0
0
V
NC
SS
NC
/R
WP
6
6
CC
X9409
X9409
SDA
A
3
NC
V
7
7
V
SCL
A
1
/R
W2 W2
/R
8
8
9
L3 L3
V
V
V
/R
V
V
/R
V
/R
L1 L1
9
L2 L2
H2 H2
H3 H3
V
/R
/R
/R
L2 L2
10
H2 H2
10
V
/R
W3 W3
H1 H1
V
/R
A
14
13
SCL
14
13
V
/R
W2 W2
11
12
0
11
12
W1 W1
V
A
3
NC
SS
NC
FN8192.3
3
October 19, 2005
X9409
PRINCIPLES OF OPERATION
The X9409 is highly integrated microcircuit
incorporating four resistor arrays and their associated
registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.
The X9409 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9409 will respond with a final acknowledge.
a
Array Description
The X9409 is comprised of four resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
Serial Interface
The X9409 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9409 will be considered a
slave device in all applications.
potentiometer (V /R and V /R inputs).
H
H
L
L
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(V /R ) output. Within each individual array only one
W
W
switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
six bits of the WCR are decoded to select, and enable,
one of sixty-four switches.
Clock and Data Conventions
Data states on the SDA line can change only during
The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
Data Registers into the WCR. These Data Registers
and the WCR can be read and written by the host
system.
SCL LOW periods (t
). SDA state changes during
LOW
SCL HIGH are reserved for indicating start and stop
conditions.
Start Condition
All commands to the X9409 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most
significant four bits of the slave address are the device
type identifier (refer to Figure 1 below). For the X9409
this is fixed as 0101[B].
while SCL is HIGH (t
). The X9409 continuously
HIGH
monitors the SDA and SCL lines for the start condition
and will not respond to any command until this
condition is met.
Stop Condition
Figure 1. Slave Address
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH.
Device Type
Identifier
Acknowledge
0
1
0
1
A3
A2
A1
A0
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.
Device Address
The next four bits of the slave address are the device
address. The physical device address is defined by
the state of the A0 - A3 inputs. The X9409 compares
the serial data stream with the address input state; a
successful compare of all four address bits is required
for the X9409 to respond with an acknowledge. The
A - A inputs can be actively driven by CMOS input
0
3
signals or tied to V
or V
.
CC
SS
FN8192.3
4
October 19, 2005
X9409
Acknowledge Polling
Figure 2. Instruction Byte Format
The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical nonvolatile write cycle time.
Once the stop condition is issued to indicate the end of
the nonvolatile write command the X9409 initiates the
internal write cycle. ACK polling can be initiated
immediately. This involves issuing the start condition
followed by the device slave address. If the X9409 is
still busy with the write operation no ACK will be
returned. If the X9409 has completed the write
operation an ACK will be returned and the master can
then proceed with the next operation.
Register
Select
I3
I2
I1
I0
R1 R0
P1 P0
Pot Select
Instructions
The four high order bits define the instruction. The
next two bits (R1 and R0) select one of the four
registers that is to be acted upon when a register
oriented instruction is issued. The last bits (P1, P0)
select which one of the four potentiometers is to be
affected by the instruction.
Flow 1. ACK Polling Sequence
Four of the nine instructions end with the transmission
of the instruction byte. The basic sequence is
illustrated in Figure 3. These two-byte instructions
exchange data between the Wiper Counter Register
and one of the data registers. A transfer from a Data
Register to a Wiper Counter Register is essentially a
write to a static RAM. The response of the wiper to this
Nonvolatile Write
Command Completed
Enter ACK Polling
Issue
START
action will be delayed t
. A transfer from the Wiper
WRL
Counter Register (current wiper position), to a Data
Register is a write to nonvolatile memory and takes a
Issue Slave
Issue STOP
Address
minimum of t
to complete. The transfer can occur
WR
between one of the four potentiometers and one of its
associated registers; or it may occur globally, wherein
the transfer occurs between all of the potentiometers
and one of their associated registers.
NO
ACK
Returned?
YES
Four instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9409; either between the host and
one of the data registers or directly between the host
and the Wiper Counter Register. These instructions
are: Read Wiper Counter Register (read the current
wiper position of the selected pot), Write Wiper
Counter Register (change current wiper position of the
selected pot), Read Data Register (read the contents
of the selected nonvolatile register) and Write Data
Register (write a new value to the selected Data
Register). The sequence of operations is shown in
Figure 4.
NO
Further
Operation?
YES
Issue
Instruction
Issue STOP
Proceed
Proceed
Instruction Structure
The next byte sent to the X9409 contains the
instruction and register pointer information. The format
is shown in Figure 2.
FN8192.3
5
October 19, 2005
X9409
Figure 3. Two-Byte Instruction Sequence
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
A
C
K
I3 I2
I1 I0 R1 R0 P1 P0
A
C
K
S
T
O
P
The Increment/Decrement command is different from
the other commands. Once the command is issued
and the X9409 has responded with an acknowledge,
the master can clock the selected wiper up and/or
down in one segment steps; thereby, providing a fine
tuning capability to the host. For each SCL clock pulse
move one resistor segment towards the V /R
H H
terminal. Similarly, for each SCL clock pulse while
SDA is LOW, the selected wiper will move one resistor
segment towards the V /R terminal. A detailed
L
L
illustration of the sequence and timing for this
operation are shown in Figures 5 and 6 respectively.
(t
) while SDA is HIGH, the selected wiper will
HIGH
Table 1. Instruction Set
Instruction Set
Instruction
I
I
I
I
R
R
P
P
Operation
3
2
1
0
1
0
1
0
Read Wiper Counter
Register
1
1
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
0
P
P
Read the contents of the Wiper Counter Register
1
0
pointed to by P - P
1
0
Write Wiper Counter
Register
0
0
1
1
0
0
P
P
P
P
P
P
P
P
Write new value to the Wiper Counter Register
pointed to by P - P
1
1
1
1
0
0
0
0
1
0
Read Data Register
R
R
Read the contents of the Data Register pointed to
by P - P and R - R
1
1
1
0
0
0
1
0
1
0
Write Data Register
R
R
R
R
Write new value to the Data Register pointed to
by P - P and R - R
1
0
1
0
XFR Data Register to
Wiper Counter Register
Transfer the contents of the Data Register
pointed to by P - P and R - R to its associated
1
0
1
0
Wiper Counter Register
Transfer the contents of the Wiper Counter
Register pointed to by P - P to the Data
XFR Wiper Counter
Register to Data
Register
1
0
1
0
1
0
0
0
1
0
0
1
0
1
0
0
R
R
R
R
R
R
P
P
1
1
1
0
0
0
1
0
1
0
Register pointed to by R - R
1
0
Global XFR Data
Registers to Wiper
Counter Registers
0
0
Transfer the contents of the Data Registers
pointed to by R - R of all four pots to their
1
0
respective Wiper Counter Registers
Global XFR Wiper
Counter Registers to
Data Register
0
0
Transfer the contents of both Wiper Counter
Registers to their respective Data Registers
pointed to by R - R of all four pots
1
0
Increment/Decrement
Wiper Counter Register
0
0
P
P
Enable Increment/decrement of the WCR Latch
pointed to by P
1
0
P
1 -
0
Note: (7) 1/0 = data is one or zero
FN8192.3
6
October 19, 2005
X9409
Figure 4. Three-Byte Instruction Sequence
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
A
C
K
I3 I2
I1 I0 R1 R0 P1 P0
A
C
K
0
0
D5 D4 D3 D2 D1 D0
A
C
K
S
T
O
P
Figure 5. Increment/Decrement Instruction Sequence
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
A
C
K
I3 I2
I1 I0 R1 R0 P1 P0
A
C
K
I
I
D
E
C
1
S
T
O
P
I
D
N
C
1
N
C
2
N
C
n
E
C
n
Figure 6. Increment/Decrement Timing Limits
INC/DEC
CMD
Issued
t
WRID
SCL
SDA
Voltage Out
V
/R
W
W
FN8192.3
October 19, 2005
7
X9409
Figure 7. Acknowledge Response from Receiver
SCL from
1
Master
8
9
Data Output
from Transmitter
Data Output
from Receiver
START
Acknowledge
Figure 8. Detailed Potentiometer Block Diagram
Serial Data Path
Serial
Bus
Input
V /R
H H
From Interface
Circuitry
C
o
u
n
t
Register 0
Register 2
Register 1
8
6
Parallel
Bus
Input
e
r
Wiper
D
e
c
o
d
e
Register 3
Counter
Register
(WCR)
INC/DEC
Logic
If WCR = 00[H] then V /R = V /R
W
W
L
L
UP/DN
UP/DN
If WCR = 3F[H] then V /R = V /R
H
W
W
H
V /R
Modified SCL
L
L
CLK
V
/R
W
W
FN8192.3
October 19, 2005
8
X9409
DETAILED OPERATION
If the application does not require storage of multiple
settings for the potentiometer, these registers can be
used as regular memory locations that could possibly
store system parameters or user preference data.
All XDCP potentiometers share the serial interface
and share a common architecture. Each potentiometer
has a Wiper Counter Register and 4 Data Registers. A
detailed discussion of the register organization and
array operation follows.
Register Descriptions
Data Registers, (6-Bit), Nonvolatile:
Wiper Counter Register
D5
NV
D4
NV
D3
NV
D2
NV
D1
NV
D0
NV
The X9409 contains four Wiper Counter Registers,
one for each XDCP potentiometer. The Wiper Counter
Register can be envisioned as a 6-bit parallel and
serial load counter with its outputs decoded to select
one of sixty-four switches along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of
the four associated Data Registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/ Decrement
instruction. Finally, it is loaded with the contents of its
Data Register zero (DR0) upon power-up.
(MSB)
(LSB)
Four 6-bit Data Registers for each XDCP. (sixteen 6-
bit registers in total).
– {D5~D0}: These bits are for general purpose not vol-
atile data storage or for storage of up to four differ-
ent wiper values. The contents of Data Register 0
are automatically moved to the wiper counter regis-
ter on power-up.
Wiper Counter Register, (6-Bit), Volatile:
WP5
V
WP4
V
WP3
V
WP2
V
WP1
V
WP0
V
The WCR is a volatile register; that is, its contents are
lost when the X9409 is powered-down. Although the
register is automatically loaded with the value in DR0
upon power-up, it should be noted this may be
different from the value present at power-down.
(MSB)
(LSB)
One 6-bit Wiper Counter Register for each XDCP.
(Four 6-bit registers in total.)
Data Registers
– {D5~D0}: These bits specify the wiper position of the
respective XDCP. The Wiper Counter Register is
loaded on power-up by the value in Data Register
Each potentiometer has four nonvolatile Data
Registers. These can be read or written directly by the
host and data can be transferred between any of the
four Data Registers and the Wiper Counter Register. It
should be noted all operations changing data in one of
these registers is a nonvolatile operation and will take
a maximum of 10ms.
R . The contents of the WCR can be loaded from
0
any of the other Data Register or directly by com-
mand. The contents of the WCR can be saved in a
DR.
FN8192.3
9
October 19, 2005
X9409
Instruction Format
Notes: (1) “MACK”/”SACK”: stands for the acknowledge sent by the master/slave.
(2) “A3 ~ A0”: stands for the device addresses sent by the master.
(3) “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
(4) “I”: stands for the increment operation, SDA held high during active SCL phase (high).
(5) “D”: stands for the decrement operation, SDA held low during active SCL phase (high).
Read Wiper Counter Register (WCR)
S device type
device
addresses
instruction
opcode
WCR
addresses
wiper position
(sent by slave on SDA)
S
A
C
K
S
A
C
K
M S
A T
C O
K P
T
A
R
T
identifier
W W W W W W
0 0 P P P P P P
A A A A
P P
1 0
0
1
0
1
1
0
0
1
0
0
3
2
1
0
5
4 3 2 1 0
Write Wiper Counter Register (WCR)
S device type
device
addresses
instruction
opcode
WCR
addresses
wiper position
(sent by master on SDA)
S
A
C
K
S
A
C
K
S S
A T
C O
K P
T
A
R
T
identifier
W W W W W W
0 0 P P P P P P
A A A A
P P
1 0
0
1
0
1
1
0
1
0
0
0
3
2
1
0
5
4 3 2 1 0
Read Data Register (DR)
S device type device
instruction DR and WCR
wiper position
(sent by slave on SDA)
S
A
C
K
S
M S
T
A
R
T
identifier
addresses
opcode
addresses
A
C
K
A T
C O
K P
W W W W W W
0 0 P P P P P P
A A A A
R
1
R
0
P
1
P
0
0
1
0
1
1
0
1
1
3
2 1 0
5
4 3 2 1 0
Write Data Register (DR)
S device type
device
addresses
instruction DR and WCR
wiper position
(sent by master on SDA)
S
S
S S
T
A
R
T
identifier
opcode
addresses
A
C
K
A
C
K
A T HIGH-VOLTAGE
C O WRITE CYCLE
K P
W W W W W W
0 0 P P P P P P
5 4 3 2 1 0
A A A A
3 2 1 0
R
1
R
0
P
1
P
0
0 1 0 1
1 1 0 0
Transfer Data Register (DR) to Wiper Counter Register (WCR)
S device type
device
addresses
instruction DR and WCR
S
A
C
K
S S
A T
C O
K P
T
A
R
T
identifier
opcode
addresses
A A A A
3 2 1 0
R
1
R
0
P
1
P
0
0 1 0 1
1 1 0 1
Write Wiper Counter Register (WCR) to Data Register (DR)
S device type
device
addresses
instruction DR and WCR
S
A
C
K
S S
T
A
R
T
identifier
opcode
addresses
A T HIGH-VOLTAGE
C O WRITE CYCLE
K P
A A A A
R
1
R
0
P
1
P
0
0
1 0
1
1 1 1 0
3
2
1
0
FN8192.3
October 19, 2005
10
X9409
Increment/Decrement Wiper Counter Register (WCR)
S
T
A
R
T
device type
identifier
device
addresses
instruction
opcode
WCR
addresses
increment/decrement
(sent by master on SDA)
S
A
C
K
S
A
C
K
S
T
O
P
A A A A
P P
1 0
I/ I/
D D
I/ I/
D D
0
1
0
1
0
0
1
0
0
0
.
.
.
.
3
2
1
0
Global Transfer Data Register (DR) to Wiper Counter Register (WCR)
S
T
A
R
T
device type
identifier
device
addresses
instruction
opcode
DR
addresses
S
A
C
K
S S
A T
C O
K P
A A A A
R R
1 0
0
1
0
1
0
0
0
1
0 0
3
2
1
0
Global Transfer Wiper Counter Register (WCR) to Data Register (DR)
S device type
device
addresses
instruction
opcode
DR
addresses
S
A
C
K
S S
A T
C O
K P
T
A
R
T
identifier
HIGH-VOLTAGE
WRITE CYCLE
A A A A
3 2 1 0
R R
0 0
1 0
0 1 0 1
1 0 0 0
SYMBOL TABLE
Guidelines for Calculating Typical Values of Bus
Pull-Up Resistors
WAVEFORM
INPUTS
OUTPUTS
120
V
CC MAX
OL MIN
R
=
=1.8kΩ
Must be
steady
Will be
steady
MIN
I
100
80
t
R
R
=
MAX
May change
from Low to
High
Will change
from Low to
High
C
BUS
Max.
Resistance
60
40
20
0
May change
from High to
Low
Will change
from High to
Low
Min.
Resistance
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
0
20 40 60 80 100 120
N/A
Center Line
is High
Impedance
Bus Capacitance (pF)
FN8192.3
11
October 19, 2005
X9409
ABSOLUTE MAXIMUM RATINGS
COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification)
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Temperature under bias.................... -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
Voltage on SDA, SCL or any address
input with respect to V ......................... -1V to +7V
SS
∆ V = |V - V | ........................................................5V
H
L
Lead temperature (soldering, 10s) .................... 300°C
RECOMMENDED OPERATING CONDITIONS
Temp
Min.
0°C
Max.
+70°C
+85°C
Device
X9409
Supply Voltage (V ) Limits
CC
Commercial
Industrial
5V ± 10%
-40°C
X9409-2.7
2.7V to 5.5V
ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
Parameter
End to end resistance tolerance
Power rating
Min.
Typ.
Max.
±20
15
Unit
%
Test Conditions
mW
mA
Ω
25°C, each pot @5V, 2.5K
I
Wiper current
-3
+3
W
R
Wiper resistance
50
150
I
= ± 3mA, V = 3V to 5V
CC
W
W
V
Voltage on any V /R or V /R pin
V
V
V
V
= 0V
TERM
H
H
L
L
SS
CC
SS
Ref: 1kHz
Noise
-120
1.6
dBV
%
(4)
Resolution
(1)
(3)
Absolute linearity
Relative linearity
-1
+1
MI
V
V
- V
w(n)(expected)
w(n)(actual)
- [V
(2)
(3)
MI
-0.2
+0.2
]
w(n) + MI
w(n + 1)
Temperature coefficient of R
Ratiometric temp. coefficient
Potentiometer capacitances
±300
ppm/°C
ppm/°C
pF
TOTAL
20
10
C /C /C
10/10/25
0.1
See Macro Model
H
L
W
I
R , R , R leakage current
µA
V
= V to V . Device is
SS CC
AL
H
L
W
IN
in stand-by mode.
Notes: (1) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as
a potentiometer.
(2) Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potenti-
ometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (V - V )/63, single pot
H
L
FN8192.3
12
October 19, 2005
X9409
D.C. OPERATING CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
I
V
V
supply current (Active)
100
µA
f = 400kHz, SDA = Open,
SCL
CC1
CC
CC
Other Inputs = V
SS
I
supply current
1
mA
f
= 400kHz, SDA = Open,
CC2
SCL
Other Inputs = V
(Nonvolatile Write)
SS
SCL = SDA = V , Addr. = V
SS
I
V
current (standby)
1
µA
µA
µA
V
SB
CC
CC
I
Input leakage current
Output leakage current
Input HIGH voltage
Input LOW voltage
Output LOW voltage
10
10
V
V
= V to V
SS CC
LI
IN
I
= V to V
SS CC
LO
OUT
V
V
x 0.7
V
+ 0.5
CC
IH
CC
-0.5
V
V
x 0.1
V
IL
CC
0.4
V
V
I
= 3mA
OL
OL
ENDURANCE AND DATA RETENTION
Parameter
Min.
Unit
Minimum endurance
Data retention
100,000
100
Data changes per bit per register
Years
CAPACITANCE
Symbol
Test
Input/output capacitance (SDA)
Input capacitance (A0, A1, A2, A3, and SCL)
Max.
Unit
pF
Test Conditions
(4)
C
8
6
V
= 0V
= 0V
I/O
I/O
(4)
C
pF
V
IN
IN
POWER-UP TIMING
Symbol
Parameter
V power-up rate
CC
Min.
Max.
Unit
(6)
t V
0.2
50
V/ms
r
CC
POWER-UP REQUIREMENTS (Power-up sequencing can affect correct recall of the wiper registers)
The preferred power-on sequence is as follows: First V , then the potentiometer pins, R , R , and R . The V
CC
H
L
W
CC
ramp rate specification should be met, and any glitches or slope changes in the V
line should be held to <100mV if
CC
possible. If V
powers down, it should be held below 0.1V for more than 1 second before powering up again in order
CC
for proper wiper register recall. Also, V
should not reverse polarity by more than 0.5V. Recall of wiper position will
CC
reaches its final value.
not be complete until V
CC
Notes: (4) This parameter is periodically sampled and not 100% tested
(5) t and t are the delays required from the time the (last) power supply (V ) is stable until the specific instruction can be issued.
PUR
PUW
CC
These parameters are periodically sampled and not 100% tested.
(6) Sample tested only.
FN8192.3
13
October 19, 2005
X9409
A.C. TEST CONDITIONS
Circuit #3 SPICE Macro Model
Input pulse levels
V
x 0.1 to V
x 0.5
x 0.9
CC
CC
R
TOTAL
Input rise and fall times
Input and output timing level
10ns
R
R
L
H
C
V
L
CC
C
H
C
W
10pF
EQUIVALENT A.C. LOAD CIRCUIT
10pF
25pF
5V
R
W
1533Ω
SDA Output
100pF
AC TIMING (over recommended operating condition)
Symbol Parameter
Min.
Max.
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
f
Clock frequency
400
SCL
t
Clock cycle time
2500
600
1300
600
600
600
100
30
CYC
t
Clock high time
HIGH
t
Clock low time
LOW
t
Start setup time
SU:STA
HD:STA
SU:STO
t
Start hold time
t
Stop setup time
t
SDA data input setup time
SDA data input hold time
SCL and SDA rise time
SCL and SDA fall time
SU:DAT
t
HD:DAT
t
300
300
900
R
t
F
t
SCL low to SDA data output valid time
SDA data output hold time
AA
DH
t
50
50
T
Noise suppression time constant at SCL and SDA inputs
Bus free time (prior to any transmission)
WP, A0, A1, A2 and A3 setup time
I
t
1300
0
BUF
t
SU:WPA
HD:WPA
t
WP, A0, A1, A2 and A3 hold time
0
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
Parameter
Typ.
Max.
Unit
t
High-voltage write cycle time (store instructions)
5
10
ms
WR
FN8192.3
14
October 19, 2005
X9409
XDCP TIMING
Symbol
Parameter
Min. Typ. Max. Unit
t
Wiper response time after the third (last) power supply is stable
Wiper response time after instruction issued (all load instructions)
2
2
2
10
10
10
µs
µs
µs
WRPO
t
WRL
t
Wiper response time from an active SCL/SCK edge (increment/decrement
instruction)
WRID
Note: (9) A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling
edge of SCL.
TIMING DIAGRAMS
START and STOP Timing
g
(START)
(STOP)
t
t
F
R
SCL
SDA
t
t
t
SU:STO
SU:STA
HD:STA
t
t
F
R
Input Timing
t
t
CYC
HIGH
SCL
SDA
t
LOW
t
t
t
BUF
SU:DAT
HD:DAT
Output Timing
SCL
SDA
t
t
DH
AA
FN8192.3
15
October 19, 2005
X9409
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
+V
R
V
R
V
/R
W
W
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Application Circuits
Noninverting Amplifier
Voltage Regulator
V
+
–
S
V
V
V (REG)
O
317
O
IN
R
1
R
2
I
adj
R
R
1
2
V
= (1+R /R )V
V
(REG) = 1.25V (1+R /R )+I
R
adj 2
O
2
1
S
O
2
1
Offset Voltage Adjustment
Comparator with Hysteresis
R
R
2
1
V
–
+
S
V
V
S
O
100kΩ
–
+
V
O
TL072
R
R
1
2
10kΩ
10kΩ
V
V
= {R /(R +R )} V (max)
1 1 2 O
UL
LL
10kΩ
= {R /(R +R )} V (min)
1
1
2
O
V
S
FN8192.3
16
October 19, 2005
X9409
Application Circuits (continued)
Attenuator
Filter
C
V
+
–
S
R
V
R
1
2
O
–
R
V
O
V
+
S
R
3
R
2
R
4
All R = 10kΩ
S
R
1
G
= 1 + R /R
2 1
V
= G V
S
O
O
fc = 1/(2πRC)
-1/2 ≤ G ≤ +1/2
Inverting Amplifier
Equivalent L-R Circuit
R
R
2
1
V
S
R
2
C
1
–
+
V
+
–
S
V
O
R
R
1
Z
IN
V
= G V
S
O
G = - R /R
2
1
3
Z
= R + s R (R + R ) C = R + s Leq
2 2 1 3 1 2
IN
(R + R ) >> R
1
3
2
Function Generator
C
R
R
1
2
–
+
–
+
R
R
}
}
A
B
frequency ∝ R , R , C
1
2
amplitude ∝ R , R
A
B
FN8192.3
17
October 19, 2005
X9409
XDCP Timing (for All Load Instructions)
(STOP)
SCL
LSB
SDA
t
WRL
VWx
XDCP Timing (for Increment/Decrement Instruction)
SCL
Wiper Register Address
Inc/Dec
Inc/Dec
SDA
t
WRID
V
/R
W
W
Write Protect and Device Address Pins Timing
(START)
(STOP)
SCL
...
(Any Instruction)
...
SDA
...
t
t
SU:WPA
HD:WPA
WP
A0, A1
A2, A3
FN8192.3
18
October 19, 2005
X9409
PACKAGING INFORMATION
24-Lead Plastic Small Outline Gull Wing Package Type S
0.393 (10.00)
0.290 (7.37)
0.299 (7.60)
0.420 (10.65)
Pin 1 Index
Pin 1
0.014 (0.35)
0.020 (0.50)
0.598 (15.20)
0.610 (15.49)
(4X) 7°
0.092 (2.35)
0.105 (2.65)
0.003 (0.10)
0.012 (0.30)
0.050 (1.27)
0.050"Typical
0.010 (0.25)
0.020 (0.50)
X 45°
0.050"
Typical
0° – 8°
0.009 (0.22)
0.013 (0.33)
0.420"
0.015 (0.40)
0.050 (1.27)
0.030" Typical
24 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
FN8192.3
October 19, 2005
19
X9409
PACKAGING INFORMATION
24-Lead Plastic, TSSOP Package Type V
.026 (.65) BSC
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.303 (7.70)
.311 (7.90)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.06)
.005 (.15)
.010 (.25)
Gage Plane
(7.72)
(4.16)
0°–8°
Seating Plane
.020 (.50)
.030 (.75)
(1.78)
(0.42)
Detail A (20X)
(0.65)
ALL MEASUREMENTS ARE TYPICAL
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8192.3
20
October 19, 2005
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