X9418_06 [INTERSIL]
Dual Digitally Controlled Potentiometers; 双数字电位器
| 型号： | X9418_06 |
| 厂家： | 
Intersil |
| 描述： | Dual Digitally Controlled Potentiometers |
| 文件： | 总20页 (文件大小：341K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X9418
Low Noise/Low Power/2-Wire Bus
®
Data Sheet
October 12, 2006
FN8194.3
DESCRIPTION
Dual Digitally Controlled Potentiometers
(XDCP™)
The X9418 integrates two digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated microcircuit.
FEATURES
• Two potentiometers in one package
• 2-wire serial interface
• Register oriented format
—Direct Read/Write/Transfer Wiper Position
—Store as many as Four Positions per
Potentiometer
The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the 2-wire
bus interface. Each potentiometer has associated with
it a volatile Wiper Counter Register (WCR) and 4
nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the
resistor array through the switches. Power up recalls
the contents of DR0 to the WCR.
• Power supplies
—V
= 2.7V to 5.5V
CC
—V+ = 2.7V to 5.5V
—V– = -2.7V to -5.5V
• Low power CMOS
—Standby current < 1µA
—Ideal for Battery Operated Applications
• High reliability
The XDCP can be used as
a three-terminal
—Endurance–100,000 Data Changes per Bit per
Register
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
—Register Data Retention–100 years
• 8-bytes of nonvolatile memory
• 2.5kΩ, 10kΩ resistor array
• Resolution: 64 taps each potentiometer
• 24-pin plastic DIP, 24-lead TSSOP and 24-lead
SOIC packages
• Pb-Free plus anneal available (RoHS compliant)
BLOCK DIAGRAM
V
V
V+
V-
CC
R0 R1
R2 R3
V
/R
H0 H0
SS
Wiper
Counter
Register
(WCR)
V
V
/R
L0 L0
WP
/R
SCL
W0 W0
SDA
A0
A1
Interface
and
Control
8
Circuitry
A2
V
/R
A3
W1 W1
Data
R0 R1
R2 R3
V
/R
Wiper
Counter
Register
(WCR)
H1 H1
Resistor
Array
XDCP1
V
/R
L1 L1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9418
Ordering Information
POTENTIOMET
ER
TEMPERATU
V
LIMITS ORGANIZATION RE RANGE
CC
PART NUMBER
X9418WV24*
PART MARKING
(V)
(kΩ)
(°C)
PACKAGE
PKG. DWG. #
X9418WV
5 ±10%
10
0 to +70
24 Ld TSSOP (4.4MM)
MDP0044
X9418WV24Z* (Note)
X9418WP24I-2.7
X9418WS24I-2.7
X9418WV Z
X9418WP G
X9418WS G
0 to +70
24 Ld TSSOP (4.4MM) (Pb-free) MDP0044
2.7 to 5.5
10
-40 to +85
-40 to +85
-40 to +85
0 to +70
24 Ld PDIP
E24.6
M24.3
24 Ld SOIC (300MIL)
X9418WS24IZ-2.7 (Note) X9418WS ZG
X9418WV24-2.7* X9418WV F
X9418WV24Z-2.7* (Note) X9418WV ZF
X9418WV24I-2.7 X9418WV G
X9418WV24IZ-2.7 (Note) X9418WV ZG
24 Ld SOIC (300MIL) (Pb-free) M24.3
24 Ld TSSOP (4.4MM)
MDP0044
0 to +70
24 Ld TSSOP (4.4MM) (Pb-free) MDP0044
-40 to +85
-40 to +85
0 to +70
24 Ld TSSOP (4.4MM)
24 Ld TSSOP (4.4MM) (Pb-free) MDP0044
24 Ld SOIC (300MIL) M24.3
24 Ld SOIC (300MIL) (Pb-free) M24.3
24 Ld SOIC (300MIL) M24.3
24 Ld SOIC (300MIL) (Pb-free) M24.3
MDP0044
X9418YS24-2.7
X9418YS F
X9418YS ZF
X9418YS G
2.5
X9418YS24Z-2.7 (Note)
X9418YS24I-2.7
0 to +70
-40 to +85
-40 to +85
-40 to +85
-40 to +85
X9418YS24IZ-2.7 (Note) X9418YS ZG
X9418YV24I-2.7* X9418YV G
24 Ld TSSOP (4.4MM)
MDP0044
X9418YV24IZ-2.7* (Note) X9418YV ZG
*Add "T1" suffix for tape and reel.
24 Ld TSSOP (4.4MM) (Pb-free) MDP0044
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
PIN DESCRIPTIONS
Host Interface Pins
Serial Clock (SCL)
Potentiometer Pins
V /R (V /R - V /R ), V /R (V /R - V /R
)
H
H
H0 H0 H1 H1 L0 L0 L1 L1
L
L
The V /R and V /R inputs are equivalent to the
H
H
L
L
terminal connections on either end of a mechanical
potentiometer.
The SCL input is used to clock data into and out of the
X9418.
V /R (V /R
W0 W0
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.
- V /R )
W1 W1
W
W
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor. For selecting typical
values, refer to the guidelines for calculating typical
values on the bus pull-up resistors graph.
Hardware Write Protect Input (WP)
The WP pin when low prevents nonvolatile writes to
the Data Registers.
Analog Supplies V+, V-
The Analog Supplies V+, V- are the supply voltages
for the XDCP analog section.
Device Address (A - A )
0
3
The Address inputs are used to set the least
significant 4 bits of the 8-bit slave address. A match in
the slave address serial data stream must be made
with the Address input in order to initiate
communication with the X9418. A maximum of 16
devices may occupy the 2-wire serial bus.
FN8194.3
October 12, 2006
2
X9418
PIN CONFIGURATION
PRINCIPLES OF OPERATION
The X9418 is highly integrated microcircuit
incorporating two resistor arrays and their associated
registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.
a
DIP/SOIC
V+
V
1
24
23
22
21
20
19
18
17
16
5
CC
NC
NC
NC
A0
NC
A3
SCL
NC
NC
R
/V
/V
2
3
L0 L0
R
H0 H0
/V
R
4
5
W0 W0
A2
Serial Interface
WP
6
The X9418 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9418 will be considered a
slave device in all applications.
X9418
SDA
7
A1
8
R
/V
9
L1 L1
R
/V
10
H1 H1
NC
V-
R
/V
11
12
14
13
W1 W1
V
SS
TSSOP
WP
A2
V
SDA
A1
1
2
3
24
23
22
21
20
19
18
17
16
Clock and Data Conventions
Data states on the SDA line can change only during
/R
R
/V
W0 W0
L1 L1
V
V
V
/R
SCL LOW periods (t
). SDA state changes during
R
/V
4
5
H0 H0
LOW
H1 H1
/R
SCL HIGH are reserved for indicating start and stop
conditions.
R
/V
L0 L0
W1 W1
V
6
7
CC
SS
X9418
NC
NC
NC
V+
A0
NC
NC
NC
8
9
Start Condition
All commands to the X9418 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
10
15
14
13
V-
SCL
A3
11
12
while SCL is HIGH (t
). The X9418 continuously
NC
HIGH
monitors the SDA and SCL lines for the start condition
and will not respond to any command until this
condition is met.
PIN NAMES
Symbol
Stop Condition
Description
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH.
SCL
Serial Clock
Serial Data
SDA
A0 - A3
Device Address
Acknowledge
V
V
/R - V /R
,
Potentiometer Pins
(terminal equivalent)
H0 H0 H1 H1
/R - V /R
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.
L0 L0
L1 L1
V
V
/R
-
Potentiometer Pins
(wiper equivalent)
W0 W0
/R
W1 W1
WP
Hardware Write Protection
Analog Supplies
V+,V-
V
V
System Supply Voltage
System Ground
CC
SS
NC
No Connection
FN8194.3
October 12, 2006
3
X9418
The X9418 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9418 will respond with a final acknowledge.
Acknowledge Polling
The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms EEPROM write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9418
initiates the internal write cycle. ACK polling can be
initiated immediately. This involves issuing the start
condition followed by the device slave address. If the
X9418 is still busy with the write operation no ACK will
be returned. If the X9418 has completed the write
operation an ACK will be returned, and the master can
then proceed with the next operation.
Array Description
The X9418 is comprised of two resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (V /R and V /R inputs).
H
H
L
L
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
Flow 1. ACK Polling Sequence
(V /R ) output. Within each individual array only one
W
W
switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
six bits of the WCR are decoded to select, and enable,
one of sixty-four switches.
Nonvolatile Write
Command Completed
Enter ACK Polling
The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
Data Registers into the WCR. These Data Registers
and the WCR can be read and written by the host
system.
Issue
START
Issue Slave
Issue STOP
Address
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most
significant four bits of the slave address are the device
type identifier (refer to Figure 1 below). For the X9418
this is fixed as 0101[B].
ACK
Returned?
NO
YES
NO
Further
Operation?
Figure 1. Slave Address
Device Type
Identifier
YES
Issue
Instruction
Issue STOP
Proceed
0
1
0
1
A3
A2
A1
A0
Device Address
Proceed
The next four bits of the slave address are the device
address. The physical device address is defined by
Instruction Structure
the state of the A - A inputs. The X9418 compares
0
3
The next byte sent to the X9418 contains the instruction
and register pointer information. The four most
significant bits are the instruction. The next four bits
point to one of the two pots and when applicable they
point to one of four associated registers. The format is
shown Figure 2.
the serial data stream with the address input state; a
successful compare of all four address bits is required
for the X9418 to respond with an acknowledge. The
A - A inputs can be actively driven by CMOS input
0
3
signals or tied to V
or V
.
CC
SS
FN8194.3
October 12, 2006
4
X9418
Figure 2. Instruction Byte Format
associated registers; or it may occur globally, wherein
the transfer occurs between both of the
potentiometers and one of their associated registers.
Register
Select
Four instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9418; either between the host and
one of the Data Registers or directly between the host
and the wiper counter register. These instructions are:
Read Wiper Counter Register (read the current wiper
position of the selected pot), write Wiper Counter
Register (change current wiper position of the selected
pot), read Data Register (read the contents of the
selected nonvolatile register) and write Data Register
(write a new value to the selected Data Register). The
sequence of operations is shown in Figure 4.
I3
I2
I1
I0
R1 R0
0
P0
Wiper Counter
Register Select
Instructions
The four high order bits define the instruction. The
next two bits (R1 and R0) select one of the four
registers that is to be acted upon when a register
oriented instruction is issued. The last bits (P0) select
which one of the two potentiometers is to be affected
by the instruction. Bit 1 is defined to be 0.
The Increment/Decrement command is different from
the other commands. Once the command is issued
and the X9418 has responded with an acknowledge,
the master can clock the selected wiper up and/or
down in one segment steps; thereby, providing a fine
tuning capability to the host. For each SCL clock pulse
Four of the nine instructions end with the transmission
of the instruction byte. The basic sequence is
illustrated in Figure 3. These two-byte instructions
exchange data between the wiper counter register and
one of the data registers. A transfer from a Data
Register to a Wiper Counter Register is essentially a
write to a static RAM. The response of the wiper to this
(t
) while SDA is HIGH, the selected wiper will
HIGH
move one resistor segment towards the V /R
H
H
action will be delayed t
. A transfer from the wiper
WRL
terminal. Similarly, for each SCL clock pulse while
SDA is LOW, the selected wiper will move one resistor
counter register (current wiper position), to a Data
Register is a write to nonvolatile memory and takes a
segment towards the V /R terminal. A detailed
L
L
minimum of t
to complete. The transfer can occur
WR
illustration of the sequence and timing for this
operation are shown in Figures 5 and 6 respectively.
between one of the two potentiometers and one of its
Figure 3. Two-Byte Instruction Sequence
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
A
C
K
I3 I2
I1 I0 R1 R0
0
P0
A
C
K
S
T
O
P
FN8194.3
October 12, 2006
5
X9418
Table 1. Instruction Set
Instruction
Read Wiper Counter
Register
Instruction Set
I
1
I
I
I
R
R
P
0
P
Operation
1/0 Read the contents of the Wiper Counter Register
pointed to by P
3
2
1
0
1
0
1
0
0
0
0
1
1
0
1
0
0
0
Write Wiper Counter
Register
1
1
1
1
1
1
0
0
0
1
0
1
0
0
0
0
0
0
1/0 Write new value to the Wiper Counter Register
pointed to by P
0
Read Data Register
1/0 1/0
1/0 1/0
1/0 1/0
1/0 Read the contents of the Data Register pointed to by
P and R - R
0
1
0
Write Data Register
1/0 Write new value to the Data Register pointed to by
P and R - R
0
1
0
XFR Data Register to
Wiper Counter Register
1/0 Transfer the contents of the Data Register pointed to
by P and R - R to its associated Wiper Counter
0
1
0
Register
XFR Wiper Counter
Register to Data Register
1
0
1
0
1
0
0
0
1
0
0
1
0
1
0
0
1/0 1/0
1/0 1/0
1/0 1/0
0
0
0
0
1/0 Transfer the contents of the Wiper Counter Register
pointed to by P to the Data Register pointed to by
0
R - R
1
0
Global XFR Data
Registers to Wiper
Counter Registers
0
0
Transfer the contents of the Data Registers pointed
to by R - R of both pots to their respective Wiper
Counter Registers
1
0
Global XFR Wiper
Counter Registers to
Data Register
Transfer the contents of both Wiper Counter
Registers to their respective data Registers pointed
to by R - R of both pots
1
0
Increment/Decrement
Wiper Counter Register
0
0
1/0 Enable Increment/decrement of the Wiper Counter
Register pointed to by P
0
Note: (7) 1/0 = data is one or zero
Figure 4. Three-Byte Instruction Sequence
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
A
C
K
I3 I2
I1 I0 R1 R0 0 P0
A
C
K
0
0
D5 D4 D3 D2 D1 D0
A
C
K
S
T
O
P
Figure 5. Increment/Decrement Instruction Sequence
SCL
SDA
X
X
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
A
C
K
I3 I2
I1 I0 R1 R0
0
P0
A
C
K
I
I
D
E
C
1
S
T
I
D
N
C
1
N
C
2
N
C
n
E
C
n
O
P
FN8194.3
October 12, 2006
6
X9418
Figure 6. Increment/Decrement Timing Limits
INC/DEC
CMD
Issued
t
WRID
SCL
SDA
Voltage Out
V
/R
W
W
Figure 7. Acknowledge Response from Receiver
SCL from
Master
1
8
9
Data Output
from Transmitter
Data Output
from Receiver
START
Acknowledge
FN8194.3
October 12, 2006
7
X9418
Figure 8. Detailed Potentiometer Block Diagram
Serial Data Path
Serial
Bus
Input
V /R
H H
From Interface
Circuitry
C
o
u
n
t
Register 0
Register 2
Register 1
8
6
Parallel
Bus
Input
e
r
Wiper
D
e
c
o
d
e
Register 3
Counter
Register
(WCR)
INC/DEC
Logic
If WCR = 00[H] then V /R = V /R
W
W
L
L
UP/DN
UP/DN
If WCR = 3F[H] then V /R = V /R
H
W
W
H
V /R
Modified SCL
L
L
CLK
V
/R
W
W
DETAILED OPERATION
Data Registers
Each potentiometer has four nonvolatile Data
Registers. These can be read or written directly by the
host and data can be transferred between any of the
four Data Registers and the Wiper Counter Register. It
should be noted all operations changing data in one of
these registers is a nonvolatile operation and will take
a maximum of 10ms.
Both XDCP potentiometers share the serial interface
and share a common architecture. Each potentiometer
has a Wiper Counter Register and four Data
Registers. A detailed discussion of the register
organization and array operation follows.
Wiper Counter Register
The X9418 contains two wiper counter registers, one
for each XDCP potentiometer. The Wiper Counter
Register can be envisioned as a 6-bit parallel and
serial load counter with its outputs decoded to select
one of sixty-four switches along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of
four associated Data Registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/Decrement
instruction. Finally, it is loaded with the contents of its
Data Register zero (DR0) upon power-up.
If the application does not require storage of multiple
settings for the potentiometer, these registers can be
used as regular memory locations that could possibly
store system parameters or user preference data.
Register Descriptions
Data Registers, (6-Bit), Nonvolatile
D5
NV
D4
NV
D3
NV
D2
NV
D1
NV
D0
NV
(MSB)
(LSB)
Four 6-bit Data Registers for each XDCP. (eight 6-bit
registers in total).
The WCR is a volatile register; that is, its contents are
lost when the X9418 is powered-down. Although the
register is automatically loaded with the value in DR0
upon power-up, it should be noted this may be
different from the value present at power-down.
– {D5~D0}: These bits are for general purpose not
volatile data storage or for storage of up to four
different wiper values. The contents of Data Register
0 are automatically moved to the Wiper Counter
Register on power-up.
FN8194.3
October 12, 2006
8
X9418
Wiper Counter Register, (6-Bit), Volatile
One 6-bit wiper counter register for each XDCP. (Four
6-bit registers in total.)
WP5
V
WP4
V
WP3
V
WP2
V
WP1
V
WP0
V
– {D5~D0}: These bits specify the wiper position of the
respective XDCP. The Wiper Counter Register is
loaded on power-up by the value in Data Register 0.
The contents of the WCR can be loaded from any of
the other Data Register or directly. The contents of
the WCR can be saved in a DR.
(MSB)
(LSB)
Instruction Format
Notes: (1) “MACK”/”SACK”: stands for the acknowledge sent by the master/slave.
(2) “A3 ~ A0”: stands for the device addresses sent by the master.
(3) “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
(4) “I”: stands for the increment operation, SDA held high during active SCL phase (high).
(5) “D”: stands for the decrement operation, SDA held low during active SCL phase (high).
Read Wiper Counter Register (WCR)
S
T
A
R
T
device type
identifier
device
addresses
instruction
opcode
WCR
addresses
wiper position
(sent by slave on SDA)
S
A
C
K
S
A
C
K
M S
A T
C O
K P
W W W W W W
0 0 P P P P P P
A A A A
P
0
0
1
0
1
1
0
0
1
0
0
0
3
2 1 0
5
4 3 2 1 0
Write Wiper Counter Register (WCR)
S
T
A
R
T
device type
identifier
device
addresses
instruction
opcode
WCR
addresses
wiper position
(sent by master on SDA)
S
A
C
K
S
A
C
K
S S
A T
C O
K P
W W W W W W
0 0 P P P P P P
A A A A
P
0
0
1
0
1
1
0
1
0
0
0
0
3
2 1 0
5
4 3 2 1 0
Read Data Register (DR)
S device type device
instruction DR and WCR
wiper position/data
(sent by slave on SDA)
S
A
C
K
S
M S
T
A
R
T
identifier
addresses
opcode
addresses
A
C
K
A T
C O
K P
W W W W W W
0 0 P P P P P P
A A A A
R
1
R
0
0
P
0
0
1
0
1
1
0
1
1
3
2 1 0
5
4 3 2 1 0
Write Data Register (DR)
S device type
device
addresses
instruction DR and WCR
wiper position/data
(sent by master on SDA)
S
S
S S
T
A
R
T
identifier
opcode
addresses
A
C
K
A
C
K
A T HIGH-VOLTAGE
C O WRITE CYCLE
K P
W W W W W W
0 0 P P P P P P
A A A A
R
1
R
0
0
1
0
1
1
1
0
0
0
P0
3
2
1
0
5
4 3 2 1 0
XFR Data Register (DR) to Wiper Counter Register (WCR)
S device type
device
addresses
instruction DR and WCR
S
A
C
K
S S
T
A
R
T
identifier
opcode
addresses
A T
C O
K P
A A A A
R
1
R
0
P
0
0
1
0
1
1
1
0
1
0
3
2
1
0
FN8194.3
October 12, 2006
9
X9418
XFR Wiper Counter Register (WCR) to Data Register (DR)
S device type
device
addresses
instruction DR and WCR
S
A
C
K
S S
T
A
R
T
identifier
opcode
addresses
A T HIGH-VOLTAGE
C O WRITE CYCLE
K P
A A A A
R
1
R
0
0
P
0
0
1
0
1
1 1 1 0
3
2 1 0
Increment/Decrement Wiper Counter Register (WCR)
S
T
A
R
T
device type
identifier
device
addresses
instruction
opcode
WCR
addresses
increment/decrement
(sent by master on SDA)
S
A
C
K
S
A
C
K
S
T
O
P
A A A A
P
0
I/ I/
D D
I/ I/
D D
0
1
0
1
0
0
1
0
0
0
0
.
.
.
.
3
2 1 0
Global XFR Data Register (DR) to Wiper Counter Register (WCR)
S
T
A
R
T
device type
identifier
device
addresses
instruction
opcode
DR
addresses
S
A
C
K
S
A
C O
S
T
A A A A
R R
1 0
0
1
0
1
0
0
0
1
0 0
K
P
3
2
1
0
Global XFR Wiper Counter Register (WCR) to Data Register (DR)
S device type
device
addresses
instruction
opcode
DR
addresses
S
A
C
K
S S
A T
C O
K P
T
A
R
T
identifier
HIGH-VOLTAGE
WRITE CYCLE
A A A A
R R
1 0
0
1
0
1
1
0
0
0
0 0
3
2
1
0
SYMBOL TABLE
Guidelines for Calculating Typical Values of Bus
Pull-Up Resistors
WAVEFORM
INPUTS
OUTPUTS
120
V
I
CC MAX
OL MIN
R
=
=1.8kΩ
MIN
Must be
steady
Will be
steady
100
80
t
R
R
=
MAX
C
BUS
May change
from Low to
High
Will change
from Low to
High
Max.
Resistance
60
40
20
0
May change
from High to
Low
Will change
from High to
Low
Min.
Resistance
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
0
20 40 60 80 100 120
N/A
Center Line
is High
Impedance
Bus Capacitance (pF)
FN8194.3
October 12, 2006
10
X9418
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias.................... -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
Voltage on SDA, SCL or any address
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification)
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
input with respect to V ......................... -1V to +7V
SS
Voltage on V+ (referenced to V )........................10V
SS
Voltage on V- (referenced to V )........................-10V
SS
(V+) - (V-) ..............................................................12V
Any V /R , V /R , V /R ........................... V- to V+
H
H
L
L
W
W
Lead temperature (soldering, 10 seconds)...... +300°C
(10 seconds)..................................................±6mA
I
W
RECOMMENDED OPERATING CONDITIONS
Temp
Commercial
Industrial
Min.
0°C
-40°C
Max.
+70°C
+85°C
Device
X9418
Supply Voltage (V ) Limits
CC
5V ± 10%
2.7V to 5.5V
X9418-2.7
ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
Parameter
End to end resistance tolerance
Power rating
Min.
-20
Typ.
Max. Unit
Test Conditions
+25°C, each pot
+20
50
%
mW
mA
Ω
I
Wiper current
-3
+3
W
R
Wiper resistance
150
40
250
100
+5.5
+5.5
-4.5
-2.7
V+
Wiper current = ± 1mA, V+, V- = ±3V
Wiper current = ± 1mA, V+, V- = ±5V
W
Ω
V
V+
V-
Voltage on V+ pin
Voltage on V- pin
X9418
+4.5
+2.7
-5.5
-5.5
V-
X9418-2.7
X9418
V
V
X9418-2.7
V
Voltage on any V /R , V /R or
H H L L
TERM
V /R
W
W
Noise
-120
1.6
dBV
%
Ref: 1kHz
(4)
Resolution
See Note 4
(4)
(1)
(3)
Absolute linearity
Relative linearity
-1
+1
MI
(3)
MI
V - V
w(n)(actual)
w(n)(expected)
(4)
(2)
-0.2
+0.2
V
[V
]
w(n + 1 - w(n) + MI
Temperature Coefficient of R
±300
ppm/°C See Note 4
±20 ppm/°C See Note 4
TOTAL
Ratiometric Temperature Coefficient
Potentiometer Capacitances
C /C /C
10/10/25
0.1
pF
See Circuit #3,
Spice Macromodel
H
L
W
I
R , R , R Leakage Current
10
µA
V
= V- to V+. Device is in Stand-by
AL
H
L
W
IN
mode.
FN8194.3
October 12, 2006
11
X9418
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
I
V
supply current
1
mA
f = 400kHz, SDA = Open,
SCL
CC1
CC
(nonvolatile write)
Other Inputs = V
SS
I
V
supply current
100
µA
f
= 400kHz, SDA = Open,
CC2
CC
(move wiper, write, read)
SCL
Other Inputs = V
SS
I
V
current (standby)
1
µA
µA
µA
V
SCL = SDA = V , Addr. = V
CC SS
SB
CC
I
Input leakage current
Output leakage current
Input HIGH voltage
Input LOW voltage
Output LOW voltage
10
10
V
V
= V to V
SS
LI
IN
CC
CC
I
= V to V
SS
LO
OUT
V
V
x 0.7
V
+ 0.5
CC
IH
CC
-0.5
V
V
x 0.1
V
IL
CC
0.4
V
V
I
= 3mA
OL
OL
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (R - R )/63, single pot
H
L
ENDURANCE AND DATA RETENTION
Parameter
Minimum endurance
Data retention
Min.
100,000
100
Unit
Data changes per bit per register
Years
CAPACITANCE
Symbol
Test
Max.
Unit
pF
Test Conditions
(4)
C
Input/output capacitance (SDA)
8
6
V
= 0V
= 0V
I/O
I/O
(4)
C
Input capacitance (A0, A1, A2, A3, and SCL)
pF
V
IN
IN
POWER-UP TIMING
Symbol
Parameter
Min.
Typ.
Max.
1
Unit
(5)
t
Power-up to initiation of read operation
Power-up to initiation of write operation
ms
ms
PUR
(5)
(6)
t
5
PUW
t V
V
Power up ramp rate
CC
0.2
50
V/msec
R CC
Power Up Requirements (Power up sequencing can affect correct recall of the wiper registers)
The preferred power-on sequence is as follows: First V , then V+ and V-, and then the potentiometer pins, R , R ,
CC
and R . Voltage should not be applied to the potentiometer pins before V+ or V- is applied. The V
H
L
ramp rate
W
CC
line should be held to <100mV if possible.
specification should be met, and any glitches or slope changes in the V
CC
If V
powers down, it should be held below 0.1V for more than 1 second before powering up again in order for
CC
proper wiper register recall. Also, V
should not reverse polarity by more than 0.5V. Recall of wiper position will not
CC
be complete until V , V+ and V- reach their final value.
CC
Notes: (4) This parameter is periodically sampled and not 100% tested
(5) t
and t
are the delays required from the time the third (last) power supply (V , V+ or V-) is stable until the specific
PUR
PUW CC
instruction can be issued. These parameters are periodically sampled and not 100% tested.
(6) This is a tested or guaranteed parameter and should only be used as a guidance.
FN8194.3
October 12, 2006
12
X9418
A.C. TEST CONDITIONS
Circuit #3 SPICE Macro Model
Input pulse levels
V
x 0.1 to V
x 0.5
x 0.9
CC
CC
R
TOTAL
Input rise and fall times
Input and output timing level
10ns
R
R
L
H
C
V
L
CC
C
H
C
W
10pF
EQUIVALENT A.C. LOAD CIRCUIT
10pF
25pF
5V
R
W
1533Ω
SDA Output
100pF
AC TIMING (over recommended operating conditions)
Symbol Parameter
Min.
Max.
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
f
Clock frequency
400
SCL
t
Clock cycle time
2500
600
1300
600
600
600
100
30
CYC
t
Clock high time
HIGH
t
Clock low time
LOW
t
Start setup time
SU:STA
HD:STA
SU:STO
t
Start hold time
t
Stop setup time
t
SDA data input setup time
SDA data input hold time
SCL and SDA rise time
SCL and SDA fall time
SU:DAT
t
HD:DAT
t
300
300
900
R
t
F
t
SCL low to SDA data output valid time
SDA data output hold time
AA
DH
t
50
50
T
Noise suppression time constant at SCL and SDA inputs
Bus free time (prior to any transmission)
WP, A0, A1, A2 and A3 setup time
I
t
1300
0
BUF
t
SU:WPA
HD:WPA
t
WP, A0, A1, A2 and A3 hold time
0
FN8194.3
October 12, 2006
13
X9418
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
Parameter
Typ.
Max.
Unit
t
High-voltage write cycle time (store instructions)
5
10
ms
WR
XDCP TIMING
Symbol
Parameter
Min. Max. Unit
t
Wiper response time after the third (last) power supply is stable
Wiper response time after instruction issued (all load instructions)
10
10
10
µs
µs
µs
WRPO
t
WRL
t
Wiper response time from an active SCL/SCK edge (increment/decrement instruction)
WRID
Note: (8) A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling
edge of SCL.
TIMING DIAGRAMS
START and STOP Timing
g
(START)
(STOP)
t
t
F
R
SCL
SDA
t
t
t
SU:STO
SU:STA
HD:STA
t
t
F
R
Input Timing
t
t
CYC
HIGH
SCL
SDA
t
LOW
t
t
t
BUF
SU:DAT
HD:DAT
Output Timing
SCL
SDA
t
t
DH
AA
FN8194.3
October 12, 2006
14
X9418
XDCP Timing (for All Load Instructions)
(STOP)
SCL
SDA
LSB
t
WRL
V
/R
W
W
XDCP Timing (for Increment/Decrement Instruction)
SCL
Wiper Register Address
Inc/Dec
Inc/Dec
SDA
t
WRID
V
/R
W
W
Write Protect and Device Address Pins Timing
(START)
(STOP)
SCL
...
(Any Instruction)
...
SDA
...
t
t
SU:WPA
HD:WPA
WP
A0, A1
A2, A3
FN8194.3
October 12, 2006
15
X9418
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
+V
R
V
R
V
/R
W
W
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Application Circuits
NONINVERTING AMPLIFIER
VOLTAGE REGULATOR
V
+
–
S
V
V
V (REG)
O
317
O
IN
R
1
R
2
I
adj
R
R
1
2
V
= (1+R /R )V
V
(REG) = 1.25V (1+R /R )+I
R
adj 2
O
2
1
S
O
2
1
OFFSET VOLTAGE ADJUSTMENT
COMPARATOR WITH HYSTERESIS
R
R
2
1
V
–
+
S
V
V
S
O
100kΩ
–
+
V
O
TL072
R
R
1
2
10kΩ
10kΩ
+12V
V
V
= {R /(R +R )} V (max)
1 1 2 O
UL
LL
10kΩ
-12V
= {R /(R +R )} V (min)
1
1
2
O
FN8194.3
October 12, 2006
16
X9418
Application Circuits (continued)
ATTENUATOR
FILTER
C
V
+
–
S
R
V
R
1
2
O
–
R
V
O
V
+
S
R
3
R
2
R
4
All R = 10kΩ
S
R
1
G
= 1 + R /R
2 1
V
= G V
S
O
O
fc = 1/(2πRC)
-1/2 ≤ G ≤ +1/2
INVERTING AMPLIFIER
EQUIVALENT L-R CIRCUIT
R
R
2
1
V
S
R
2
C
1
–
+
V
+
–
S
V
O
R
R
1
Z
IN
V
= G V
S
O
G = - R /R
2
1
3
Z
= R + s R (R + R ) C = R + s Leq
2 2 1 3 1 2
IN
(R + R ) >> R
1
3
2
FUNCTION GENERATOR
C
R
R
1
2
–
+
–
+
R
R
}
}
A
B
frequency ∝ R , R , C
1
2
amplitude ∝ R , R
A
B
FN8194.3
October 12, 2006
17
X9418
Dual-In-Line Plastic Packages (PDIP)
E24.6 (JEDEC MS-011-AA ISSUE B)
N
24 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
INCHES
MILLIMETERS
1
2
3
N/2
SYMBOL
MIN
MAX
0.250
-
MIN
-
MAX
6.35
-
NOTES
-B-
-C-
A
A1
A2
B
-
4
-A-
D
E
0.015
0.125
0.014
0.030
0.008
1.150
0.005
0.600
0.485
0.39
3.18
0.356
0.77
0.204
4
BASE
PLANE
0.195
0.022
0.070
0.015
1.290
-
4.95
0.558
1.77
0.381
-
A2
A
-
SEATING
PLANE
L
C
L
B1
C
8
D1
B1
eA
A1
A
-
D1
e
eC
C
D
29.3
32.7
5
B
eB
D1
E
0.13
15.24
12.32
-
5
0.010 (0.25) M
C
B S
0.625
0.580
15.87
14.73
6
E1
e
5
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
0.100 BSC
0.600 BSC
2.54 BSC
15.24 BSC
-
e
e
6
A
B
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
-
0.700
0.200
-
17.78
5.08
7
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
L
0.115
2.93
4
9
4. Dimensions A, A1 and L are measured with the package seated in
N
24
24
JEDEC seating plane gauge GS-3.
Rev. 0 12/93
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
e
6. E and
are measured with the leads constrained to be perpendic-
A
-C-
ular to datum
.
7. e and e are measured at the lead tips with the leads unconstrained.
B
C
e
must be zero or greater.
C
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
FN8194.3
October 12, 2006
18
X9418
Small Outline Plastic Packages (SOIC)
M24.3 (JEDEC MS-013-AD ISSUE C)
N
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
MAX
2.65
0.30
0.51
0.32
15.60
7.60
NOTES
-B-
A
A1
B
C
D
E
e
0.0926
0.0040
0.013
0.1043
0.0118
0.020
-
-
1
2
3
L
9
SEATING PLANE
A
0.0091
0.5985
0.2914
0.0125
-
-A-
o
0.6141 15.20
3
h x 45
D
0.2992
7.40
4
-C-
0.05 BSC
1.27 BSC
-
α
µ
H
h
0.394
0.010
0.016
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C A M B S
N
α
24
24
7
o
o
o
o
0
8
0
8
-
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
FN8194.3
October 12, 2006
19
X9418
Thin Shrink Small Outline Package Family (TSSOP)
MDP0044
THIN SHRINK SMALL OUTLINE PACKAGE FAMILY
0.25 M C A B
D
A
(N/2)+1
SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE
N
A
A1
A2
b
1.20
0.10
0.90
0.25
0.15
5.00
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
5.00
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
6.50
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
7.80
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
9.70
6.40
4.40
0.65
0.60
1.00
Max
±0.05
PIN #1 I.D.
E
E1
±0.05
+0.05/-0.06
+0.05/-0.06
±0.10
c
0.20 C B A
2X
1
(N/2)
D
N/2 LEAD TIPS
B
E
Basic
TOP VIEW
E1
e
±0.10
Basic
L
±0.15
0.05
H
e
L1
Reference
Rev. E 12/02
C
NOTES:
SEATING
PLANE
1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
0.10 M C A B
b
0.10 C
N LEADS
SIDE VIEW
2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.
3. Dimensions “D” and “E1” are measured at dAtum Plane H.
SEE DETAIL “X”
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
END VIEW
L1
A2
A
GAUGE
PLANE
0.25
L
A1
0° - 8°
DETAIL X
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8194.3
October 12, 2006
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