X9421WS16I_技术文档

X9421

®

Low Noise/Low Power/SPI Bus

Data Sheet

September 23, 2005

FN8196.1

DESCRIPTION

The X9421 integrates a single digitally controlled

Single Digitally Controlled (XDCP™)

Potentiometer

potentiometer (XDCP) on

integrated circuit.

a

monolithic CMOS

FEATURES

• Single Voltage Potentiometer

• 64 Resistor Taps

The digital controlled potentiometer is implemented

using 63 resistive elements in a series array. Between

each element are tap points connected to the wiper

terminal through switches. The position of the wiper on

the array is controlled by the user through the SPI bus

interface. The potentiometer has associated with it a

volatile Wiper Counter Register (WCR) and a four non-

volatile Data Registers that can be directly written to

and read by the user. The contents of the WCR

controls the position of the wiper on the resistor array

though the switches. Powerup recalls the contents of

the default data register (DR0) to the WCR.

• SPI Serial Interface for Write, Read, and Transfer

Operations of the Potentiometer

• Wiper Resistance, 150Ω Typical at 5V

• 4 Non-Volatile Data Registers

• Non-Volatile Storage of Multiple Wiper Positions

• Power-on Recall. Loads Saved Wiper Position

on Power-up.

• Standby Current < 5µA Max

• V

: 2.7V to 5.5V Operation

CC

• 2.5kΩ, 10kΩ End to End Resistance

• 100 yr. Data Retention

• Endurance: 100, 000 Data Changes per Bit per

Register

• 14 Ld TSSOP, 16 Ld SOIC

The XDCP can be used as a three-terminal

potentiometer or as a two terminal variable resistor in

a wide variety of applications including control,

parameter adjustments, and signal processing.

• Low Power CMOS

• Pb-Free Plus Anneal Available (RoHS Compliant)

BLOCK DIAGRAM

V

R /V

CC

H

write

read

10kΩ

transfer

inc / dec

address

data

status

Power-on Recall

64-taps

wiper

Wiper Counter

Register (WCR)

Bus

Interface &

Control

POT

SPI

bus

interface

Data Registers

4 Bytes

control

R

/V

W

V

R /V

W

SS

L

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

1

X9421

Ordering Information

POTENTIOMETER

ORGANIZATION

(kΩ)

PART NUMBER

X9421YS16*

PART MARKING

V

LIMITS (V)

TEMP RANGE (°C)

0 to 70

PACKAGE

CC

X9421YS

5 ±10%

2.5

16 Ld SOIC (300 mil)

X9421YS16Z* (Note)

X9421YS16I*

X9421YS Z

0 to 70

16 Ld SOIC (300 mil) (Pb-free)

16 Ld SOIC (300 mil)

-40 to 85

0 to 70

X9421YS16IZ* (Note)

X9421YV14*

X9421YS Z I

16 Ld SOIC (300 mil) (Pb-free)

14 Ld TSSOP (4.4mm)

16 Ld SOIC (300 mil)

X9421YV14I*

-40 to 85

0 to 70

X9421WS16*

X9421WS

10

X9421WS16Z* (Note)

X9421WS16I*

X9421WS Z

X9421WS I

X9421WS Z I

X9421WV

0 to 70

16 Ld SOIC (300 mil) (Pb-free)

16 Ld SOIC (300 mil)

-40 to 85

0 to 70

X9421WS16IZ* (Note)

X9421WV14*

16 Ld SOIC (300 mil) (Pb-free)

14 Ld TSSOP (4.4mm)

16 Ld SOIC (300 mil)

X9421WV14I*

X9421WV I

-40 to 85

0 to 70

X9421YS16-2.7*

X9421YS16Z-2.7* (Note)

X9421YS16I-2.7*

X9421YS16IZ-2.7* (Note)

X9421YV14-2.7*

X9421YV14I-2.7*

X9421WS16-2.7*

X9421WS16Z-2.7* (Note)

X9421WS16I-2.7*

X9421WS16IZ-2.7* (Note)

X9421WV14-2.7*

X9421WV14I-2.7*

2.7 to 5.5

2.5

X9421YS Z F

X9421YS Z G

0 to 70

16 Ld SOIC (300 mil) (Pb-free)

16 Ld SOIC (300 mil)

-40 to 85

0 to 70

16 Ld SOIC (300 mil) (Pb-free)

14 Ld TSSOP (4.4mm)

16 Ld SOIC (300 mil)

X9421YV G

X9421WS F

X9421WS Z F

X9421WS G

X9421WS Z G

X9421WV F

X9421WV G

-40 to 85

0 to 70

10

0 to 70

16 Ld SOIC (300 mil) (Pb-free)

16 Ld SOIC (300 mil)

-40 to 85

0 to 70

16 Ld SOIC (300 mil) (Pb-free)

14 Ld TSSOP (4.4mm)

-40 to 85

*Add "T1" suffix for tape and reel.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

FN8196.1

2

September 23, 2005

X9421

DETAILED FUNCTIONAL DIAGRAM

V

CC

Power-on Recall

10kΩ

64--taps

DR0

DR1

R /V

H

WIPER

HOLD

COUNTER

REGISTER

(WCR)

Control

DATA

CS

SCK

SO

DR2 DR3

R /V

L

INTERFACE

AND

CONTROL

R

/V

W

CIRCUITRY

SI

A0

WP

V

SS

CIRCUIT LEVEL APPLICATIONS

SYSTEM LEVEL APPLICATIONS

• Adjust the contrast in LCD displays

• Control the power level of LED transmitters in

communication systems

• Vary the gain of a voltage amplifier

• Provide programmable dc reference voltages for

comparators and detectors

• Control the volume in audio circuits

• Trim out the offset voltage error in a voltage

amplifier circuit

• Set and regulate the DC biasing point in an RF

power amplifier in wireless systems

• Control the gain in audio and home entertainment

systems

• Set the output voltage of a voltage regulator

• Trim the resistance in Wheatstone bridge circuits

• Control the gain, characteristic frequency and

Q-factor in filter circuits

• Set the scale factor and zero point in sensor signal

conditioning circuits

• Vary the frequency and duty cycle of timer ICs

• Vary the dc biasing of a pin diode attenuator in RF

circuits

• Provide the variable DC bias for tuners in RF

wireless systems

• Set the operating points in temperature control

systems

• Control the operating point for sensors in industrial

systems

• Trim offset and gain errors in artificial intelligent

systems

• Provide a control variable (I, V, or R) in feedback

circuits

FN8196.1

September 23, 2005

3

X9421

PIN CONFIGURATION

TSSOP

SOIC

V

S0

NC

CC

14

13

12

11

10

1

2

3

4

5

6

7

V

NC

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

CC

R /V

NC

L

SO

NC

R /V

L

R /V

L

H

R

/V

R /V

H

CS

W

H

X9421

SCK

SI

R /V

W W

HOLD

A0

HOLD

SI

9

8

VSS

WP

A0

NC

VSS

WP

PIN ASSIGNMENTS

TSSOP pin

SOIC pin

Symbol

SO

Brief Description

1

2

3

Serial Data Output

No Connect

NC

3

NC

No Connect

4

5

CS

Chip Select

5

SCK

SI

Serial Clock

6

Serial Data Input

System Ground

7

8

V

SS

8

9

WP

A0

Hardware Write Protect

Device Address

9

10

11

12

13

14

16

1

10

11

12

13

14

HOLD

Device select. Pause the serial bus.

Wiper Terminal of the Potentiometer.

High Terminal of the Potentiometer.

Low Terminal of the Potentiometer.

System Supply Voltage

No Connect

R

/ V

W

H

L

R

H

R / V

L

V

CC

NC

7

No Connect

15

No Connect

FN8196.1

4

September 23, 2005

X9421

PIN DESCRIPTIONS

Potentiometer Pins

V /R , V /R

L

Hos t Interface Pins

H

L

The V /R and V /R inputs are equivalent to the

terminal connections on either end of a mechanical

potentiometer.

H

L

Serial Output (SO)

SO is a push/pull serial data output pin. During a read

cycle, data is shifted out on this pin. Data is clocked

out by the falling edge of the serial clock.

V /R

W

The wiper output is equivalent to the wiper output of a

mechanical potentiometer.

Serial Input

SI is the serial data input pin. All opcodes, byte

addresses and data to be written to the potentiometer

and pot register are input on this pin. Data is latched

by the rising edge of the serial clock.

Hardware Write Protect Input (WP)

The WP pin when LOW prevents nonvolatile writes to

the Data Registers. Writing to the Wiper Counter

Register is not restricted.

Serial Clock (SCK)

System/Digital Supply (V

)

The SCK input is used to clock data into and out of the

X9421.

CC

V

is the supply voltage for the system/digital

CC

section. V is the system ground.

SS

Chip Select (CS)

PRINCIPLES OF OPERATION

When CS is HIGH, the X9421 is deselected and the

SO pin is at high impedance, and (unless an internal

write cycle is underway) the device will be in the

standby state. CS LOW enables the X9421, placing it

in the active power mode. It should be noted that after

a power-up, a HIGH to LOW transition on CS is

required prior to the start of any operation.

The X9421 is

a

highly integrated microcircuit

incorporating a resistor array and associated registers

and counter and the serial interface logic providing

direct communication between the host and the XDCP

potentiometer.

Serial Interface

Hold (HOLD)

The X9421 supports the SPI interface hardware

conventions. The device is accessed via the SI input

with data clocked in on the rising SCK. CS must be

LOW and the HOLD and WP pins must be HIGH

during the entire operation.

HOLD is used in conjunction with the CS pin to select

the device. Once the part is selected and a serial

sequence is underway, HOLD may be used to pause

the serial communication with the controller without

resetting the serial sequence. To pause, HOLD must

be brought LOW while SCK is LOW. To resume

communication, HOLD is brought HIGH, again while

SCK is LOW. If the pause feature is not used, HOLD

should be held HIGH at all times.

The SO and SI pins can be connected together, since

they have three state outputs. This can help to reduce

system pin count.

Array Description

Device Address (A )

0

The X9421 is comprised of one resistor array

containing 63 discrete resistive segments that are

connected in series. The physical ends of each array

are equivalent to the fixed terminals of a mechanical

potentiometer (V /R and V /R inputs).

The address input is used to set the least significant bit

of the 8-bit slave address. A match in the slave

address serial data stream must be made with the

address input in order to initiate communication with

the X9421. A maximum of 2 devices may occupy the

SPI serial bus.

H

L

FN8196.1

5

September 23, 2005

X9421

At both ends of the array and between each resistor

segment is a CMOS switch connected to the wiper

Data Registers

The potentiometer has four 6-bit nonvolatile Data

Registers. These can be read or written directly by the

host. Data can also be transferred between any of the

four Data Registers and the WCR. It should be noted all

operations changing data in one of the Data Registers is

a nonvolatile operation and will take a maximum of 10ms.

(V /R ) output. Within the individual array only one

W

switch may be turned on at a time.

These switches are controlled by a Wiper Counter

Register (WCR). The six bits of the WCR are decoded to

select, and enable, one of sixty-four switches. The block

diagram of the potentiometer is shown in Figure 1.

If the application does not require storage of multiple

settings for the potentiometer, the Data Registers can

be used as regular memory locations for system

parameters or user preference data.

Wiper Counter Register (WCR)

The X9421 contains a Wiper Counter Register. The

WCR can be envisioned as a 6-bit parallel and serial

load counter with its outputs decoded to select one of

sixty-four switches along its resistor array. The

contents of the WCR can be altered in four ways: it

may be written directly by the host via the Write Wiper

Counter Register instruction (serial load); it may be

written indirectly by transferring the contents of one of

four associated Data Registers via the XFR Data

Register instruction (parallel load); it can be modified

one step at a time by the Increment/ Decrement

instruction. Finally, it is loaded with the contents of its

data register zero (DR0) upon power-up.

Register Descriptions

Table 1. Data Registers, (6-bit), Nonvolatile

0

D5

D4

D3

D2

D1

D0

(MSB)

(LSB)

There are four 6-bit Data Registers associated with the

potentiometer.

– {D5~D0}: These bits are for general purpose Non-

volatile data storage or for storage of up to four dif-

ferent wiper values.

The Wiper Counter Register is a volatile register; that

is, its contents are lost when the X9421 is powered-

down. Although the register is automatically loaded

with the value in DR0 upon power-up, this may be

different from the value present at power-down.

Table 2. Wiper Counter Register, (6-bit), Volatile

0

WP5 WP4 WP3 WP2 WP1 WP0

(MSB)

(LSB)

– {WP5~WP0}: These bits specify the wiper position

of the potentiometer.

FN8196.1

September 23, 2005

6

X9421

Figure 1. Detailed Potentiometer Block Diagram

Serial Data Path

V

Serial

Bus

Input

H

From Interface

Circuitry

C

O

U

N

T

Register 0

Register 1

8

6

Parallel

Bus

Input

E

R

Wiper

D

E

C

O

D

E

REGISTER 2

REGISTER 3

Counter

Register

(WCR)

INC/DEC

Logic

IF WCR = 00[H] THEN V = V

W

L

UP/DN

Modified SCK

IF WCR = 3F[H] THEN V = V

UP/DN

W

H

V

L

CLK

W

Write in Process

Figure 2. Address/Identification Byte Format

The contents of the Data Registers are saved to

nonvolatile memory when the CS pin goes from LOW to

HIGH after a complete write sequence is received by

the device. The progress of this internal write operation

can be monitored by a Write In Process bit (WIP). The

WIP bit is read with a Read Status command.

Device Type

Identifier

0

1

0

1

0

A0

Device Address

INSTRUCTIONS

Instruction Byte

Address/Identification (ID) Byte

The next byte sent to the X9421 contains the

instruction and register pointer information. The four

most significant bits are the instruction. The next two

bits point to one of four Data Registers. The format is

shown below in Figure 3.

The first byte sent to the X9421 from the host,

following a CS going HIGH to LOW, is called the

Address or Identification byte. The most significant

four bits of the slave address are a device type

identifier, for the X9421 this is fixed as 0101[B] (refer

to Figure 2).

Figure 3. Instruction Byte Format

The least significant bit in the ID byte selects one of

two devices on the bus. The physical device address

Register

Select

is defined by the state of the A input pin. The X9421

0

compares the serial data stream with the address

input state; a successful compare of the address bit is

required for the X9421 to successfully continue the

I3

I2

I1

I0

R1 R0

0

command sequence. The A input can be actively

0

Instructions

driven by a CMOS input signal or tied to V

or V

.

CC

SS

The remaining three bits in the ID byte must be set to 110.

FN8196.1

September 23, 2005

7

X9421

The four high order bits of the instruction byte specify

the operation. The next two bits (R and R ) select

one of the four registers that is to be acted upon when

a register oriented instruction is issued. The last two

bits are defined as 0.

Five instructions require a three-byte sequence to

complete. These instructions transfer data between

the host and the X9421; either between the host and

one of the Data Registers or directly between the host

and the WCR. These instructions are:

1

0

Two of the eight instructions are two bytes in length

and end with the transmission of the instruction byte.

These instructions are:

– Read Wiper Counter Register—read the current

wiper position of the pot,

– Write Wiper Counter Register—change current

wiper position of the pot,

– XFR Data Register to Wiper Counter Register —

This instruction transfers the contents of one speci-

fied Data Register to the Wiper Counter Register.

– Read Data Register—read the contents of the

selected data register;

– XFR Wiper Counter Register to Data Register—This

instruction transfers the contents of the Wiper

Counter Register to the specified associated Data

Register.

– Write Data Register—write a new value to the

selected data register.

– Read Status—This command returns the contents

of the WIP bit which indicates if the internal write

cycle is in progress.

The basic sequence of the two byte instructions is

illustrated in Figure 4. These two-byte instructions

exchange data between the WCR and one of the Data

Registers. A transfer from a Data Register to a WCR is

essentially a write to a static RAM, with the static RAM

controlling the wiper position. The response of the wiper

The sequence of these operations is shown in Figure

5 and Figure 6.

The final command is Increment/Decrement. It is

different from the other commands, because it’s length

is indeterminate. Once the command is issued, the

master can clock the wiper up and/or down in one

resistor segment steps; thereby, providing a fine

tuning capability to the host. For each SCK clock pulse

to this action will be delayed by t

. A transfer from

WRL

the WCR (current wiper position), to a Data Register is

a write to nonvolatile memory and takes a minimum of

t

to complete. The transfer can occur between the

WR

potentiometer and one of its associated registers.

(t

) while SI is HIGH, the selected wiper will move

HIGH

one resistor segment towards the V /R terminal.

H

Similarly, for each SCK clock pulse while SI is LOW,

the selected wiper will move one resistor segment

towards the V /R terminal. A detailed illustration of

L

the sequence and timing for this operation are shown

in Figure 7 and Figure 8.

Figure 4. Two-Byte Instruction Sequence

CS

SCK

SI

0

1

0

1

0

A0 I3 I2

I1 I0 R1 R0

0

FN8196.1

8

September 23, 2005

X9421

Figure 5. Three-Byte Instruction Sequence (Write)

CS

SCL

SI

1

0

1

0

1

0

A0

I3 I2

I1 I0 R1 R0

0

D5 D4 D3 D2 D1 D0

Figure 6. Three-Byte Instruction Sequence (Read)

CS

SCL

SI

Don’t Care

1

0

1

0

1

0

A0

I3 I2

I1 I0 R1 R0

0

S0

0

D5 D4 D3 D2 D1 D0

Figure 7. Increment/Decrement Instruction Sequence

CS

SCK

SI

0

1

0

1

0

A0

I3 I2

I1 I0

0

I

D

E

C

1

I

D

E

C

n

N

C

1

N

C

2

N

C

n

Figure 8. Increment/Decrement Timing Limits

t

WRID

SCK

SI

Voltage Out

V

W

INC/DEC CMD Issued

FN8196.1

September 23, 2005

9

X9421

Table 3. Instruction Set

Instruction

Instruction Set

I

R

0

Operation

3

2

1

0

1

Read Wiper Counter

Register

1

0

1

0

1

0

Read the contents of the Wiper Counter Register

Write Wiper Counter

Register

0

1

0

1

0

Write new value to the Wiper Counter Register

Read the contents of the Data Register pointed to

Read Data Register

Write Data Register

1/0 1/0

by R - R

1

0

Write new value to the Data Register pointed to by

R - R

1

0

XFR Data Register to

Wiper Counter

Register

Transfer the contents of the Data Register pointed

to by R - R to the Wiper Counter Register

1

0

1

0

1/0 1/0

0

1

0

XFR Wiper Counter

Register to Data

Register

Transfer the contents of the Wiper Counter

Register to the Data Register pointed to by R - R

1

0

Increment/Decrement

Wiper Counter

Register

Enable Increment/decrement of the Wiper Counter

Register

0

1

0

1

0

1

Read the status of the internal write cycle, by

checking the WIP bit.

Read Status (WIP bit)

FN8196.1

September 23, 2005

10

X9421

Instruction Format

Notes: (1) “A0”: stands for the device addresses sent by the master.

(2) WPx refers to wiper position data in the Wiper Counter Register

“I”: stands for the increment operation, SI held HIGH during active SCK phase (high).

(3) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).

Read Wiper Counter Register (WCR)

device type

identifier

device

addresses

instruction

opcode

wiper position

(sent by X9421 on SO)

CS

Falling

Edge

Rising

Edge

W W W W W W

0 P P P P P P

A

0

1

0

1

0

1

0

1

0

5

4 3 2 1 0

Write Wiper Counter Register (WCR)

device type

identifier

device

instruction

opcode

Data Byte

(sent by Host on SI)

addresses

CS

Falling

Edge

CS

Rising

Edge

W W W W W W

0 P P P P P P

A

0

1

0

1

0

1

0

1

0

5

4 3 2 1 0

Read Data Register (DR)

Read the contents of the Register pointed to by R1 - R0.

device type

identifier

device

addresses

instruction

opcode

register

addresses

Data Byte

(sent by X9421 on SO)

CS

Falling

Edge

Rising

Edge

W W W W W W

0 0 0 0 P P P P P P

A

0

R R

0

1

0

1

0

1

0

1

0

5

4 3 2 1 0

Write Data Register (DR)

Write a new value to the Register pointed to by R1 - R0.

device type

identifier

device

addresses

instruction

opcode

register

addresses

Data Byte

(sent by host on SI)

CS

Falling

Edge

CS

Rising

Edge

HIGH-VOLTAGE

WRITE CYCLE

W W W W W W

0 P P P P P P

A

0

R R

0

1

0

1

0

1

0

1

0

5

4 3 2 1 0

Transfer Data Register (DR) to Wiper Counter Register (WCR)

Transfer the contents of the Register pointed to by R1 - R0 to the WCR.

device type

identifier

device

addresses

instruction

opcode

register

addresses

CS

Falling

Edge

CS

Rising

Edge

A

0

R R

0

1

0

1

0

1

0

1

0 0

1

0

FN8196.1

September 23, 2005

11

X9421

Transfer Wiper Counter Register (WCR) to Data Register (DR)

device type

identifier

device

addresses

instruction

opcode

register

addresses

CS

Falling

Edge

CS

Rising

Edge

HIGH-VOLTAGE

WRITE CYCLE

A

0

R R

0

1

0

1

0

1

0

0 0

1

0

Increment/Decrement Wiper Counter Register (WCR)

device type

identifier

device

addresses

instruction

opcode

increment/decrement

(sent by master on SDA)

CS

Falling

Edge

CS

Rising

Edge

A

0

1

0

1

0

1

0

0 I/D I/D

.

I/D I/D

Read Status

device type

identifier

device

addresses

instruction

opcode

Data Byte

(sent by X9421 on SO)

CS

Falling

Edge

Rising

Edge

W

I

P

A

0

1

0

1

0

1

0

1

0

1

0

FN8196.1

12

September 23, 2005

X9421

ABSOLUTE MAXIMUM RATINGS

COMMENT

Temperature under bias. . . . . . . . . . . . .-65°C to +135°C

Storage temperature . . . . . . . . . . . . . . .-65°C to +150°C

Voltage on SCK any address input

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

This is a stress rating only; functional operation of the

device (at these or any other conditions above those

listed in the operational sections of this specification)

is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device

reliability.

with respect to V . . . . . . . . . . . . . . . . . .-1V to +7V

SS

∆V = | (V - V ) | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V

H

L

Lead temperature (soldering, 10 seconds) . . . . . . 300°C

(10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . .±6mA

I

W

Any V /R , V /R , V /R . . . . . . . . . . . V to V

H

L

W

SS CC

RECOMMENDED OPERATING CONDITIONS

Temp

Min.

0°C

Max.

+70°C

+85°C

Device

X9421

Supply Voltage (V ) Limits

CC

Commercial

Industrial

5V ± 10%

-40°C

X9421-2.7

2.7V to 5.5V

ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)

Limits

Symbol

Parameter

End to End Resistance Tolerance

Power Rating

Min.

Typ.

Max. Units

Test Conditions

25°C, each pot

±20

50

%

mW

mA

Ω

I

Wiper Current

±3

W

R

Wiper Resistance

150

400

250

Wiper Current = ± 1mA,

= 5V

W

V

CC

Wiper Current = ± 1mA,

1000

Ω

V

= 3V

CC

V

Voltage on any V /R , V /R , V /R

V

= 0V

TERM

H

L

W

SS

CC

SS

Noise

-120

1.6

dBV

%

Ref: 1kHz

(4)

Resolution

See Note 5

(1)

(3)

Absolute Linearity

(2)

±1

MI

(3)

MI

V

- V

w(n)(expected)

]

w(n) + MI

w(n)(actual)

- [V

Relative Linearity

±0.2

w(n + 1)

Temperature Coefficient of R

±300

ppm/°C See Note 5

±20 ppm/°C See Note 5

TOTAL

Ratiometric Temperature

Coefficient

C /C /C

Potentiometer Capacitances

Rh, RI, Rw leakage current

10/10/25

0.1

pF

µA

See Circuit #3

H

L

W

I

10

Vin = Vss to Vcc. Device is in

stand-by mode.

AL

Notes: (1) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as

a potentiometer.

(2) Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a

potentiometer. It is a measure of the error in step size.

(3) MI = RTOT/63 or (V - V )/63, single pot

H

L

(4) Typical = Individual array resolution.

FN8196.1

13

September 23, 2005

X9421

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

Limits

Symbol

Parameter

Min.

Typ.

Max.

Units

Test Conditions

I

V

Supply Current

400

µA

f = 2MHz, SO = Open,

SCK

CC1

CC

(Active)

Other Inputs = V

SS

I

V

Supply Current

1

mA

f

= 2MHz, SO = Open,

CC2

CC

(Non-volatile Write)

SCK

Other Inputs = V

SS

I

V

Current (Standby)

1

µA

V

SCK = SI = V , Addr. = V

SS SS

SB

CC

I

Input Leakage Current

Output Leakage Current

Input HIGH Voltage

Input LOW Voltage

10

V

= V to V

SS

LI

IN

CC

I

= V to V

SS

LO

OUT

V

x 0.7

V

+ 0.5

IH

CC

-0.5

CC

V

x 0.1

V

IL

CC

0.4

V

Output LOW Voltage

V

I

= 3mA

OL

ENDURANCE AND DATA RETENTION

Parameter

Minimum Endurance

Data Retention

Min.

Units

100,000

100

Data Changes per Bit per Register

Years

CAPACITANCE

Symbol

Test

Output Capacitance (SO)

Max.

Units

pF

Test Conditions

= 0V

(5)

C

8

6

V

OUT

V = 0V

IN

(5)

C

Input Capacitance (A0, SI, and SCK)

pF

IN

POWER-UP TIMING

Symbol

(5)

Parameter

Max.

0.2

Max.

50

Units

V/msec

t V

V

Power-up Ramp

R CC

CC

POWER-UP REQUIREMENTS (Power-up sequencing can affect correct recall of the wiper registers)

The preferred power-on sequence is as follows: First V and then the potentiometer pins, R , R , and R . Voltage

CC

should not be applied to the potentiometer pins before V

H

L

W

is applied. The V

ramp rate specification should be

CC

line should be held to <100mV if possible. Also, V

CC

met, and any glitches or slope changes in the V

should not

CC

reaches its final value.

reverse polarity by more than 0.5V. Recall of wiper position will not be complete until V

CC

Notes: (5) This parameter is periodically sampled and not 100% tested.

A.C. TEST CONDITIONS

V

0.9

x 0.1 to V x

CC

Input pulse levels

Input rise and fall times

10ns

Input and output timing level

V

CC

x 0.5

FN8196.1

September 23, 2005

14

X9421

EQUIVALENT A.C. LOAD CIRCUIT

Circuit #3 SPICE Macro Model

5V

2.7V

R

TOTAL

R

L

H

C

L

1533Ω

C

H

C

W

10pF

SDA Output

10pF

25pF

100pF

R

W

AC TIMING

Symbol

Parameter

Min.

Max.

Units

MHz

ns

µs

ns

µs

ns

f

SSI/SPI Clock Frequency

SSI/SPI Clock Cycle Time

SSI/SPI Clock High Time

SSI/SPI Clock Low Time

Lead Time

2.0

SCK

t

500

200

250

50

CYC

t

WH

t

WL

t

LEAD

t

Lag Time

LAG

t

SI, SCK, HOLD and CS Input Setup Time

SI, SCK, HOLD and CS Input Hold Time

SI, SCK, HOLD and CS Input Rise Time

SI, SCK, HOLD and CS Input Fall Time

SO Output Disable Time

SU

t

50

H

t

2

RI

t

2

FI

t

0

500

100

DIS

t

SO Output Valid Time

V

t

SO Output Hold Time

HO

RO

t

SO Output Rise Time

50

t

SO Output Fall Time

FO

t

HOLD Time

400

100

HOLD

t

HOLD Setup Time

HSU

t

HOLD Hold Time

HH

t

HOLD Low to Output in High Z

HOLD High to Output in Low Z

100

20

HZ

t

LZ

T

Noise Suppression Time Constant at SI, SCK, HOLD and CS inputs

CS Deselect Time

I

t

2

0

CS

t

WP, A0 and A1 Setup Time

WPASU

t

WP, A0 and A1 Hold Time

WPAH

FN8196.1

September 23, 2005

15

X9421

HIGH-VOLTAGE WRITE CYCLE TIMING

Symbol Parameter

Typ.

Max.

Units

t

High-voltage Write Cycle Time (Store Instructions)

5

10

ms

WR

XDCP TIMING

Symbol

Parameter

Min. Max. Units

t

Wiper Response Time After The Third (Last) Power Supply Is Stable

Wiper Response Time After Instruction Issued (All Load Instructions)

10

µs

WRPO

t

WRL

Wiper Response Time From An Active SCL/SCK Edge (Increment/Decrement

Instruction)

t

450

ns

WRID

SYMBOL TABLE

WAVEFORM

INPUTS

OUTPUTS

Must be

steady

Will be

steady

May change

from Low to

High

Will change

from Low to

High

May change

from High to

Low

Will change

from High to

Low

Don’t Care:

Changes

Allowed

Changing:

State Not

Known

N/A

Center Line

is High

Impedance

FN8196.1

16

September 23, 2005

X9421

TIMING DIAGRAMS

Input Timing

t

CS

t

LAG

LEAD

t

CYC

SCK

...

WH

t

RI

t

FI

t

WL

SU

H

...

MSB

LSB

SI

High Impedance

SO

Output Timing

CS

SCK

SO

SI

...

t

DIS

V

HO

MSB

LSB

ADDR

Hold Timing

CS

t

HH

HSU

SCK

SO

...

t

FO

RO

t

LZ

HZ

SI

t

HOLD

FN8196.1

17

September 23, 2005

X9421

XDCP Timing (for All Load Instructions)

CS

SCK

...

t

WRL

MSB

LSB

SI

V

W

High Impedance

SO

XDCP Timing (for Increment/Decrement Instruction)

CS

SCK

...

t

WRID

...

V

W

...

ADDR

Inc/Dec

SI

Inc/Dec

High Impedance

SO

Write Protect and Device Address Pins Timing

(Any Instruction)

CS

t

WPAH

WPASU

WP

A0

A1

FN8196.1

18

September 23, 2005

X9421

APPLICATIONS INFORMATION

Electronic potentiometers provide three powerful application advantages: (1) the variability and reliability of a solid-

state potentiometer, (2) the flexibility of computer-based digital controls, and (3) the retentivity of nonvolatile memory

used for the storage of multiple potentiometer settings or data.

Basic Configurations of Electronic Potentiometers

V

R

V

R

V

H

V

W

V

L

I

Three terminal Potentiometer;

Variable voltage divider

Two terminal Variable Resistor;

Variable current

Basic Circuits

Buffered Reference Voltage

Cascading Techniques

Noninverting Amplifier

R

+5V

1

+V

LM308A

V

+

–

S

+5V

V

O

X

V

OP-07

W

+

–

V

-5V

W

V

= V

W

OUT

V

W

R

2

+V

-5V

R

1

V

W

V

= (1+R /R )V

2 1 S

(a)

(b)

O

Offset Voltage Adjustment

Comparator with Hysterisis

Voltage Regulator

R

2

1

V

–

+

S

V

V (REG)

O

317

IN

V

S

O

100kΩ

R

1

–

+

V

O

I

adj

TL072

R

1

2

R

2

10kΩ

+12V

V

= {R /CR +R } V (max)

1 1 2 O

UL

LL

10kΩ

-12V

= {R /CR +R } V (min)

V

(REG) = 1.25V (1+R /R )+I

R

adj 2

1

2

O

2

1

FN8196.1

September 23, 2005

19

X9421

PACKAGING INFORMATION

16-Lead Plastic SOIC (300 Mil Body) Package Type S

0.290 (7.37)

0.299 (7.60)

0.393 (10.00)

0.420 (10.65)

PIN 1 INDEX

PIN 1

0.014 (0.35)

0.020 (0.51)

0.403 (10.2 )

0.413 ( 10.5)

(4X) 7°

0.092 (2.35)

0.105 (2.65)

0.003 (0.10)

0.012 (0.30)

0.050 (1.27)

0.010 (0.25)

0.050" Typical

X 45°

0.020 (0.50)

0° - 8 °

0.050"

0.0075 (0.19)

0.010 (0.25)

Typical

0.420"

0.015 (0.40)

0.050 (1.27)

0.030" Typical

16 Places

FOOTPRINT

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

FN8196.1

20

September 23, 2005

X9421

PACKAGING INFORMATION

14-Lead Plastic, TSSOP, Package Type V

.025 (.65) BSC

.169 (4.3)

.177 (4.5)

.252 (6.4) BSC

.193 (4.9)

.200 (5.1)

.047 (1.20)

.0075 (.19)

.0118 (.30)

.002 (.05)

.006 (.15)

.010 (.25)

Gage Plane

0° - 8°

Seating Plane

.019 (.50)

.029 (.75)

Detail A (20X)

.031 (.80)

.041 (1.05)

See Detail “A”

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8196.1

21

September 23, 2005


型号：	X9421WS16I
厂家：	Intersil
描述：	Single Digitally Controlled (XDCP) Potentiometer 单数控（ XDCP ）电位计
文件：	总21页 (文件大小：365K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

X9421WS16I [INTERSIL]

相关型号：

X9421WS16I-2.7

X9421WS16I-2.7-T1

X9421WS16I-T1

X9421WS16IT1

X9421WS16IZ

X9421WS16IZ-2.7

X9421WS16IZ-2.7-T1

X9421WS16IZ-2.7T1

X9421WS16IZ-T1

X9421WS16IZT1

X9421WS16Z

X9421WS16Z-2.7