X95820_06_技术文档

X95820

®

Dual Digital Controlled Potentiometers (XDCP™)

Data Sheet

July 18, 2006

FN8212.2

2

Low Noise/Low Power/I C^®Bus/256 Taps

Features

The X95820 integrates two digitally controlled

potentiometers (XDCP) on a monolithic CMOS integrated

circuit.

• Two potentiometers in one package

• 256 resistor taps-0.4% resolution

2

• I C serial interface

The digitally controlled potentiometers are implemented with

a combination of resistor elements and CMOS switches. The

position of the wipers are controlled by the user through the

- Three address pins, up to eight devices/bus

• Wiper resistance: 70Ω typical @ 3.3V

• Non-volatile storage of wiper position

• Standby current < 5µA max

2

I C bus interface. Each potentiometer has an associated

volatile Wiper Register (WR) and a non-volatile Initial Value

Register (IVR), that can be directly written to and read by the

user. The contents of the WR controls the position of the

wiper. At power up the device recalls the contents of the two

DCP’s IVR to the corresponding WRs.

• Power supply: 2.7V to 5.5V

• 50kΩ, 10kΩ total resistance

• High reliability

The DCPs can be used as three-terminal potentiometers or

as two-terminal variable resistors in a wide variety of

applications including control, parameter adjustments, and

signal processing.

- Endurance: 150,000 data changes per bit per register

- Register data retention: 50 years @ T ≤ 75°C

• 14 Ld TSSOP

• Pb-free plus anneal available (RoHS compliant)

Ordering Information

PART

MARKING

RESISTANCE

OPTION

Pinouts

PART NUMBER

PACKAGE

X95820

(14 LD TSSOP)

TOP VIEW

X95820WV14I-2.7* X95820WV G

10kΩ

14 Ld TSSOP

X95820WV14IZ-2.7* X95820WV Z G

(Note)

14 Ld TSSOP

(Pb-free)

V

CC

14

13

1

2

3

4

5

6

7

A1

WP

RH0

RL0

X95820UV14I-2.7* X95820UV G

50kΩ

14 Ld TSSOP

A0

RH1

12

11

X95820UV14IZ-2.7* X95820UV Z G

(Note)

14 Ld TSSOP

(Pb-free)

RL1

RW1

GND

RW0

10

9

*Add "T1" suffix for tape and reel.

A2

NOTE: Intersil Pb-free plus anneal products employ special Pb-free

material sets; molding compounds/die attach materials and 100%

matte tin plate termination finish, which are RoHS compliant and

compatible with both SnPb and Pb-free soldering operations. Intersil

Pb-free products are MSL classified at Pb-free peak reflow

temperatures that meet or exceed the Pb-free requirements of

IPC/JEDEC J STD-020.

SCL

SDA

8

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

1

X95820

Block Diagram

V

CC

2

R

I C

H1

POWER-UP,

INTERFACE,

CONTROL AND

STATUS LOGIC

INTERFACE

WR1

W1

SDA

SCL

R

L1

A2

A1

A0

R

H0

W0

L0

WR0

NON-VOLATILE

REGISTERS

WP

GND

PiN Descriptions

SYMBOL

DESCRIPTION

1

V

Power supply pin

CC

2

WP

RH0

RL0

RW0

A2

Hardware write protection pin. Active low. Prevents any “Write” operation of the I C interface.

3

“High” terminal of DCP0

“Low” terminal of DCP0

“Wiper” terminal of DCP0

4

5

2

6

Device address for the I C interface

2

7

SCL

SDA

GND

RW1

RL1

RH1

A0

I C interface clock

2

8

Serial data I/O for the I C interface

9

Ground

10

11

12

13

14

“Wiper” terminal of DCP1

“Low” terminal of DCP1

“High” terminal of DCP1

2

Device address for the I C interface

2

A1

Device address for the I C interface

FN8212.2

July 18, 2006

2

X95820

Absolute Maximum Ratings

Recommended Operating Conditions

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Temperature Range (Industrial). . . . . . . . . . . . . . . . . .-40°C to 85°C

Voltage at Any Digital Interface Pin

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

CC

with Respect to GND . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V +0.3

Power Rating of Each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW

Wiper Current of Each DCP. . . . . . . . . . . . . . . . . . . . . . . . . .±3.0mA

CC

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V

CC

Voltage at Any DCP Pin with Respect to GND . . . . . . -0.3V to V

CC

Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . .300°C

(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

I

W

CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional

operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

Analog Specifications Over recommended operating conditions unless otherwise stated.

TYP

SYMBOL

PARAMETER

to R Resistance

TEST CONDITIONS

W, U versions respectively

MIN

(Note 1)

MAX

UNIT

kΩ

%

R

10, 50

TOTAL

H

L

to R Resistance Tolerance

-20

+20

200

H

L

R

Wiper Resistance

V

= 3.3V @ 25°C

70

Ω

W

CC

Wiper current = V /R

CC TOTAL

C /C /C

W

Potentiometer Capacitance (Note 15)

Leakage on DCP Pins (Note 15)

10/10/25

0.1

pF

µA

H

L

I

Voltage at pin from GND to V

1

LkgDCP

CC

VOLTAGE DIVIDER MODE (0V @ RL ; V

@ RH ; measured at RW , unloaded; i = 0 or 1)

i

CC

i

INL (Note 6) Integral Non-linearity

-1

1

LSB

(Note 2)

DNL (Note 5) Differential Non-linearity

Monotonic over all tap positions

-0.5

0.5

LSB

(Note 2)

ZSerror

(Note 3)

Zero-scale Error

U option

W option

U option

W option

0

1

0.5

-1

7

2

0

2

LSB

(Note 2)

FSerror

(Note 4)

Full-scale Error

-7

-2

LSB

(Note 2)

-1

V

DCP to DCP Matching

Any two DCPs at same tap position, same

voltage at all RH terminals, and same

voltage at all RL terminals

LSB

(Note 2)

MATCH

(Note 7)

TC (Note 8) Ratiometric Temperature Coefficient

DCP Register set to 80 hex

±4

ppm/°C

V

RESISTOR MODE (Measurements between RW and RL with RH not connected, or between RW and RH with RL not

i

connected. i = 0 or 1)

RINL

(Note 12)

Integral Non-linearity

DCP register set between 20 hex and

FF hex. Monotonic over all tap positions

-1

-0.5

0

1

0.5

7

MI

(Note 9)

RDNL

(Note 11)

Differential Non-linearity

Offset

MI

(Note 9)

Roffset

(Note 10)

DCP Register set to 00 hex, U option

DCP Register set to 00 hex, W option

1

MI

(Note 9)

0

0.5

2

MI

(Note 9)

R

DCP to DCP Matching

Any two DCPs at the same tap position with

the same terminal voltages.

-2

2

MI

(Note 9)

MATCH

(Note 13)

TC

(Note 14)

Resistance Temperature Coefficient

DCP register set between 20 hex and FF

hex

±45

ppm/°C

R

FN8212.2

July 18, 2006

3

X95820

Operating Specifications Over the recommended operating conditions unless otherwise specified.

TYP

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

(Note 1)

MAX

UNITS

2

I

V

Supply Current

f

= 400kHz;SDA = Open; (for I C,

1

mA

CC1

CC

SCL

(Volatile write/read)

Active, Read and Volatile Write States only)

2

I

V

Supply Current

f

= 400kHz; SDA = Open; (for I C,

SCL

3

mA

CC2

CC

(nonvolatile write)

Active, Nonvolatile Write State only)

2

I

V

Current (standby)

V

= +5.5V, I C Interface in Standby State

5

2

µA

SB

CC

2

= +3.6V, I C Interface in Standby State

I

Leakage Current, at Pins A0, Voltage at pin from GND to V

-10

10

LkgDig

CC

A1, A2, SDA, SCL, and WP

Pins

t

DCP Wiper Response Time SCL falling edge of last bit of DCP Data Byte to

wiper change

1

µs

DCP

(Note 15)

Vpor

Power-on Recall Voltage

Ramp Rate

Minimum V

at which memory recall occurs

1.8

0.2

2.6

V

CC

VccRamp

V

V/ms

ms

CC

t

(Note 15) Power-up Delay

V

above Vpor, to DCP Initial Value Register recall

CC

3

D

2

completed, and I C Interface in standby state

EEPROM SPECS

EEPROM Endurance

EEPROM Retention

SERIAL INTERFACE SPECS

150,000

50

Cycles

Years

Temperature ≤ 75°C

V

WP, A2, A1, A0, SDA, and

SCL input buffer LOW

voltage

-0.3

0.3*Vcc

Vcc+0.3

V

IL

V

WP, A2, A1, A0, SDA, and

SCL Input Buffer HIGH

Voltage

0.7*Vcc

IH

Hysterisis

(Note 15)

SDA and SCL input buffer

hysterisis

0.05*

Vcc

V

SDA Output Buffer LOW

Voltage, Sinking 4mA

0

0.4

10

OL

(Note 15)

Cpin

(Note 15)

WP, A2, A1, A0, SDA, and

SCL Pin Capacitance

pF

f

SCL Frequency

400

50

kHz

ns

SCL

t

Pulse Width Suppression

Time at SDA and SCL Inputs suppressed.

Any pulse narrower than the max spec is

IN

(Note 15)

t

SCL Falling Edge to SDA

Output Data Valid

SCL falling edge crossing 30% of V , until SDA

CC

900

ns

AA

(Note 15)

exits the 30% to 70% of V

window.

CC

t

Time the Bus Must be Free SDA crossing 70% of V

Before the Start of a New

Transmission

during a STOP condition,

1300

BUF

(Note 15)

CC

to SDA crossing 70% of V

during the following

CC

START condition.

t

Clock LOW Time

Clock HIGH Time

Measured at the 30% of V

Measured at the 70% of V

crossing.

1300

600

ns

LOW

CC

t

HIGH

CC

t

START Condition Setup

Time

SCL rising edge to SDA falling edge. Both crossing

70% of V

600

SU:STA

.

CC

t

START Condition Hold Time From SDA falling edge crossing 30% of V

to SCL

600

ns

HD:STA

CC

falling edge crossing 70% of V

.

CC

FN8212.2

July 18, 2006

4

X95820

Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)

TYP

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

(Note 1)

MAX

UNITS

t

Input Data Setup Time

From SDA exiting the 30% to 70% of V

window, to SCL rising edge crossing 30% of V

100

ns

SU:DAT

HD:DAT

SU:STO

HD:STO

CC

t

Input Data Hold Time

From SCL rising edge crossing 70% of V

to SDA

0

ns

pF

kΩ

CC

window.

entering the 30% to 70% of V

CC

t

STOP Condition Setup Time From SCL rising edge crossing 70% of V , to SDA

CC

600

0

rising edge crossing 30% of V

.

CC

STOP Condition Setup Time From SDA rising edge to SCL falling edge. Both

crossing 70% of V

t

.

CC

t

(Note 15) Output Data Hold Time

From SCL falling edge crossing 30% of V , until

DH

CC

window.

SDA enters the 30% to 70% of V

CC

t

(Note 15) SDA and SCL Rise Time

(Note 15) SDA and SCL Fall Time

From 30% to 70% of V

20 +

0.1 * Cb

250

400

R

CC

t

From 70% to 30% of V

20 +

0.1 * Cb

F

CC

Cb (Note 15) Capacitive Loading of SDA

or SCL

Total on-chip and off-chip

10

1

Rpu (Note 15) SDA and SCL Bus Pull-up

resIstor Off-chip

Maximum is determined by t and t .

R F

For Cb = 400pF, max is about 2~2.5kΩ.

For Cb = 40pF, max is about 15~20kΩ.

t

Non-volatile Write Cycle

12

20

ms

ns

WP

(Notes 15, 16) Time

t

A2, A1, A0, and WP Setup

Time

Before START condition

After STOP condition

600

SU:WPA

t

A2, A1, A0, and WP Hold

Time

HD:WPA

SDA vs. SCL Timing

t

R

F

HIGH

LOW

SCL

t

SU:DAT

t

SU:STO

SU:STA

HD:DAT

t

HD:STA

SDA

(INPUT TIMING)

t

BUF

AA

DH

SDA

(OUTPUT TIMING)

WP, A0, A1, and A2 Pin Timing

STOP

START

SCL

Clk 1

SDA IN

t

HD:WPA

SU:WPA

WP, A0, A1, or A2

FN8212.2

July 18, 2006

5

X95820

NOTES:

1. Typical values are for T = 25°C and 3.3V supply voltage.

A

2. LSB: [V(RW)

255

- V(RW) ] / 255. V(RW) and V(RW) are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the

255 0

0

incremental voltage when changing from one tap to an adjacent tap.

3. ZS error = V(RW) / LSB.

0

4. FS error = [V(RW)

255

- V ] / LSB.

CC

5. DNL = [V(RW) - V(RW) ] / LSB-1, for i = 1 to 255. i is the DCP register setting.

i-1

i

6. INL = [V(RW) – (i • LSB – V(RW) )]/LSB for i = 1 to 255.

i

0

7. V

= [V(RWx) - V(RWy) ] / LSB, for i = 0 to 255, x = 0 to 1 and y = 0 to 1.

i i

MATCH

Max(V(RW) ) – Min(V(RW) )

6

10

i

--------------------------------------------------------------------------------------------- ----------------

TC

=

×

8.

V

[Max(V(RW) ) + Min(V(RW) )] ⁄ 2 125°C

i

for i = 16 to 240 decimal, T = -40°C to 85°C. Max( ) is the maximum value of the wiper voltage and Min ( ) is the minimum value of the wiper

voltage over the temperature range.

9. MI = |R

- R | / 255. R

and R are the measured resistances for the DCP register set to FF hex and 00 hex respectively.

255 0

255

0

10. Roffset = R / MI, when measuring between RW and RL.

0

Roffset = R

/ MI, when measuring between RW and RH.

255

11. RDNL = (R - R ) / MI, for i = 32 to 255.

i

i-1

12. RINL = [R - (MI • i) - R ] / MI, for i = 32 to 255.

i

0

13. R

14.

= (R - R ) / MI, for i = 0 to 255, x = 0 to 1 and y = 0 to 1.

i,x i,y

MATCH

6

[Max(Ri) – Min(Ri)]

10

--------------------------------------------------------------- ----------------

TC

=

×

R

125°C

[Max(Ri) + Min(Ri)] ⁄ 2

for i = 32 to 255, T = -40°C to 85°C. Max( ) is the maximum value of the resistance and Min ( ) is the minimum value of the resistance over the

temperature range.

15. This parameter is not 100% tested.

16. t

is the minimum cycle time to be allowed for any non-volatile Write by the user, unless Acknowledge Polling is used. It is the time from a

WC

2

valid STOP condition at the end of a Write sequence of a I C serial interface Write operation, to the end of the self-timed internal non-volatile

write cycle.

Typical Performance Curves

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

160

140

120

100

80

V

= 2.7, T = 85°C

CC

V

= 2.7, T = -40°C

CC

V = 2.7, T = 25°C

CC

-40°C

85°C

60

40

V

= 5.5, T = 85°C

CC

= 5.5, T = 25°C

20

25°C

V

= 5.5, T = -40°C

V

CC

0

2.7

3.2

3.7

4.2

(V)

4.7

5.2

0

50

100

150

200

250

V

CC

TAP POSITION (DECIMAL)

FIGURE 2. STANDBY I

vs V

CC

FIGURE 1. WIPER RESISTANCE vs TAP POSITION

[ I(RW) = V /R ] FOR 50kΩ (U)

CC

CC TOTAL

FN8212.2

July 18, 2006

6

X95820

Typical Performance Curves (Continued)

0.3

0.2

0.1

0

0.2

V

= 2.7, T = -40°C

CC

= 5.5, T = -40°C

V

= 5.5, T = -40°C

CC

V

= 2.7, T = -40°C

CC

V

= 5.5, T = 85°C

CC

0.15

0.1

V

= 2.7, T = 25°C

CC

0.05

0

V

= 2.7, T = 25°C

CC

-0.05

-0.1

-0.15

-0.2

V

= 2.7, T = 85°C

CC

-0.1

-0.2

-0.3

V

= 5.5, T = 25°C

CC

V

= 5.5, T = 25°C

CC

V

= 5.5, T = 85°C

V

= 2.7, T = 85°C

CC

0

50

100

150

200

250

0

50

100

150

200

250

TAP POSITION (DECIMAL)

FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER

FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER

MODE FOR 10kΩ (W)

0

-0.1

-0.2

0.4

0.35

V

= 5.5V

= 2.7V

CC

-0.3

-0.4

-0.5

-0.6

-0.7

-0.8

0.3

V

CC

2.7V

0.25

0.2

5.5V

-0.9

-1

0.15

0

-40

-20

20

40

60

80

-40

-20

0

20

40

60

80

TEMPERATURE (°C)

FIGURE 6. FSerror vs TEMPERATURE

FIGURE 5. ZSerror vs TEMPERATURE

0.3

0.5

0.4

0.3

0.2

0.1

0

V

= 2.7, T = 25°C

CC

V

= 2.7, T = 25°C

CC

0.2

0.1

0

V

= 5.5, T = 25°C

CC

V

= 5.5, T = -40°C

CC

V

= 5.5, T = 85°C

CC

-0.1

-0.2

-0.3

-0.4

-0.5

-0.1

-0.2

-0.3

V

= 5.5, T = 85°C

CC

V

= 2.7, T = 85°C

CC

V

= 2.7, T = -40°C

CC

V

= 2.7, T = 85°C

CC

V

= 5.5, T = -40°C

CC

V

= 5.5, T = 25°C

V

= 2.7, T = -40°C

CC

32

82

132

182

232

32

82

132

182

232

TAP POSITION (DECIMAL)

FIGURE 8. INL vs TAP POSITION IN Rheostat MODE FOR

FIGURE 7. DNL vs TAP POSITION IN Rheostat MODE FOR

50kΩ (U)

FN8212.2

July 18, 2006

7

X95820

Typical Performance Curves (Continued)

1.50

1.00

20

10

0

0.50

2.7V

5.5V

0.00

-0.50

-1.00

-1.50

-10

-20

32

82

132

182

232

-40

-20

0

20

40

60

80

TEMPERATURE (°C)

TAP POSITION (DECIMAL)

FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm

FIGURE 9. END TO END R

% CHANGE vs

TOTAL

TEMPERATURE

35

25

15

5

INPUT

OUTPUT

-5

Tap Position = Mid Point

-15

-25

R

= 9.4K

TOTAL

32

57

82

107

132

157

182

207

232

TAP POSITION (DECIMAL)

FIGURE 12. FREQUENCY RESPONSE (2.2MHz)

FIGURE 11. TC FOR Rheostat MODE IN ppm

SCL

Signal at Wiper (Wiper Unloaded)

Signal at Wiper

(Wiper Unloaded Movement

From ffh to 00h)

Wiper Movement Mid Point

From 80h to 7fh

FIGURE 13. MIDSCALE GLITCH, CODE 80h TO 7Fh (WIPER 0)

FIGURE 14. LARGE SIGNAL SETTLING TIME

FN8212.2

July 18, 2006

8

X95820

When the byte at address 8 is all zeroes, which is the default

at power up:

Principles of Operation

The X95820 in as integrated circuit incorporating two DCPs

with their associated registers, non-volatile memory, and a

• A read operation to addresses 0 or 1 outputs the value of

the non-volatile IVRs.

2

I C serial interface providing direct communication between

a host and the potentiometers and memory.

• A write operation to addresses 0 or 1 writes the same

value to the WR and IVR of the corresponding DCP.

DCP Description

When the byte at address 8 is 80h (128 decimal):

Each DCP is implemented with a combination of resistor

elements and CMOS switches. The physical ends of each

DCP are equivalent to the fixed terminals of a mechanical

potentiometer (RH and RL pins). The RW pin of each DCP is

connected to intermediate nodes, and is equivalent to the

wiper terminal of a mechanical potentiometer. The position

of the wiper terminal within the DCP is controlled by an 8-bit

volatile Wiper Register (WR). Each DCP has its own WR.

When the WR of a DCP contains all zeroes (WR<7:0>: 00h),

its wiper terminal (RW) is closest to its “Low” terminal (RL).

When the WR of a DCP contains all ones (WR<7:0>: FFh),

its wiper terminal (RW) is closest to its “High” terminal (RH).

As the value of the WR increases from all zeroes (00h) to all

ones (255 decimal), the wiper moves monotonically from the

position closest to RL to the closest to RH. At the same time,

the resistance between RW and RL increases monotonically,

while the resistance between RH and RW decreases

monotonically.

• A read operation to addresses 0 or 1 outputs the value of

the volatile WR.

• A write operation to addresses 0 or 1only writes to the

corresponding volatile WR.

It is not possible to write to an IVR without writing the same

value to its corresponding WR.

00h and 80h are the only values that should be written to

address 8. All other values are reserved and must not be

written to address 8.

To access the general purpose bytes at addresses 2, 3, 4, 5,

or 6, the value at address 8 must be all zeros.

The X95820 is pre-programmed with 80h in the two IVRs.

TABLE 1. MEMORY MAP

ADDRESS

NON-VOLATILE

VOLATILE

8

7

-

Access Control

While the X95820 is being powered up, all two WRs are

reset to 80h (128 decimal), which locates RW roughly at the

center between RL and RH. Soon after the power supply

voltage becomes large enough for reliable non-volatile

memory reading, the X95820 reads the value stored on two

different non-volatile Initial Value Registers (IVRs) and loads

them into their corresponding WRs.

Reserved

6

5

4

3

2

General Purpose

Not Available

1

0

IVR1

IVR0

WR1

WR0

The WRs and IVRs can be read or written directly using the

2

I C serial interface as described in the following sections.

WR: Wiper Register, IVR: Initial value Register.

Memory Description

2

I C Serial Interface

The X95820 contains eight non-volatile bytes. they are

2

accessed by I C interface operations with Address Bytes 0

The X95820 supports a bidirectional I C bus oriented

through 7 decimal. The first two non-volatile bytes at

addresses 0 and 1 contain the initial value loaded at power-

up into the volatile Wiper Registers (WRs) of DCP0 and

DCP1 respectively. Bytes at addresses 2, 3, 4, 5, and 6 are

available to the user as general purpose registers. The byte

at address 7 is reserved; the user should not write to it, and

its value should be ignored if read.

protocol. The protocol defines any device that sends data

onto the bus as a transmitter and the receiving device as the

receiver. The device controlling the transfer is a master and

the device being controlled is the slave. The master always

initiates data transfers and provides the clock for both

transmit and receive operations. Therefore, the X95820

operates as a slave device in all applications.

2

The volatile WR, and the non-volatile Initial Value Register

(IVR) of a DCP are accessed with the same Address Byte.

All communication over the I C interface is conducted by

sending the MSB of each byte of data first.

A volatile byte at address 8 decimal, controls what byte is

read or written when accessing DCP registers: the WR, the

IVR, or both.

Protocol Conventions

Data states on the SDA line can change only during SCL

LOW periods. SDA state changes during SCL HIGH are

reserved for indicating START and STOP conditions (See

Figure 15). On power up of the X95820 the SDA pin is in the

input mode.

FN8212.2

July 18, 2006

9

X95820

2

All I C interface operations must begin with a START

receiver pulls the SDA line LOW to acknowledge the

condition, which is a HIGH to LOW transition of SDA while

SCL is HIGH. The X95820 continuously monitors the SDA

and SCL lines for the START condition and does not

respond to any command until this condition is met (See

Figure 15). A START condition is ignored during the power

up sequence and during internal non-volatile write cycles.

reception of the eight bits of data (See Figure 16).

The X95820 responds with an ACK after recognition of a

START condition followed by a valid Identification Byte, and

once again after successful receipt of an Address Byte. The

X95820 also responds with an ACK after receiving a Data

Byte of a write operation. The master must respond with an

ACK after receiving a Data Byte of a read operation

2

All I C interface operations must be terminated by a STOP

condition, which is a LOW to HIGH transition of SDA while

SCL is HIGH (See Figure 15). A STOP condition at the end

of a read operation, or at the end of a write operation to

volatile bytes only places the device in its standby mode. A

STOP condition during a write operation to a non-volatile

byte, initiates an internal non-volatile write cycle. The device

enters its standby state when the internal non-volatile write

cycle is completed.

A valid Identification Byte contains 1010 as the four MSBs,

and the following three bits matching the logic values

present at pins A2, A1, and A0. The LSB in the Read/Write

bit. Its value is “1” for a Read operation, and “0” for a Write

operation (See Table 2).

TABLE 2. IDENTIFICATION BYTE FORMAT

Logic values at pins A2, A1, and A0 respectively

An ACK, Acknowledge, is a software convention used to

indicate a successful data transfer. The transmitting device,

either master or slave, releases the SDA bus after

1

0

1

0

A2

A1

A0

R/W

(MSB)

(LSB)

transmitting eight bits. During the ninth clock cycle, the

SCL

SDA

START

DATA

STOP

STABLE CHANGE STABLE

FIGURE 15. VALID DATA CHANGES, START, AND STOP CONDITIONS

SCL from Master

1

8

9

SDA Output from

Transmitter

High Impedance

SDA Output from

Receiver

START

ACK

FIGURE 16. ACKNOWLEDGE RESPONSE FROM RECEIVER

Write

S

Signals from the

Master

t

a

r

S

t

o

p

Data

Byte

Address

Byte

Identification

Byte

t

Signal at SDA

1 0 1 0

A2A1A00

0 0 0 0

Signals from the

X95820

A

C

K

A

C

K

A

C

K

FIGURE 17. BYTE WRITE SEQUENCE

FN8212.2

July 18, 2006

10

X95820

pulse that loads the last bit (LSB) of the Data Byte. If the

Write Operation

Address Byte is between 0 and 6 (inclusive), and the Access

Control Register is all zeros (default), then the STOP

condition initiates the internal write cycle to non-volatile

memory.

A Write operation requires a START condition, followed by a

valid Identification Byte, a valid Address Byte, a Data Byte,

and a STOP condition. After each of the three bytes, the

X95820 responds with an ACK. At this time, if the Data Byte

is to be written only to volatile registers, then the device

enters its standby state. If the Data Byte is to be written also

to non-volatile memory, the X95820 begins its internal write

cycle to non-volatile memory. During the internal non-volatile

write cycle, the device ignores transitions at the SDA and

SCL pins, and the SDA output is at a high impedance state.

When the internal non-volatile write cycle is completed, the

X95820 enters its standby state (See Figure 17).

Read Operation

A Read operation consists of a three byte instruction

followed by one or more Data Bytes (See Figure 18). The

master initiates the operation issuing the following

sequence: a START, the Identification byte with the R/W bit

set to “0”, an Address Byte, a second START, and a second

Identification byte with the R/W bit set to “1”. After each of

the three bytes, the X95820 responds with an ACK. Then the

X95820 transmits Data Bytes as long as the master

responds with an ACK during the SCL cycle following the

eight bit of each byte. The master terminates the read

operation (issuing a STOP condition) following the last bit of

the last Data Byte (See Figure 18).

The byte at address 00001000 bin (8 decimal) determines if

the Data Byte is to be written to volatile and/or non-volatile

memory. See “Memory Description” on page 9.

Data Protection

The WP pin has to be at logic HIGH to perform any Write

operation to the device. When the WP is active (LOW) the

device ignores Data Bytes of a Write Operation, does not

respond to the Data Bytes with an ACK, and instead, goes to

its standby state waiting for a new START condition.

The Data Bytes are from the memory location indicated by

an internal pointer. This pointer initial value is determined by

the Address Byte in the Read operation instruction, and

increments by one during transmission of each Data Byte.

After reaching the memory location 01Fh (8 decimal) the

pointer “rolls over” to 00h, and the device continues to output

data for each ACK received.

A STOP condition also acts as a protection of non-volatile

memory. A valid Identification Byte, Address Byte, and total

number of SCL pulses act as a protection of both volatile

and non-volatile registers. During a Write sequence, the

Data Byte is loaded into an internal shift register as it is

received. If the Address Byte is 0, 1, or 8 decimal, the Data

Byte is transferred to the appropriate Wiper Register (WR) or

to the Access Control Register, at the falling edge of the SCL

The byte at address 00001000 bin (8 decimal) determines if

the Data Bytes being read are from volatile or non-volatile

memory. See “Memory Description” on page 9.

S

t

a

r

S

t

a

r

Identification

Byte

Identification

Signals

from the

Master

S

t

o

p

Byte

with

R/W=1

with

R/W=0

A

C

K

A

C

K

Address

Byte

t

Signal at SDA

1 0 1 0

1

0

A

C

K

A

C

K

A

C

K

Signals from the

Slave

Last Read Data

Byte

First Read Data

Byte

FIGURE 18. READ SEQUENCE

FN8212.2

July 18, 2006

11

X95820

Thin Shrink Small Outline Plastic Packages (TSSOP)

M14.173

N

14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC

PACKAGE

INDEX

AREA

0.25(0.010)

M

B M

E

E1

-B-

INCHES

MIN

MILLIMETERS

GAUGE

PLANE

SYMBOL

MAX

0.047

0.006

0.041

0.0118

0.0079

0.199

0.177

MIN

-

MAX

1.20

0.15

1.05

0.30

0.20

5.05

4.50

NOTES

A

A1

A2

b

-

1

2

3

0.002

0.031

0.0075

0.0035

0.195

0.169

0.05

0.80

0.19

0.09

4.95

4.30

-

L

0.25

0.010

-

0.05(0.002)

SEATING PLANE

A

9

-A-

D

c

-

D

3

-C-

α

E1

e

4

A2

e

A1

0.026 BSC

0.65 BSC

-

c

b

0.10(0.004)

E

0.246

0.256

6.25

0.45

6.50

0.75

-

0.10(0.004) M

C

A M B S

L

0.0177

0.0295

6

N

14

7

NOTES:

o

0

8

0

8

-

α

1. These package dimensions are within allowable dimensions of

JEDEC MO-153-AC, Issue E.

Rev. 2 4/06

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm

(0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per

side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable dambar

protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-

sion at maximum material condition. Minimum space between protru-

sion and adjacent lead is 0.07mm (0.0027 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact. (Angles in degrees)

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8212.2

July 18, 2006

12


型号：	X95820_06
厂家：	Intersil
描述：	Dual Digital Controlled Potentiometers 双通道数字电位器电位器
文件：	总12页 (文件大小：1118K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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