X9C503 [INTERSIL]
Digitally Controlled Potentiometer; 数字控制电位器
| 型号： | X9C503 |
| 厂家： | 
Intersil |
| 描述： | Digitally Controlled Potentiometer |
| 文件： | 总10页 (文件大小：235K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X9C102, X9C103, X9C104, X9C503
®
Data Sheet
July 20, 2009
FN8222.3
Digitally Controlled Potentiometer
(XDCP™)
Features
• Solid-State Potentiometer
• Three-Wire Serial Interface
• 100 Wiper Tap Points
The X9C102, X9C103, X9C104, X9C503 are Intersils’
digitally controlled (XDCP) potentiometers. The device
consists of a resistor array, wiper switches, a control section,
and non-volatile memory. The wiper position is controlled by
a three-wire interface.
- Wiper Position Stored in Non-volatile Memory and
Recalled on Power-up
• 99 Resistive Elements
The potentiometer is implemented by a resistor array
composed of 99 resistive elements and a wiper switching
network. Between each element and at either end are tap
points accessible to the wiper terminal. The position of the
wiper element is controlled by the CS, U/D, and INC inputs.
The position of the wiper can be stored in non-volatile
memory and then be recalled upon a subsequent power-up
operation.
- Temperature Compensated
- End-to-End Resistance, ±20%
- Terminal Voltages, ±5V
• Low Power CMOS
- VCC = 5V
- Active Current, 3mA max.
- Standby Current, 750µA max.
The device can be used as a three-terminal potentiometer or
as a two-terminal variable resistor in a wide variety of
applications ranging from control to signal processing to
parameter adjustment.
• High Reliability
- Endurance, 100,000 Data Changes per Bit
- Register Data Retention, 100 years
• X9C102 = 1kΩ
• X9C103 = 10kΩ
• X9C503 = 50kΩ
• X9C104 = 100kΩ
Pinout
X9C102, X9C103, X9C104, X9C503
(8 LD SOIC, 8 LD PDIP)
TOP VIEW
INC
U/D
V
CC
1
2
3
4
8
7
6
5
• Packages
- 8 Ld SOIC
- 8 Ld PDIP
CS
V /R
L
V /R
L
H
H
V
V /R
W W
SS
• Pb-Free Available (RoHS Compliant)
Block Diagram
U/D
INC
CS
7-BIT
UP/DOWN
COUNTER
99
R
V
H
H/
98
97
96
V
(SUPPLY VOLTAGE)
CC
7-BIT
V /R
H
H
UP/DOWN (U/D)
INCREMENT (INC)
NON-VOLATILE
MEMORY
ONE
OF
CONTROL
AND
MEMORY
R
/V
W
W
ONE-
HUNDRED
DECODER
RESISTOR
ARRAY
TRANSFER
GATES
DEVICE
SELECT
(CS)
V /R
L
L
2
1
0
V
(GROUND)
SS
STORE AND
RECALL
CONTROL
CIRCUITRY
GENERAL
V
CC
GND
R /V
L
L
R
/V
W
DETAILED
W
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
1
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006, 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9C102, X9C103, X9C104, X9C503
Ordering Information
PART
NUMBER
PART
MARKING
RTOTAL
(kΩ)
TEMP RANGE
(°C)
PACKAGE
DWG. #
PACKAGE
8 Ld PDIP
X9C102P
X9C102P
X9C102P Z
1
0 to +70
0 to +70
MDP0031
X9C102PZ (Notes 1, 2)
X9C102PI
8 Ld PDIP (Pb-free)
8 Ld PDIP
MDP0031
MDP0031
MDP0031
MDP0027
MDP0027
MDP0027
MDP0027
MDP0031
MDP0031
MDP0031
MDP0031
MDP0027
MDP0027
MDP0027
MDP0027
MDP0031
MDP0031
MDP0031
MDP0031
MDP0027
MDP0027
MDP0027
MDP0027
MDP0031
MDP0031
MDP0031
MDP0027
MDP0027
MDP0027
MDP0027
X9C102P I
X9C102P ZI
X9C102S
-40 to +85
-40 to +85
0 to +70
X9C102PIZ (Notes 1, 2)
X9C102S*, **
8 Ld PDIP (Pb-free)
8 Ld SOIC
X9C102SZ* (Note 1)
X9C102SI*, **
X9C102S Z
X9C102S I
X9C102S ZI
X9C103P
0 to +70
8 Ld SOIC (Pb-free)
8 Ld SOIC
-40 to +85
-40 to +85
0 to +70
X9C102SIZ*, ** (Note 1)
X9C103P
8 Ld SOIC (Pb-free)
8 Ld PDIP
10
X9C103PZ (Notes 1, 2)
X9C103PI
X9C103P Z
X9C103P I
X9C103P ZI
X9C103S
0 to +70
8 Ld PDIP (Pb-free)
8 Ld PDIP
-40 to +85
-40 to +85
0 to +70
X9C103PIZ (Note 1)
X9C103S*, **
8 Ld PDIP (Pb-free)
8 Ld SOIC
X9C103SZ*, ** (Note 1)
X9C103SI*, **
X9C103S Z
X9C103S I
X9C103S ZI
X9C503P
0 to +70
8 Ld SOIC (Pb-free)
8 Ld SOIC
-40 to +85
-40 to +85
0 to +70
X9C103SIZ*, ** (Note 1)
X9C503P
8 Ld SOIC (Pb-free)
8 Ld PDIP
50
X9C503PZ (Notes 1, 2)
X9C503PI
X9C503P Z
X9C503P I
X9C503P ZI
X9C503S
0 to +70
8 Ld PDIP (Pb-free)
8 Ld PDIP
-40 to +85
-40 to +85
0 to +70
X9C503PIZ (Notes 1, 2)
X9C503S*
8 Ld PDIP (Pb-free)
8 Ld SOIC
X9C503SZ* (Note 1)
X9C503SI*, **
X9C503S Z
X9C503S I
X9C503S ZI
X9C104P
0 to +70
8 Ld SOIC (Pb-free)
8 Ld SOIC
-40 to +85
-40 to +85
0 to +70
X9C503SIZ*, ** (Note 1)
X9C104P
8 Ld SOIC (Pb-free)
8 Ld PDIP
100
X9C104PI
X9C104P I
X9C104P ZI
X9C104S
-40 to +85
-40 to +85
0 to +70
8 Ld PDIP
X9C104PIZ (Notes 1, 2)
X9C104S*, **
8 Ld PDIP (Pb-free)
8 Ld SOIC
X9C104SZ*, ** (Note 1)
X9C104SI*, **
X9C104S Z
X9C104S I
X9C104S ZI
0 to +70
8 Ld SOIC (Pb-free)
8 Ld SOIC
-40 to +85
-40 to +85
X9C104SIZ*, ** (Note 1)
8 Ld SOIC (Pb-free)
*Add “T1” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
**Add “T2” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
2. Pb-free PDIPs can be used for through-hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
FN8222.3
July 20, 2009
2
X9C102, X9C103, X9C104, X9C503
Pin Descriptions
PIN
NUMBER
PIN NAME
DESCRIPTION
1
INC
INCREMENT The INC input is negative-edge triggered. Toggling INC will move the wiper and either increment or
decrement the counter in the direction indicated by the logic level on the U/D input.
2
3
U/D
UP/DOWN The U/D input controls the direction of the wiper movement and whether the counter is incremented or
decremented.
VH/RH
VH/RH The high (VH/RH) terminals of the X9C102, X9C103, X9C104, X9C503 are equivalent to the fixed terminals of
a mechanical potentiometer. The minimum voltage is -5V and the maximum is +5V. The terminology of VH/RH and VL/RL
references the relative position of the terminal in relation to wiper movement direction selected by the U/D input and
not the voltage potential on the terminal.
4
5
VSS
VSS
VW/RW
VW/RW VW/RW is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. The
position of the wiper within the array is determined by the control inputs. The wiper terminal series resistance is typically
40Ω.
6
RL/VL
RL/VL The low (VL/RL) terminals of the X9C102, X9C103, X9C104, X9C503 are equivalent to the fixed terminals of a
mechanical potentiometer. The minimum voltage is -5V and the maximum is +5V. The terminology of VH/RH and VL/RL
references the relative position of the terminal in relation to wiper movement direction selected by the U/D input and
not the voltage potential on the terminal.
7
8
CS
CS The device is selected when the CS input is LOW. The current counter value is stored in non-volatile memory when
CS is returned HIGH while the INC input is also HIGH. After the store operation is complete the X9C102, X9C103,
X9C104, X9C503 device will be placed in the low power standby mode until the device is selected once again.
VCC
VCC
FN8222.3
July 20, 2009
3
X9C102, X9C103, X9C104, X9C503
Absolute Maximum Ratings
Thermal Information
Voltage on CS, INC, U/D and VCC with Respect to VSS . -1V to +7V
Voltage on VH/RH and VL/RL Referenced to VSS. . . . . . . -8V to +8V
ΔV = |VH/RH - VL/RL|
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
X9C102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4V
X9C103, X9C104, and X9C503 . . . . . . . . . . . . . . . . . . . . . . . .10V
W (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8.8mA
Power Rating
*Pb-free PDIPs can be used for through-hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
I
X9C102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16mW
X9C103 X0C104, and X9C503 . . . . . . . . . . . . . . . . . . . . . .10mW
Recommended Operating Conditions
Commercial Temperature Range. . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial Temperature Range . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage Range (VCC) . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
Electrical Specifications Over recommended operating conditions unless otherwise stated.
LIMITS
TYP
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
MAX
UNIT
POTENTIOMETER CHARACTERISTICS
RTOTAL
VVH/RH
VVL/RL
IW
End-to-End Resistance Variation
-20
-5
+20
+5
%
VH Terminal Voltage
VL Terminal Voltage
Wiper Current
V
-5
+5
V
mA
-4.4
4.4
100
RW
Wiper Resistance
Wiper Current = ±1mA
Ref 1kHz
40
-120
20
Ω
Resistor Noise (Note 7)
Charge Pump Noise (Note 7)
Resolution
dBV
@ 850kHz
mVRMS
%
1
Absolute Linearity (Note 3)
Relative Linearity (Note 4)
VW(n)(actual) - VW(n)(EXPECTED)
-1
+1
MI (Note 5)
V
W(n + 1)(ACTUAL) - [VW(n) + MI
]
-0.2
+0.2 MI (Note 5)
ppm/°C
R
TOTAL Temperature Coefficient
TOTAL Temperature Coefficient
X9C103, X9C503, X9C104
X9C102
±300 (Note 7)
±600 (Note 7)
±20
R
ppm/°C
Ratiometric Temperature Coefficient
Potentiometer Capacitances
ppm/°C
CH/CL/CW
(Note 7)
See “Circuit #3 SPICE Macro
Model” on page 5.
10/10/25
pF
DC OPERATING CHARACTERISTICS
ICC
VCC Active Current
CS = V , U/D = VIL or VIH and
IL
1
3
mA
µA
INC = 0.4V to 2.4V at Max tCYC
ISB
Standby Supply Current
CS = VCC - 0.3V, U/D and
INC = VSS or VCC - 0.3V
200
750
±10
ILI
CS, INC, U/D Input Leakage Current
CS, INC, U/D input HIGH Voltage
CS, INC, U/D input LOW Voltage
CS, INC, U/D Input Capacitance (Note 7)
VIN = VSS to VCC
µA
V
VIH
VIL
CIN
2
0.8
V
VCC = 5V, VIN = VSS, TA = +25°C,
f = 1MHz
10
pF
FN8222.3
July 20, 2009
4
X9C102, X9C103, X9C104, X9C503
Electrical Specifications Over recommended operating conditions unless otherwise stated. (Continued)
LIMITS
TYP
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
MAX
UNIT
AC OPERATION CHARACTERISTICS
tCl
tlD
CS to INC Setup
100
100
2.9
1
ns
ns
INC HIGH to U/D Change
U/D to INC Setup
tDI
µs
tlL
INC LOW Period
µs
tlH
INC HIGH Period
1
µs
tlC
INC Inactive to CS Inactive
CS Deselect Time (STORE)
CS Deselect Time (NO STORE)
INC to VW/RW Change
INC Cycle Time
1
µs
tCPH
tCPH
20
100
ms
ns
(5)
tIW
100
500
µs
tCYC
tCYC
tR, tF
tPU
2
µs
INC Input Rise and Fall Time
Power-up to Wiper Stable (Note 7)
500
50
µs
µs
V
CC Power-up Rate (Note 7)
0.2
V/ms
NOTES:
3. Absolute linearity is utilized to determine actual wiper voltage vs expected voltage = [VW(n)(actual) - VW(n)(expected )] = ±1 MI Maximum.
4. Relative linearity is a measure of the error in step size between taps = VW(n + 1) - [VW(n) + MI] = +0.2 MI.
5. 1 MI = Minimum Increment = RTOT/99.
6. Typical values are for TA = +25°C and nominal supply voltage.
7. This parameter is not 100% tested.
Test Circuit #1
Test Circuit #2
Circuit #3 SPICE Macro Model
V /R
V /R
R
H
H
H
R
TOTAL
R
R
H
L
TEST POINT
C
L
C
C
W
L
V
10pF
S
TEST POINT
V /R
V
/R
w
W
w
W
FORCE
CURRENT
10pF
25pF
V /R
L
V /R
L
L
L
R
W
Power-up and Down Requirements
Endurance and Data Retention
At all times, voltages on the potentiometer pins must be less
than ±VCC. The recall of the wiper position from non-volatile
memory is not in effect until the VCC supply reaches its final
value. The VCC ramp rate specification is always in effect.
PARAMETER
MIN
UNIT
Medium Endurance
100,000
Data changes per bit
per register
Data Retention
100
years
AC Conditions of Test
Input Pulse Levels
0V to 3V
10ns
Input Rise and Fall Times
Input Reference Levels
1.5V
FN8222.3
July 20, 2009
5
X9C102, X9C103, X9C104, X9C503
AC Timing Diagram
CS
t
CYC
t
t
t
CPH
CI
t
t
IH
IC
IL
90%
90%
INC
U/D
10%
t
t
t
t
R
ID
DI
F
t
IW
MI (NOTE)
V
W
NOTE: MI REFERS TO THE MINIMUM INCREMENTAL CHANGE IN THE V OUTPUT DUE TO A CHANGE IN THE WIPER POSITION.
W
Pin Descriptions
Principles of Operation
There are three sections of the X9C102, X9C103, ISL9C104
and ISL9C503: the input control, counter and decode section;
the non-volatile memory; and the resistor array. The input
control section operates just like an up/down counter. The
output of this counter is decoded to turn on a single electronic
switch connecting a point on the resistor array to the wiper
output. Under the proper conditions, the contents of the
counter can be stored in non-volatile memory and retained for
future use. The resistor array is comprised of 99 individual
resistors connected in series. At either end of the array and
between each resistor is an electronic switch that transfers the
potential at that point to the wiper.
R /V and R /V
L
L
H
H
The high (V /R ) and low (V /R ) terminals of the
H
H
L
L
ISLX9C102, X9C103, X9C104, X9C503 are equivalent to
the fixed terminals of a mechanical potentiometer. The
minimum voltage is -5V and the maximum is +5V. The
terminology of V /R and V /R references the relative
H
H
L
L
position of the terminal in relation to wiper movement
direction selected by the U/D input and not the voltage
potential on the terminal.
RW/V
W
V /R is the wiper terminal, and is equivalent to the
W
W
movable terminal of a mechanical potentiometer. The
position of the wiper within the array is determined by the
control inputs. The wiper terminal series resistance is typically
40Ω.
The wiper, when at either fixed terminal, acts like its
mechanical equivalent and does not move beyond the last
position. That is, the counter does not wrap around when
clocked to either extreme.
Up/Down (U/D)
The electronic switches on the device operate in a
“make-before-break” mode when the wiper changes tap
positions. If the wiper is moved several positions, multiple
taps are connected to the wiper for tIW (INC to VW/RW
change). The RTOTAL value for the device can temporarily be
reduced by a significant amount if the wiper is moved
several positions.
The U/D input controls the direction of the wiper movement
and whether the counter is incremented or decremented.
Increment (INC)
The INC input is negative-edge triggered. Toggling INC will
move the wiper and either increment or decrement the
counter in the direction indicated by the logic level on the
U/D input.
When the device is powered-down, the last wiper position
stored will be maintained in the non-volatile memory. When
power is restored, the contents of the memory are recalled
and the wiper is reset to the value last stored.
Chip Select (CS)
The device is selected when the CS input is LOW. The
current counter value is stored in non-volatile memory when
CS is returned HIGH while the INC input is also HIGH. After
the store operation is complete the ISLX9C102, X9C103,
X9C104, X9C503 device will be placed in the low power
standby mode until the device is selected once again.
The internal charge pump allows a wide range of voltages
(from -5V to 5V) applied to XDCP terminals yet given a
convenience of single power supply. The typical charge
pump noise of 20mV at 850kHz should be taken in
consideration when designing an application circuit.
FN8222.3
July 20, 2009
6
X9C102, X9C103, X9C104, X9C503
Mode Selection
Instructions and Programming
The INC, U/D and CS inputs control the movement of the
wiper along the resistor array. With CS set LOW, the device is
selected and enabled to respond to the U/D and INC inputs.
HIGH to LOW transitions on INC will increment or decrement
(depending on the state of the U/D input) a 7-bit counter. The
output of this counter is decoded to select one of one-hundred
wiper positions along the resistive array.
CS
INC
U/D
MODE
L
H
Wiper Up
L
L
Wiper Down
H
X
Store Wiper Position
H
X
L
X
X
Standby Current
No Store, Return to Standby
The value of the counter is stored in non-volatile memory
whenever CS transitions HIGH while the INC input is also
HIGH.
L
L
H
L
Wiper Up (not recommended)
Wiper Down (not recommended)
The system may select the X9Cxxx, move the wiper and
deselect the device without having to store the latest wiper
position in non-volatile memory. After the wiper movement is
performed as previously described and once the new
position is reached, the system must keep INC LOW while
taking CS HIGH. The new wiper position will be maintained
until changed by the system or until a power-down/up cycle
recalled the previously stored data.
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
This procedure allows the system to always power-up to a
pre-set value stored in non-volatile memory; then during
system operation, minor adjustments could be made. The
adjustments might be based on user preference, i.e.: system
parameter changes due to temperature drift, etc.
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
The state of U/D may be changed while CS remains LOW.
This allows the host system to enable the device and then
move the wiper up and down until the proper trim is attained.
Performance Characteristics
Contact the factory for more information.
Applications Information
Electronic digitally controlled (XCDP) potentiometers provide
three powerful application advantages:
1. The variability and reliability of a solid-state
potentiometer.
2. The flexibility of computer-based digital controls.
3. The retentivity of non-volatile memory used for the
storage of multiple potentiometer settings or data.
FN8222.3
July 20, 2009
7
X9C102, X9C103, X9C104, X9C503
Basic Configurations of Electronic Potentiometers
V
R
V
R
V /R
H
H
V
/R
W
W
V /R
L
L
I
THREE TERMINAL POTENTIOMETER;
VARIABLE VOLTAGE DIVIDER
TWO TERMINAL VARIABLE RESISTOR;
VARIABLE CURRENT
Basic Circuits
+V
+V
+V
+5V
R
1
LM308A
V
+V
+
–
S
+5V
V
O
V
W
OP-07
+
–
X
V
-5V
REF
V
/R
W
V
W
OUT
R
2
-5V
R
1
V
/R
W
W
V
= V /R
W W
OUT
V
= (1+R /R )V
2 1 S
O
(a)
(b)
BUFFERED REFERENCE VOLTAGE
CASCADING TECHNIQUES
NONINVERTING AMPLIFIER
R
R
2
1
LT311A
–
V
V
V (REG)
O
317
S
IN
V
S
V
O
100kΩ
+
R
1
–
+
V
O
I
adj
TL072
R
10kΩ
10kΩ
2
R
R
2
1
10kΩ
V
V
= {R /(R + R )} V (MAX)
1 1 2 O
= {R /(R + R )} V (MIN)
UL
LL
V
(REG) = 1.25V (1+R /R )+I
R
1
1
2
O
O
2
1
adj 2
+12V
-12V
(FOR ADDITIONAL CIRCUITS SEE AN1145)
COMPARATOR WITH HYSTERESIS
VOLTAGE REGULATOR
OFFSET VOLTAGE ADJUSTMENT
FN8222.3
July 20, 2009
8
X9C102, X9C103, X9C104, X9C503
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M
C A B
e
H
C
A2
A1
GAUGE
PLANE
SEATING
PLANE
0.010
L
4° ±4°
0.004 C
b
0.010 M
C
A
B
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
SO24
(SOL-24)
SO28
(SOL-28)
SYMBOL
SO-8
0.068
0.006
0.057
0.017
0.009
0.193
0.236
0.154
0.050
0.025
0.041
0.013
8
SO-14
0.068
0.006
0.057
0.017
0.009
0.341
0.236
0.154
0.050
0.025
0.041
0.013
14
(SOL-20)
0.104
0.007
0.092
0.017
0.011
0.504
0.406
0.295
0.050
0.030
0.056
0.020
20
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.068
0.006
0.057
0.017
0.009
0.390
0.236
0.154
0.050
0.025
0.041
0.013
16
0.104
0.007
0.092
0.017
0.011
0.406
0.406
0.295
0.050
0.030
0.056
0.020
16
0.104
0.007
0.092
0.017
0.011
0.606
0.406
0.295
0.050
0.030
0.056
0.020
24
0.104
0.007
0.092
0.017
0.011
0.704
0.406
0.295
0.050
0.030
0.056
0.020
28
-
±0.003
±0.002
±0.003
±0.001
±0.004
±0.008
±0.004
Basic
-
-
-
c
-
D
1, 3
E
-
E1
e
2, 3
-
L
±0.009
Basic
-
L1
h
-
Reference
Reference
-
N
-
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
FN8222.3
July 20, 2009
9
X9C102, X9C103, X9C104, X9C503
Plastic Dual-In-Line Packages (PDIP)
E
N
1
D
PIN #1
INDEX
A2
A
E1
SEATING
PLANE
L
c
A1
NOTE 5
2
N/2
eA
eB
e
b
b2
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE
INCHES
SYMBOL
PDIP8
0.210
0.015
0.130
0.018
0.060
0.010
0.375
0.310
0.250
0.100
0.300
0.345
0.125
8
PDIP14
0.210
0.015
0.130
0.018
0.060
0.010
0.750
0.310
0.250
0.100
0.300
0.345
0.125
14
PDIP16
0.210
0.015
0.130
0.018
0.060
0.010
0.750
0.310
0.250
0.100
0.300
0.345
0.125
16
PDIP18
PDIP20
0.210
0.015
0.130
0.018
0.060
0.010
1.020
0.310
0.250
0.100
0.300
0.345
0.125
20
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.210
0.015
0.130
0.018
0.060
0.010
0.890
0.310
0.250
0.100
0.300
0.345
0.125
18
MIN
±0.005
±0.002
b2
c
+0.010/-0.015
+0.004/-0.002
±0.010
D
1
2
E
+0.015/-0.010
±0.005
E1
e
Basic
eA
eB
L
Basic
±0.025
±0.010
N
Reference
Rev. C 2/07
NOTES:
1. Plastic or metal protrusions of 0.010” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.
4. Dimension eB is measured with the lead tips unconstrained.
5. 8 and 16 lead packages have half end-leads as shown.
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FN8222.3
July 20, 2009
10
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