ZL2008ALBFT_技术文档

NOT RECOMMENDED FOR NEW DESIGNS

RECOMMENDED REPLACEMENT PART

ZL6105

Digital DC/DC Controller with Drivers and Pin-Strap

Current Sharing

ZL2008

Features

The ZL2008 is a digital power controller with integrated

MOSFET drivers. Current sharing allows multiple devices to be

connected in parallel to source loads with very high current

demands. Adaptive performance optimization algorithms

improve power conversion efficiency. Zilker Labs Digital-DC™

technology enables a blend of power conversion performance

and power management features.

Power Conversion

• Efficient synchronous buck controller

• Adaptive light load efficiency optimization

• 3V to 14V input range

• 0.54V to 5.5V output range (with margin)

• POLA and DOSA voltage trim modes

• ±1% output voltage accuracy

The ZL2008 is designed to be a flexible building block for DC

power and can be easily adapted to designs ranging from a

single-phase power supply operating from a 3.3V input to a

multi-phase supply operating from a 12V input. The ZL2008

eliminates the need for complicated power supply managers

as well as numerous external discrete components.

• Internal 3A MOSFET drivers

• Fast load transient response

• Current sharing and phase interleaving

• Snapshot™ parameter capture

• RoHS compliant (6mmx6mm) QFN package

Key operating features can be configured by pin-straps,

including compensation, current sharing and output voltage.

The ZL2008 uses the I²C/SMBus™ with PMBus™ protocol for

communication with a host controller and the Digital-DC bus

for communication between Zilker Labs devices.

Power Management

• Digital soft-start/stop

• Precision delay and ramp-up

Applications

• Servers/storage equipment

• Telecom/datacom equipment

• Power supply modules

• Power good/enable

• Voltage tracking, sequencing and margining

• Voltage, current and temperature monitoring

• I²C/SMBus interface, PMBus compatible

• Output voltage and current protection

• Internal non-volatile memory (NVM)

Block Diagram

Efficiency vs Load Current

100

EN PG

CFG UVLO V25 VR VDD

DLY FC ILIM

V_OUT= 3.3V

V_OUT= 1.5V

95

90

85

80

75

70

65

60

55

V

SS

LDO

VTRK

POWER

MANAGEMENT

MGN

BST

GH

SYNC

DDC

DRIVER

SW

GL

NON-

VOLATILE

VSEN+

VSEN-

PWM

CONTROLLER

MEMORY

CURRENT

SENSE

ISENA

ISENB

V_IN= 12V

f_SW= 400kHz

SCL

SDA

SALRT

TEMP

SENSOR

MONITOR

ADC

I²C

SA

Circuit of Figure 4

50

0

4

10

14 16 18 20

2

6

8

12

Load Current (A)

FIGURE 2. EFFICIENCY vs LOAD CURRENT

XTEMP

PGND SGND DGND

FIGURE 1. BLOCK DIAGRAM

April 29, 2011

FN6859.4

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

1

ZL2008

Table of Contents

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Thermal Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Typical Application Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

ZL2008 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Digital-DC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Power Conversion Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Power Management Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Multi-mode Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Power Conversion Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Internal Bias Regulators and Input Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

High-side Driver Boost Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Start-up Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Soft-start Delay and Ramp Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Power Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Switching Frequency and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Power Train Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Current Limit Threshold Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Non-linear Response (NLR) Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Efficiency Optimized Driver Dead-time Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Adaptive Diode Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Adaptive Frequency Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Power Management Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Input Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Output Overvoltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Output Pre-Bias Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Output Overcurrent Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Thermal Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Voltage Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Voltage Margining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

I2C/SMBus Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

I2C/SMBus Device Address Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Digital-DC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Phase Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Output Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Fault Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Temperature Monitoring Using the XTEMP Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Active Current Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Phase Adding/Dropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Monitoring via I2C/SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Snapshot Parameter Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Non-Volatile Memory and Device Security Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Pin-strap Current Sharing Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

SMBus Address (SA0, SA1 Pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Current Share Pin-Straps (CFG0, CFG2 Pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

FN6859.4

April 29, 2011

2

ZL2008

SYNC Clock (CFG1 Pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Soft-start (SS Pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Phase Enable (PH_EN Pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

MFR_CONFIG Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

VOUT_DROOP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Current Sharing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Related Tools and Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

FN6859.4

April 29, 2011

3

ZL2008

Absolute Maximum Ratings

Thermal Information

DC Supply Voltage for VDD Pin . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 17V

MOSFET Drive Reference for VR Pin. . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V

2.5V Logic Reference for V25 Pin . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 3V

Logic I/O Voltage for CFG(0, 1 ,2), DDC, EN, FC(0,1),

ILIM, MGN, PG, PH_EN, SA(0, 1), SALRT, SCL,

SDA, SS, SYNC, UVLO, V(0, 1) Pins . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V

Analog Input Voltages for ISENB, VSEN, VTRK,

Thermal Resistance (Typical)

36 Ld QFN (Notes 2, 3) . . . . . . . . . . . . . . . .

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

θ

_JA(°C/W)

θ

_JC(°C/W)

5

35

XTEMP Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V

Analog Input Voltages for ISENA PIn . . . . . . . . . . . . . . . . . . . . -1.5V to 6.5V

High Side Supply Voltage for BST Pin . . . . . . . . . . . . . . . . . . . . -0.3V to 30V

Boost to Switch Voltage for BST -SW Pins . . . . . . . . . . . . . . . . . . -0.3V to 8V

High Side Drive Voltage for GH Pin. . . . . . . . . . . .(V_SW-0.3V) to (V_BST+0.3V)

Low Side Drive Voltage for GL Pin . . . . . . . . . . . (PGND-0.3V) to (VR+0.3V)

Switch Node Continuous for SW Pin . . . . . . . . . . . . . . .(PGND-0.3V) to 30V

Switch Node Transient (<100ns) for SW Pin. . . . . . . . . . (PGND-5V) to 30V

Ground Differential for DGND – SGND, PGND - SGND Pins . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V

ESD Rating

Recommended Operating Conditions

Input Supply Voltage Range, V_DD(See Figure 9)

VDD tied to VR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0V to 5.5V

VR floating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 14V

Output Voltage Range, V_OUT(Note 4) . . . . . . . . . . . . . . . . . . . . 0.54V to 5.5V

Operating Junction Temperature Range, T_J. . . . . . . . . . . . . . . . . . . -40°C to +125°C

Input Voltage

V

_IN, Rise Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5ms minimum

_INRamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Monotonic

Human Body Model (Note 1, Tested per JESD22-A114E). . . . . . . . . . . . . . . . .2kV

Machine Model (Tested per JESD22-A115-A). . . . . . . . . . . . . . . . . 500V

Latch Up (Tested per JESD78). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

1. BST, SW pins rated at 1.5kV.

2. θ_JAis measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech

Brief TB379.

3. For θ_JC, the “case temp” location is the center of the exposed metal pad on the package underside.

4. Includes margin limits.

Electrical Specifications V_DD= 12V, T_A= -40°C to +85°C unless otherwise noted. Typical values are at T_A= +25°C. Boldface limits apply

over the operating temperature range, -40°C to +85°C.

MIN

MAX

PARAMETER

Input and Supply Characteristics

I_DDSupply Current at f_SW= 200kHz

I_DDSupply Current at f_SW= 1.4MHz

I_DDSShutdown Current

CONDITIONS

(Note 14)

TYP

(Note 14)

UNIT

GH, GL no load

MISC_CONFIG[7] = 1

EN = 0V

–

16

25

30

50

9

mA

6.5

No I²C/SMBus activity

V_DD> 6V, I_VR< 20mA

V_R> 3V, I_V25< 20mA

Vr Reference Output Voltage

4.5

5.2

2.5

5.5

V

V25 Reference Output Voltage

Output Characteristics

2.25

2.75

Output Voltage Adjustment Range (Note 5)

Output Voltage Set-point Resolution

V

_IN> V_OUT

0.6

–

5.0

–

V

Set using resistors

10

mV

Set using I²C/SMBus

–

±0.025

–

% FS

(Note 6)

Output Voltage Accuracy (Note 7)

Vsen Input Bias Current

Includes line, load, temp

VSEN = 5.5V

-1

–

110

–

1

%

200

100

µA

mV

Current Sense Differential Input

Voltage (Ground Referenced)

V_ISENA-V_ISENB

-100

Current Sense Differential Input Voltage (V_out

Referenced, V_out< 4.0V)

V_ISENA-V_ISENB

-50

–

50

mV

µA

Current Sense Input Bias Current

Ground referenced

-100

100

FN6859.4

April 29, 2011

4

ZL2008

Electrical Specifications V_DD= 12V, T_A= -40°C to +85°C unless otherwise noted. Typical values are at T_A= +25°C. Boldface limits apply

over the operating temperature range, -40°C to +85°C. (Continued)

MIN

MAX

PARAMETER

CONDITIONS

(Note 14)

TYP

(Note 14)

UNIT

µA

ms

s

Current Sense Input Bias Current

(V_outReferenced, V_out< 4.0V)

ISENA

ISENB

-1

-100

2

–

1

100

30

500

-

–

Soft-start Delay Duration Range

(Note 8)

Set using SS pin or resistor

Set using I²C/SMBus

0.002

-

–

Soft-start Delay Duration Accuracy

Turn-on delay (precise mode)

(Notes 8, 9, 10)

±0.25

ms

Turn-on delay (normal mode) (Note 10)

Turn-off delay (Note 10)

Set using SS pin or resistor

Set using I²C

-

-0.25/+4

-

ms

µs

-

-0.25/+4

Soft-start Ramp Duration Range

2

0

–

20

200

–

Soft-start Ramp Duration Accuracy

Logic Input/Output Characteristics

Logic Input Leakage Current

Logic Input Low, V_IL

100

EN, PG, SCL, SDA, SALRT pins

Multi-mode logic pins

-250

–

250

0.8

–

nA

V

Logic Input OPEN (N/C)

–

1.4

–

V

Logic Input High, V_IH

2.0

–

V

Logic Output Low, V_OL

I_OL≤ 4mA

I_OH≥ -2mA

–

0.4

–

V

Logic Output High, V_OH

2.25

–

V

Oscillator and Switching Characteristics

Switching Frequency Range

Switching Frequency Set-point Accuracy

Maximum Pwm Duty Cycle

Minimum Sync Pulse Width

Input Clock Frequency Drift Tolerance

Gate Drivers

200

-5

–

1400

5

kHz

%

Predefined settings (See Table 11)

Factory default

95

–

%

150

-13

–

ns

%

External clock source

13

High-side driver voltage (V_BST-V_SW

)

–

2

4.5

3

–

V

High-side Driver Peak Gate Drive

Current (Pull-down)

(V_BST-V_SW) = 4.5V

A

High-side Driver Pull-up Resistance

High-side Driver Pull-down Resistance

(V_BST-V_SW) = 4.5V, (V_BST-V_GH) = 50mV

(V_BST-V_SW) = 4.5V, (V_GH-V_SW) = 50mV

V_R= 5V

–

0.8

0.5

2.5

2

–

Ω

A

Low-side Driver Peak Gate

Drive Current (Pull-up)

Low-side Driver Peak Gate

Drive Current (Pull-down)

V_R= 5V

–

1.8

–

A

Low-side Driver Pull-up Resistance

Low-side Driver Pull-down Resistance

Switching Timing

V_R= 5V, (V_R-V_GL) = 50mV

–

1.2

0.5

2

Ω

V_R= 5V, (V_GL-PGND) = 50mV

(V_BST-V_SW) = 4.5V, C_LOAD= 2.2nF

V_R= 5V, C_LOAD= 2.2nF

–

5

20

ns

Gh Rise and Fall Time

Gl Rise and Fall Time

Tracking

VTRK Input Bias Current

VTRK Tracking Ramp Accuracy

VTRK Regulation Accuracy

VTRK = 5.5V

–

-100

-1

110

–

200

+ 100

1

µA

mV

%

100% Tracking, V_OUT-VTRK

–

FN6859.4

April 29, 2011

5

ZL2008

Electrical Specifications V_DD= 12V, T_A= -40°C to +85°C unless otherwise noted. Typical values are at T_A= +25°C. Boldface limits apply

over the operating temperature range, -40°C to +85°C. (Continued)

MIN

MAX

PARAMETER

Fault Protection Characteristics

UVLO Threshold Range

CONDITIONS

(Note 14)

TYP

(Note 14)

UNIT

Configurable via I²C/SMBus

2.85

-150

–

16

150

–

V

mV

UVLO Set-point Accuracy

UVLO Hysteresis

Factory default

3

%

Configurable via I²C/SMBus

0

–

100

2.5

–

%

UVLO Delay

–

µs

Power Good V_OUTThreshold

Power Good V_OUTHysteresis

Power Good Delay

Factory default

–

90

5

% V_OUT

%

Factory default

–

Using pin-strap or resistor (Note 11)

Configurable via I²C/SMBus

Factory default

0

–

200

500

–

ms

0

–

s

VSEN Undervoltage Threshold

VSEN Overvoltage Threshold

VSEN Undervoltage Hysteresis

–

85

–

% V_OUT

µs

Configurable via I²C/SMBus

Factory default

0

110

–

115

–

Configurable via I²C/SMBus

0

115

–

5

VSEN Undervoltage/Overvoltage

Fault Response Time

Factory default

–

16

–

Configurable via I²C/SMBus

5

60

–

µs

Current Limit Set-point Accuracy

(V_OUTReferenced)

–

±10

% FS

(Note 12)

Current Limit Set-point Accuracy

(Ground Referenced)

–

1

±10

5

–

% FS

(Note 12)

Current Limit Protection Delay

Factory default

t_SW

(Note 13)

Configurable via I²C/SMBus

–

32

t_SW

(Note 13)

Temperature Compensation of

Factory default

4400

ppm/°C

Current Limit Protection Threshold

Configurable via I²C/SMBus

Factory default

100

–

12700

Thermal Protection Threshold

(Junction Temperature)

125

–

125

–

°C

Configurable via I²C/SMBus

-40

–

Thermal Protection Hysteresis

15

NOTES:

5. Does not include margin limits.

6. Percentage of Full Scale (FS) with temperature compensation applied.

7. V_OUTmeasured at the termination of the VSEN+ and VSEN-sense points.

8. The device requires a delay period following an enable signal and prior to ramping its output. Precise timing mode limits this delay period to approx

2ms, where in normal mode it may vary up to 4ms. Current Share member minimum delay is 5ms. Current share reference must be 10ms greater

than member delay.

9. Precise ramp timing mode is only valid when using EN pin to enable the device rather than PMBus enable.

10. The devices may require up to a 4ms delay following the assertion of the enable signal (normal mode) or following the de-assertion of the enable

signal.

11. Factory default Power Good delay is set to the same value as the soft-start ramp time.

12. Percentage of Full Scale (FS) with temperature compensation applied

13. t_SW= 1/f_SW, where f_SWis the switching frequency.

14. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

15. Nominal capacitance of logic pins is 5pF.

FN6859.4

April 29, 2011

6

ZL2008

Pin Configuration

ZL2008

(36 LD QFN)

TOP VIEW

1

2

3

4

5

6

7

8

9

27

26

25

DGND

SYNC

SA0

SA1

ILIM

CFG0

SCL

SDA

VDD

BST

GH

36-Pin QFN

6 x 6 mm

²⁴SW

23

PGND

GL

VR

ISENA

ISENB

22

21

20

19

Exposed Paddle

Connect to SGND

SALRT

Pin Descriptions

Type

1

Label

(Note 16)

Description

DGND

PWR

Digital ground. Common return for digital signals. Connect to low impedance ground plane.

2

SYNC

I/O, M

(Note 17)

Clock synchronization input. Used to set switching frequency of internal clock or for synchronization to external

frequency reference.

3

4

5

SA0

SA1

ILIM

I, M

Serial address select pins. Used to assign unique SMBus address to each IC or to enable certain management

features.

Current limit select. Sets the overcurrent threshold voltage for ISENA and ISENB.

6

7

CFG0

SCL

I, M

I/O

O

Configuration pin. Used to setup current sharing and non-linear response.

Serial clock. Connect to external host and/or to other ZL devices.

Serial data. Connect to external host and/or to other ZL devices.

Serial alert. Connect to external host if desired.

8

SDA

SALRT

FC0

9

10

11

12

13

14

I

Loop compensation configuration pins.

FC1

V0

I

Output voltage selection pins. Used to set V_OUTset-point and V_OUTmax.

V1

UVLO

I, M

Undervoltage lockout selection. Sets the minimum value for V_DDvoltage to enable V_OUT.

15

SS

Soft-start pin. Sets the output voltage ramp time during turn-on and turn-off. Sets the delay from when EN is

asserted until the output voltage starts to ramp.

16

17

18

19

20

VTRK

VSEN+

VSEN-

ISENB

ISENA

I

Tracking sense input. Used to track an external voltage source.

Output voltage feedback. Connect to output regulation point.

Output voltage feedback. Connect to load return or ground regulation point.

Differential voltage input for current limit.

Differential voltage input for current limit. High voltage tolerant.

FN6859.4

April 29, 2011

7

ZL2008

Pin Descriptions(Continued)

Type

21

22

23

24

25

26

27

Label

VR

(Note 16)

PWR

O

Description

Internal 5V reference used to power internal drivers.

Low side FET gate drive.

GL

PGND

SW

PWR

O

Power ground. Connect to low impedance ground plane.

Drive train switch node.

GH

High-side FET gate drive.

BST

PWR

High-side drive boost voltage.

Supply voltage.

VDD

(Note 18)

28

29

V25

PWR

I

Internal 2.5V reference used to power internal circuitry.

XTEMP

External temperature sensor input. Connect to external 2N3904 diode connected transistor.

30

31

32

33

DDC

MGN

CFG1

EN

I/O

Digital-DC Bus. (Open Drain) Interoperability between Zilker Labs devices.

Signal that enables margining of output voltage.

I

I, M

I

Configuration pin. Used to setup clock synchronization and sequencing.

Enable input (active high). Pull-up to enable PWM switching and pull-down to disable PWM switching.

34

35

PH_EN

CFG2

PG

I

Phase enable input (active high). Pull-up to enable phase and pull-down to disable phase for current sharing.

Configuration pin. Sets the phase offset (single-phase) or current sharing group position (multi-phase).

Power good output.

I, M

O

36

ePad

SGND

PWR

Exposed thermal pad. Common return for analog signals; internal connection to SGND. Connect to low

impedance ground plane.

NOTES:

16. I = Input, O = Output, PWR = Power or Ground. M = Multi-mode pins. Please refer to “Multi-mode Pins” on page 12.

17. The SYNC pin can be used as a logic pin, a clock input or a clock output.

18. V_DDis measured internally and the value is used to modify the PWM loop gain.

FN6859.4

April 29, 2011

8

ZL2008

Typical Application Circuit

The following application circuit represents a typical implementation of the ZL2008. For PMBus operation, it is recommended to tie the

enable pin (EN) to SGND.

V_IN12V

F.B.¹

ENABLE

C

IN

4.7 µF

25 V

3 x 10 µF

25 V

PHASE ENABLE

DDC Bus ³

10 µF

4 V

C_V25

POWER GOOD OUTPUT

QH

DB

BAT54

1 µF

16 V

1

2

3

4

5

6

7

8

9

DGND

VDD 27

BST 26

V25

CB

SYNC

SA0

GH

V_OUT

25

L_OUT

SA1

SW 24

2.2 µH

C_OUT

ILIM

PGND 23

ZL2008

CFG0

SCL

GL

22

I²C/SMBus ²

VR 21

2 x 47 µF

6.3 V

470 µF 2*220 µF

SDA

ISENA 20

2.5 V

6.3 V

SALRT

ISENB

POS-CAP

19

100 m

QL

EPAD

C_VR

4.7 µF 6.3 V

RTN

Ground unification

Notes:

1. Ferrite bead is optional for input noise suppression

2. The I²C/SMBus requires pull-up resistors. Please refer to the I C/SMBus specifications for more details.

3. The DDC bus requires a pull-up resistor. The resistance will vary based on the capacitive loading of the bus(and on the number of devices

2

connected). The 10 kΩ default value, assuming a maximum of100 pF per device, provides the necessary 1 µs pull-up rise time. Please refer to the

DDC Bus section for more details.

FIGURE 3. 12V to 1.8V/16A Application Circuit

FN6859.4

April 29, 2011

9

ZL2008

Its unique PWM loop utilizes an ideal mix of analog and digital

ZL2008 Overview

Digital-DC Architecture

The ZL2008 is an innovative mixed-signal power conversion and

power management IC based on Zilker Labs patented Digital-DC

technology that provides an integrated, high performance step-

down converter for a wide variety of power supply applications.

blocks to enable precise control of the entire power conversion

process with no software required, resulting in a very flexible

device that is also very easy to use. An extensive set of power

management functions are fully integrated and can be

configured using simple pin connections. The user configuration

can be saved in an internal non-volatile memory (NVM).

Additionally, all functions can be configured and monitored via

the SMBus hardware interface using standard PMBus

commands, allowing ultimate flexibility.

Today’s embedded power systems are typically designed for

optimal efficiency at maximum load, reducing the peak thermal

stress by limiting the total thermal dissipation inside the system.

Unfortunately, many of these systems are often operated at load

levels far below the peak where the power system has been

optimized, resulting in reduced efficiency. While this may not

cause thermal stress to occur, it does contribute to higher

electricity usage and results in higher overall system operating

costs.

Once enabled, the ZL2008 is immediately ready to regulate

power and perform power management tasks with no

programming required. Advanced configuration options and real-

time configuration changes are available via the I²C/SMBus

interface if desired and continuous monitoring of multiple

operating parameters is possible with minimal interaction from a

host controller. Integrated sub-regulation circuitry enables single

supply operation from any supply between 3V and 14V with no

secondary bias supplies needed.

Zilker Labs’ efficiency-adaptive ZL2008 DC/DC controller helps

mitigate this scenario by enabling the power converter to

automatically change their operating state to increase efficiency

and overall performance with little or no user interaction needed.

Input Voltage Bus

>

PG

MGN

CFG(0,1,2)

ILIM

V(0,1)

EN

SS

FC(0,1)

NVM

VDD

VR

VTRK

Power Management

BST

MOSFET

Drivers

SYNC

GEN

Digital

Compensator

D-PWM

SW

V_OUT

NLR

SYNC

DDC

PLL

VSEN

-

ADC

Σ

+

ISENB

ISENA

REFCN

DAC

VDD

Voltage

Sensor

VSEN+

VSEN-

MUX

SALRT

SDA

ADC

XTEMP

I²C

Communication

SCL

SA(0,1)

TEMP

Sensor

FIGURE 4. ZL2008 Block Diagram

FN6859.4

April 29, 2011

10

ZL2008

Typically, buck converters specify a maximum duty cycle that

Power Conversion Overview

effectively limits the maximum output voltage that can be

realized for a given input voltage. This duty cycle limit ensures

that the lowside MOSFET is allowed to turn on for a minimum

amount of time during each switching cycle, which enables the

bootstrap capacitor (CB in Figure 5) to be charged up and provide

adequate gate drive voltage for the high-side MOSFET. See

section“High-side Driver Boost Circuit” on page 12 for more

details.

The ZL2008 operates as a voltage-mode, synchronous buck

converter with a selectable constant frequency pulse width

modulator (PWM) control scheme that uses external MOSFETs,

capacitors, and an inductor to perform power conversion.

V_IN

DB

C

IN

VR

BST

In general, the size of components L1 and C_OUTas well as the

overall efficiency of the circuit are inversely proportional to the

switching frequency, f_SW. Therefore, the highest efficiency circuit

may be realized by switching the MOSFETs at the lowest possible

frequency; however, this will result in the largest component size.

Conversely, the smallest possible footprint may be realized by

switching at the fastest possible frequency but this gives a

somewhat lower efficiency. Each user should determine the

optimal combination of size and efficiency when determining the

switching frequency for each application.

QH

QL

GH

SW

CB

ZL

V_OUT

C_OUT

GL

FIGURE 5. Synchronous Buck Converter

Figure 5 illustrates the basic synchronous buck converter

topology showing the primary power train components. This

converter is also called a step-down converter, as the output

voltage must always be lower than the input voltage. In its most

simple configuration, the ZL2008 requires two external N-

channel power MOSFETs, one for the top control MOSFET (QH)

and one for the bottom synchronous MOSFET (QL). The amount

of time that QH is on as a fraction of the total switching period is

known as the duty cycle D, which is described by Equation 1:

The block diagram for the ZL2008 is illustrated in Figure 4. In

this circuit, the target output voltage is regulated by connecting

the differential VSEN pins directly to the output regulation point.

The VSEN signal is then compared to a reference voltage that has

been set to the desired output voltage level by the user. The error

signal derived from this comparison is converted to a digital

value with a low-resolution, analog to digital (A/D) converter. The

digital signal is applied to an adjustable digital compensation

filter, and the compensated signal is used to derive the

appropriate PWM duty cycle for driving the external MOSFETs in a

way that produces the desired output.

V_OUT

(EQ. 1)

D ≈

V_IN

During time D, QH is on and V_IN– V_OUTis applied across the

inductor. The current ramps up as shown in Figure 6.

The ZL2008 has several features to improve the power

conversion efficiency. A non-linear response (NLR) loop improves

the response time and reduces the output deviation as a result of

a load transient. The ZL2008 monitors the power converter’s

operating conditions and continuously adjusts the turn-on and

turn-off timing of the high-side and low-side MOSFETs to optimize

the overall efficiency of the power supply. Adaptive performance

optimization algorithms such as dead-time control, diode

emulation, and frequency control are available to provide greater

efficiency improvement.

When QH turns off (time 1-D), the current flowing in the inductor

must continue to flow from the ground up through QL, during

which the current ramps down. Since the output capacitor C_OUT

exhibits a low impedance at the switching frequency, the AC

component of the inductor current is filtered from the output

voltage so the load sees nearly a DC voltage.

Power Management Overview

V_IN- V_OUT

IL_PK

The ZL2008 incorporates a wide range of configurable power

management features that are simple to implement with no

external components. Additionally, the ZL2008 includes circuit

protection features that continuously safeguard the device and

load from damage due to unexpected system faults. The ZL2008

can continuously monitor input voltage, output voltage/current,

internal temperature, and the temperature of an external

thermal diode. A Power Good output signal is also included to

enable power-on reset functionality for an external processor.

I_O

0

IL_V

-V_OUT

All power management functions can be configured using either

pin configuration techniques (see Figure 7) or via the I²C/SMBus

interface. Monitoring parameters can also be pre-configured to

provide alerts for specific conditions. See Application Note

AN2033 for more details on SMBus monitoring.

D

1 - D

Time

FIGURE 6. Inductor Waveform

FN6859.4

April 29, 2011

11

ZL2008

The SMBus device address and VOUT_MAX are the only

Multi-mode Pins

parameters that must be set by external pins. All other device

parameters can be set via the I²C/SMBus. The device address is

set using the SA0 and SA1 pins. VOUT_MAX is determined as

10% greater than the voltage set by the V0 and V1 pins.

In order to simplify circuit design, the ZL2008 incorporates

patented multi-mode pins that allow the user to easily configure

many aspects of the device with no programming. Most power

management features can be configured using these pins. The

multi-mode pins can respond to four different connections as

shown in Table 1. These pins are sampled when power is applied

or by issuing a PMBus Restore command (See Application Note

AN2033).

Power Conversion Functional

Description

Internal Bias Regulators and Input Supply

Connections

The ZL2008 employs two internal low dropout (LDO) regulators to

supply bias voltages for internal circuitry, allowing it to operate

from a single input supply. The internal bias regulators are as

follows:

Pin-strap Settings: This is the simplest implementation method,

as no external components are required. Using this method, each

pin can take on one of three possible states: LOW, OPEN, or

HIGH. These pins can be connected to the V25 pin for logic HIGH

settings as this pin provides a regulated voltage higher than 2V.

Using a single pin, one of three settings can be selected. Using

two pins, one of nine settings can be selected.

VR: The VR LDO provides a regulated 5V bias supply for the

MOSFET driver circuits. It is powered from the VDD pin. A 4.7µF

filter capacitor is required at the VR pin.

TABLE 1. Multi-mode Pin Configuration

Pin Tied To

Value

V25: The V25 LDO provides a regulated 2.5V bias supply for the

main controller circuitry. It is powered from an internal 5V node.

A 10µF filter capacitor is required at the V25 pin.

LOW

(Logic LOW)

< 0.8VDC

OPEN

(N/C)

No connection

> 2.0VDC

When the input supply (VDD) is higher than 5.5V, the VR pin

should not be connected to any other pins. It should only have a

filter capacitor attached as shown in Figure 8. Due to the dropout

voltage associated with the VR bias regulator, the VDD pin must

be connected to the VR pin for designs operating from a supply

below 5.5V. Figure 8 illustrates the required connections for both

cases.

HIGH

(Logic HIGH)

Resistor to SGND

Set by resistor value

V_IN

Logic

high

VDD

VR

VDD

VR

ZL

Open

Multi-mode Pin

R_SET

Logic

low

Pin-strap

Settings

Resistor

Settings

3V ≤V_IN≤ 5.5V

5.5V <V_IN≤ 14V

FIGURE 8. Input Supply Connections

FIGURE 7. Pin-strap and Resistor Setting Examples

Note: the internal bias regulators are not designed to be outputs

for powering other circuitry. Do not attach external loads to any of

these pins. The multi-mode pins may be connected to the V25

pin for logic HIGH settings.

Resistor Settings: This method allows a greater range of

adjustability when connecting a finite value resistor (in a

specified range) between the multi-mode pin and SGND.

Standard 1% resistor values are used, and only every fourth E96

resistor value is used so the device can reliably recognize the

value of resistance connected to the pin while eliminating the

error associated with the resistor accuracy. Up to 31 unique

selections are available using a single resistor.

High-side Driver Boost Circuit

The gate drive voltage for the high-side MOSFET driver is

generated by a floating bootstrap capacitor, CB (see Figure 5).

When the lower MOSFET (QL) is turned on, the SW node is pulled

to ground and the capacitor is charged from the internal VR bias

regulator through diode DB. When QL turns off and the upper

MOSFET (QH) turns on, the SW node is pulled up to V_DDand the

voltage on the bootstrap capacitor is boosted approximately 5V

above V_DDto provide the necessary voltage to power the

high-side driver. A Schottky diode should be used for DB to help

maximize the high-side drive supply voltage.

I²C/SMBus Method: Almost any ZL2008 function can be

configured via the I²C/SMBus interface using standard PMBus

commands. Additionally, any value that has been configured

using the pin-strap or resistor setting methods can also be

re-configured and/or verified via the I²C/SMBus. See Application

Note AN2033 for more details.

FN6859.4

April 29, 2011

12

ZL2008

TABLE 3. Output Voltage Resistors Settings

R0 or R1

Output Voltage Selection

STANDARD MODE

Index

(kΩ)

The output voltage may be set to any voltage between 0.6V and

5.0V provided that the input voltage is higher than the desired

output voltage by an amount sufficient to prevent the device

from exceeding its maximum duty cycle specification. Using the

pin-strap method, V_OUTcan be set to any of nine standard

voltages as shown in Table 2.

0

1

10

11

2

12.1

13.3

14.7

16.2

17.8

19.6

21.5

23.7

26.1

28.7

31.6

34.8

38.3

42.2

46.4

51.1

56.2

61.9

68.1

75

3

4

TABLE 2. Output Voltage Pin-strap Settings

V0

5

6

LOW

(V)

OPEN

(V)

HIGH

(V)

7

LOW

OPEN

HIGH

0.6

1.2

2.5

0.8

1.5

3.3

1.0

1.8

5.0

8

V1

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

The resistor setting method can be used to set the output voltage

to levels not available in Table 2. Resistors R0 and R1 are

selected to produce a specific voltage between 0.6V and 5.0V in

10mV steps. Resistor R1 provides a coarse setting and resistor

R0 provides a fine adjustment, thus eliminating the additional

errors associated with using two 1% resistors (this typically adds

approx 1.4% error).

To set V_OUTusing resistors, follow the steps below to calculate an

index value and then use Table 3 to select the resistor that

corresponds to the calculated index value as follows:

1. Calculate Index1:

Index1 = 4 x V_OUT(V_OUTin 10mV steps)

2. Round the result down to the nearest whole number.

3. Select the value of R1 from Table 3 using the Index1 rounded

value from step 2.

82.5

90.9

100

4. Calculate Index0:

5. Index0 = 100 x V_OUT– (25 x Index1)

6. Select the value of R0 from Table 3 using the Index0 value

from Step 4.

Example from Figure 9: For V_OUT= 1.33V,

Index1 = 4 x 1.33V = 5.32;

From Table 3, R1 = 16.2kΩ

Index0 = (100 x 1.33V) – (25 x 5) = 8;

From Table 3, R0 = 21.5kΩ

SMBUS MODE

The output voltage may be set to any value between 0.6V and

5.0V using a PMBus command over the I²C/SMBus interface.

See Application Note AN2033 for details.

FN6859.4

April 29, 2011

13

ZL2008

V_IN

POLA

MODULE

ZL

GH

SW

V_OUT

1.33V

ZL

V0

V1

GL

110 kΩ

10 kΩ

V0

V1

R0

21. 5 kΩ

R1

16.2 kΩ

Rset

FIGURE 9. Output Voltage Resistor Setting Example

FIGURE 11. R_SETon a POLA Module

POLA VOLTAGE TRIM MODE

The POLA mode is activated through pin-strap by connecting a

110kΩ resistor on V0 to SGND. The V1 pin is then used to adjust

the output voltage as shown in Table 4.

The output voltage mapping can be changed to match the

voltage setting equations for POLA and DOSA standard modules.

The standard method for adjusting the output voltage for a POLA

module is defined by Equation 2:

The POLA mode can also be activated through PMBus

commands. See Application Note AN2033 for more details.

0.69V

TABLE 4. POLA Mode V_OUTSettings

(EQ. 2)

R_SET= 10kΩ×

−1.43kΩ

V_OUT− 0.69V

V_OUT

(V)

R_SET(kΩ)

In series with 10kΩ resistor

The resistor, R_SET, is external to the POLA module. See Figure 10.

0.700

162

110

0.752

POLA Module

0.758

100

0.765

90.9

82.5

75.0

56.2

51.1

46.4

42.2

34.8

31.6

28.7

23.7

21.5

19.6

16.2

13.3

12.1

9.09

7.50

5.62

4.64

2.87

2.37

1.21

0.162

0.69V

+

0.772

0.790

V_OUT

-

0.800

0.821

0.834

10kΩ

1.43kΩ

0.848

0.880

Rset

0.899

0.919

0.965

FIGURE 10. Output Voltage Setting on POLA Module

0.991

1.000

To stay compatible with this existing method for adjusting the

output voltage and to keep the same external R_SETresistor when

using the ZL2008, the module manufacturer should add a 10kΩ

resistor on the module as shown in Figure 11. Now, the same

R_SETused for an analog POLA module will provide the same

output voltage when using a digital POLA module based on the

ZL2008.

1.100

1.158

1.200

1.250

1.500

1.669

1.800

2.295

2.506

3.300

5.000

NOTE: (R0 = 110kΩ, R1 = R_SET+ 10kΩ)

FN6859.4

April 29, 2011

14

ZL2008

DOSA VOLTAGE TRIM MODE

On a DOSA module, the V_OUTsetting follows Equation 3:

6900

Start-up Procedure

The ZL2008 follows a specific internal start-up procedure after

power is applied to the VDD pin. Table 6 describes the start-up

sequence.

(EQ. 3)

R_SET

=

V_OUT− 0.69V

To maintain DOSA compatibility, the same scheme is used as with a

POLA module except the 10kΩ resistor is replaced with a 8.66kΩ

resistor as shown in Figure 12.

If the device is to be synchronized to an external clock source, the

clock frequency must be stable prior to asserting the EN pin. The

device requires approximately 5ms to 10ms to check for specific

values stored in its internal memory. If the user has stored values

in memory, those values will be loaded. The device will then

check the status of all multi-mode pins and load the values

associated with the pin settings.

DOSA

ZL

Once this process is completed, the device is ready to accept

commands via the I²C/SMBus interface and the device is ready

to be enabled. Once enabled, the device requires approximately

2ms before its output voltage may be allowed to start its ramp-

up process. If a soft-start delay period less than 2ms has been

configured (using PMBus commands), the device will default to a

2ms delay period. If a delay period greater than 2ms is

configured, the device will wait for the configured delay period

prior to starting to ramp its output.

MODULE

V0

V1

110 kΩ

8.66 kΩ

Rset

After the delay period has expired, the output will begin to ramp

towards its target voltage according to the pre-configured

soft-start ramp time that has been set using the SS pin. It should

be noted that if the EN pin is tied to VDD, the device will still

require approx 5ms to 10ms before the output can begin its

ramp-up as described in Table 6.

FIGURE 12. R_SETon a DOSA Module

The DOSA mode V_OUTsettings are listed in Table 5.

TABLE 5. DOSA Mode V_OUTSettings

V_OUT

(V)

R_SET(kΩ)

In series with 8.660kΩ resistor

Soft-start Delay and Ramp Times

0.700

0.752

0.758

0.765

0.772

0.790

0.800

0.821

0.834

0.848

0.880

0.899

0.919

0.965

0.991

1.000

1.100

1.158

1.200

1.250

1.500

1.669

1.800

2.295

2.506

3.300

5.000

162

113

It may be necessary to set a delay from when an enable signal is

received until the output voltage starts to ramp to its target

value. In addition, the designer may wish to precisely set the time

required for V_OUTto ramp to its target value after the delay period

has expired. These features may be used as part of an overall

inrush current management strategy or to precisely control how

fast a load IC is turned on. The ZL2008 gives the system designer

several options for precisely and independently controlling both

the delay and ramp time periods.

100

90.9

82.5

75.0

57.6

52.3

47.5

43.2

36.5

33.2

30.1

25.5

22.6

21.0

17.8

14.7

13.3

10.5

8.87

6.98

6.04

4.32

3.74

2.61

1.50

The soft-start delay period begins when the EN pin is asserted

and ends when the delay time expires. The soft-start delay period

is set using the SS pin. Precise ramp delay timing reduces the

delay time variations but is only available when the appropriate

bit in the MISC_CONFIG register has been set. Please refer to

Application Note AN2033 for details.

The soft-start ramp timer enables a precisely controlled ramp to

the nominal V_OUTvalue that begins once the delay period has

expired. The ramp-up is guaranteed monotonic and its slope may

be precisely set using the SS pin.

The soft-start delay and ramp times can be set to standard

values according to Table 7.

NOTE: (R0 = 110kΩ, R1 = R_SET+ 8.66kΩ)

FN6859.4

April 29, 2011

15

ZL2008

TABLE 6. ZL2106 START-UP SEQUENCE

DESCRIPTION

STEP #

1

STEP NAME

TIME DURATION

Power Applied

Input voltage is applied to the ZL2008’s VDD pin

Depends on input supply ramp

time

2

Internal Memory Check The device will check for values stored in its internal memory. This step Approx 5ms to 10ms (device will

is also performed after a Restore command.

ignore an enable signal or PMBus

traffic during this period)

3

4

5

Multi-mode Pin Check

Device Ready

The device loads values configured by the multi-mode pins.

The device is ready to accept an enable signal.

-

Pre-ramp Delay

The device requires approximately 2ms following an enable signal and

prior to ramping its output. Additional pre-ramp delay may be

configured using the SS pin.

Approximately 2ms

A PG delay period is defined as the time from when all conditions

within the ZL2008 for asserting PG are met to when the PG pin is

actually asserted. This feature is commonly used instead of using

an external reset controller to control external digital logic. By

default, the ZL2008 PG delay is set equal to the soft-start ramp

time setting. Therefore, if the soft-start ramp time is set to 10ms,

the PG delay will be set to 10ms. The PG delay may be set

independently of the soft-start ramp using the I²C/SMBus as

described in Application Note AN2033.

TABLE 7. Soft-start Pin-strap Settings

Delay Time

(ms)

Ramp Time

SS Pin

(ms)

LOW

OPEN

HIGH

2

5

2

5

10

If the desired soft-start delay and ramp times are not one of the

values listed in Table 7, the times can be set to a custom value by

connecting a resistor from the SS pin to SGND using the

appropriate resistor value from Table 8. The value of this resistor

is measured upon start-up or Restore and will not change if the

resistor is varied after power has been applied to the ZL2008.

See Figure 13 for typical connections using resistors.

TABLE 8. SS Resistor Settings

R_SS

(kΩ)

Delay Time

(ms)

Ramp Time

(ms)

10

5

10

20

2

11

2

12.1

13.3

14.7

16.2

17.8

19.6

21.5

23.7

26.1

28.7

31.6

34.8

38.3

42.2

46.4

51.1

56.2

61.9

68.1

75

5

ZL

10

20

2

R_SS

5

10

15

20

30

10

20

2

FIGURE 13. SS Pin Resistor Connections

The soft-start delay and ramp times can also be set to custom

values via the I²C/SMBus interface. When the SS delay time is

set to 0ms, the device will begin its ramp-up after the internal

circuitry has initialized (approx. 2ms). When the soft-start ramp

period is set to 0ms, the output will ramp up as quickly as the

output load capacitance and loop settings will allow. It is

generally recommended to set the soft-start ramp to a value

greater than 500µs to prevent inadvertent fault conditions due to

excessive inrush current.

5

10

20

2

5

10

20

2

Power Good

The ZL2008 provides a Power Good (PG) signal that indicates the

output voltage is within a specified tolerance of its target level

and no fault condition exists. By default, the PG pin will assert if

the output is within

-10% of the target voltage. These limits and the polarity of the pin

may be changed via the I²C/SMBus interface. See Application

Note AN2033 for details.

5

10

20

82.5

FN6859.4

April 29, 2011

16

ZL2008

clock signal must also exhibit the necessary performance

Switching Frequency and PLL

requirements (see “Electrical Specifications” on page 4). In the

event of a loss of the external clock signal, the output voltage

may show transient over/undershoot.

The ZL2008 incorporates an internal phase-locked loop (PLL) to

clock the internal circuitry. The PLL can be driven by an external

clock source connected to the SYNC pin. When using the internal

oscillator, the SYNC pin can be configured as a clock source for

other Zilker Labs devices.

If this happens, the ZL2008 will automatically switch to its

internal oscillator and switch at a frequency close to the previous

incoming frequency.

The SYNC pin is a unique pin that can perform multiple functions

depending on how it is configured. The CFG1 pin is used to select

the operating mode of the SYNC pin as shown in Table 9.

Figure 14 illustrates the typical connections for each mode.

Configuration C: SYNC AUTO DETECT

When the SYNC pin is configured in auto detect mode (CFG1 pin

is left OPEN), the device will automatically check for a clock

signal on the SYNC pin after enable is asserted.

TABLE 9. SYNC Pin Function Selection

CFG1 Pin

LOW

SYNC Pin Function

SYNC is configured as an input

Auto Detect mode

If a clock signal is present, The ZL2008’s oscillator will then

synchronize the rising edge of the external clock. Refer to SYNC

INPUT description.

OPEN

HIGH

If no incoming clock signal is present, the ZL2008 will configure

the switching frequency according to the state of the SYNC pin as

listed in Table 10. In this mode, the ZL2008 will only read the

SYNC pin connection during the start-up sequence. Changes to

SYNC pin connections will not affect f_SWuntil the power (VDD) is

cycled off and on.

SYNC is configured as an output

f_SW= 400kHz

Configuration A: SYNC OUTPUT

When the SYNC pin is configured as an output (CFG1 pin is tied

HIGH), the device will run from its internal oscillator and will drive the

resulting internal oscillator signal (preset to 400kHz) onto the SYNC

pin so other devices can be synchronized to it. The SYNC pin will not

be checked for an incoming clock signal while in this mode.

TABLE 10. Switching Frequency Pin-strap Setting

SYNC Pin

LOW

Frequency

200kHz

Configuration B: SYNC INPUT

OPEN

400kHz

HIGH

1MHz

When the SYNC pin is configured as an input (CFG1 pin is tied

LOW), the device will automatically check for a clock signal on

the SYNC pin each time EN is asserted. The ZL2008’s oscillator

will then synchronize with the rising edge of the external clock.

Resistor

See Table 11

If the user wishes to run the ZL2008 at a frequency not listed in

Table 10, the switching frequency can be set using an external

resistor, R_SYNC, connected between SYNC and SGND using Table 11.

The incoming clock signal must be in the range of 200kHz to

1.4MHz and must be stable when the enable pin is asserted. The

Logic

high

SYNC

200 kHz – 1.33MHz

ZL

SYNC

200kHz – 1.4MHz

ZL

A) SYNC = output

B) SYNC = input

N/ C

Logic

high

Open

SYNC

200kHz – 1.4MHz

OR

R_SYNC

ZL

Logic

low

C) SYNC = Auto Detect

FIGURE 14. Sync Pin Configurations

FN6859.4

April 29, 2011

17

ZL2008

TABLE 11. Switching Frequency Resistor Settings

TABLE 12. Power Supply Requirements

R_SYNC

f_SW

(kΩ)

(kHz)

Parameter

Input voltage (V_IN

Output voltage (V_OUT

Output current (I_OUT

Output voltage ripple

Range

Example Value

12V

10

200

222

242

267

296

320

364

400

421

471

)

3.0V to 14.0V

0.6V to 5.0V

0A to ~25A

< 3% of V_OUT

11

)

1.2V

12.1

13.3

14.7

16.2

17.8

19.6

21.5

23.7

26.1

28.7

31.6

34.8

38.3

46.4

51.1

56.2

68.1

)

20A

1% of V_OUT

(V_orip

)

Output load step (I_ostep

Output load step rate

)

< Io

—

50% of I_o

10A/µs

± 50mV

Output deviation due to load step

—

Maximum PCB temp.

Desired efficiency

+120°C

—

+85°C

85%

533

571

Other considerations

Various

Optimize for small

size

615

727

800

889

1000

1143

1333

DESIGN GOAL TRADE-OFFS

The design of the buck power stage requires several

compromises among size, efficiency, and cost. The inductor core

loss increases with frequency, so there is a trade-off between a

small output filter made possible by a higher switching frequency

and getting better power supply efficiency. Size can be decreased

by increasing the switching frequency at the expense of

efficiency. Cost can be minimized by using through-hole

inductors and capacitors; however these components are

physically large.

The switching frequency can also be set to any value between

200kHz and 1.33MHz using the I²C/SMBus interface. The

available frequencies below 1.4MHz are defined by f_SW= 8MHz/N,

where the whole number N is 6 ≤ N ≤ 40. See Application Note

AN2033 for details.

To start the design, select a switching frequency based on

Table 13. This frequency is a starting point and may be adjusted

as the design progresses.

TABLE 13. Circuit Design Consideration

Frequency Range

200kHz to 400kHz

400kHz to 800kHz

800kHz to 1.4MHz

Efficiency

Highest

Moderate

Lower

Circuit Size

Larger

If a value other than f_SW= 8MHz/N is entered using a PMBus

command, the internal circuitry will select the valid switching

frequency value that is closest to the entered value. For example,

if 810kHz is entered, the device will select 800kHz (N=10).

Smaller

Smallest

When multiple Zilker Labs devices are used together, connecting

the SYNC pins together will force all devices to synchronize with

each other. The CFG1 pin of one device must set its SYNC pin as

an output and the remaining devices must have their SYNC pins

set as Auto Detect.

INDUCTOR SELECTION

The output inductor selection process must include several trade-

offs. A high inductance value will result in a low ripple current

(I_opp), which will reduce output capacitance and produce a low

output ripple voltage, but may also compromise output transient

load performance. Therefore, a balance must be struck between

output ripple and optimal load transient performance. A good

starting point is to select the output inductor ripple equal to the

expected load transient step magnitude (I_ostep):

Note: The switching frequency read back using the appropriate

PMBus command will differ slightly from the selected values in

Table 11. The difference is due to hardware quantization.

Power Train Component Selection

The ZL2008 is a synchronous buck converter that uses external

MOSFETs, inductor and capacitors to perform the power

conversion process. The proper selection of the external

components is critical for optimized performance.

(EQ. 4)

I_opp= I_ostep

To select the appropriate external components for the desired

performance goals, the power supply requirements listed in

Table 12 must be known.

FN6859.4

April 29, 2011

18

ZL2008

Now the output inductance can be calculated using Equation 5,

where V_INMis the maximum input voltage:

shown in Equations 9 and 10:

I_opp

C_OUT

=

⎛

⎞

V_OUT

V_INM

(EQ. 9)

V_orip

⎜

⎟

V_OUT× 1−

⎜

8× f_sw×

(EQ. 5)

⎝

⎠

2

L_OUT

=

fsw× I_opp

V_orip

(EQ. 10)

The average inductor current is equal to the maximum output

current. The peak inductor current (I_Lpk) is calculated using

Equation 6 where I_OUTis the maximum output current:

ESR =

2× I_opp

Use these values to make an initial capacitor selection, using a

single capacitor or several capacitors in parallel.

I_opp

(EQ. 6)

I_Lpk= I_OUT

+

2

After a capacitor has been selected, the resulting output voltage

ripple can be calculated using Equation 11:

Select an inductor rated for the average DC current with a peak

current rating above the peak current computed above.

I_opp

(EQ. 11)

V_orip= I_opp× ESR +

In overcurrent or short-circuit conditions, the inductor may have

currents greater than 2X the normal maximum rated output

current. It is desirable to use an inductor that still provides some

inductance to protect the load and the MOSFETs from damaging

currents in this situation.

8× f_sw×C_OUT

Because each part of this equation was made to be less than or

equal to half of the allowed output ripple voltage, the V_oripshould

be less than the desired maximum output ripple.

Once an inductor is selected, the DCR and core losses in the

inductor are calculated. Use the DCR specified in the inductor

manufacturer’s datasheet.

INPUT CAPACITOR

It is highly recommended that dedicated input capacitors be

used in any point-of-load design, even when the supply is

powered from a heavily filtered 5V or 12V “bulk” supply from an

off-line power supply. This is because of the high RMS ripple

current that is drawn by the buck converter topology. This ripple

(I_CINrms) can be determined from Equation 12:

2

(EQ. 7)

P

= DCR× I_Lrms

LDCR

I_Lrmsis given by Equation 8:

2

(

+

)

I_opp

2

(EQ. 8)

I_Lrms= I_OUT

12

(EQ. 12)

I_CINrms= I_OUT× D × (1− D)

where I_OUTis the maximum output current. Next, calculate the

core loss of the selected inductor. Since this calculation is

specific to each inductor and manufacturer, refer to the chosen

inductor datasheet. Add the core loss and the ESR loss and

compare the total loss to the maximum power dissipation

recommendation in the inductor datasheet.

Without capacitive filtering near the power supply circuit, this

current would flow through the supply bus and return planes,

coupling noise into other system circuitry. The input capacitors

should be rated at 1.2X the ripple current calculated above to

avoid overheating of the capacitors due to the high ripple current,

which can cause premature failure. Ceramic capacitors with X7R

or X5R dielectric with low ESR and 1.1X the maximum expected

input voltage are recommended.

OUTPUT CAPACITOR SELECTION

Several trade-offs must also be considered when selecting an

output capacitor. Low ESR values are needed to have a small

output deviation during transient load steps (V_osag) and low

output voltage ripple (V_orip). However, capacitors with low ESR,

such as semi-stable (X5R and X7R) dielectric ceramic capacitors,

also have relatively low capacitance values. Many designs can

use a combination of high capacitance devices and low ESR

devices in parallel.

BOOTSTRAP CAPACITOR SELECTION

The high-side driver boost circuit utilizes an external Schottky

diode (D_B) and an external bootstrap capacitor (C_B) to supply

sufficient gate drive for the high-side MOSFET driver. D_Bshould

be a 20mA, 30V Schottky diode or equivalent device and C_B

should be a 1µF ceramic type rated for at least 6.3V.

For high ripple currents, a low capacitance value can cause a

significant amount of output voltage ripple. Likewise, in high

transient load steps, a relatively large amount of capacitance is

needed to minimize the output voltage deviation while the

inductor current ramps up or down to the new steady state

output current value.

QL SELECTION

The bottom MOSFET should be selected primarily based on the

device’s R_DS(ON)and secondarily based on its gate charge. To

choose QL, use the following equation and allow 2% to 5% of the

output power to be dissipated in the R_DS(ON)of QL (lower output

voltages and higher step-down ratios will be closer to 5%):

As a starting point, apportion one-half of the output ripple

voltage to the capacitor ESR and the other half to capacitance, as

FN6859.4

April 29, 2011

19

ZL2008

Calculate the RMS current in QL as follows:

where Q_gis the gate charge of the selected QH and I_gdris the

peak gate drive current available from the ZL2008.

(EQ. 13)

(EQ. 14)

P = 0.05×V_OUT× I_OUT

QL

Although the ZL2008 has a typical gate drive current of 3A, use

the minimum guaranteed current of 2A for a conservative

design. Using the calculated switching time, calculate the

switching power loss in QH using:

I_botrms= I_Lrms× 1− D

(EQ. 22)

P

=V_INM×t_sw× I_OUT× f_sw

swtop

Calculate the desired maximum R_DS(ON)as follows:

P

QL

The total power dissipated by QH is given by Equation 23:

(EQ. 15)

R_{DS (ON )}

=

2

(

I_botrms

)

(EQ. 23)

P

= P + P

QHtot

QH

swtop

Note that the R_DS(ON)given in the manufacturer’s datasheet is

measured at +25°C. The actual R_DS(ON)in the end-use

application will be much higher. For example, a Vishay Si7114

MOSFET with a junction temperature of +125°C has an R_DS(ON)

that is 1.4 times higher than the value at +25°C. Select a

candidate MOSFET, and calculate the required gate drive current

as follows:

MOSFET THERMAL CHECK

Once the power dissipations for QH and QL have been calculated,

the MOSFETs junction temperature can be estimated. Using the

junction-to-case thermal resistance (R_th) given in the MOSFET

manufacturer’s datasheet and the expected maximum printed

circuit board temperature, calculate the junction temperature as

follows:

(EQ. 16)

I_g= f_SW×Q_g

(EQ. 24)

(

)

T_{j max}= T_pcb+ P × R_th

Q

Keep in mind that the total allowed gate drive current for both QH

and QL is 80mA.

CURRENT SENSING COMPONENTS

Once the current sense method has been selected (refer to

section “Current Limit Threshold Selection” on page 21), the

components are selected as follows.

MOSFETs with lower R_DS(ON)tend to have higher gate charge

requirements, which increases the current and resulting power

required to turn them on and off. Since the MOSFET gate drive

circuits are integrated in the ZL2008, this power is dissipated in

the ZL2008 according to Equation 17:

When using the inductor DCR sensing method, the user must

also select an R/C network comprised of R1 and CL (see

Figure 15).

(EQ. 17)

P = f_sw×Q_g×V_INM

QL

GH

SW

QH SELECTION

In addition to the R_DS(ON)loss and gate charge loss, QH also has

switching loss. The procedure to select QH is similar to the

procedure for QL. First, assign 2% to 5% of the output power to

be dissipated in the R_DS(ON)of QH using the equation for QL

above. As was done with QL, calculate the RMS current as

follows:

CL

R1

ZL

GL

R2

ISENA

ISENB

FIGURE 15. DCR Current Sensing

(EQ. 18)

I_toprms= I_Lrms× D

For the voltage across C_Lto reflect the voltage across the DCR of

the inductor, the time constant of the inductor must match the

time constant of the RC network. That is:

Calculate a starting R_DS(ON)as follows, in this example using 5%:

(EQ. 19)

τ_RC= τ_{L/ DCR}

P

= 0.05×V_OUT× I_OUT

QH

(EQ. 25)

L

R₁⋅C_L=

P

QH

(EQ. 20)

DCR

R_{DS (ON )}

=

2

(

)

I_toprms

For L, use the average of the nominal value and the minimum

value. Include the effects of tolerance, DC Bias and switching

frequency on the inductance when determining the minimum

value of L. Use the typical value for DCR.

Select a MOSFET and calculate the resulting gate drive current.

Verify that the combined gate drive current from QL and QH does

not exceed 80mA.

Next, calculate the switching time using:

The value of R₁should be as small as feasible and no greater

than 5kΩ for best signal-to-noise ratio. The designer should

make sure the resistor package size is appropriate for the power

dissipated and include this loss in efficiency calculations. In

calculating the minimum value of R₁, the average voltage across

Q_g

(EQ. 21)

t_SW

=

I_gdr

FN6859.4

April 29, 2011

20

ZL2008

C_L(which is the average I_OUTDCR product) is small and can be

neglected. Therefore, the minimum value of R₁may be

V_IN

approximated Equation 26:,

2

)

2

GH

D

(

V_{IN −max}−V_OUT

+

(

1− D ⋅V_OUT

)

(EQ. 26)

R_1−min

=

SW

ISENA

V_OUT

ZL

P_R1pkg−max⋅δ_P

GL

where P_R1pkg-maxis the maximum power dissipation

ISENB

specification for the resistor package and _Pis the derating factor

for the same parameter (eg.: P_R1pkg-max= 0.0625W for 0603

package, _P= 50% @ 85°C). Once R_1-minhas been calculated,

solve for the maximum value of C_Lfrom Equation 27:

MOSFET R_DS(ON)Sensing

V_IN

L

(EQ. 27)

C_L−max

=

GH

SW

R_1−min⋅ DCR

V_OUT

and choose the next-lowest readily available value (e.g.: For

C_L-max= 1.86µF, C_L= 1.5µF is a good choice). Then substitute

the chosen value into the same equation and re-calculate the

value of R₁. Choose the 1% resistor standard value closest to this

re-calculated value of R₁. The error due to the mismatch of the

two time constants is expressed in Equation 28:

ZL

GL

ISENA

ISENB

Inductor DCR Sensing

(V_OUTmust be less than 4.0 V)

FIGURE 16. Current Sensing Methods

⎛

⎞

⎟

⎠

R₁⋅C_L⋅ DCR

(EQ. 28)

⎜

ε_τ= 1−

⋅100%

⎜

L_avg

To set the current limit threshold, the user must first select a

current sensing method. The ZL2008 incorporates two methods

for current sensing, synchronous MOSFET R_DS(ON)sensing and

inductor DC resistance (DCR) sensing; Figure 16 shows a

simplified schematic for each method. The current sensing

method can be selected using the CFG2 pin, as shown in

Tables 26 and 28, or via the I²C/SMBus interface. Please refer to

Application Note AN2033 for details.

⎝

The value of R₂should be simply five times that of R₁:

(EQ. 29)

R₂= 5⋅ R₁

For the R_DS(ON)current sensing method, the external low side

MOSFET will act as the sensing element as indicated in

Figure 16.

In addition to selecting the current sensing method, the ZL2008

gives the power supply designer several choices for the fault

response during over or under current condition. The user can

select the number of violations allowed before declaring fault, a

blanking time and the action taken when a fault is detected.

Current Limit Threshold Selection

It is recommended that the user include a current limiting

mechanism in their design to protect the power supply from

damage and prevent excessive current from being drawn from

the input supply in the event that the output is shorted to ground

or an overload condition is imposed on the output. Current

limiting is accomplished by sensing the current through the

circuit during a portion of the duty cycle.

The blanking time represents the time when no current

measurement is taken. This is to avoid taking a reading just after

a switching transition (less accurate due to potential ringing). It is

a configurable parameter.

Output current sensing can be accomplished by measuring the

voltage across a series resistive sensing element according to

Equation 30:

Once the sensing method has been selected, the user must

select the voltage threshold (VLIM), the desired current limit

threshold, and the resistance of the sensing element.

(EQ. 30)

V_LIM= I_LIM× R_SENSE

The current limit threshold voltage can be selected by simply

connecting the ILIM pin as shown in Table 14. The ground-

referenced sensing method is being used in this mode. By

default, the IOUT_CAL_GAIN is set to 1mΩ for DCR mode and

2mΩ for RDS mode.

Where:

I_LIMis the desired maximum current that should flow in the

circuit.

R_SENSEis the resistance of the sensing element.

TABLE 14. Current Limit Threshold Voltage Pin-strap Settings

V_LIMis the voltage across the sensing element at the point the

circuit should start limiting the output current.

R

_DSV_LIM

(mV)

DCR V_LIM

(mV)

ILIM Pin

LOW

The ZL2008 supports “lossless” current sensing by measuring

the voltage across a resistive element that is already present in

the circuit. This eliminates additional efficiency losses incurred

by devices that must use an additional series resistance in the

circuit.

50

60

70

25

30

35

OPEN

HIGH

FN6859.4

April 29, 2011

21

ZL2008

TABLE 15. Current Limit Threshold Voltage Resistor Settings

V_IN

R_LIM

(kΩ)

R_DSV_LIM

(mV)

DCR V_LIM

(mV)

D

L

10

0

5

0

DPWM

V_OUT

11

2.5

5

1-D

C

R_O

12.1

13.3

14.7

16.2

17.8

19.6

21.5

23.7

26.1

28.7

31.6

34.8

38.3

42.2

46.4

51.1

56.2

61.9

68.1

75

10

15

20

25

30

35

40

45

50

55

60

65

70

75

80

85

90

95

100

105

110

115

120

R_C

7.5

10

12.5

15

Compensation

17.5

20

FIGURE 17. Control Loop Block Diagram

In the ZL2008, the compensation zeros and gain are set by

configuring the FC0 and FC1 pins or via the I²C/SMBus interface

once the user has calculated the required settings. This method

eliminates the inaccuracies due to the component tolerances

associated with using external resistors and capacitors required

with traditional analog controllers.

22.5

25

27.5

30

32.5

35

The compensation is configured using a baseline set of PID taps

which are scaled on the factors of Gain, Q and Fn as shown in

Tables 16, 17 and 18. The parameters Gain, Q and Fn are defined

in AN2035 and are parameters of the compensator (not the

power stage being compensated).

37.5

40

42.5

45

The selection of these scaling factors is based on compensation

required for additional output capacitance used in an

application.

47.5

50

TABLE 16. FC0 Pin-strap Settings

52.5

55

FC0 Pin

LOW

Gain Scale (dB)

Q-new/Q-base

1

82.5

90.9

100

-12

0

57.5

60

OPEN

HIGH

6

The threshold voltage can also be selected in 5mV increments by

connecting a resistor, R_LIM, between the ILIM pin and ground

according to Table 15. This method is preferred if the user does not

desire to use or does not have access to the I²C/SMBus interface

and the desired threshold value is contained in Table 15.

TABLE 17. FC1 Pin-strap Settings

FC1 Pin

Fn-new/Fn-base

LOW

OPEN

HIGH

The current limit threshold can also be set to a custom value via

the I²C/SMBus interface. Please refer to Application Note

AN2033 for further details.

1

Loop Compensation

The scaling factors are applied to the baseline set of taps to

achieve the desired compensation results. These baseline taps

correspond to zeroes of the form:

The ZL2008 operates as a voltage-mode synchronous buck

controller with a fixed frequency PWM scheme. Although the

ZL2008 uses a digital control loop, it operates much like a

traditional analog PWM controller. Figure 17 is a simplified block

diagram of the ZL2008 control loop, which differs from an

analog control loop only by the constants in the PWM and

compensation blocks. As in the analog controller case, the

compensation block compares the output voltage to the desired

voltage reference and compensation zeroes are added to keep

the loop stable. The resulting integrated error signal is used to

drive the PWM logic, converting the error signal to a duty cycle to

drive the external MOSFETs.

2

⎡

⎤

⎥

⎦

⎛

⎞

s

(EQ. 31)

⎜

⎟

G

^base1+

+

⎢

(Q^base∗2π fnbase

)

(Qbase*2π fnbase)

⎝

⎠

⎣

Where G_base= 20dB

_base= 2

f_nbase= f_SW/10

Q

Both the baseline taps and the calculated taps determined by the

FC0 and FC1 resistors can be read via the I²C/SMBus interface.

Please refer to Application Note AN2033 for further details.

FN6859.4

April 29, 2011

22

ZL2008

TABLE 18. Loop Compensation Resistor Settings

R_FC0

(kΩ)

Gain Scale

(dB)

R_FC1

(kΩ)

Q-new/Q-base

0.6813

0.4642

0.3162

0.2154

0.1468

0.1000

0.6813

0.4642

0.3162

0.2154

0.1468

0.1000

0.6813

0.4642

0.3162

0.2154

0.1468

0.1000

1.0000

0.6813

0.4642

0.3162

0.2154

0.1468

0.1000

0.6813

0.4642

0.3162

0.2154

0.1468

0.1000

Fn-new/Fn-base

1.0000

0.9050

0.8190

0.7411

0.6707

0.6070

0.5493

0.4971

0.4498

0.4071

0.3684

0.3334

0.3017

0.2730

0.2471

0.2236

0.2024

0.1831

0.1657

0.1500

0.1357

0.1228

0.1112

0.1006

0.0910

0.0824

0.0745

0.0675

0.0611

0.0553

0.0500

10

11

12.1

13.3

14.7

16.2

17.8

19.6

21.5

23.7

26.1

28.7

31.6

34.8

38.3

42.2

46.4

51.1

56.2

61.9

68.1

75

12.1

13.3

14.7

16.2

17.8

19.6

21.5

23.7

26.1

28.7

31.6

34.8

38.3

42.2

46.4

51.1

56.2

61.9

68.1

75

12

6

0

-6

82.5

90.9

100

110

121

133

147

162

178

82.5

90.9

100

110

121

133

147

162

178

-12

FN6859.4

April 29, 2011

23

ZL2008

Non-linear Response (NLR) Settings

Adaptive Diode Emulation

The ZL2008 incorporates a non-linear response (NLR) loop that

decreases the response time and the output voltage deviation in

the event of a sudden output load current step. The NLR loop

incorporates a secondary error signal processing path that

bypasses the primary error loop when the output begins to

transition outside of the standard regulation limits. This scheme

results in a higher equivalent loop bandwidth than what is

possible using a traditional linear loop.

Most power converters use synchronous rectification to optimize

efficiency over a wide range of input and output conditions.

However, at light loads the synchronous MOSFET will typically

sink current and introduce additional energy losses associated

with higher peak inductor currents, resulting in reduced

efficiency. Adaptive diode emulation mode turns off the low-side

FET gate drive at low load currents to prevent the inductor current

from going negative, reducing the energy losses and increasing

overall efficiency. Diode emulation is available to single-phase

devices only.

When a load current step function imposed on the output causes

the output voltage to drop below the lower regulation limit, the

NLR circuitry will force a positive correction signal that will turn

on the upper MOSFET and quickly force the output to increase.

Conversely, a negative load step (i.e. removing a large load

current) will cause the NLR circuitry to force a negative correction

signal that will turn on the lower MOSFET and quickly force the

output to decrease.

Note: the overall bandwidth of the device may be reduced when

in diode emulation mode. It is recommended that diode

emulation is disabled prior to applying significant load steps.

Adaptive Frequency Control

Since switching losses contribute to the efficiency of the power

converter, reducing the switching frequency will reduce the

switching losses and increase efficiency. The ZL2008 includes

Adaptive Frequency Control mode, which effectively reduces the

observed switching frequency as the load decreases.

NLR can be configured using resistor pin-straps as follows:

CFG0 disables NLR or enables NLR inner thresholds to 1.5%,

2% or 3% (see Table 30).

CFG1 sets NLR inner thresholds timeout and blanking to 1

and 4 or 2 and 8 (see Table 27).

Adaptive frequency mode is enabled by setting bit 0 of

MISC_CONFIG to 1 and is only available while the device is

operating within Adaptive Diode Emulation Mode. As the load

current is decreased, diode emulation mode decreases the GL

on-time to prevent negative inductor current from flowing. As the

load is decreased further, the GH pulse width will begin to

decrease while maintaining the programmed frequency, f_PROG

(set by the FREQ_SWITCH command).

Please refer to Application Note AN2032 for more details

regarding NLR settings.

Efficiency Optimized Driver Dead-time

Control

The ZL2008 utilizes a closed loop algorithm to optimize the

dead-time applied between the gate drive signals for the top and

bottom FETs. In a synchronous buck converter, the MOSFET drive

circuitry must be designed such that the top and bottom

MOSFETs are never in the conducting state at the same time.

Potentially damaging currents flow in the circuit if both top and

bottom MOSFETs are simultaneously on for periods of time

exceeding a few nanoseconds. Conversely, long periods of time in

which both MOSFETs are off reduce overall circuit efficiency by

allowing current to flow in their parasitic body diodes.

f_SW(D)

f_PROG

f_MIN

D

It is therefore advantageous to minimize this dead-time to

provide optimum circuit efficiency. In the first order model of a

buck converter, the duty cycle is determined by Equation 32:

0

D_NOM

2

Duty Cycle

V_OUT

(EQ. 32)

D ≈

FIGURE 18. Adaptive Frequency

V_IN

However, non-idealities exist that cause the real duty cycle to

extend beyond the ideal. Dead-time is one of those non-idealities

that can be manipulated to improve efficiency. The ZL2008 has

an internal algorithm that constantly adjusts dead-time non-

overlap to minimize duty cycle, thus maximizing efficiency. This

circuit will null out dead-time differences due to component

variation, temperature, and loading effects.

Once the GH pulse width (D) reaches 50% of the nominal duty

cycle, D_NOM(determined by Vin and Vout), the switching

frequency will start to decrease according to Equation 33:

If

DNOM

2

This algorithm is independent of application circuit parameters

such as MOSFET type, gate driver delays, rise and fall times and

circuit layout. In addition, it does not require drive or MOSFET

voltage or current waveform measurements.

then,

2( f^SW− f^MIN

)

⎛

⎜

⎞

⎟

(EQ. 33)

D + fMIN

DNOM

⎝

⎠

FN6859.4

April 29, 2011

24

ZL2008

Otherwise f_SW(D) = f_PROG

TABLE 20. UVLO Threshold Resistor Settings

This is illustrated in Figure 18. Due to quantizing effects inside

the IC, the ZL2008 will decrease its frequency in steps between

f_SWand f_MIN. The quantity and magnitude of the steps will

depend on the difference between f_SWand f_MINas well as the

frequency range.

R_UVLO

(kΩ)

UVLO

(V)

17.8

19.6

21.5

23.7

26.1

28.7

31.6

34.8

38.3

42.2

46.4

51.1

56.2

61.9

68.1

75

2.85

3.14

3.44

3.79

4.18

4.59

5.06

5.57

6.13

6.75

7.42

8.18

8.99

9.9

Adaptive frequency mode is not available for current sharing

groups when using an external clock, or if the device is outputting

a clock signal on its SYNC pin.

Power Management Functional

Description

Input Undervoltage Lockout

The input undervoltage lockout (UVLO) prevents the ZL2008 from

operating when the input falls below a preset threshold,

indicating the input supply is out of its specified range. The UVLO

threshold (V_UVLO) can be set between 2.85V and 16V using the

UVLO pin. The simplest implementation is to connect the UVLO

pin as shown in Table 19. If the UVLO pin is left unconnected, the

UVLO threshold will default to 4.5V.

TABLE 19. UVLO Threshold Pin-strap Settings

10.9

12

UVLO Threshold

UVLO Pin

LOW

(V)

3

82.5

90.9

100

13.2

14.54

16

OPEN

HIGH

4.5

10.8

The UVLO voltage can also be set to any value between 2.85V

and 16V via the I²C/SMBus interface.

If the desired UVLO threshold is not one of the listed choices, the

user can configure a threshold between 2.85V and 16V by

connecting a resistor between the UVLO pin and SGND by

selecting the appropriate resistor from Table 20.

Once an input undervoltage fault condition occurs, the device

can respond in a number of ways as follows:

1. Continue operating without interruption.

2. Continue operating for a given delay period, followed by

shutdown if the fault still exists. The device will remain in

shutdown until instructed to restart.

3. Initiate an immediate shutdown until the fault has been

cleared. The user can select a specific number of retry

attempts.

The default response from a UVLO fault is an immediate

shutdown of the device. The device will continuously check for

the presence of the fault condition. If the fault condition is no

longer present, the ZL2008 will be re-enabled.

FN6859.4

April 29, 2011

25

ZL2008

Please refer to Application Note AN2033 for details on how to

configure the UVLO threshold or to select specific UVLO fault

response options via the I²C/SMBus interface.

duty cycle to match the original target voltage and the output will

ramp down to the pre-configured output voltage.

Output Overvoltage Protection

The ZL2008 offers an internal output overvoltage protection

circuit that can be used to protect sensitive load circuitry from

being subjected to a voltage higher than its prescribed limits. A

hardware comparator is used to compare the actual output

voltage (seen at the VSEN pin) to a threshold set to 15% higher

than the target output voltage (the default setting). If the VSEN

voltage exceeds this threshold, the PG pin will de-assert and the

device can then respond in a number of ways as follows:

1. Initiate an immediate shutdown until the fault has been

cleared. The user can select a specific number of retry

attempts.

2. Turn off the high-side MOSFET and turn on the low-side

MOSFET. The low-side MOSFET remains ON until the device

attempts a restart.

The default response from an overvoltage fault is to immediately

shut down. The device will continuously check for the presence of

the fault condition, and when the fault condition no longer exists

the device will be re-enabled.

For continuous overvoltage protection when operating from an

external clock, the only allowed response is an immediate

shutdown.

Please refer to Application Note AN2033 for details on how to

select specific overvoltage fault response options via I²C/SMBus.

Output Pre-Bias Protection

FIGURE 19. Output Responses to Pre-bias Voltages

An output pre-bias condition exists when an externally applied

voltage is present on a power supply’s output before the power

supply’s control IC is enabled. Certain applications require that

the converter not be allowed to sink current during start up if a

pre-bias condition exists at the output. The ZL2008 provides

pre-bias protection by sampling the output voltage prior to

initiating an output ramp.

If a pre-bias voltage higher than the overvoltage limit exists, the

device will not initiate a turn-on sequence and will declare an

overvoltage fault condition to exist. In this case, the device will

respond based on the output overvoltage fault response method

that has been selected. See “Output Overvoltage Protection” on

page 26 for response options due to an overvoltage condition.

If a pre-bias voltage lower than the target voltage exists after the

pre-configured delay period has expired, the target voltage is set

to match the existing pre-bias voltage and both drivers are

enabled. The output voltage is then ramped to the final

regulation value at the ramp rate set by the SS pin.

Pre-bias protection is not offered for current sharing groups that

also have tracking enabled.

Output Overcurrent Protection

The ZL2008 can protect the power supply from damage if the

output is shorted to ground or if an overload condition is imposed

on the output. Once the current limit threshold has been selected

(see “Current Limit Threshold Selection” on page 21), the user

may determine the desired course of action in response to the

fault condition. The following overcurrent protection response

options are available:

The actual time the output will take to ramp from the pre-bias

voltage to the target voltage will vary depending on the pre-bias

voltage but the total time elapsed from when the delay period

expires and when the output reaches its target value will match

the pre-configured ramp time. See Figure 19.

If a pre-bias voltage higher than the target voltage exists after the

pre-configured delay period has expired, the target voltage is set

to match the existing pre-bias voltage and both drivers are

enabled with a PWM duty cycle that would ideally create the

pre-bias voltage.

1. Initiate a shutdown and attempt to restart an infinite number

of times with a preset delay period between attempts.

2. Initiate a shutdown and attempt to restart a preset number of

times with a preset delay period between attempts.

Once the pre-configured soft-start ramp period has expired, the

PG pin will be asserted (assuming the pre-bias voltage is not

higher than the overvoltage limit). The PWM will then adjust its

3. Continue operating for a given delay period, followed by

shutdown if the fault still exists.

FN6859.4

April 29, 2011

26

ZL2008

4. Continue operating through the fault (this could result in

permanent damage to the power supply).

The default response from a temperature fault is an immediate

shutdown of the device. The device will continuously check for

the fault condition, and once the fault has cleared the ZL2008

will be re-enabled.

5. Initiate an immediate shutdown.

The default response from an overcurrent fault is an immediate

shutdown of the device. The device will continuously check for

the presence of the fault condition, and if the fault condition no

longer exists the device will be re-enabled.

Please refer to Application Note AN2033 for details on how to

select specific temperature fault response options via

I²C/SMBus.

Please refer to Application Note AN2033 for details on how to

select specific overcurrent fault response options via I²C/SMBus.

Voltage Tracking

Numerous high performance systems place stringent demands

on the order in which the power supply voltages are turned on.

This is particularly true when powering FPGAs, ASICs, and other

advanced processor devices that require multiple supply voltages

to power a single die. In most cases, the I/O interface operates at

a higher voltage than the core and therefore the core supply

voltage must not exceed the I/O supply voltage according to the

manufacturers' specifications.

Thermal Overload Protection

The ZL2008 includes an on-chip thermal sensor that

continuously measures the internal temperature of the die and

shuts down the device when the temperature exceeds the preset

limit. The default temperature limit is set to +125°C in the

factory, but the user may set the limit to a different value if

desired. See Application Note AN2033 for details. Note that

setting a higher thermal limit via the I²C/SMBus interface may

result in permanent damage to the device. Once the device has

been disabled due to an internal temperature fault, the user may

select one of several fault response options as follows:

Voltage tracking protects these sensitive ICs by limiting the

differential voltage between multiple power supplies during the

power-up and power down sequence. The ZL2008 integrates a

lossless tracking scheme that allows its output to track a voltage

that is applied to the VTRK pin with no external components

required. The VTRK pin is an analog input that, when tracking

mode is enabled, configures the voltage applied to the VTRK pin

to act as a reference for the device’s output regulation.

1. Initiate a shutdown and attempt to restart an infinite number

of times with a preset delay period between attempts.

2. Initiate a shutdown and attempt to restart a preset number of

times with a preset delay period between attempts.

The ZL2008 offers two mode of tracking as follows:

3. Continue operating for a given delay period, followed by

shutdown if the fault still exists.

1. Coincident. This mode configures the ZL2008 to ramp its

output voltage at the same rate as the voltage applied to the

VTRK pin.

4. Continue operating through the fault (this could result in

permanent damage to the power supply).

2. Ratiometric. This mode configures the ZL2008 to ramp its

output voltage at a rate that is a percentage of the voltage

applied to the VTRK pin. The default setting is 50%, but an

external resistor string may be used to configure a different

tracking ratio.

5. Initiate an immediate shutdown.

If the user has configured the device to restart, the device will

wait the preset delay period (if configured to do so) and will then

check the device temperature. If the temperature has dropped

below a threshold that is approx +15°C lower than the selected

temperature fault limit, the device will attempt to re-start. If the

temperature still exceeds the fault limit the device will wait the

preset delay period and retry again.

Figure 20 illustrates the typical connection and the two tracking

modes.

The master ZL2008 device in a tracking group is defined as the

device that has the highest target output voltage within the group.

This master device will control the ramp rate of all tracking devices

and is not configured for tracking mode. A delay of at least 10ms

must be configured into the master device using the SS pin, and the

user may also configure a specific ramp rate using the SS pin. Any

device that is configured for tracking mode will ignore its soft-start

delay and ramp time settings (SS pin) and its output will take on the

turn-on/turn-off characteristics of the reference voltage present at

the VTRK pin. All of the ENABLE pins in the tracking group must be

connected together and driven by a single logic source. Tracking is

configured via the I²C/SMBus interface by using the TRACK_CONFIG

PMBus command. Please refer to Application Note AN2033 for

more information on configuring tracking mode using PMBus.

FN6859.4

April 29, 2011

27

ZL2008

TABLE 21. Tracking Resistor Settings

Upper Track Limit

R_SS

(kΩ)

Track Ratio

(%)

Ramp-up/down Behavior

Output does not decrease before PG

Output always follows VTRK

90.9

100

110

121

133

147

162

178

Limited by target

Limited by VTRK

Limited by target

Limited by VTRK

100

50

Output does not decrease before PG

Output always follows VTRK

Output does not decrease before PG

Output always follows VTRK

Output does not decrease before PG

Output always follows VTRK

It should be noted that current sharing groups that are also

configured to track another voltage do not offer pre-bias

protection; a minimum load should therefore be enforced to

avoid the output voltage from being held up by an outside force.

Additionally, a device set up for tracking must have both

Alternate Ramp Control and Precise Ramp-Up Delay disabled.

Voltage Margining

The ZL2008 offers a simple means to vary its output higher or

lower than its nominal voltage setting in order to determine

whether the load device is capable of operating over its specified

supply voltage range. The MGN command is set by driving the

MGN pin or through the I²C/SMBus interface. The MGN pin is a

tri-level input that is continuously monitored and can be driven

directly by a processor I/O pin or other logic-level output.

V_IN

GH

ZL SW

GL

Q1

Q2

The ZL2008’s output will be forced higher than its nominal set

point when the MGN command is set HIGH, and the output will

be forced lower than its nominal set point when the MGN

command is set LOW. Default margin limits of V_NOM±5% are

pre-loaded in the factory, but the margin limits can be modified

through the I²C/SMBus interface to as high as V_NOM+ 10% or as

low as 0V, where V_NOMis the nominal output voltage set point

determined by the V0 and V1 pins. A safety feature prevents the

user from configuring the output voltage to exceed V_NOM+ 10%

under any conditions.

V_OUT

L1

C1

V_TRK

V_OUT

V_TRK

The margin limits and the MGN command can both be set

individually through the I²C/SMBus interface. Additionally, the

transition rate between the nominal output voltage and either

margin limit can be configured through the I²C interface. Please

refer to Application Note AN2033 for detailed instructions on

modifying the margining configurations.

V_OUT

Time

2

I C/SMBus Communications

Coincident

The ZL2008 provides an I²C/SMBus digital interface that

enables the user to configure all aspects of the device operation

as well as monitor the input and output parameters. The ZL2008

can be used with any standard 2-wire I²C host device. In addition,

the device is compatible with SMBus version 2.0 and includes an

SALRT line to help mitigate bandwidth limitations related to

continuous fault monitoring. Pull-up resistors are required on the

I²C/SMBus as specified in the SMBus 2.0 specification. The

ZL2008 accepts most standard PMBus commands. When

controlling the device with PMBus commands, it is

V_OUT

V_TRK

V_OUT

recommended that the enable pin is tied to SGND.

Time

Ratiometric

FIGURE 20. Tracking Modes

FN6859.4

April 29, 2011

28

ZL2008

2

If more than 25 unique device addresses are required or if other

I C/SMBus Device Address Selection

SMBus address values are desired, both the SA0 and SA1 pins

can be configured with a resistor to SGND according to

Equation 34 and Table 24.

When communicating with multiple SMBus devices using the

I²C/SMBus interface, each device must have its own unique

address so the host can distinguish between the devices. The

device address can be set according to the pin-strap options

listed in Table 22. Address values are right-justified.

SMBus address = 25 x (SA1 index) + (SA0 index) (in decimal)

(EQ. 34)

TABLE 22. SMBus Address Pin-strap Selection

SA0

TABLE 24. SMBus Address Index Values

R_SA

LOW

0x20

0x23

0x26

OPEN

0x21

0x24

0x27

HIGH

0x22

(kΩ)

SA0 or SA1 Index

LOW

OPEN

HIGH

10

0

1

SA1

0x25

11

Reserved

12.1

13.3

14.7

16.2

17.8

19.6

21.5

23.7

26.1

28.7

31.6

34.8

38.3

42.2

46.4

51.1

56.2

61.9

68.1

75

2

3

If additional device addresses are required, a resistor can be

connected to the SA0 pin according to Table 23 to provide up to

25 unique device addresses. In this case, the SA1 pin should be

tied to SGND.

4

5

6

TABLE 23. SMBus Address Resistor Selection

7

R_SA0

(kΩ)

SMBus

Address

8

10

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

9

11

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

12.1

13.3

14.7

16.2

17.8

19.6

21.5

23.7

26.1

28.7

31.6

34.8

38.3

42.2

46.4

51.1

56.2

61.9

68.1

75

82.5

90.9

100

Using this method, the user can theoretically configure up to 625

unique SMBus addresses, however the SMBus is inherently

limited to 128 devices so attempting to configure an address

higher than 128 (0x80) will cause the device address to repeat

(i.e., attempting to configure a device address of 129 (0x81)

would result in a device address of 1). Therefore, the user should

use index values 0-4 on the SA1 pin and the full range of index

values on the SA0 pin, which will provide 125 device address

combinations.

82.5

90.9

100

Note that the SMBus address 0x4B is reserved for device test and

cannot be used in the system.

FN6859.4

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29

ZL2008

TABLE 26. Phase Offset Resistor Settings

Digital-DC Bus

The Digital-DC Communications (DDC) bus is used to

communicate between Zilker Labs Digital-DC devices. This

R_CFG2

(kΩ)

Phase Offset

(°)

Current

Sense

dedicated bus provides the communication channel between

devices for features such as sequencing, fault spreading, and

current sharing. The DDC pin on all Digital-DC devices in an

application should be connected together. A pull-up resistor is

required on the DDC bus in order to guarantee the rise time as

follows:

10

22.5

45

11

12.1

13.3

14.7

16.2

17.8

19.6

21.5

23.7

26.1

28.7

31.6

34.8

38.3

42.2

46.4

51.1

56.2

61.9

68.1

75

67.5

90

112.5

135

Rise time = R_PU* C_LOAD1µs

(EQ. 35)

where R_PUis the DDC bus pull-up resistance and C_LOADis the bus

loading. The pull-up resistor may be tied to VR or to an external

3.3V or 5V supply as long as this voltage is present prior to or

during device power-up. As rules of thumb, each device

connected to the DDC bus presents approx 10pF of capacitive

loading, and each inch of FR4 PCB trace introduces approx 2pF.

The ideal design will use a central pull-up resistor that is well-

matched to the total load capacitance. In power module

applications, the user should consider whether to place the pull-

up resistor on the module or on the PCB of the end application.

The minimum pull-up resistance should be limited to a value that

enables any device to assert the bus to a voltage that will ensure

a logic 0 (typically 0.8V at the device monitoring point) given the

pull-up voltage (5V if tied to VR) and the pull-down current

capability of the ZL2008 (nominally 4mA).

157.5

180

DCR

202.5

225

247.5

270

292.5

315

337.5

22.5

45

Phase Spreading

When multiple point of load converters share a common DC

input supply, it is desirable to adjust the clock phase offset of

each device such that not all devices start to switch

simultaneously. Setting each converter to start its switching cycle

at a different point in time can dramatically reduce input

capacitance requirements and efficiency losses. Since the peak

current drawn from the input supply is effectively spread out over

a period of time, the peak current drawn at any given moment is

reduced and the power losses proportional to the I_RMS²are

reduced dramatically.

67.5

90

112.5

135

157.5

180

82.5

90.9

100

110

121

133

147

162

RDS

202.5

225

247.5

270

In order to enable phase spreading, all converters must be

synchronized to the same switching clock. The CFG1 pin is used

to set the configuration of the SYNC pin for each device as

described in section “Switching Frequency and PLL” on page 17 .

292.5

315

The phase offset of each single-phase device may be set to any

value between 0° and 337.5° in 22.5° increments using the

CFG2 pin as shown in Tables 25 and 26.

337.5

The phase offset of (multi-phase) current sharing devices is

automatically set to a value between 0° and 337.5° in 22.5°

increments as described in “Active Current Sharing” on page 31.

TABLE 25. Phase Offset Pin-strap Settings

Phase Offset

R_CFG2

LOW

(°)

90

0

Current Sense

DCR

The phase offset of each device may also be set to any value

between 0° and 360° in 22.5° increments via the I²C/SMBus

interface. Refer to Application Note AN2033 for further details.

OPEN

HIGH

180

FN6859.4

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ZL2008

Output Sequencing

Fault Spreading

A group of Digital-DC devices may be configured to power up in a

predetermined sequence. This feature is especially useful when

powering advanced processors, FPGAs, and ASICs that require

one supply to reach its operating voltage prior to another supply

reaching its operating voltage in order to avoid latch-up from

occurring. Multi-device sequencing can be achieved by

Digital DC devices can be configured to broadcast a fault event

over the DDC bus to the other devices in the group. When a non-

destructive fault occurs and the device is configured to shut down

on a fault, the device will shut down and broadcast the fault

event over the DDC bus. The other devices on the DDC bus will

shut down together or in sequencing order, if configured to do so,

and will attempt to re-start in their prescribed order if configured

to do so.

configuring each device through the I²C/SMBus interface or by

using Zilker Labs patented autonomous sequencing mode.

Autonomous sequencing mode configures sequencing by using

events transmitted between devices over the DDC bus. This mode

is not available on current sharing rails.

Temperature Monitoring Using the XTEMP Pin

The ZL2008 supports measurement of an external device

temperature using either a thermal diode integrated in a

processor, FPGA or ASIC, or using a discrete diode-connected

2N3904 NPN transistor. Figure 21 illustrates the typical

connections required.

The sequencing order is determined using each device’s SMBus

address. Using autonomous sequencing mode (configured using

the CFG1 pin), the devices must be assigned sequential SMBus

addresses with no missing addresses in the chain. This mode will

also constrain each device to have a phase offset according to its

SMBus address as described “Phase Spreading” on page 30.

XTEMP

100 pF

2N3904

ZL

The sequencing group will turn on in order starting with the

device with the lowest SMBus address and will continue through

to turn on each device in the address chain until all devices

connected have been turned on. When turning off, the device

with the highest SMBus address will turn off first followed in

reverse order by the other devices in the group.

SGND

Discrete NPN

µP

XTEMP

FPGA

DSP

ASIC

Sequencing is configured by connecting a resistor from the CFG1

pin to ground as described in Table 27. The CFG1 pin is also used

to set the configuration of the SYNC pin as well as to determine

the sequencing method and order. Please refer to “Switching

Frequency and PLL” on page 17 for more details on the operating

parameters of the SYNC pin.

100pF

ZL

SGND

Embedded Thermal Diode

FIGURE 21. External Temperature Monitoring

Multiple device sequencing may also be achieved by issuing

PMBus commands to assign the preceding device in the

sequencing chain as well as the device that will follow in the

sequencing chain. This method places fewer restrictions on

SMBus address (no need of sequential address) and also allows

the user to assign any phase offset to any device irrespective of

its SMBus device address.

Active Current Sharing

Paralleling multiple ZL2008 devices can be used to increase the

output current capability of a single power rail. By connecting the

DDC pins of each device together and configuring the devices as

a current sharing rail, the units will share the current equally

within a few percent.

The Enable pins of all devices in a sequencing group must be tied

together and driven high to initiate a sequenced turn-on of the

group. Enable must be driven low to initiate a sequenced turnoff

of the group.

Figure 22 illustrates a typical connection for three devices.

The ZL2008 uses a low-bandwidth, first-order digital current

sharing technique to balance the unequal device output loading

by aligning the load lines of member devices to a reference

device.

Refer to Application Note AN2033 for details on sequencing via

the I²C/SMBus interface.

Droop resistance is used to add artificial resistance in the output

voltage path to control the slope of the load line curve,

calibrating out the physical parasitic mismatches due to power

train components and PCB layout.

FN6859.4

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31

ZL2008

TABLE 27. Sequencing Pin-strap and Resistor Settings

Sequencing Configuration

NLR Timeout and

Blanking

R_CFG1

LOW

SYNC Pin Config

Input

OPEN

Auto detect

Output

Sequencing is disabled.

1 and 4

HIGH

10kΩ

Input

11kΩ

Auto detect

Output

12.1kΩ

14.7kΩ

16.2kΩ

17.8kΩ

21.5kΩ

23.7kΩ

26.1kΩ

31.6kΩ

34.8kΩ

38.3kΩ

46.4kΩ

51.1kΩ

56.2kΩ

68.1kΩ

75kΩ

Input

The ZL2008 is configured as the first device in a nested sequencing group. Turn on

order is based on the device SMBus address.

Auto detect

Output

1 and 4

Input

The ZL2008 is configured as a last device in a nested sequencing group. Turn on order

is based on the device SMBus address.

Auto detect

Output

Input

The ZL2008 is configured as the middle device in a nested sequencing group. Turn on

order is based on the device SMBus address.

Auto detect

Output

Input

Auto detect

Output

Sequencing is disabled.

Input

The ZL2008 is configured as the first device in a nested sequencing group. Turn on

order is based on the device SMBus address.

Auto detect

Output

82.5kΩ

100kΩ

110kΩ

121kΩ

147kΩ

162kΩ

178kΩ

2 and 8

Input

The ZL2008 is configured as a last device in a nested sequencing group. Turn on order

is based on the device SMBus address.

Auto detect

Output

Input

The ZL2008 is configured as the middle device in a nested sequencing group. Turn on

order is based on the device SMBus address.

Auto detect

Output

FN6859.4

April 29, 2011

32

ZL2008

The ISHARE_CONFIG command is used to configure the device

V_IN

3.3V - 5V

for active current sharing. The default setting is a stand-alone

non-current sharing device. A current sharing rail can be part of a

system sequencing group.

C_IN

ZL

DDC

For fault configuration, the current share rail is configured in a

quasi-redundant mode. In this mode, when a member device

fails, the remaining members will continue to operate and

attempt to maintain regulation. Of the remaining devices, the

device with the lowest member position will become the

reference. If fault spreading is enabled, the current share rail

failure is not broadcast until the entire current share rail fails.

C_OUT

C_IN

V_OUT

C_OUT

Up to eight (8) devices can be configured in a given current

sharing rail.

C_IN

TABLE 28. Current Share Position Settings

R_CFG2

C_OUT

(kΩ)

10

Current Share Position

Current Sense

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

FIGURE 22. Current Sharing Group

11

12.1

13.3

14.7

16.2

17.8

19.6

42.2

46.4

51.1

56.2

61.9

68.1

75

DCR

V_REFERENCE

-R

V_MEMBER

-R

RDS

I_MEMBER

I_OUT

I_REFERENCE

FIGURE 23. Active Current Sharing

Upon system start-up, the device with the lowest member

position as selected in ISHARE_CONFIG is defined as the

reference device. The remaining devices are members. The

reference device broadcasts its current over the DDC bus. The

members use the reference current information to trim their

voltages (V_MEMBER) to balance the current loading of each device

in the system.

82.5

TABLE 29. Current Share Pin-strap Settings

Current Share # of

CFG0 Pin

NLR

1.5%

Members

0

Current Sharing

Disabled

Figure 23 shows that, for load lines with identical slopes, the

member voltage is increased towards the reference voltage

which closes the gap between the inductor currents.

LOW

OPEN

HIGH

Disabled

2%

The relation between reference and member current and voltage

is given by Equation 36:

(EQ. 36)

V_MEMBER= V_OUT+ R ×

(

I_REFERENCE− I_MEMBER

)

where R is the value of the droop resistance.

FN6859.4

April 29, 2011

33

ZL2008

The phase offset of a current sharing group is automatically set

to a value between 0° and 337.5° in 22.5° increments as

follows:

TABLE 30. Current Share Resistor Settings

Current Share # of

R_CFG0

(kΩ)

NLR

Members

Current Sharing

Phase Offset = (SMBus Address[4:0] – Current Share

Position) * 22.5°

10

2

3

4

5

6

7

8

0

2

3

4

5

6

7

8

0

2

3

4

5

6

7

8

0

2

3

4

5

6

7

8

(EQ. 37)

11

The phase of the individual members in a group are spread

evenly from the phase offset of the group.

12.1

13.3

14.7

16.2

17.8

19.6

21.5

23.7

26.1

28.7

31.6

34.8

38.3

42.2

46.4

51.1

56.2

61.9

68.1

75

Disabled

Enabled

Please refer to Application Note AN2034 for additional details on

current sharing.

Phase Adding/Dropping

The ZL2008 allows multiple power converters to be connected in

parallel to supply higher load currents than can be addressed

using a single-phase design. In doing so, the power converter is

optimized at a load current range that requires all phases to be

operational. During periods of light loading, it may be beneficial

to disable one or more phases in order to eliminate the current

drain and switching losses associated with those phases,

resulting in higher efficiency.

Disabled

Enabled

3%

The ZL2008 offers the ability to add and drop phases using a the

phase enable pin or a PMBus command in response to an

observed load current change. All phases in a current share rail

are considered active prior to the current sharing rail ramp to

power-good.

Disabled

Enabled

Phases can be dropped after power-good is reached. The phase

enable pin can be used to drop and add phases:

• Set PH_EN = 0 to drop a phase

• Set PH_EN = 1 to add a phase

2%

The time to detect a change of state of the phase enable pin is

between 0ms and 3ms (max).

Any member of the current sharing rail can be dropped. If the

reference device is dropped, the remaining active device with the

lowest member position will become the new reference.

82.5

90.9

100

110

121

133

147

Disabled

Enabled

Additionally, any change to the number of members of a current

sharing rail will precipitate autonomous phase distribution within

the rail where all active phases realign their phase position

based on their order within the number of active members.

1.5%

If the members of a current sharing rail are forced to shut down

due to an observed fault, all members of the rail will attempt to

re-start simultaneously after the fault has cleared.

162

178

For single phase operation, that is, not current sharing, the

PH_EN pin is ignored and can be left open.

FN6859.4

April 29, 2011

34

ZL2008

2

may be observed if the device’s V_DDsupply drops below 3.0V

during this process.

Monitoring via I C/SMBus

A system controller can monitor a wide variety of different

ZL2008 system parameters through the I²C/SMBus interface.

The device can monitor for fault conditions by monitoring the

SALRT pin, which will be pulled low when any number of

pre-configured fault conditions occur.

TABLE 31. SNAPSHOT_CONTROL Command

Data Value

1

Description

Copies current SNAPSHOT values from Flash memory to

RAM for immediate access using SNAPSHOT command.

The device can also be monitored continuously for any number of

power conversion parameters including but not limited to the

following:

2

Writes current SNAPSHOT values to Flash memory. Only

available when device is disabled.

• Input voltage/Output voltage

• Output current

In the event that the device experiences a fault and power is lost,

the user can extract the last SNAPSHOT parameters stored

during the fault by writing a 1 to SNAPSHOT_CONTROL (transfers

data from Flash memory to RAM) and then issuing a SNAPSHOT

command (reads data from RAM via SMBus).

• Internal and external temperature

• Switching frequency

• Duty cycle

Non-Volatile Memory and Device Security

Features

The ZL2008 has internal non-volatile memory where user

configurations are stored. Integrated security measures ensure

that the user can only restore the device to a level that has been

made available to them. Refer to “Start-up Procedure” on

page 15 for details on how the device loads stored values from

internal memory during start-up.

The PMBus Host should respond to SALRT as follows:

1. ZL device pulls SALRT Low

2. PMBus Host detects that SALRT is now low, performs

transmission with Alert Response Address to find which ZL

device is pulling SALRT low.

3. PMBus Host talks to the ZL device that has pulled SALRT low.

The actions that the host performs are up to the System

Designer.

During the initialization process, the ZL2008 checks for stored

values contained in its internal non-volatile memory. The ZL2008

offers two internal memory storage units that are accessible by

the user as follows:

If multiple devices are faulting, SALRT will still be low after doing

the above steps and will require transmission with the Alert

Response Address repeatedly until all faults are cleared.

1. Default Store: A power supply module manufacturer may

want to protect the module from damage by preventing the

user from being able to modify certain values that are related

to the physical construction of the module. In this case, the

module manufacturer would use the Default Store and would

allow the user to restore the device to its default setting but

would restrict the user from restoring the device to the factory

settings.

Please refer to Application Note AN2033 for details on how to

monitor specific parameters via the I²C/SMBus interface.

Snapshot Parameter Capture

The ZL2008 offers a special feature that enables the user to

capture parametric data during normal operation or following a

fault. The Snapshot functionality is enabled by setting bit 1 of

MISC_CONFIG to 1.

2. User Store: The manufacturer of a piece of equipment may

want to provide the ability to modify certain power supply

settings while still protecting the equipment from modifying

values that can lead to a system level fault. The equipment

manufacturer would use the User Store to achieve this goal.

See AN2033 for details on using the Snapshot in addition to the

parameters supported. The Snapshot feature enables the user to

read status and parameters via a block read transfer through the

SMBus. This can be done during normal operation, although it

should be noted that reading the 22 bytes will occupy the SMBus

for some time.

Please refer to Application Note AN2033 for details on how to set

specific security measures via the I²C/SMBus interface.

The SNAPSHOT_CONTROL command enables the user to store

the snapshot parameters to Flash memory in response to a

pending fault as well as to read the stored data from Flash

memory after a fault has occurred. Table 31 describes the usage

of this command. Automatic writes to Flash memory following a

fault are triggered when any fault threshold level is exceeded,

provided that the specific fault’s response is to shut down

(writing to Flash memory is not allowed if the device is configured

to re-try following the specific fault condition). It should also be

noted that the device’s V_DDvoltage must be maintained during

the time when the device is writing the data to Flash memory; a

process that requires between 700µs to 1400µs depending on

whether the data is set up for a block write. Undesirable results

Pin-strap Current Sharing

Configuration

A 3-phase current sharing group example is shown in Figure 24.

Each ZL2008 device in the group is connected to the same DDC

bus and SMBus. Also, the enable pins are connected together to

allow all devices in the current sharing group to enable

simultaneously.

The device with the lowest position number becomes the

reference device. The reference device provides the load current

information to each member device. If the reference device is

FN6859.4

April 29, 2011

35

ZL2008

dropped or faults then the device with the next lowest position

number will become the new reference device.

SYNC Clock (CFG1 Pin)

Typically the reference device sources the SYNC clock. However,

any device internal or external to the current sharing group can

source the SYNC clock. If the reference device is sourcing the

SYNC clock, then resistor pin-strap the CFG1 pin to configure the

SYNC pin as an output. Otherwise configure the reference

device’s SYNC pin as an input. For member devices, resistor

pin-strap the CFG1 pin to configure the SYNC pin as an input.

3.3V

VCC

Rail_1

Rail DDC ID = 5

DEV_1

0x20

Rout Cout

REF.

POS_0

POS_1

PH_1

DDC

SDA

SCL

Soft-start (SS Pin)

SYNC_Out

SYNC

VCC

Current sharing groups require proper synchronization prior to

ramp events. Resistor pin-strap the SS pin to set the following

parameters:

DEV_2

0x21

MEM_1

a. Delay Time – The reference device’s soft-start delay time

must be at least 10ms greater than any member device to

ramp up/down current sharing. The reference device requires

this additional time to coordinate a synchronization signal to

all member devices.

POS_2

POS_1

PH_2

SYNC_In

VCC

DEV_3

0x22

b. Ramp Time – A minimum soft-start ramp time of 5ms is

required for both reference and member devices to ramp

up/down current sharing.

MEM_2

POS_3

POS_2

PH_3

Phase Enable (PH_EN Pin)

SYNC_In

Phase enable is used to dynamically add or drop a current

sharing phase during operation. Set the PH_EN pin high to

enable a phase and low to disable a phase (open is an invalid

state). The PH_EN pin replaces the PHASE_CONTROL command.

FIGURE 24. 3-phase Current Sharing Group

SMBus Address (SA0, SA1 Pins)

For proper operation, the pin must be externally driven high or

low without switching glitches. Also, ensure phase enable is high

for the reference and member devices of a current sharing group

prior to ramp-up.

Assign sequential SMBus addresses to each device in the current

sharing group. If other non-current sharing devices are connected

to the same SMBus then assign addresses to these devices that

are before or after the current sharing group.

MFR_CONFIG Command

Current Share Pin-Straps (CFG0, CFG2 Pins)

Application specific values are set by the MFR_CONFIG

command. The following parameters must be set to properly

configure current sharing.

Resistor pin-strap the CFG0 pin to set the following parameters:

a. Current Share # of Members – Number of devices or phases

in a current sharing group (2 minimum and 8 maximum).

a. Current Sense Blanking Delay (bits 15:11) – The current

sense delay parameter controls the blanking time when no

current measurement is taken. This allows the filtering of

noise from the current measurement circuit when the FETs

b. Current Share Control – Current sharing is automatically

enabled when the number of members is 2 (and disabled

when members is = 0).

Resistor pin-strap the CFG2 pin to set the current share position:

are switching. The actual value selected depends on f_SW

,

sensing method and ring-out duration. The same delay is

used for both reference and member devices.

c. Current Share Position – Sequential numbering from 0 to 7

(max) of N number of members starting with the reference

device in position 0 and ending with the last member device

in position N-1.

b. Current Sense Control (bits 5:4) – Three modes of current

sensing are available depending on duty cycle and switching

frequency as listed in Table 33 (also refer to “Current Limit

Threshold Selection” on page 21). The same sensing is used

for both reference and member devices.

For the 3-phase group the parameters for each device are shown

in Table 32.

TABLE 32. Current Share Parameters

Device

SMBus Address # of Members Position

Control

Enabled

Reference

Member_1

Member_2

0x20

0x21

0x22

3

0

1

2

FN6859.4

April 29, 2011

36

ZL2008

Note, the following parameters are automatically set when

current sharing is enabled.

VOUT_DROOP Command

The droop or load-line resistance is used as part of the current

sharing algorithm. When current sharing is enabled,

VOUT_DROOP is automatically set to a value of 0xBA80

(1.25mΩ). The same droop value is used for both reference and

member devices.

Alternate Ramp Control (bit 2) – Automatically set to “1”

(enabled) for both reference and member devices when current

sharing is enabled.

SYNC Pin Output Control (bit 0) – Automatically set to push-pull

for a SYNC clock output and open-drain for a SYNC clock input.

Current Sharing Example

TABLE 33. Current Sense Options

Example pin-strap resistor values for the current sharing group in

Figure 24 are shown in Table 34. Sequential SMBus addresses

are used with the reference device at the lowest address. The

reference device outputs the SYNC clock to the member devices

SYNC clock input. The devices are configured for 3-phase current

sharing with all phases enabled. The reference device soft-start

ramp time is at least 5ms and soft-start delay time is at least

10ms greater than the member devices for proper

Current Sense Configuration

Usage

Ground referenced, down slope

(R_DS(ON)sensing)

Low duty cycle and low f_SW

V_outreferenced, down slope

(Inductor DCR sensing)

Low duty cycle and high f_SW

High duty cycle

V_outreferenced, up slope

(Inductor DCR sensing)

synchronization and output voltage ramp.

TABLE 34. Pin-Strap Current Sharing Resistor Values

Reference

Low, Low

Member_1

Open, Low

Member_2

Description

SA0, SA1

High, Low

SMBus Address = 0x20 for Reference

SMBus Address = 0x21 for Member_1

SMBus Address = 0x22 for Member_2

CFG0

CFG1

CFG2

23.7kΩ

High

23.7kΩ

Low

23.7kΩ

Low

Current Share # of Members = 3

Current Share Control = Enabled

SYNC = Output for Reference

SYNC = Input for Member_1 and Member_2

42.2kΩ

46.4kΩ

51.1kΩ

Current Share Position = 0 for Reference

Current Share Position = 1 for Member_1

Current Share Position = 2 for Member_2

SS

31.6kΩ

14.7kΩ

Delay = 15ms, Ramp = 5ms for Reference

Delay = 5ms, Ramp = 5ms for Member_1

Delay = 5ms, Ramp = 5ms for Member_2

PH_EN

High

All Phases Enabled

Reference

Member_1

Member_2

Position = 2

SMBus = 0x22

SYNC = Input

Delay = 5 ms

Ramp = 5 ms

Position = 0

SMBus = 0x20

SYNC = Output

Delay = 15 ms

Ramp = 5 ms

Position = 1

SMBus = 0x21

SYNC = Input

Delay = 5 ms

Ramp = 5 ms

FIGURE 25.

FN6859.4

April 29, 2011

37

ZL2008

Ordering Information

PART NUMBER

(Notes 19, 20, 21)

TEMP RANGE

(°C)

PKG.

DWG. #

PART MARKING

2008

PACKAGE

36 Ld 6mmx6mm QFN

ZL2008ALBFT

ZL2008ALBFT1

NOTES:

-40 to +85

L36.6x6A

2008

19. Please refer to TB347 for details on reel specifications.

20. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-

free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

21. For Moisture Sensitivity Level (MSL), please see device information page for ZL2008. For more information on MSL please see techbrief TB363.


型号：	ZL2008ALBFT
厂家：	Intersil
描述：	Digital DC/DC Controller with Drivers and Pin-Strap Current Sharing 数字DC / DC控制器与驱动器和引脚带电流共享驱动器控制器
文件：	总42页 (文件大小：1064K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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