ZL8800-2CH-DEMO1Z_技术文档

DATASHEET

Dual Channel/Dual Phase PMBus™ ChargeMode™

Control DC/DC Digital Controller

ZL8800

Features

The ZL8800 is a dual output or dual phase digital DC/DC

controller. Each output can operate independently or be used

together in a dual phase configuration for high current

applications.

• Unique compensation-free design – always stable

• Output voltage range: 0.54V to 5.5V

• Input voltage range: 4.5V to 14V

• 1% Output Voltage accuracy over line, load and temperature

The ZL8800 supports a wide range of output voltages

(0.54V to 5.5V) operating from input voltages as low as 4.5V

up to 14V.

• ChargeMode control achieves fast transient response,

reduced output capacitance and provides output stability

without compensation.

With the fully digital ChargeMode™ Control the ZL8800 will

respond to a transient load step within a single switching cycle.

This unique compensation-free modulation technique allows

designs to meet transient specifications with minimum output

capacitance thus saving cost and board space.

• Switching frequency range 200kHz to 1.33MHz

• Proprietary single wire DDC (Digital-DC) serial bus enables

voltage sequencing and fault spreading with other Intersil

ICs

• Tracking of an external power supply

Intersil’s proprietary single wire DDC (Digital-DC™) serial bus

enables the ZL8800 to communicate between other Intersil

ICs. By using the DDC, the ZL8800 achieves complex functions

such as inter-IC phase current balancing, sequencing and fault

spreading, eliminating complicated power supply managers

with numerous external discrete components.

• Cycle-by-cycle inductor peak current protection

• Digital fault protection for output voltage UV/OV, input

voltage UV/OV, temperature and MOSFET driver voltage

• 10-bit average output current measurement with adjustable

gain settings for sensing with high current, low DCR

inductors

The ZL8800 features cycle-by-cycle output overcurrent

protection. The input voltage, output voltages and

DrMOS/MOSFET driver supply voltages are overvoltage and

overvoltage protected. Two external and one internal

temperature sensor are available for temperature monitoring,

one of which is used for under and over-temperature

protection. A snapshot parametric capture feature allows

users to take a snapshot of operating and fault data during

normal or fault conditions.

• 10-bit monitor ADC measures input voltage, input current,

output voltage, internal, external temperature, driver voltage

• Configurable to use stand-alone MOSFET drivers or

integrated Driver-MOSFET (DrMOS) devices

• Nonvolatile memory for storing operating parameters and

fault events.

• PMBus™ compliant

Integrated Low Dropout (LDO) regulators allow the ZL8800 to

be operated from a single input supply eliminating the need

for additional linear regulators. The LDO output can be used to

power external drivers or DrMOS devices.

Applications

• Servers/storage equipment

• Telecom/datacom equipment

• Power supplies (memory, DSP, ASIC, FPGA)

With full PMBus™ compliance the ZL8800 is capable of

measuring and reporting input voltage, input current, output

voltage, output current as well as the device’s internal

temperature, 2 external temperatures and an auxiliary voltage

input.

Related Literature

• AN1877, “ZL8800-2CH-DEMO1Z Demonstration Board User

Guide”

• AN1900, “USB to PMBus™ Adapter User Guide”

• AN1901, “ZL8800-2PH-DEMO1Z Demonstration Board”

TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS

PART NUMBER

ZL8800

DUAL OUTPUT

DUAL PHASE

DDC CURRENT SHARE

SPS SUPPORT

Yes

No

Yes

No

Yes

No

ZL8801

ZL8802

Yes

September 14, 2015

FN7558.3

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

Intersil (and design), Digital-DC and ChargeMode are trademarks owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

ZL8800

Table of Contents

Simplified Two Output Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

ZL8800 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Digital-DC Architecture Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Power Management Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Multimode Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Configurable Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

SMBus Device Address Selection (SA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Output Voltage and VOUT_MAX Selection (VSET0,1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Switching Frequency Setting (SYNC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Input Voltage Undervoltage Lockout Setting (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Internal Bias Regulators and Input Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Start-up Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Ton Delay and Rise Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Power-Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Power Management Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Output Overvoltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Output Prebias Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Output Overcurrent Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Current Limit Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Input Current Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Thermal Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Voltage Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Voltage Margining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

External Voltage Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

SMBus Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Digital-DC™ Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Phase Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Output Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Fault Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Active Current Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Temperature Monitoring Using XTEMP Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Nonvolatile Memory and Security Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

DC/DC Converter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Power Train Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Monitoring via SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

PMBus™ Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

PMBus™ Data Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

PMBus™ Command Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Firmware Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

FN7558.3

September 14, 2015

Submit Document Feedback

2

ZL8800

Simplified Two Output Application

VIN

4.5V TO 14V

VDD

VDRV

ZL8800

VOUT1

0.54V TO 5.5V

VDD

VOUT0

0.54V TO 5.5V

VDD

GH

BST

GL

GH

BST

GL

PWMH1

PWMH0

PWML0

PWML1

ISENA1

ISENB1

ISENA0

ISENB0

VSENP1

VSENN1

VSENP0

VSENN0

INTER-DEVICE

COMMUNICATION

DDC

EN0

EN1

CONTROL AND

STATUS

SDA

PG0

PG1

SCL

SALRT

PMBus™

GND

FIGURE 1. SIMPLIFIED TWO OUTPUT APPLICATION

FN7558.3

September 14, 2015

Submit Document Feedback

3

ZL8800

Block Diagram

PWMH0

PWML0

ASCR

DIGITAL PWM

MODULATOR

PWM+

DEAD

TIME

ADC

VSEN0P/N

PWMH1

PWML1

ASCR

DIGITAL PWM

MODULATOR

PWM+

DEAD

TIME

VSEN1P/N

XTEMP1P/N

XTEMP0P/N

MONITOR

ADC

MGN0/1

EN0/1

VTRKP/N

DIGITAL LOGIC

+

OV/UV/OC/UC

COMPARATORS

VMON

VDD

PG0/1

OSC

ISENA0

CLK

GEN

I

/

PEAK

PLL

SYNC

DDC

IAVG

ADC

ISENB0

ISENA1

DIGITAL-DC

INTER-DEVICE

COMMUNICATIONS

MICROCONTROLLER

AND

NONVOLATILE

MEMORY

I

/

PEAK

IAVG

ADC

ISENB1

SDA

IIN

ADC

I²C AND SMBus

SERIAL

SCL

INTERFACE

SALRT

PIN-STRAP

RESISTOR

DETECTION

LDOs

VDD

GAIN

FIGURE 2. BLOCK DIAGRAM

FN7558.3

September 14, 2015

Submit Document Feedback

4

ZL8800

Pin Configuration

ZL8800

(44 LD QFN)

TOP VIEW

33

32

31

30

29

28

27

26

25

24

23

VDD

1

2

3

4

5

6

7

8

9

SCL

SDA

VR5

VR6

SALRT

SGND

VDRV

ISENA1

ISENB1

PWML1

PWMH1

PWMH0

PWML0

ISENB0

SA

VMON

DGND

Exposed Paddle

Connect to SGND

MGN0

MGN1

VSET0 10

VSET1

11

Pin Description

TYPE

1

LABEL

SCL

(Note 1)

I/O

DESCRIPTION

Serial clock. Connect to external host and/or to other ZL devices.

Serial data. Connect to external host and/or to other ZL devices.

Serial alert. Connect to external host if desired.

2

SDA

I/O

3

SALRT

SGND

O

Connect to low impedance ground plane. Internal connection to SGND.

4

PWR

Serial address select pin. Used to assign unique address for each individual device or to enable certain management

features.

5

6

SA

M

I

External voltage monitoring (can be used for external driver bias (VDRV) monitoring). Requires an external 16:1 resistor

divider network.

VMON

Digital ground. Connect to low impedance ground plane.

Channel 0 margin pin.

7

DGND

MGN0

MGN1

VSET0

VSET1

PG0

PWR

8

I

Channel 1 margin pin.

9

Channel 0 output voltage selection pin. Used to set V

Channel 1 output voltage selection pin. Used to set V

Channel 0 power-good output.

and V

max.

10

11

12

13

14

M

O

OUT0

OUT1

Undervoltage lockout selection. Sets the minimum value for V voltage to enable V

DD

.

UVLO

DDC

M

I/O

I

OUT

Single wire DDC bus (Current sharing, inter device communication).

External temperature sensor input for channel 0. Connect to external 2N3904 (Base Emitter junction) or equivalent

embedded thermal diode.

15 XTEMP0P

16 XTEMP0N

External temperature sensor input for channel 0 return

I

Tracking sense positive input. Used to track an external voltage source.

Tracking sense negative input (return).

17

18

19

VTRKP

VTRKN

VSEN0P

Differential output channel 0 voltage sense feedback. Connect to positive output regulation point.

FN7558.3

September 14, 2015

Submit Document Feedback

6

ZL8800

Pin Description (Continued)

TYPE

20

LABEL

(Note 1)

DESCRIPTION

Differential output channel 0 voltage sense feedback. Connect to negative output regulation point.

VDRV (MOSFET driver bias supply) Enable. Leave unconnected (float) or pull-up to VR5 to enable, tie to ground to disable.

Positive differential voltage input for channel 0 DCR current sensing.

Negative differential voltage input for channel 0 DCR current sensing.

PWM0 low signal/DrMOS enable.

VSEN0N

I

21 VDRVEN

I

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

ISENA0

ISENB0

PWML0

PWMH0

PWMH1

PWML1

ISENB1

ISENA1

VDRV

I

O

PWM0 high signal.

O

PWM1 high signal.

O

PWM1 low signal/DrMOS enable.

O

Negative differential voltage input for channel 1 DCR current sensing.

Positive differential voltage input for channel 1 DCR current sensing.

MOSFET driver bias supply regulator output.

I

PWR

Internal 6V reference used to power internal circuitry.

Internal 5V reference used to power internal circuitry.

Supply voltage.

VR6

PWR

VR5

PWR

VDD

PWR

Input current monitor negative input.

IINN

I

Input current monitor positive input.

IINP

I

Internal 2.5V reference used to power internal circuitry.

Channel 1 power-good output.

V25

PWR

PG1

O

I

Differential output channel 1 voltage sense feedback. Connect to negative output regulation point.

Differential output channel 1 voltage sense feedback. Connect to positive output regulation point.

External temperature sensor input for channel 1 return.

VSEN1N

VSEN1P

I

40 XTEMP1N

41 XTEMP1P

I

External temperature sensor input for channel 1. Connect to external 2N3904 (base emitter junction) or equivalent

embedded thermal diode.

I

Enable channel 0. Active signal enables PWM0 switching.

Enable channel 1. Active signal enables PWM1 switching.

42

43

EN0

EN1

I

Clock synchronization input. Used to set the frequency of the internal clock, to sync to an external clock or to output internal

clock.

44

SYNC

SGND

M/I/O

PWR

Exposed thermal pad. Connect to low impedance ground plane. Internal connection to SGND.

PAD

NOTE:

1. I = Input, O = Output, PWR = Power or Ground, M = Multimode pins.

FN7558.3

September 14, 2015

Submit Document Feedback

7

ZL8800

Ordering Information

FIRMWARE

REVISION

(Note 5)

PART

NUMBER

(Notes 2, 3, 4)

TEMP. RANGE

(°C)

PACK

METHOD

PACKAGE

(RoHS Compliant)

PART

MARKING

PKG.

DWG. #

ZL8800ALAFTK

8800

1.04

1.06

-40 to +85

Tape and Reel 1k

Tape and Reel 4k

Tape and Reel 1k

44 Lead QFN

L44.7x7B

ZL8800ALAFT

ZL8800ALBFT

ZL8800ALBFTK

ZL8800-2CH-DEMO1Z Demonstration Board, 2 independent 30A synchronous buck converters with compensation-free ChargeMode control

ZL8800-2PH-DEMO1Z Demonstration Board, 2-phase 60A synchronous buck converter with compensation-free ChargeMode control

NOTES:

2. Please refer to TB347 for details on reel specifications.

3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

Pb-free products are MSL classified at Pbfree peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

4. For Moisture Sensitivity Level (MSL), please see device information page for ZL8800 For more information on MSL please see techbrief TB363.

5. See “Firmware Revision History” on page 83; only the latest firmware revision is recommended for new designs.

ZL8800

A L A F T

Product Designator

Shipping Option

T = Tape and Reel - 4000 pcs

TK = Tape and Reel - 1000 pcs

Contact factory for other options

Lead Finish

F = Lead-free matte tin

Firmware Revision (Alpha character)

A: 1.04

B: 1.06

Operating Temperature Range

L = -40°C to +85°C

Package Designator

A = QFN package

FN7558.3

September 14, 2015

Submit Document Feedback

8

ZL8800

Absolute Maximum Ratings

Thermal Information

DC Supply Voltage: VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 17V

Logic I/O Voltage: DDC, EN0, EN1, MGN0, MGN1, PG0,

Thermal Resistance (Typical)

44 Ld QFN Package (Notes 7, 8) . . . . . . . .



(°C/W)

25



(°C/W)

1.5

JA

JC

PG1, SA, VDRVEN, SALRT, SCL, SDA, SYNC, UVLO,

VMON, VSET0, VSET1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V

Analog Input Voltages: VSEN0P, VSEN0N, VSEN1P, VSEN1N,

Storage Temperature range . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C

Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493

VTRKP, VTRKN, ISENA0, ISENA1, ISENB0, ISENB1 . . . . . . -0.3V to 6.5V

XTEMP0P, XTEMP1P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V

XTEMP0N, XTEMP1N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V

IINN, IINP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 17V

Logic Reference: V25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 3V

Bias Supplies: VR5, VR6, VDRV. . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V

PWM Logic OUTPUTS, PWMH0, PWMH1, PWML0, PWML1 . . .-0.3V to 6.5V

Ground Voltage Differential (VDGND-VSGND), . . . . . . . . . . . . . . .-0.3V to +0.3V

ESD Ratings

Recommended Operating Conditions

Input Supply Voltage Range, VDD . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 14V

Output Voltage Range, VOUT. . . . . . . . . . . . . . . . . . . . . . . . . . . 0.54V to 5.5V

Operating Junction Temperature Range, T . . . . . . . . . . . .-40°C to +125°C

J

Ambient Temperature Range, T . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

A

5V (VR5) Supply Total Supplied Current (Note 9) . . . . . . . . . . . . . . . . . 5mA

5V LDO Supply (VDRV) (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 80mA

Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . 3000V

Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . . 200V

Charged Device Model (Tested per JESD22-C1010-D) . . . . . . . . . . 1000V

Latch-up (Tested per JESD78C; Class 2, Level A) . . . . . . . . . . . . . . . 100mA

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

6. Output current is limited by device thermal dissipation.

7.  is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech

JA

Brief TB379.

8. For  , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

9. Total of current used by pull-ups to SDA, SCL, SALRT, DDC, EN, PG (including push-pull configuration).

Electrical Specifications

V

= 12V. Typical values are at T = +25°C. Boldface limits apply across the operating ambient temperature

DD A

range, T -40°C to +85°C

A

MIN

MAX

PARAMETER

TEST CONDITIONS

(Note 15)

TYP

(Note 15)

UNIT

IC INPUT AND BIAS SUPPLY CHARACTERISTICS

IDD Supply Current

f

= 200kHz

-

26

50

80

mA

V

SW

= 1.33MHz

SW

IDD Device Disabled Current

EN = 0V, SMBus inactive, V = 12V, f

DD SW

= 400kHz

-

20

30

VR5 Reference Output Voltage

V25 Reference Output Voltage

VR6 Reference Output Voltage

VDRV 5V Output Voltage (Note 10)

OUTPUT CHARACTERISTICS

V

> 6V, I < 5mA

4.5

2.25

5.5

4.5

5.0

2.5

6.1

5.25

5.5

2.75

6.6

5.5

DD

For Reference only, VR > 3V

For Reference only, V = 12V

V

DD

V

> 6.0V; 0-80mA

V

DD

Output Voltage Adjustment Range

Output Voltage Set-point Accuracy (Note 12)

V

> V

OUT

+ 1.8V

0.54

-1

-

5.5

1

V

IN

Across line, load, temperature variation

0.72 < V < 5.50

% V

OUT

Output Voltage Set-point Resolution (Note 11)

Output Voltage Positive Sensing Bias Current

Output Voltage Negative Sensing Bias Current

LOGIC INPUT/OUTPUT CHARACTERISTICS

Logic Input Leakage Current

Set using PMBus™ command

VSEN[0,1] P = 4V (negative = sinking)

VSEN[0,1] N = 0V

-

-100

-

±0.025

20

-

100

-

% V

OUT

µA

20

µA

Logic I/O - Multimode Pins

-100

-

100

0.8

-

nA

V

Logic Input Low, V

-

IL

Logic Input High, V

2

-

V

IH

Logic Output Low, V

2mA sinking

0.5

-

V

OL

Logic Output High, V

2mA sourcing

2.25

V

OH

FN7558.3

September 14, 2015

Submit Document Feedback

9

ZL8800

Electrical Specifications

V

= 12V. Typical values are at T = +25°C. Boldface limits apply across the operating ambient temperature

A

DD

range, T -40°C to +85°C (Continued)

A

MIN

MAX

PARAMETER

PWM INPUT/OUTPUT CHARACTERISTICS

PWM Output Low

TEST CONDITIONS

(Note 15)

TYP

(Note 15)

UNIT

2mA sinking

2mA sourcing

Vpwm = 2.5V

-

4.25

-

0.5

-

V

PWM Output High

PWM Tri-state Input Bias Current (PWMH0,1)

OSCILLATOR AND SWITCHING CHARACTERISTICS

Switching Frequency Range

10

µA

200

-5

-

1334

5

kHz

%

Switching Frequency Set-point Accuracy

Minimum SYNC Pulse Width

50% to 50%

150

-10

100

-

ns

Input Clock Frequency Drift Tolerance

PMBus™ Clock Frequency (Note 13)

Maximum allowed drift of external clock

10

400

%

kHz

POWER MANAGEMENT

SOFT-START/ RAMP CHARACTERISTICS

Ton Delay/Toff Delay

Factory default

-

5

-

ms

µs

Ton Delay/Toff Delay Range

Set using PMBus™ command

Turn-on, turn-off delay

Factory default

2

5000

Ramp Delay/Toff Delay Accuracy

Soft-start/Ton Ramp/Toff Ramp Duration

Soft-start/Ton Ramp/Toff Ramp Duration Range

Soft-start/Ton Ramp/Toff Ramp Duration Accuracy

TRACKING

-

-0/+2

5

-

0.5

-

100

-

Set using PMBus™ command

±250

VTRK Input Bias Current

VTRK = 5V

-

70

-

200

2

µA

15

VTRK Regulation Accuracy

100% tracking, V

– VTRK

-2

% V

OUT

POWER-GOOD

Power-good V

Threshold

Hysteresis

Factory default

-

90

5

-

% V

OUT

-

%

OUT

Power-good Delay

Applies to turn-on only (LOW to HIGH transition)

-

1

-

ms

Set using PMBus™ command

0

-

5000

MONITORING AND FAULT MANAGEMENT

INPUT VOLTAGE MONITOR AND FAULT DETECTION

VDD/VIN UVLO Threshold Range

VDD/VIN Monitor Accuracy

2.85

-

16

V

Full Scale (FS) = 14V

-

±2

-

%FS

µs

VDD/VIN Monitor Resolution

±0.15

100

VIN UV/OV Fault Response delay

INPUT CURRENT

Input Current Sense Differential Input Voltage

Input Current Sense Input Offset Voltage

Input Current Sense Accuracy

V

-V

IINP IINN

0

-

20

mV

µV

V -V

IINP IINN

±100

±5

-

% of full scale (20mV)

-

% FS

OUTPUT VOLTAGE MONITOR AND FAULT DETECTION

VOUT Monitor Accuracy

FS = Vset voltage (Vo)

-2

-

2

-

%FS

µs

VOUT Monitor Resolution

-

± 0.15

10

VOUT UV/OV Fault Response Delay

-

FN7558.3

September 14, 2015

Submit Document Feedback

10

ZL8800

Electrical Specifications

V

= 12V. Typical values are at T = +25°C. Boldface limits apply across the operating ambient temperature

A

DD

range, T -40°C to +85°C (Continued)

A

MIN

MAX

PARAMETER

TEST CONDITIONS

OUTPUT CURRENT

(Note 15)

TYP

(Note 15)

UNIT

OUTPUT CURRENT SENSE RESOLUTION

Low Range

±25mV full scale

-

37.5

56.25

75.0

-

µV

Medium Range

± 35mV full scale

±50mV full scale

High Range

OUTPUT CURRENT SENSE INPUT BIAS CURRENT

VOUT Referenced

ISENA0 or ISENA1

ISENB0 or ISENB1

-100

-25

-

100

25

nA

µA

OUTPUT CURRENT SENSE MONITOR AND FAULT DETECTION

Output Current DCR Monitor Temperature

Compensation

Factory default

3900

ppm/°C

Configurable via PMBus™

100

12700 ppm/°C

VMON BIAS MONITOR AND FAULT DETECTION

VMON UVLO Threshold Range

VMON Accuracy (Note 14)

Using VMON pin with 16:1 resistor divider

Full Scale (FS) = 1.15V

2.85

-

5

2

-

V

-2

% FS

µs

VMON Resolution

Full Scale (FS) = 1.15V

-

±0.15

200

VMON UV/OV Fault Response Delay

-

TEMPERATURE SENSING

Tested at +100°C

INTERNAL TEMPERATURE SENSOR

Internal Temperature Accuracy

Internal Temperature Resolution

-5

–

1

5

°C

-

Thermal Protection Threshold

(Junction Temperature)

Factory default

-

-40

-

125

–

-

125

-

Configurable via PMBus™

Thermal Protection Hysteresis

15

EXTERNAL TEMPERATURE SENSOR: XTEMP0 and XTEMP1

External Temperature Accuracy

External Temperature Resolution

Thermal Protection Threshold

Filter capacitance <100pF

-

±5

1

-

°C

-

Factory default

-

-40

-

125

–

-

125

-

Configurable via PMBus™

Thermal protection hysteresis

NOTES:

15

10. Output current is limited by device thermal dissipation.

11. Percentage of Full Scale (FS) with temperature compensation applied.

12. V

OUT

measured at the termination of the VSENxP and VSENxN sense points.

13. For operation at 400kHz, see PMBus™ Power System Management Protocol Specification Part 1, Section 5.2.6.2 for timing parameter limits.

14. Does not include errors due to resistor divider tolerances.

15. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

16. Only 1 output voltage can track the VTRK input: Channel 0, Channel 1 or the output of a 2-phase configuration.

FN7558.3

September 14, 2015

Submit Document Feedback

11

ZL8800

All power management functions can be configured using either

ZL8800 Overview

Digital-DC Architecture Overview

The ZL8800 is an innovative mixed-signal power conversion and

power management IC based on Intersil patented Digital-DC™

technology that provides an integrated, high performance

step-down converter for a wide variety of power supply

applications.

pin configuration techniques described in this document or via

the SMBus interface using PMBus™ commands. Monitoring

parameters can also be preconfigured to provide alerts for

specific conditions. The “PMBus™ Command Summary” on

page 25 contains a listing of all the PMBus™ commands

supported by the ZL8800 and a detailed description of the use of

each of these commands.

Multimode Pins

The ZL8800 DC/DC controller is a dual channel, dual phase

controller based on an architecture that does not require loop

compensation. Adaptive algorithms enable the power converter to

automatically change the operating state to increase efficiency

and overall performance with no user interaction needed.

In order to simplify circuit design, the ZL8800 incorporates

patented multimode pins that allow the user to easily configure

many aspects of the device with no programming. Most power

management features can be configured using these pins. The

multimode pins can respond to four different connections as

shown in Table 2. These pins are sampled when power is applied.

The ZL8800s full digital loop achieves precise control of the

entire power conversion process with no software required

resulting in a very flexible device that is also very easy to use. The

ChargeMode control algorithm is implemented that responds to

output current changes within a single PWM switching cycle,

achieving a smaller total output voltage variation with less output

capacitance than traditional PWM controllers. An extensive set of

power management functions are fully integrated and can be

configured using simple pin connections. The user configuration

can be saved in an internal Nonvolatile Memory (NVM).

Additionally, all functions can be configured and monitored via

the SMBus hardware interface using standard PMBus™

commands, allowing ultimate flexibility. The ZL8800 is compliant

with the PMBus™ Power System Management Protocol

Specification Part I & II version 1.2.

Pin-strap Settings: This is the simplest implementation method,

as no external components are required. Using this method, each

pin can take on one of three possible states: LOW, OPEN, or

HIGH. These pins can be connected to the V25 pin for logic HIGH

settings (excluding VDRVEN, which should be left floating). Using

a single pin, one of three settings can be selected.

TABLE 2. MULTIMODE PIN CONFIGURATION

PIN TIED TO

VALUE

LOW (Logic LOW)

< 0.8 VDC

OPEN (N/C)

No connection

> 2.0 VDC

HIGH (Logic HIGH)

Resistor to SGND

Once enabled, the ZL8800 is immediately ready to regulate

power and perform power management tasks with no

programming required. Advanced configuration options and

real-time configuration changes are available via PMBus™

commands if desired and continuous monitoring of multiple

operating parameters is possible with minimal interaction from a

host controller. Integrated subregulation circuitry enables single

supply operation from any supply between 4.5V and 14V with no

bias supplies needed.

Set by resistor value

V25

LOGIC

HIGH

MULTIMODE

OPEN

The ZL8800 can be configured by simply connecting its pins

according to the tables provided in the following sections.

Additionally, a comprehensive set of online tools and application

notes are available to help simplify the design process. A

demonstration board is also available to help the user become

familiar with the device. This board can be evaluated as a

standalone platform using pin configuration settings. A

Windows™-based GUI is also provided to enable full configuration

and monitoring capability via the SMBus interface and the

included USB cable.

LOGIC

LOW

PIN-STRAP

SETTINGS

RESISTOR

SETTINGS

FIGURE 4. PIN-STRAP AND RESISTOR SETTING

Power Management Overview

Resistor Settings: This method allows a greater range of

adjustability when connecting a finite value resistor (in a

specified range) between the multimode pin and SGND.

Standard 1% resistor values are used, and only every fourth E96

resistor value is used so the device can reliably recognize the

value of resistance connected to the pin while eliminating the

error associated with the resistor accuracy. Up to 31 unique

selections are available using a single resistor.

The ZL8800 incorporates a wide range of configurable power

management features that are simple to implement with no

external components. Additionally, the ZL8800 includes circuit

protection features that continuously safeguard the device and load

from damage due to unexpected system faults. The ZL8800 can

continuously monitor input voltage and current, output voltage and

current, internal temperature and the temperature of 2 external

thermal diodes. A Power-good output signal is also included to

enable power-on reset functionality for an external processor.

FN7558.3

September 14, 2015

Submit Document Feedback

12

ZL8800

SMBus: Almost any ZL8800 function can be configured via the

Output Voltage and VOUT_MAX Selection

(VSET0,1)

The output voltage may be set to any voltage between 0.54V and

5.5V provided that the input voltage is higher than the desired

SMBus interface using standard PMBus™ commands.

Additionally, any value that has been configured using the

pin-strap or resistor setting methods can also be reconfigured

and/or verified via the SMBus. The PMBus™ commands

description section of this document explains the use of the

PMBus™ commands in detail.

output voltage by at least 1.1V. Using the pin-strap method, V

OUT

can be set to any of the voltages shown in Table 4. V

OUT

can also

be set using a PMBus™ command. VOUT_MAX is also

determined by this pin-strap setting, and is 10% greater than the

VSET0 and VSET1 voltage settings.

Configurable Pins

Four operating parameters can be set using the pin-strap or

resistor setting method: SMBus address (pin 5, SA), output

voltage (pins 10 and 11, VSET0,1), switching frequency (pin 44,

SYNC) and input voltage undervoltage lockout (pin 13, UVLO).

TABLE 4.

RVSET (kΩ)

LOW

OPEN

HIGH

10

VOUT (V)

1.00

1.20

2.50

0.60

0.65

0.70

0.75

0.80

0.85

0.90

0.95

1.00

1.05

1.10

1.15

1.20

1.25

RVSET (kΩ)

38.3

42.2

46.4

51.1

56.2

61.9

68.1

75

VOUT (V)

1.30

1.40

1.50

1.60

1.70

1.80

1.90

2.00

2.10

2.20

2.30

2.50

2.80

3.00

3.30

4.00

5.00

The SMBus device address and the output voltage are the only

parameters that must be set by external pins. All other device

parameters can be set via the PMBus™. The device address is set

using the SA pin. The output voltage is set using the VSET0 and

VSET1 pins.

11

SMBus Device Address Selection (SA)

12.1

13.3

14.7

16.2

17.8

When communicating with multiple SMBus devices using the

SMBus interface, each device must have its own unique address

so the host can distinguish between the devices. The device

address can be set according to the pin-strap options listed in

Table 3. Because the ZL8800 is a 2-channel device, the next

higher sequential address after the selected ZL8800 address

should not be used by any device on the SMBus. For example, if

Address 0x26 is used, 0x27 should not be used by any device

sharing the same SMBus (See DDC_CONFIG command for

details). The SMBus address cannot be changed with a PMBus™

command.

82.5

90.9

100

19.6

21.5

23.7

26.1

28.7

31.6

34.8

110

121

133

TABLE 3. SMBus DEVICE ADDRESS SELECTION

147

RSA

SMBus

RSA

(kΩ)

SMBus

ADDRESS

(kΩ)

ADDRESS

162

LOW

OPEN

10

0x26h

0x28h

0x19h

0x1Ah

0x1Bh

0x1Ch

0x1Dh

0x1Eh

0x1Fh

0x20h

0x21h

0x22h

0x23h

0x24h

0x25h

0x26h

0x27h

42.2

46.4

51.1

56.2

61.9

68.1

75

0x28h

0x29h

0x2Ah

0x2Bh

0x2Ch

0x2Dh

0x2Eh

0x2Fh

0x30h

0x31h

0x32h

0x33h

0x34h

0x35h

0x36h

0x37h

178

Switching Frequency Setting (SYNC)

11

The device’s switching frequency set from 200kHz to 1333kHz

using the pin-strap method as shown in Table 5, or by using a

PMBus™ command. The ZL8800 generates the device switching

frequency by dividing an internal precision 16MHz clock by

integers from 11 to 80. 500kHz (n = 32) and 1000kHz (n = 16)

are not recommended operating frequencies; use 533kHz and

1067kHz for best performance.

12.1

13.3

14.7

16.2

17.8

19.6

21.5

23.7

26.1

28.7

31.6

34.8

38.3

82.5

90.9

100

110

121

133

147

162

178

TABLE 5.

RSYNC (kΩ)

SGND

OPEN

HIGH

10

FREQ (kHz)

200

RSYNC kΩ

23.7

FREQ (kHz)

471

400

26.1

533

1067

200

28.7

571

31.6

615

11

222

34.8

727

12.1

242

38.3

800

13.3

267

42.2

842

FN7558.3

September 14, 2015

Submit Document Feedback

13

ZL8800

TABLE 5. (Continued)

using the pin-strap method as shown in Table 6. UVLO can also be

set or changed using the VIN_UV_FAULT_LIMIT command.

RSYNC (kΩ)

14.7

FREQ (kHz)

RSYNC kΩ

46.4

FREQ (kHz)

889

TABLE 6.

296

320

364

400

421

RUVLO

(kΩ)

UVLO

(V)

RUVLO

(kΩ)

UVLO

(V)

16.2

51.1

1067

17.8

56.2

1143

LOW

OPEN

HIGH

26.1

28.7

31.6

34.8

38.3

42.2

Not used

4.5

46.4

51.1

56.2

61.9

68.1

75

7.42

8.18

19.6

61.9

1231

10.8

4.18

4.59

5.06

5.57

6.13

6.75

8.99

21.5

68.1

1333

9.90

The ZL8800 incorporates an internal Phase-locked Loop (PLL) to

clock the internal circuitry. The PLL can be driven by an external

clock source connected to the SYNC pin. When using the internal

oscillator, the SYNC pin can be configured as a clock source for

other Intersil devices.

10.90

12.00

13.20

14.54

16.00

82.5

90.9

100

By default, the SYNC pin is configured as an input. The device will

automatically check for a clock signal on the SYNC pin each time

EN is asserted. The ZL8800’s oscillator will then synchronize with

the rising edge of the external clock.

Once an input undervoltage fault condition occurs, the user may

determine the desired response to the fault condition. The

following input undervoltage protection response options are

available:

The incoming clock signal must be in the range of 200kHz to

1.33MHz and must be stable when the enable pin (EN0, EN1) is

asserted. When using an external clock, the frequencies are not

limited to discrete values as when using the internal clock. The

external clock signal must not vary more than 10% from its initial

value, and should have a minimum pulse width of 150ns. In the

event of a loss of the external clock signal, the output voltage

may show transient overshoot or undershoot.

1. Shut down and stay off until the fault has cleared and the

device has been disabled and reenabled.

2. Shut down, and when the fault is no longer present, attempt

to restart.

3. Shut down and restart continuously after a delay.

The default response from an undervoltage fault is to shut down

and stay off until the fault has cleared and the device has been

disabled and reenabled (#1).

If loss of synchronization occurs, the ZL8800 will automatically

switch to its internal oscillator and switch at its programmed

frequency.

Refer to the PMBus™ Commands section of this document for

details on how to select specific overvoltage fault response

options using the VIN_UV_FAULT_RESPONSE command.

The SYNC pin can also be configured as an output. The device will

run from its internal oscillator and will drive the SYNC pin so

other devices can be synchronized to it. The SYNC pin will not be

checked for an incoming clock signal while in this mode.

When controlling the ZL8800 exclusively through the PMBus™, a

high voltage setting for UVLO can be used to prevent the ZL8800

from being enabled until a lower voltage for UVLO is set using the

VIN_UV_FAULT_LIMIT command.

The switching frequency can be set to any value between 200kHz

and 1.33MHz using a PMBus™ command. The available

frequencies below 1.33MHz are defined by f

= 16MHz/N,

SW

where 11 ≤ N ≤ 80.

Internal Bias Regulators and Input Supply

Connections

If a value other than f

SW

= 16MHz/N is entered using a PMBus™

command, the internal circuitry will select the switching

frequency value using N as a whole number to achieve a value

close to the entered value. For example, if 810kHz is entered, the

device will select 800kHz (N = 20).

The ZL8800 employs internal Low Dropout (LDO) regulators to

supply bias voltages for internal circuitry, allowing it to operate

from a single input supply. The internal bias regulators are as

follows:

VR6: The VR6 LDO provides a regulated 6.1V bias supply for

internal circuitry. It is powered from the VDD pin. A 4.7µF

ceramic X5R or X7R filter capacitor to SGND is required at the

VR6 pin.

Input Voltage Undervoltage Lockout Setting

(UVLO)

The input Undervoltage Lockout (UVLO) prevents the ZL8800 from

operating when the input falls below a preset threshold, indicating

the input supply is out of its specified range. The input voltage

undervoltage lockout threshold can be set between 2.85V and 16V

VR5: The VR5 LDO provides a regulated 5.1V bias supply for

internal circuitry. It is powered from the VDD pin. A 4.7µF

ceramic X5R or X7R filter capacitor to SGND is required at the

VR5 pin. This supply may be used for to provide a pull-up supply

as long as load current does not exceed 5mA.

V25: The V25 LDO provides a regulated 2.5V bias supply for the

main controller circuitry. It is powered from an internal 5V node.

FN7558.3

September 14, 2015

Submit Document Feedback

14

ZL8800

A 4.7µF ceramic X5R or X7R filter capacitor to SGND is required

at the V25 pin.

used as part of an overall inrush current management strategy or

to precisely control how fast a load IC is turned on. The ZL8800

gives the system designer several options for precisely and

independently controlling both the delay and ramp time periods.

VDRV: The VDRV LDO provides a regulated 5.25V bias supply for

external MOSFET driver ICs or DrMOS integrated drivers/FETs. A

4.7µF ceramic X5R or X7R filter capacitor to PGND is required,

however, additional capacitance will be needed as specified by

the MOSFET driver or DrMOS device selected. The maximum

rated output current is 80mA, but device thermal limits must be

considered. The power dissipated by the VDRV supply will be

(VIN - 5.25V) x IDRV, where IDRV is the current supplied by the

VDRV bias supply. VDRV is enabled by leaving the VDRVEN

unconnected (floating) or connecting it to VR5, and is disabled by

connecting VDRVEN to ground.

The Ton-delay time begins when the EN pin is asserted. The

Ton-delay time is set using the PMBus™ command TON_DELAY.

The Ton-rise time enables a precisely controlled ramp to the

nominal V

value that begins once the Ton-delay time has

OUT

expired. The ramp-up is monotonic and its slope may be precisely

set using the PMBus™ command TON_RISE.

The Ton-delay and Ton-ramp times can be set using PMBus™

commands TON_DELAY and TON_RISE over the serial bus

interface. When the Ton-delay time is set to 0ms, the device will

begin its ramp after the internal circuitry has initialized.

NOTE: The internal bias regulators, VR6, VR5 and V25, are not

designed to be outputs for powering other circuitry. The

multimode pins may be connected to the V25 pin for logic HIGH

settings, and the VR5 supply can be used to provide up to 5mA of

pull-up current for the SDA, SCL, SALRT, DDC and PG pins.

The Ton-delay and Ton-ramp times can be set using PMBus™

commands TON_DELAY and TON_RISE over the serial bus

interface. When the Ton-delay time is set to 0ms, the device will

begin its ramp after the internal circuitry has initialized, which

takes approximately 2ms to complete. The Ton-rise time may be

set to values less than 2ms, however the Ton-rise time should be

set to a value greater than 500µs to prevent inadvertent fault

conditions due to excessive inrush current. A lower Ton-rise time

limit can be estimated using the formula: Ton-rise =

Start-Up Procedure

The ZL8800 follows a specific internal start-up procedure after

power is applied to the VDD pin, as shown in Figure 5.

The device requires approximately 70ms to check for specific

values stored in its internal memory. If the user has stored values

in memory, those values will be loaded.

C

*V /I

where C

is the total output capacitance,

OUT OUT LIMIT

OUT

is the output voltage and I

V

is the current limit setting

OUT

LIMIT

for the ZL8800.

Once this process is completed, the device is ready to accept

commands via the serial interface and the device is ready to be

enabled. If the device is to be synchronized to an external clock

source, the clock frequency must be stable prior to asserting the

EN pin. Once enabled, the device requires approximately 2ms

before its output voltage may be allowed to start its ramp-up

process.

Enable

The enable pins (EN0 and EN1) are used to enable and disable

each channel of the ZL8800. When operated as a 2-phase

converter, use EN0 and ground EN1. The enable pins should be

held low whenever a configuration file or script is used to

configure the ZL8800, or a PMBus™ command is sent that could

potentially damage the application circuit. When the ZL8800 is

used in a self-enabled mode, for example, when EN0 or EN1 is

tied to VR5, or to a resistor divider to VIN, the user must consider

the ZL8800's default factory settings. When a configuration file

is used to configure the ZL8800, the factory default settings are

restored to both the user and default stores in order to set the

ZL8800 to an initialized state. Since the default state of the

ZL8800 is to be enabled when the enable pin is high, it is

possible for the ZL8800 to be enabled while the PMBus™

commands are sent to the ZL8800 during the configuration

process.

After the Ton-delay period has expired, the output will begin to

ramp towards its target voltage according to the preconfigured

Ton-rise time.

Internal Memory Check

60ms to 70ms

Input Power Applied

Device will ignore an

enable signal or PMBus™

commands

Pre-ramp delay

minimum 2ms

Power-Good

delay between enable

signal and start of output

ramp. Additional delay may

be added with PMBus™

command

Device Ready

The ZL8800 provides a Power-good (PG0, PG1) signal for each

channel that indicates the output voltage is within a specified

tolerance of its target level and no fault condition exists. By

default, the PG pin will assert if the output is within 10% of the

target voltage. These limits and the polarity of the pin may be

changed using PMBus™ commands.

FIGURE 5. ZL8800 INTERNAL START-UP PROCEDURE

Ton Delay and Rise Times

A PG delay period is defined as the time from when all conditions

within the ZL8800 for asserting PG are met to when the PG pin is

actually asserted. This feature is commonly used instead of using

an external reset controller to control external digital logic. By

default, the ZL8800 PG delay is set equal to 1ms. The PG delay

In some applications, it may be necessary to set a delay from

when an enable signal is received until the output voltage starts

to ramp to its target value. In addition, the designer may wish to

precisely set the time required for V

to ramp to its target

value after the delay period has expired. These features may be

OUT

FN7558.3

September 14, 2015

Submit Document Feedback

15

ZL8800

may be set using a PMBus™ command as described in the

“PMBus™ Command Summary” on page 25.

V_OUT

Desired Output

Voltage

Power Management Functional

Description

Pre-bias voltage

Output Overvoltage Protection

The ZL8800 offers an internal output overvoltage protection

circuit that can be used to protect sensitive load circuitry from

being subjected to a voltage higher than its prescribed limits. A

hardware comparator is used to compare the actual output

voltage (seen at the VSEN pin) to a programmable threshold set

to 15% higher than the target output voltage (the default setting).

If the VSEN voltage exceeds this threshold, the PG pin will

deassert and the device can then respond in a number of ways

as follows:

Time

Ton

Delay

Ton

Rise

V_PREBIAS< V_TARGET

V_OUT

Pre-bias voltage

1. Shut down and stay off until the fault has cleared and the

device has been disabled and reenabled.

Desired Output

Voltage

2. Shut down, and when the fault is no longer present, attempt

to restart.

3. Shut down and restart continuously after a delay.

Time

The default response from an overvoltage fault is to immediately

shut down with no retries (#1).

Ton

Delay

Ton

Rise

Refer to the PMBus™ Commands section of this document for

details on how to select specific overvoltage fault response

options using the VOUT_OV_FAULT_RESPONSE command.

V_PREBIAS> V_TARGET

FIGURE 6. OUTPUT RESPONSES TO PREBIAS VOLTAGES

If a prebias voltage higher than the target voltage exists after the

preconfigured Ton-delay time and Ton-rise time have completed,

the ZL8800 starts switching with a duty cycle that matches the

prebias voltage. This ensures that the ramp-down from the

prebias voltage is monotonic. The output voltage is then ramped

down to the desired output voltage.

Output Prebias Protection

An output prebias condition exists when an externally applied

voltage is present on a power supply's output before the power

supply's control IC is enabled. Certain applications require that

the converter not be allowed to sink current during start-up if a

prebias condition exists at the output. The ZL8800 provides

prebias protection by sampling the output voltage prior to

initiating an output ramp.

If a prebias voltage higher than the overvoltage limit exists, the

device will not initiate a turn-on sequence and will stay off with

an output OV fault recorded.

If a prebias voltage lower than the desired output voltage is

present after the Ton-delay time, the ZL8800 starts switching

with a duty cycle that matches the prebias voltage. This ensures

that the ramp-up from the prebias voltage is monotonic. The

output voltage is then ramped to the desired output voltage at

the ramp rate set by the TON_RISE command.

Output Overcurrent Protection

The ZL8800 can protect the power supply from damage if the

output is shorted to ground or if an overload condition is imposed

on the output. Once the current limit threshold has been selected

(see “Current Limit Configuration” on page 17), the user may

determine the desired response to the fault condition. The

following overcurrent protection response options are available:

The resulting output voltage rise time will vary depending on the

prebias voltage, but the total time elapsed from the end of the

Ton-delay time to when the Ton-rise time is complete and the

output is at the desired value will match the preconfigured ramp

time, (see Figure 6).

1. Shut down and stay off until the fault has cleared and the

device has been disabled and reenabled.

2. Shut down, and when the fault is no longer present, attempt

to restart.

3. Shut down and restart continuously after a delay.

The default response from an overcurrent voltage fault is to shut

down and stay off until the fault has cleared and the device has

been disabled and reenabled (#1).

Refer to the PMBus™ Commands section of this document for

details on how to select specific overvoltage fault response

options using the IOUT_OC_FAULT_RESPONSE command.

FN7558.3

September 14, 2015

Submit Document Feedback

16

ZL8800

The blanking time represents the time when no current

CURRENT SENSING COMPONENTS

measurement is taken. This is to avoid taking a reading just after

a current load step (less accurate due to potential ringing). It is a

configurable parameter from 0 to 832ns.

The ZL8800 uses the inductor DCR current sensing technique.

Current sensing is achieved by selecting an R/C network as

shown in Figure 7.

ZL8800 provides an adjustable maximum full scale sensing

range. Three ranges are available: ±25mV, ±35mV and ±50mV

maximum input voltage.

VIN

VDRV

ZL8800

PWMH

VDD

GH

BST

GL

L

VOUT

By default current sensing is enabled during the inductor current

down slope period of the switching period (D’). In applications

where the steady state duty cycle is >0.5, for example, a 5V to

3.3V converter, the ZL8800 can be configured to sense current

during the inductor up slope period of the switching cycle (D).

PWML

R1

C1

ISENA

ISENB

The user has the option of selecting how many consecutive

overcurrent readings must occur before an overcurrent fault and

subsequent shutdown are initiated. Either 1, 3, 5, 7, 9, 11 or 13

consecutive faults can be selected.

FIGURE 7. DCR CURRENT SENSING

For the voltage across C to reflect the voltage across the DCR of

1

the inductor, the time constant of the inductor must match the

time constant of the RC network. That is:

Once the ISENSE_CONFIG parameters have been selected, the

user must select the desired current limit thresholds and the

resistance of the sensing element.

_RC_{L / DCR}

The current limit thresholds are set with 4 commands:

L

• IOUT_OC_FAULT_LIMIT – this sets the overcurrent threshold

that must be exceeded by the number of consecutive times

chosen in ISENSE_CONFIG.

R1 C1

DCR

For L, use the average of the nominal value and the minimum

value. Include the effects of tolerance, DC bias and switching

frequency on the inductance when determining the minimum

value of L. Use the typical room temperature value for DCR.

• IOUT_UC_FAULT_LIMIT – this is the same as

IOUT_OC_FAULT_LIMIT, but represents the negative current that

flows lower FET during the D’ interval. Large negative currents

can flow during faults such as a higher voltage rail being

shorted to a lower voltage rail.

The value of R should be as small as feasible and no greater

1

than 5kΩ for best signal-to-noise ratio. The designer should

make sure the resistor package size is appropriate for the power

dissipated and include this loss in efficiency calculations. In

• IOUT_AVG_OC_FAULT_LIMIT – this limit is similar to

IOUT_OC_FAULT_LIMIT, but the limit represents an average

reading over several switching cycles. Since it is an average,

the response time is slower, but the limit can be set closer to

the maximum average expected output current.

calculating the minimum value of R , the average voltage across

1

C (which is the average I

· DCR product) is small and can be

1

OUT

neglected. Therefore, the minimum value of R may be

1

approximated by the following equation:

• IOUT_AVG_UC_FAULT_LIMIT – this limit is similar to

IOUT_AVG_OC_FAULT_LIMIT, but represents the negative

current that flows lower FET during the D’ interval.

2

D

V_INV_OUT



²

P_R1



1 D V_OUT



R1_min



Input Current Monitor

where P is the maximum power dissipation specification for

R1

the resistor. Once R1

has been calculated, solve for the

min

The input current can be monitored through the IINN and IINP

pins. When there is no input current being measured through the

IINN and IINP pins, the input current can be estimated using the

measured duty cycle and measured average output current. Fault

detection is not allowed using the estimated input current. This

estimation is enabled by setting IIN_SCALE to zero.

maximum value of C from:

1

L

C1_max



R1_minDCR

and choose the next-lowest readily available value (e.g., for

C1 = 1.86µF, C = 1.5µF is a good choice). Then substitute

max

the chosen value into the same equation and recalculate the

value of R . Choose the 1% resistor standard value closest to this

1

The input current monitor input should be connected across a

current sensing resistor in series with the input supply. The IINP

pin is connected to the input supply side of the current sense

resistor, the IINN pin is connected to the ZL8800 VDD side of the

current sense resistor. Using the IIN_SCALE command, set the

current sense resistor value. Select the current sense resistor

value such that the maximum expected input current times the

current sense resistor value does not exceed the maximum

current sensing input voltage of 20mV.

1

recalculated value of R .

1

Current Limit Configuration

The ZL8800 gives the power supply designer several choices for

the fault response during over or undercurrent condition. The

user can select the number of violations allowed before declaring

fault, a blanking time and the action taken when a fault is

detected. These parameters are configured using the

ISENSE_CONFIG command.

If this feature is not used, IINN and IINP should be tied to VDD.

FN7558.3

September 14, 2015

Submit Document Feedback

17

ZL8800

external resistor string may be used to configure a different

Thermal Overload Protection

tracking ratio. The device that is tracking another output

voltage (slave) must be set to its desired steady-state output

voltage.

The ZL8800 includes an on-chip thermal sensor that continuously

measures the internal temperature of the die. This thermal sensor

is used to provide both over-temperature and under-temperature

protection. If the over-temperature limit is exceeded, or the

temperature falls below the under-temperature limit, the ZL8800

is shut down. The over-temperature and under-temperature limits

are set by the OT_FAULT_LIMIT and UT_FAULT_LIMIT respectively.

The ZL8800 will not attempt to restart until the temperature has

fallen below the OT_WARN_LIMIT for over-temperature faults or

has risen above the UT_WARN_LIMIT for under-temperature faults.

The default temperature limits are +125°C and -45°C, but the

user may set the limits to different values if desired. Note that

setting a higher over-temperature or under-temperature limit may

result in permanent damage to the device. Once the device has

been disabled due to an internal temperature fault, the user may

select one of several fault response options as follows:

The master ZL8800 device in a tracking group is defined as the

device that has the highest target output voltage within the

group. This master device will control the ramp rate of all

tracking devices and is not configured for tracking mode. The

maximum tracking rise time is 1V/ms. The slave device must be

enabled before the master.

Any device that is configured for tracking mode will ignore its

Ton-delay and Ton-rise settings and its output will take on the

turn-on/turn-off characteristics of the reference voltage present

at the VTRK pin.

Tracking mode can be configured by using the TRACK_CONFIG

command.

1. Shut down and stay off until the fault has cleared and the

device has been disabled and reenabled.

Note that current sharing groups that are also configured to track

another voltage do not offer prebias protection; a minimum load

should therefore be enforced to avoid the output voltage from

being held up by an outside source.

2. Shut down, and when the fault is no longer present, attempt

to restart.

V

IN

3. Shut down and restart continuously after a delay.

The default response from an over or under-temperature fault is

to shut down and stay off until the fault has cleared and the

device has been disabled and reenabled (#1).

Q1

ZL8800

Vo2

L1

C

1

Q2

Refer to the PMBus™ Commands section of this document for

details on how to select specific overvoltage fault response

options using the OT_FAULT_RESPONSE and

Vo1

UT_FAULT_RESPONSE commands.

V

OUT

Vo1

Vo2

Voltage Tracking

Numerous high performance systems place stringent demands

on the order in which the power supply voltages are turned on.

This is particularly true when powering FPGAs, ASICs and other

advanced processor devices that require multiple supply voltages

to power a single die. In most cases, the I/O interface operates at

a higher voltage than the core and therefore the core supply

voltage must not exceed the I/O supply voltage according to the

manufacturers' specifications.

TIME

COINCIDENT

V

OUT

The ZL8800 integrates a tracking scheme that allows one of its

outputs (Channel 0 or Channel 1, or the single output in a dual

phase application) to track a voltage that is applied to the VTRK

pin with no external components required. The VTRK pin is an

analog input that, when tracking mode is enabled, configures the

voltage applied to the VTRK pin to act as a reference for the

device’s output regulation.

Vo1

Vo2

TIME

Figure 8 illustrates the typical connection and the two tracking

modes:

RATIOMETRIC

FIGURE 8. TRACKING MODES

• Coincident. This mode configures the ZL8800 to ramp its

output voltage at the same rate as the voltage applied to the

VTRK pin until it reaches its desired output voltage. The device

that is tracking another output voltage (slave) must be set to

its desired steady-state output voltage.

• Ratio-metric. This mode configures the ZL8800 to ramp its

output voltage at a rate that is a percentage of the voltage

applied to the VTRK pin. The default setting is 50%, but an

FN7558.3

September 14, 2015

Submit Document Feedback

18

ZL8800

(noise). Excessive noise on the data and clock lines that cause

Voltage Margining

the voltage on these lines to cross the high and low logic

thresholds of 2.0V and 0.8V respectively will cause command

transmissions to be interrupted and result in slow bus operation

or missed commands. For less than 10 devices on an SMBus a

10kΩ resistor on each line provides good performance.

The ZL8800 offers a simple means to vary its output higher or

lower than its nominal voltage setting in order to determine

whether the load device is capable of operating over its specified

supply voltage range. Margining is controlled through the

OPERATION command.

The ZL8800 accepts most standard PMBus™ commands. When

enabling the device with ON_OFF_CONFIG command, it is

recommended that the enable pin is tied to SGND.

Default margin limits of V

OUT

±5% are preloaded in the factory,

but the margin limits can be modified through PMBus™

commands to be as high as V + 10% or as low as 0V, where

OUT

is the nominal output voltage set point determined by the

V

In addition to bus noise considerations, it is important to ensure

that user connections to the SMBus are compliant to the

PMBus™ command standards. Any device that can malfunction

in a way that permanently shorts SMBus lines will disable

PMBus™ communications. Incomplete PMBus™ commands can

also cause the ZL8800 to halt PMBus™ communications. This

can be corrected by disabling, then reenabling the device.

OUT

VSET pin or the VOUT_COMMAND command.

A safety feature prevents the user from configuring the output

voltage to exceed V

+ 10% under any condition.

OUT

Additionally, the transition rate between the nominal output

voltage and either margin limit can be configured using the

VOUT_TRANSITION_RATE command.

Digital-DC™ Bus

External Voltage Monitoring

The Digital-DC™ Communications (DDC) bus is used to

communicate between Intersil Digital-DC devices, and within the

ZL8800 itself. This dedicated bus provides the communication

channel between devices for features such as sequencing, fault

spreading, and current sharing. The DDC pin must be pulled up to an

external 3.3V or 5.0V supply, (or configured as a push-pull output

using the GLOBAL_USER_CONGFIG command) even if the ZL8800

is operating in stand-alone. In addition, the DDC pin must be pulled

up or configured as a push-pull output before the Enable pin is set

high. Push-pull mode can only be used when the ZL8800 is

operating in stand-alone. The DDC pin on all Digital-DC devices that

utilize sequencing, fault spreading or current sharing must be

connected together. The DDC pin on all Digital-DC devices in an

application should be connected together. A pull-up resistor is

required on the DDC bus in order to guarantee the rise time as

follows:

The voltage monitoring (VMON) pin is available to monitor the

voltage supply for the external driver IC. The VMON input must be

scaled by a 16:1 ratio in order to read-back the VMON voltage

correctly. A 100kΩ and 6.65kΩ resistor divider is recommended.

Overvoltage and undervoltage fault thresholds can be set using

MFR_VMON_OV_FAULT_LIMIT and MFR_ VMON_UV_FAULT_LIMIT

commands. The response to these limits are set using the

VMON_OV_FAULT_RESPONSE and VMON_ UV_FAULT_RESPONSE

commands.

Once the device has been disabled due to VMON fault, the user

may select one of several fault response options as follows:

1. Shut down and stay off until the fault has cleared and the

device has been disabled and reenabled.

2. Shut down, and when the fault is no longer present, attempt

to restart.

Rise time = R * C

PU LOAD

≤ 1 µs

3. Shut down and restart continuously after a delay.

Where R is the DDC bus pull-up resistance and C

PU LOAD

is the

The default response from an over or undervoltage VMON fault is

to shut down and stay off until the fault has cleared and the

device has been disabled and reenabled (#1).

bus loading. The pull-up resistor may be tied to VR5 or to an

external 3.3V or 5V supply as long as this voltage is present prior

to or during device power-up. As a rule of thumb, each device

connected to the DDC bus presents approximately 12pF of

capacitive loading. The ideal design will use a central pull-up

resistor that is well-matched to the total load capacitance. In

power module applications, the user should consider whether to

place the pull-up resistor on the module or on the PCB of the end

application. The minimum pull-up resistance should be limited to

a value that enables any device to assert the bus to a voltage that

will ensure a logic 0 (typically 0.8V at the device monitoring

point) given the pull-up voltage (5V if tied to VR5) and the

pull-down current capability of the ZL8800 (nominally 4mA). As

with SMBus data and clock lines, the DDC data line should be

routed with a closely coupled return or ground plane to minimize

coupled interference (noise). Excessive noise on the DDC signal

can cause the voltage on this line to cross the high and low logic

thresholds of 2V and 0.8V respectively and will cause command

transmissions to be interrupted and result in slow bus operation

or missed commands. For less than 10 devices on the DDC bus a

10kΩ resistor provides good performance.

SMBus Communications

The ZL8800 provides a SMBus digital interface. The ZL8800 can

be used with any standard 2-wire SMBus host device. In addition,

the device is compatible with SMBus version 2.0 and includes an

SALRT line to help mitigate bandwidth limitations related to

continuous fault monitoring. Pull-up resistors are required on the

SMBus. The pull-up resistor may be tied to VR5 or to an external

3.3V or 5V supply as long as this voltage is present prior to or

during device power-up. The ideal design will use a central pull-up

resistor that is well-matched to the total load capacitance. The

minimum pull-up resistance should be limited to a value that

enables any device to assert the bus to a voltage that will ensure

a logic 0 (typically 0.8V at the device monitoring point) given the

pull-up voltage (5V if tied to VR5) and the pull-down current

capability of the ZL8800 (nominally 4mA). A pull-up resistor of

10kΩ is a good value for most applications.

SMBus data and clock lines should be routed with a closely

coupled return or ground plane to minimize coupled interference

FN7558.3

September 14, 2015

Submit Document Feedback

19

ZL8800

TON_RISE commands and choosing appropriate delay and rise

Phase Spreading

durations such that sequel devices start after their associated

prequel devices. The drawback to this method is that if a prequel

device fails to start properly, its sequel device will still start and

ramp on according to its delay and rise time settings.

When multiple point of load converters share a common DC

input supply, it is desirable to adjust the clock phase offset of

each device such that not all devices have coincident rising

edges. Setting each converter to start its switching cycle at a

different point in time can dramatically reduce input capacitance

requirements. Since the peak current drawn from the input

supply is effectively spread out over a period of time, the peak

Fault Spreading

Digital DC devices can be configured to broadcast a fault event

over the DDC bus to the other devices in the group. When a fault

occurs and the device is configured to shut down on a fault, the

device will shut down and broadcast the fault event over the DDC

bus. The other devices on the DDC bus will shut down together if

configured to do so, and will attempt to restart in their prescribed

order if configured to do so.

current drawn at any given moment is reduced and the power

2

losses proportional to I

are reduced.

RMS

In order to enable phase spreading, all converters must be

synchronized to the same switching clock. Configuring the SYNC

pin is described in “Configurable Pins” on page 13. Selecting the

phase offset for the device is accomplished by selecting a device

address according to the following equation:

Active Current Sharing

The two channels of the ZL8800 can be used in parallel to create

a dual phase power rail. The device outputs will share the current

equally within a few percent.

Phase offset = device address x 45°

This behavior is illustrated in Table 7:

TABLE 7.

Figure 9 shows a typical connection for a dual phase application.

When used in this configuration the ZL8800 can current share

between phases without utilizing output voltage droop.

PHASE OFFSET

(°)

PHASE OFFSET

(°)

ADDRESS LSB

0

1

2

3

4

5

6

7

0

8

9

A

B

C

D

E

F

0

V

IN

45

90

135

180

225

270

315

135

180

225

270

315

V

OUT

ZL8800

VIN

The phase offset of each device may also be set to any value

between 0° and 360° in 22.5° increments using the

INTERLEAVE PMBus™ command.

Output Sequencing

A group of Intersil devices may be configured to power up in a

predetermined sequence. This feature is especially useful when

powering advanced processors, FPGAs and ASICs that require

one supply to reach its operating voltage prior to another supply

reaching its operating voltage in order to avoid latch-up from

occurring. Multidevice sequencing can be achieved by

configuring each device using the SEQUENCE PMBus™

command.

FIGURE 9. DUAL PHASE EXAMPLE

Multiple device sequencing is achieved by issuing PMBus™

commands to assign the preceding device in the sequencing

chain as well as the device that will follow in the sequencing

chain.

Temperature Monitoring Using XTEMP Pin

Each channel of the ZL8800 supports measurement of an

external device temperature using either a thermal diode

integrated in a processor, FPGA or ASIC, or using a discrete

diode-connected 2N3904 NPN transistor. Figure 10 on page 21

illustrates the typical connections required. A noise filtering

capacitor, not exceeding 100pF, should be connected across the

external temperature sensing device. The external temperature

sensors can be used to provide the temperature reading for

over-temperature and under-temperature faults. The external

sensors can also be used to provide more accurate temperature

compensation for inductor DCR current sensing by being placed

The enable (EN) pins of all devices in a sequencing group must be

tied together and driven high to initiate a sequenced turn-on of

the group. Enable must be driven low to initiate a sequenced

turnoff of the group.

Sequencing can also be accomplished by connecting the enable

pin of a sequel device to the power-good pin of a prequel device.

Sequencing is also achieved by using the TON_DELAY and

FN7558.3

September 14, 2015

Submit Document Feedback

20

ZL8800

close to the inductor. These options for the external temperature

VIN

sensors are selected using the USER_CONFIG PMBus™

command.

QH

QL

XTEMPxP

100 pF

ZL

L

ZL8800

VOUT

C

2N3904

XTEMPxN

Discrete NPN

FIGURE 11. SYNCHRONOUS BUCK CONVERTER

Figure 11 illustrates the basic synchronous buck converter

topology showing the primary power train components. This

converter is also called a step-down converter, as the output

voltage must always be lower than the input voltage.

µP

FPGA

DSP

XTEMPxP

100pF

ZL

ASIC

XTEMPxN

DUAL OUTPUT PWM PER CHANNEL

The ZL8800 has been designed to provide independent upper

and lower FET drive signals to a 2-input MOSFET driver such as

the ZL1505.

Embedded Thermal Diode

FIGURE 10. EXTERNAL TEMPERATURE MONITORING

The ZL8800 utilizes adaptive dead time control to improve the

power conversion efficiency. The ZL8800 monitors the power

converter’s operating conditions and continuously adjusts the

turn-on and turn-off timing of the high-side and low-side driver

input signals to optimize the overall efficiency of the power supply.

Nonvolatile Memory and Security Features

The ZL8800 has internal nonvolatile memory where user

configurations are stored. Integrated security measures ensure

that the user can only restore the device to a level that has been

made available to them. During the initialization process, the

ZL8800 checks for stored values contained in its internal

non-volatile memory. The ZL8800 offers two internal memory

storage units that are accessible by the user as follows:

The ZL8800 can also be used with single-ended DrMOS

integrated driver and MOSFET devices. Power supplies using

DrMOS devices can be made smaller than discrete solutions

utilizing separate drivers and MOSFETs, but at a slightly lower

efficiency. The option to use DrMOS or drivers and discrete

MOSFETs is set using the USER_CONFIG command.

• Default Store: A power supply module manufacturer may want

to protect the module from damage by preventing the user

from being able to modify certain values that are related to the

physical construction of the module. In this case, the module

manufacturer would use the Default Store and would allow the

user to restore the device to its default setting but would

restrict the user from restoring the device to the factory

settings.

Power Train Component Selection

The ZL8800 is a dual output or dual phase synchronous buck

converter that uses external Drivers, MOSFETs, inductors and

capacitors to perform the power conversion process. The proper

selection of the external components is critical for optimized

performance.

• User Store: The manufacturer of a piece of equipment may

want to provide the ability to modify certain power supply

settings while still protecting the equipment from modifying

values that can lead to a system level fault. The equipment

manufacturer would use the User Store to achieve this goal.

To select the appropriate external components for the desired

performance goals, the power supply requirements listed in

Table 8 must be known.

TABLE 8. POWER SUPPLY REQUIREMENTS

The User Store takes priority over the Default Store. If there are

no values set in the User or Default Store, then the device will use

the pin-strap setting value.

PARAMETER

EXAMPLE VALUE

Input Voltage (V

)

12V

1.2V

30A

IN

Output Voltage (V

)

OUT

DC/DC Converter Design

Output Current (I

)

OUT

The ZL8800 operates as a voltage-mode, synchronous buck

converter with a selectable constant frequency pulse width

modulator (PWM) control scheme that uses external driver,

MOSFETs, capacitors and an inductor to perform power

conversion.

Output Voltage Ripple (V

)

1% of V

OUT

orip

Output Load Step (I

)

50% of I

o

ostep

Output Load Step Rate

10A/µs

Output Deviation Due to Load Step

Maximum PCB Temperature

Desired Efficiency

±2%

85°C

90%

Other Considerations

Optimize for small size

FN7558.3

September 14, 2015

Submit Document Feedback

21

ZL8800

I

is given by:

DESIGN GOAL TRADE-OFFS

Lrms

The design of the buck power stage requires several

2



I_L

12



I_Lrms I_OUT²

compromises among size, efficiency and cost. The inductor core

loss increases with frequency, so there is a trade-off between a

small output filter made possible by a higher switching frequency

and getting better power supply efficiency. Size can be decreased

by increasing the switching frequency at the expense of

efficiency. Cost can be minimized by using through-hole

inductors and capacitors; however these components are

physically large.

Where I

is the maximum output current. Next, calculate the

OUT

core loss of the selected inductor. Since this calculation is

specific to each inductor and manufacturer, refer to the chosen

inductor datasheet. Add the core loss and the ESR loss and

compare the total loss to the maximum power dissipation

recommendation in the inductor datasheet.

To start the design, select a switching frequency based on

Table 9. This frequency is a starting point and may be adjusted as

the design progresses.

OUTPUT CAPACITOR SELECTION

Several trade-offs must also be considered when selecting an

output capacitor. Low ESR values are needed to have a small

TABLE 9. CIRCUIT DESIGN CONSIDERATIONS

output deviation (V

) during transient load steps and low output

step

FREQUENCY RANGE

200 to 400kHz

EFFICIENCY

Highest

CIRCUIT SIZE

Larger

voltage ripple (ΔV). However, capacitors with low ESR, such as X5R

and X7R dielectric ceramic capacitors, also have relatively low

capacitance values. Many designs can use a combination of high

capacitance devices and low ESR devices in parallel.

400 to 800kHz

Moderate

Lower

Smaller

800kHz to 1.33MHz

Smallest

For high ripple currents, a low capacitance value can cause a

significant amount of output voltage ripple. Likewise, in high

transient load steps, a relatively large amount of capacitance is

needed to minimize the output voltage deviation while the

inductor current ramps up or down to the new steady state

output current value.

INDUCTOR SELECTION

The output inductor selection process must include several

trade-offs. A high inductance value will result in a low ripple

current (ΔI ), which will reduce output capacitance and produce a

L

low output ripple voltage, but may also compromise output

transient load performance. Therefore, a balance must be struck

between output ripple and optimal load transient performance. A

good starting point is to select the output inductor ripple equal to

As a starting point, apportion one-half of the output ripple

voltage to the capacitor ESR and the other half to capacitance, as

shown in the following equations:

I_L

30 to 50% of the maximum output current (I

).

OUT

C_OUT



V

ΔI = 0.5* I

OUT

L

8 f_sw

2

Now the output inductance can be calculated using the following

equation, where V is the input voltage:

IN

V

ESR 





V_OUT

V_IN

2I_L





V_OUT 1



Use these values to make an initial capacitor selection, using a

single capacitor or several capacitors in parallel.





L 

f_swI_L

After a capacitor has been selected, the resulting output voltage

ripple can be calculated using the following equation:

The average inductor current is equal to the maximum output

current. The peak inductor current (I ) is calculated using the

Lpk

is the maximum output current:

I_L

V  I_L ESR 

8 f_swC_OUT

following equation where I

OUT

I

I_Lpk I_OUT



Because each part of this equation was made to be less than or

equal to half of the allowed output ripple voltage, the ΔV should

be less than the desired maximum output ripple.

2

Select an inductor rated for the average DC current and with

saturation current rating above the peak current calculated above.

INPUT CAPACITOR

Once an inductor is selected, the DCR and core losses in the

inductor are calculated. Use the DCR specified in the inductor

manufacturer’s datasheet.

It is highly recommended that dedicated input capacitors be

used in any point-of-load design, even when the supply is

powered from a heavily filtered 5V or 12V “bulk” supply from an

off-line power supply. This is because of the high RMS ripple

current that is drawn by the buck converter topology. This ripple

2

P

 DCR I_Lrms

LDCR

(I

) can be determined from the following equation:

inRMS

I_inRMS I_OUT D

FN7558.3

September 14, 2015

Submit Document Feedback

22

ZL8800

Without capacitive filtering near the power supply circuit, this

MOSFET THERMAL CHECK

current would flow through the supply bus and return planes,

coupling noise into other system circuitry. The input capacitors

should be rated above the ripple current calculated above and

the maximum expected input voltage.

Once the power dissipations for QH and QL have been calculated,

the MOSFET’s junction temperature can be estimated. Using the

junction-to-case thermal resistance (R ) given in the MOSFET

th

manufacturer’s datasheet and the expected maximum printed

circuit board temperature, calculate the junction temperature as

follows:

QL SELECTION

The bottom or lower MOSFET should be selected with the lowest





T_{j max} T_pcb P  R_th

Q

possible r

cost.

while maintaining the desired circuit size and

DS(ON)

To calculate power losses and junction temperature rise in

DrMOS devices, consult the datasheet and application notes for

the DrMOS device selected.

Calculate the RMS current in QL as follows:

I_QLRMS I_OUT 1 D

EFFICIENCY OPTIMIZED DRIVER DEAD TIME CONTROL

Calculate the power dissipated due to r

as follows:

DS(ON)

The ZL8800 utilizes a closed loop algorithm to optimize the dead

time applied between the gate drive signals for the top and

bottom FETs. In a synchronous buck converter, the MOSFET drive

circuitry must be designed such that the top and bottom

MOSFETs are never in the conducting state at the same time.

Potentially damaging currents flow in the circuit if both top and

bottom MOSFETs are simultaneously on for periods of time

exceeding a few nanoseconds. Conversely, long periods of time in

which both MOSFETs are off reduce overall circuit efficiency by

allowing current to flow in their parasitic body diodes.

2

P  R_DSON



I_botrms



QL

Note that the r

given in the manufacturer’s datasheet is

DS(ON)

measured at +25°C. The actual r

in the end-use

DS(ON)

application will be much higher. Select a candidate MOSFET, and

calculate the required gate drive current as follows:

I_g f_SW Q_g

MOSFETs with lower r

DS(ON)

tend to have higher gate charge

It is therefore advantageous to minimize this dead time to

provide optimum circuit efficiency. In the first order model of a

buck converter, the duty cycle is determined by the equation:

requirements, which increases the current and resulting power

required to turn them on and off.

QH SELECTION

V_OUT

D 

In addition to the r

loss and gate charge loss, QH also has

DS(ON)

switching loss. Select QH with a lower gate charge, keeping in

mind that QH’s r will be higher as a result. As was done

V_IN

DS(ON)

However, non-idealities exist that cause the real duty cycle to

extend beyond the ideal. Dead time is one of those nonidealities

that can be manipulated to improve efficiency. The ZL8800 has

an internal algorithm that constantly adjusts dead time

nonoverlap to minimize duty cycle, thus maximizing efficiency.

This circuit will null out dead time differences due to component

variation, temperature and loading effects. This algorithm is

independent of application circuit parameters such as MOSFET

type, gate driver delays, rise and fall times and circuit layout. In

addition, it does not require drive or MOSFET voltage or current

waveform measurements. Adaptive dead time is enabled using

the DEADTIME_CONFIG PMBus™ command. Adaptive dead time

is only effective when a discrete driver (such as the ZL1505) and

MOSFETs are used. When DrMOS devices are selected using

USER_CONFIG, adaptive dead time is automatically disabled.

Dead time minimum and maximum limits can be set using the

DEADTIME PMBus™ command.

with QL, calculate the RMS current as follows:

I_QHRMS I_OUT D

2





P

 R_DSONI_QHRMS

QH

Next, calculate the switching time using:

Q_g

t_SW



I_DR

Where Q is the gate charge of the selected QH and I is the

DR

g

peak gate drive current available from the gate drive IC.

To calculate the switching time, use the ZL1505s minimum

guaranteed drive current of 3 A for a conservative design. Using

the calculated switching time, calculate the switching power loss

in QH using:

Monitoring via SMBus

P

 V_INMt_sw I_OUT f_sw

swtop

A system controller can monitor a wide variety of different

ZL8800 parameters through the SMBus interface. The device

can monitor for fault conditions by monitoring the SALRT pin,

which will be asserted when any number of preconfigured fault

conditions occur.

The total power dissipated by QH is given by the following

equation:

P_QHtot P  P

QH

swtop

FN7558.3

September 14, 2015

Submit Document Feedback

23

ZL8800

The device can also be monitored continuously for any number of

power conversion parameters including but not limited to the

following:

The PMBus™ Host should respond to SALRT as follows:

1. ZL device pulls SALRT Low.

2. PMBus™ Host detects that SALRT is now low, performs

transmission with Alert Response Address to find which ZL

device is pulling SALRT low.

• Input voltage

• Output voltage

3. PMBus™ Host talks to the ZL device that has pulled SALRT

low. The actions that the host performs are up to the System

Designer.

• Input current

• Output current

• Internal junction temperature

• Temperature of an external device

• Switching frequency

• Duty cycle

If multiple devices are faulting, SALRT will still be low after doing

the above steps and will require transmission with the Alert

Response Address repeatedly until all faults are cleared.

Please refer to the PMBus™ Commands section of this document

for details on how to monitor specific parameters via the SMBus

interface.

• Fault status information

FN7558.3

September 14, 2015

Submit Document Feedback

24

ZL8800

PMBus™ Command Summary

DATA

TYPE FORMAT

DEFAULT

VALUE

CODE

COMMAND NAME

DESCRIPTION

DEFAULT SETTING

00h PAGE

Selects Controller 0, 1, or both

Enable/disable, margin settings

On/off configuration settings

Clears faults

R/W

BIT

00h

17h

N/A

13h

Both controllers addressed

01h OPERATION

Immediate off, nominal margin

02h ON_OFF_CONFIG

03h CLEAR_FAULTS

ENABLE pin control, active high

Write N/A

N/A

11h STORE_DEFAULT_ALL

12h RESTORE_DEFAULT_ALL

15h STORE_USER_ALL

16h RESTORE_USER_ALL

20h VOUT_MODE

Stores values to default store

Restores values from default store

Stores values to user store

Restores values from user store

N/A

Reports V

OUT

mode and exponent

set-point

Read

BIT

Linear Mode, Exponent = -13

21h VOUT_COMMAND

23h VOUT_CAL_OFFSET

Sets nominal V

OUT

R/W L16u

Pin-strap Setting

0V

Applies offset voltage to V

OUT

set-point

0000h

1.1 X VOUT_COMMAND pin-strap

setting

24h VOUT_MAX

Sets maximum V

OUT

set-point

R/W L16u

1.05 x VOUT_COMMAND pin-strap

setting

25h VOUT_MARGIN_HIGH

26h VOUT_MARGIN_LOW

27h VOUT_TRANSITION_RATE

Sets V

set-point during margin high

OUT

0.95 x VOUT_COMMAND pin-strap

setting

Sets V

set-point during margin low

transition rate during margin

OUT

R/W

L11

BA00h

0000h

1V/ms

commands

28h VOUT_DROOP

Sets V/I slope

R/W

L11

0mV/A

33h FREQUENCY_SWITCH

Sets switching frequency

Pin-strap setting

Configures phase offset during group

operation

37h INTERLEAVE

R/W

BIT

Set by pin-strapped PMBus™ address

38h IOUT_CAL_GAIN

Sets impedance of current sense circuit R/W

Sets an offset to I sense circuit R/W

L11

AA66h

0000h

0.3mΩ

39h IOUT_CAL_OFFSET

0A

OUT

1.15 x VOUT_COMMAND pin-strap

setting

40h VOUT_OV_FAULT_LIMIT

41h VOUT_OV_FAULT_RESPONSE

44h VOUT_UV_FAULT_LIMIT

45h VOUT_UV_FAULT_RESPONSE

46h IOUT_OC_FAULT_LIMIT

Sets the V

overvoltage fault threshold R/W L16u

OUT

Sets the V

overvoltage fault response R/W

undervoltage fault

BIT

80h

Disable, no retry

OUT

Sets the V

threshold

0.85 x VOUT_COMMAND pin-strap

setting

R/W L16u

Sets the V

undervoltage fault response R/W

BIT

80h

Disable, no retry

20 A

OUT

Sets the I

threshold

peak overcurrent fault

OUT

R/W

L11

DA80h

Sets the I

threshold

valley undercurrent fault

OUT

4Bh IOUT_UC_FAULT_LIMIT

R/W

L11

-1 x IOUT_OC_FAULT_LIMIT

4Fh OT_FAULT_LIMIT

50h OT_FAULT_RESPONSE

51h OT_WARN_LIMIT

52h UT_WARN_LIMIT

53h UT_FAULT_LIMIT

Sets the over-temperature fault limit

L11

BIT

EBE8h

80h

+125˚C

Sets the over-temperature fault response R/W

Sets the over-temperature warning limit R/W

Sets the under-temperature warning limit R/W

Disable, no retry

+110°C

-30°C

L11

EB70h

DC40h

E530h

Sets the under-temperature fault limit

R/W

-45°C

Sets the under-temperature fault

response

54h UT_FAULT_RESPONSE

55h VIN_OV_FAULT_LIMIT

BIT

80h

Disable, no retry

14V

Sets the V overvoltage fault threshold R/W

IN

L11

D380h

FN7558.3

September 14, 2015

Submit Document Feedback

25

ZL8800

PMBus™ Command Summary (Continued)

DATA

TYPE FORMAT

DEFAULT

VALUE

CODE

COMMAND NAME

DESCRIPTION

Sets the V overvoltage fault response

DEFAULT SETTING

Disable, no retry

56h VIN_OV_FAULT_RESPONSE

57h VIN_OV_WARN_LIMIT

R/W

BIT

80h

IN

Sets the V overvoltage warning

IN

threshold

L11

D360h

13.5V

Sets the V undervoltage warning

IN

threshold

1.03 x VIN_UV_FAULT_LIMIT

pin-strap setting

58h VIN_UV_WARN_LIMIT

R/W

L11

N/A

59h VIN_UV_FAULT_LIMIT

Sets the V undervoltage fault threshold R/W

IN

L11

BIT

N/A

80h

Pin-strap setting

Disable, no retry

5Ah VIN_UV_FAULT_RESPONSE

Sets the V undervoltage fault response R/W

IN

Sets the voltage threshold for Power-good

indication

0.9 x VOUT_COMMAND pin-strap

setting

5Eh POWER_GOOD_ON

60h TON_DELAY

61h TON_RISE

R/W L16u

N/A

CA80h

0000h

N/A

Sets the delay time from enable to V

rise

OUT

R/W

L11

5ms

Sets the rise time of V

and TON_DELAY

after ENABLE

OUT

5ms

Sets the delay time from DISABLE to start

of V fall

64h TOFF_DELAY

65h TOFF_FALL

0ms

OUT

Sets the fall time for V

and TOFF_DELAY

after DISABLE

OUT

1.0 x TON_RISE

78h STATUS_BYTE

79h STATUS_WORD

7Ah STATUS_VOUT

7Bh STATUS_IOUT

7Ch STATUS_INPUT

7Dh STATUS_TEMP

Summary of most critical faults

Summary of critical faults

Read

BIT

00h

0000h

00h

no faults

Reports V

warnings/faults

OUT

Reports I

00h

OUT

Reports input warnings/faults

00h

Reports temperature warnings/faults

00h

Reports communication, memory, logic

errors

7Eh STATUS_CML

Read

BIT

00h

no errors

no faults

Reports voltage monitoring/clock

synchronization faults

80h STATUS_MFR_SPECIFIC

88h READ_VIN

89h READ_IIN

8Bh READ_VOUT

8Ch READ_IOUT

Reports input voltage measurement

Reports input current measurement

Reports output voltage measurement

Reports output current measurement

Read L11

Read L16u

Read L11

N/A

Reports internal temperature

measurement

8Dh READ_TEMPERATURE_1

8Eh READ_TEMPERATURE_2

Read L11

N/A

Reports external temperature

measurement

94h READ_DUTY_CYCLE

95h READ_FREQUENCY

99h MFR_ID

Reports actual duty cycle

Read L11

N/A

Reports actual switching frequency

Sets a user defined identification

Sets a user defined revision

N/A

R/W

ASC

<null>

9Bh MFR_REVISION

9Ch MFR_LOCATION

9Dh MFR_DATE

Sets a user defined location identifier

Sets a user defined date

9Eh MFR_SERIAL

ADh IC_DEVICE_ID

AEh IC_DEVICE_REV

Sets a user defined serialized identifier

Reports device identification information Read CUS 49A02400h Intersil, ZL8800

Reports device revision information Read CUS 00000000h Initial Release

FN7558.3

September 14, 2015

Submit Document Feedback

26

ZL8800

PMBus™ Command Summary (Continued)

DATA

TYPE FORMAT

DEFAULT

VALUE

CODE

COMMAND NAME

DESCRIPTION

DEFAULT SETTING

B0h USER_DATA_00

BFh DEADTIME_MAX

Sets a user defined data

R/W

ASC

BIT

N/A

<null>

Sets the max dead time value for the

adaptive dead time

3838h

56ns, 56ns

Downslope, 5 fault count, 256ns

blanking, low range

D0h ISENSE_CONFIG

D1h USER_CONFIG

D2h IIN_CAL_GAIN

D3h DDC_CONFIG

Configures current sensing circuitry

Configures several user-level features

R/W

BIT

4204h

0402h

C200h

N/A

Enable XTEMP0, 1, PG open-drain,

DRMOS enabled

Sets the resistance of the input current

sensing resistor

2mΩ

Configures the DDC addressing and

current sharing

Set by pin-strapped PMBus™ address

Sets the delay between PG threshold and

PG assertion

D4h POWER_GOOD_DELAY

D6h INDUCTOR

R/W

L11

BA00h

B23D

1ms

Sets the inductor value

0.56µH

5%

% MARGIN_HIGH, LOW above/below

VOUT_COMMAND

D7h VOUT_MARGIN_RATIO

CA80h

Configures output voltage OV/UV fault

detection

Low-side FET off on fault, 1 violation

triggers fault.

D8h OVUV_CONFIG

D9h XTEMP_SCALE

DAh XTEMP_OFFSET

R/W

BIT

L11

00h

Calibrates external temperature sensor

BA00h

0000h

1/°C

Offset calibration for external

temperature sensor

No offset

DCh TEMPCO_CONFIG

DDh DEADTIME

Sets tempco settings

R/W

BIT

27h

3900ppm/°C

16ns/16ns

Sets default dead time settings

L8s

1010h

Configures the adaptive dead time

optimization mode

Adaptive dead time enabled,

8ns/8ns

DEh DEADTIME_CONFIG

R/W

BIT

0808h

DFh ASCR_CONFIG

E0h SEQUENCE

Configures the ASCR settings

R/W

BIT

015A0100h Gain = 256, Residual = 90

DDC rail sequencing configuration

Configures voltage tracking modes

Configures group ID, fault spreading,

00h

Prequel and sequel disabled

Tracking disabled

E1h TRACK_CONFIG

Ignore broadcast, sequenced

shutdown

E2h DDC_GROUP

R/W

BIT

000000h

N/A

OPERATION and V

OUT

E4h DEVICE_ID

Returns the device identifier string

Read ASC

ZL8800, current revisions

Disable, no retry

Configures the I

response

overcurrent fault

OUT

E5h MFR_IOUT_OC_FAULT_RESPONSE

R/W

Read

R/W

BIT

L11

BIT

80h

Configures the I

response

undercurrent fault

OUT

E6h MFR_IOUT_UC_FAULT_RESPONSE

E7h IOUT_AVG_OC_FAULT_LIMIT

E8h IOUT_AVG_UC_FAULT_LIMIT

E9h USER_GLOBAL_CONFIG

EAh SNAPSHOT

80h

N/A

Disable, no retry

Sets the I

threshold

average overcurrent fault

OUT

0.8 x IOUT_OC_FAULT_LIMIT

0.8 x IOUT_UC_FAULT_LIMIT

Numerous device settings

<null>

Sets the I

threshold

average undercurrent fault

OUT

N/A

Sets options pertaining to advanced

features

0000h

N/A

32-byte read back of parametric and

status values

Indicates recently saved parameter

values

EBh BLANK_PARAMS

FFF...FFFh <null>

00000000h <null>

Configures fault group compatibility with

older Intersil digital power devices

F0h LEGACY_FAULT_GROUP

FN7558.3

September 14, 2015

Submit Document Feedback

27

ZL8800

PMBus™ Command Summary (Continued)

DATA

TYPE FORMAT

DEFAULT

VALUE

CODE

COMMAND NAME

DESCRIPTION

DEFAULT SETTING

F3h SNAPSHOT_CONTROL

F4h RESTORE_FACTORY

Snapshot feature control command

R/W

BIT

N/A

Restores device to the hard-coded default

values

Write N/A

Sets the VMON overvoltage fault

threshold

F5h MFR_VMON_OV_FAULT_LIMIT

R/W

L11

D300h

12V

Sets the VMON undervoltage fault

threshold

F6h MFR_VMON_UV_FAULT_LIMIT

F7h MFR_READ_VMON

CA40h

N/A

4.5V

N/A

Reads the VMON voltage

Read L11

Configures the VMON overvoltage fault

response

F8h VMON_OV_FAULT_RESPONSE

R/W

BIT

80h

Disable, no retry

Configures the VMON undervoltage fault

response

F9h VMON_UV_FAULT_RESPONSE

80h

01h

Disable, no retry

FAh SECURITY_LEVEL

FBh PRIVATE_PASSWORD

FCh PUBLIC_PASSWORD

FDh UNPROTECT

Reports the security level

Read Hex

Public security level

Sets the private password string

Sets the public password string

R/W

ASC

00…00h <null>

FF…FFh N/A

Identifies which commands are protected R/W Custom

PMBus™ Data Formats

Linear-11 (L11)

L11 data format uses 5-bit two’s compliment exponent (N) and 11-bit two’s compliment mantissa (Y) to represent real world decimal

value (X).

Data Byte High

Data Byte Low

7 6 5 4 3 2 1 0

Exponent (N)

Mantissa (Y)

N

Relation between real world decimal value (X), N and Y is: X = Y·2

Linear-16 Unsigned (L16u)

L16u data format uses a fixed exponent (hard-coded to N = -13h) and a 16-bit unsigned integer mantissa (Y) to represent real world

-13

decimal value (X). Relation between real world decimal value (X), N and Y is: X = Y·2

Linear-16 Signed (L16s)

L16s data format uses a fixed exponent (hard-coded to N = -13h) and a 16-bit two’s compliment mantissa (Y) to represent real world

decimal value (X).

-13

Relation between real world decimal value (X), N and Y is: X = Y·2

Bit Field (BIT)

Breakdown of Bit Field is provided in “PMBus™ Command Detail” on page 29.

Custom (CUS)

Breakdown of Custom data format is provided in “PMBus™ Command Detail” on page 29. A combination of Bit Field and integer are

common type of Custom data format.

ASCII (ASC)

A variable length string of text characters uses ASCII data format.

FN7558.3

September 14, 2015

Submit Document Feedback

28

ZL8800

PMBus™ Command Detail

PAGE (00h)

Definition: Selects Controller 0, Controller 1 or both Controllers 0 and 1 to receive commands. All commands following this command

will be received and acted on by the selected controller or controllers.

Data Length in Bytes: 1

Data Format: Bit Field

Type: R/W

Protectable: No

Default Value: 00h (Page 0)

Units: N/A

COMMAND

Format

PAGE (00h)

Bit Field

Bit Position

Access

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

0

BITS 7:4

BITS 3:0

0000

PAGE

0000

1111

0

1

0001

1111

Both

OPERATION (01h)

Definition: Sets Enable, Disable and V

Margin settings. Data values of OPERATION that force margin high or low only take effect

OUT

when the MGN pin is left open (i.e., in the NOMINAL margin state). This command can also be monitored to read the operating state of

the device on bits 7:6.

Paged or Global: Paged

Data Length in Bytes: 1

Data Format: Bit Field

Type: R/W

Protectable: Yes

Default Value: 00h (immediate off)

Units: N/A

COMMAND

Format

OPERATION (01h)

Bit Field

Bit Position

Access

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

0

BITS 3:0

BITS 7:6

BITS 5:4

00

(NOT USED)

UNIT ON OR OFF

MARGIN STATE

N/A

00

0000

Immediate off

(No sequencing)

01

00

Soft off

N/A

(With sequencing)

10

00

01

10

0000

On

Nominal

Margin Low

Margin High

NOTE: Bit combinations not listed above may cause command errors.

FN7558.3

September 14, 2015

Submit Document Feedback

29

ZL8800

ON_OFF_CONFIG (02h)

Definition: Configures the interpretation and coordination of the OPERATION command and the ENABLE pin (EN).

Paged or Global: Paged

Data Length in Bytes: 1

Data Format: Bit Field

Type: R/W

Protectable: Yes

Default Value: 17h (ENABLE pin control, active high, turn off output immediately – no ramp down)

Units: N/A

COMMAND

Format

ON_OFF_CONFIG (02h)

Bit Field

Bit Position

Access

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

0

1

0

1

BIT NUMBER

PURPOSE

Not Used

BIT VALUE

000

MEANING

7:5

Not Used

Device starts any time power is present regardless of ENABLE pin or

OPERATION command states.

000

Sets the default to either operate any time

power is present or for the on/off to be

controlled by ENABLE pin, OPERATION

command, or when both the Enable pin and

OPERATION command are valid.

101

110

Device starts from ENABLE pin only.

4:2

Device starts from OPERATION command only.

Device starts when the ENABLE pin is active and OPERATION “on”

command has been sent.

111

0

1

0

1

Active low (Pull pin low to start the device)

Active high (Pull pin high to start the device)

Use the programmed ramp down settings

Turn off the output immediately

1

0

Polarity of the ENABLE pin

ENABLE pin action when commanding the unit

to turn off

CLEAR_FAULTS (03h)

Definition: Clears all fault bits in all registers and releases the SALRT pin (if asserted) simultaneously. If a fault condition still exists, the

bit will reassert immediately. This command will not restart a device if it has shut down, it will only clear the faults.

Paged or Global: Global

Data Length in Bytes: 0 Byte

Data Format: N/A

Type: Write only

Protectable: Yes

Default Value: N/A

Units: N/A

STORE_DEFAULT_ALL (11h)

Definition: Stores all current PMBus™ values from the operating memory into the nonvolatile DEFAULT Store memory. To clear the

DEFAULT store, perform a RESTORE_FACTORY then STORE_DEFAULT_ALL. To add to the DEFAULT store, perform a

RESTORE_DEFAULT_ALL, write commands to be added, then STORE_DEFAULT_ALL. This command should not be used during device

operation, the device will be unresponsive for 20ms while storing values.

Paged or Global: Global

Data Length in Bytes: 0

Data Format: N/A

Type: Write only

Default Value: N/A

Units: N/A

FN7558.3

September 14, 2015

Submit Document Feedback

30

ZL8800

RESTORE_DEFAULT_ALL (12h)

Definition: Restores PMBus™ settings from the nonvolatile DEFAULT Store memory into the operating memory. These settings are

loaded at power-up if not superseded by settings in USER store. Security level is changed to level 1 following this command. This

command should not be used during device operation, the device will be unresponsive for 20ms while storing values.

Paged or Global: Global

Data Length in Bytes: 0

Data Format: N/A

Type: Write only

Default Value: N/A

Units: N/A

STORE_USER_ALL (15h)

Definition: Stores all PMBus™ settings from the operating memory to the nonvolatile USER store memory. To clear the USER store,

perform a RESTORE_FACTORY then STORE_USER_ALL. To add to the USER store, perform a RESTORE_USER_ALL, write commands to

be added, then STORE_USER_ALL. This command should not be used during device operation, the device will be unresponsive for 20ms

while storing values.

Paged or Global: Global

Data Length in Bytes: 0

Data Format: N/A

Type: Write only

Default Value: N/A

Units: N/A

RESTORE_USER_ALL (16h)

Definition: Restores all PMBus™ settings from the USER store memory to the operating memory. Command performed at power-up.

Security level is changed to Level 1 following this command. This command should not be used during device operation, the device will

be unresponsive for 20ms while storing values.

Paged or Global: Global

Data Length in Bytes: 0

Data Format: N/A

Type: Write only

Default Value: N/A

Units: N/A

VOUT_MODE (20h)

Definition: Reports the V

Data Length in Bytes: 1

Data Format: BIT

mode and provides the exponent used in calculating several V

settings.

OUT

Type: Read-only

Default Value: 13h (Linear Mode, Exponent = -13)

Units: N/A

COMMAND

Format

VOUT_MODE (20h)

Bit Field

Bit Position

Access

7

R

6

R

5

R

4

R

3

R

2

R

1

R

0

R

Function

See Following Table

Default Value

0

1

0

1

MODE

Linear

BITS 7:5

000

BITS 4:0 (PARAMETER)

Five bit two’s complement exponent for the mantissa delivered as the data bytes for an output

voltage related command.

FN7558.3

September 14, 2015

Submit Document Feedback

31

ZL8800

VOUT_COMMAND (21h)

Definition: This command sets or reports the target output voltage. The integer value is multiplied by 2 raised to the power of -13h. This

command cannot be set to be higher than the lowest setting of either VOUT_MAX or 110% of the pin-strap V

setting.

OUT

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear -16 Unsigned

Type: R/W

Protectable: Yes

Default Value: Pin-strap setting

Units: Volts

Equation: V

-13

= VOUT_COMMAND × 2

OUT

Range: 0 to VOUT_MAX

Example: VOUT_COMMAND = 699Ah = 27,034

-13

Target voltage equals 27034 × 2

= 3.3V

COMMAND

Format

VOUT_COMMAND (21h)

Linear, unsigned binary

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Pin-strap setting

Default Value

VOUT_CAL_OFFSET (23h)

Definition: The VOUT_CAL_OFFSET command is used to apply a fixed offset voltage to the output voltage command value. This

command is typically used by the user to calibrate a device in the application circuit. The two bytes are formatted as a two’s

complement binary mantissa, used in conjunction with the exponent of -13h.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear -16 Signed

Type: R/W

Protectable: Yes

Default Value: 0000h

Units: Volts

Equation: V

-13

cal offset = VOUT_CAL_OFFSET×2

OUT

Range: ±3.99V

COMMAND

Format

VOUT_CAL_OFFSET (23h)

Linear-16 Signed

Bit Position

Access

15

R/W

0

14

R/W

0

13

R/W

0

12

R/W

0

11

R/W

0

10

R/W

0

9

R/W

0

8

R/W

0

7

R/W

0

6

R/W

0

5

R/W

0

4

R/W

0

3

R/W

0

2

R/W

0

1

R/W

0

R/W

0

Default Value

FN7558.3

September 14, 2015

Submit Document Feedback

32

ZL8800

VOUT_MAX (24h)

Definition: The VOUT_ MAX command sets an upper limit on the output voltage the unit can command regardless of any other

commands or combinations. The intent of this command is to provide a safeguard against a user accidentally setting the output

voltage to a possibly destructive level rather than to be the primary output overprotection. If a VOUT_COMMAND is sent with a value

higher than VOUT_MAX, the device will set the output voltage to VOUT_MAX.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear -16 Unsigned

Type: R/W

Protectable: Yes

Default Value: 1.10 x VOUT_COMMAND pin-strap setting

Units: Volts

Equation: V

-13

max = VOUT_MAX × 2

OUT

Range: 0V to 5.5V

COMMAND

Format

VOUT_MAX (24h)

Linear, unsigned binary

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

1.10 x VOUT_COMMAND Pin-strap Setting

Default Value

VOUT_MARGIN_HIGH (25h)

Definition: Sets the value of the V

which the output is to be changed when the OPERATION command is set to “Margin High”.

during a margin high. This VOUT_MARGIN_HIGH command loads the unit with the voltage to

OUT

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-16 Unsigned.

Type: R/W word

Protectable: Yes

Default Value: 1.05 x VOUT_COMMAND setting

Units: V

Equation: V

-13

margin high = VOUT_MARGIN_HIGH x 2

OUT

Range: 0V to VOUT_MAX

COMMAND

Format

VOUT_MARGIN_HIGH (25h)

Linear-16 Unsigned

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

1.05 x VOUT_COMMAND

Default Value

FN7558.3

September 14, 2015

Submit Document Feedback

33

ZL8800

VOUT_MARGIN_LOW (26h)

Definition: Sets the value of the V

the output is to be changed when the OPERATION command is set to “Margin Low”.

during a margin low. This VOUT_MARGIN_LOW command loads the unit with the voltage to which

OUT

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-16 Unsigned.

Type: R/W

Protectable: Yes

Default Value: 0.95 x VOUT_COMMAND pin-strap setting

Units: V

Equation: V

margin low = VOUT_MARGIN_LOW

OUT

Range: 0V to VOUT_MAX

COMMAND

Format

VOUT_MARGIN_LOW (26h)

Linear, two’s complement binary

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

0.95 x VOUT_COMMAND

Default Value

VOUT_TRANSITION_RATE (27h)

Definition: This command sets the rate at which the output should change voltage when the device receives an OPERATION command

(Margin High, Margin Low) that causes the output voltage to change. The maximum possible positive value of the two data bytes

indicates that the device should make the transition as quickly as possible. This commanded rate does not apply when the device is

commanded to turn on or to turn off.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11.

Type: R/W

Protectable: Yes

Default Value: BA00h (1.0V/ms)

Units: V/ms

N

Equation: VOUT_TRANSITION_RATE = Y×2

Range: 0.1 to 4V/ms

COMMAND

Format

VOUT_TRANSITION_RATE (27h)

Linear Data Format

Bit Position

Access

15

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Signed Exponent, N Signed Mantissa, Y

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Function

Default Value

1

0

1

0

1

0

FN7558.3

September 14, 2015

Submit Document Feedback

34

ZL8800

VOUT_DROOP (28h)

Definition: The VOUT_DROOP sets the effective load line (V/I slope) for the rail in which the device is used. It is the rate, in mV/A at

which the output voltage decreases with increasing output current. For devices that are set to sink output current (negative output

current), the output voltage continues to increase as the output current is negative. VOUT_DROOP is not needed for 2-phase operation

with a single ZL8800.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11.

Type: R/W

Protectable: Yes

Default Value: 0000h (0mV/A)

Units: mV/A

N

Equation: VOUT_DROOP = Y×2

Range: 0 to 40mV/A

COMMAND

Format

VOUT_DROOP (28h)

Linear-11

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

Signed Exponent, N

Signed Mantissa, Y

Default Value

0

FREQUENCY_SWITCH (33h)

Definition: Sets the switching frequency of the device. Initial default value is defined by a pin-strap and this value can be overridden by

writing this command. If an external SYNC is utilized, this value should be set as close as possible to the external clock value. The

output must be disabled when writing this command. Available frequencies are defined by the equation f

11 ≤ n ≤ 80

= 16MHz/n where

SW

Paged or Global: Global

Data Length in Bytes: 2

Data Format: Linear-11.

Type: R/W

Protectable: Yes

Default Value: Pin-strap setting

Units: kHz

N

Equation: FREQUENCY_SWITCH = Y×2

Range: 200kHz to 1.33MHz

COMMAND

Format

FREQUENCY_SWITCH (33h)

Linear-11

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Function

Signed Exponent, N

Signed Mantissa, Y

Default Value

Pin-strapped Value

FN7558.3

September 14, 2015

Submit Document Feedback

35

ZL8800

INTERLEAVE (37h)

Definition: Configures the phase offset of a device that is sharing a common SYNC clock with other devices. An INTERLEAVE group

number and desired phase position are specified. Interleave is used for setting the phase offset in noncurrent sharing devices. For

current sharing rails INTERLEAVE is ignored and DDC_CONFIG is used to configure the phase relationship between current sharing

phases.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Bit Field

Type: R/W

Protectable: Yes

Default Value: Set by pin-strapped PMBus™ address

Units: N/A

COMMAND

Format

INTERLEAVE (37h)

Bit Field

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

See Following Table

Function

Default Value

0

Four LSB’s of SMBus Address Four LSB’s of SMBus Address

BITS

15:8

7:4

PURPOSE

Not Used

VALUE

0

DESCRIPTION

Not Used

Group Number

0 to 15

Sets the group number. A value of 0 is interpreted as 16

Sets position of the device’s rail within the group. A value of 0 is interpreted as 16.

Position 1 will have a 22.5° offset.

3:0

Position of Device

0 to 15

IOUT_CAL_GAIN (38h)

Definition: Sets the effective impedance across the current sense circuit for use in calculating output current at +25°C.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11.

Type: R/W

Protectable: Yes

Default Value: AA66h (0.3mΩ)

Units: mΩ

N

Equation: IOUT_CAL_GAIN = Y×2

COMMAND

Format

IOUT_CAL_GAIN (38h)

Linear-11

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

Signed Exponent, N

Signed Mantissa, Y

Default Value

1

0

1

0

1

0

1

0

1

0

1

0

FN7558.3

September 14, 2015

Submit Document Feedback

36

ZL8800

IOUT_CAL_OFFSET (39h)

Definition: Used to null out any offsets in the output current sensing circuit, and to compensate for delayed measurements of current

ramp due to Isense blanking time.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11.

Type: R/W

Protectable: Yes

Default Value: 0000h (0A)

Units: A

N

Equation: IOUT_CAL_OFFSET = Y×2

COMMAND

Format

IOUT_CAL_OFFSET (39h)

Linear-11

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

Signed Exponent, N

Signed Mantissa, Y

Default Value

0

VOUT_OV_FAULT_LIMIT (40h)

Definition: Sets the V overvoltage fault threshold.

OUT

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-16 Unsigned.

Type: R/W

Protectable: Yes

Default Value: 1.15 x VOUT_COMMAND pin-strap setting

Units: V

-13

Equation: VOUT OV fault limit = VOUT_OV_FAULT_LIMIT×2

Range: 0V to 7.99V

COMMAND

Format

VOUT_OV_FAULT_LIMIT (40h)

Linear-16 Unsigned

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

1.15 x VOUT_COMMAND

Default Value

FN7558.3

September 14, 2015

Submit Document Feedback

37

ZL8800

VOUT_OV_FAULT_RESPONSE (41h)

Definition: Configures the V overvoltage fault response. Note that the device cannot be set to ignore this fault mode.The retry time is

OUT

the time between restart attempts.

Paged or Global: Paged

Data Length in Bytes: 1

Data Format: Bit Field.

Type: R/W

Protectable: Yes

Default Value: 80h (Shut down immediately, no retries)

Units: Retry time = 70ms

COMMAND

Format

VOUT_OV_FAULT_RESPONSE (41h)

Bit Field

Bit Position

Access

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

1

0

BIT

FIELD NAME

VALUE

00-01

10

DESCRIPTION

Response Behavior: the device:

• Pulls SALRT low

Not Used

Disable and Retry according to the setting in bits [5:3].

• Sets the related fault bit in the

status registers. Fault bits are

only cleared by the

7:6

Output is disabled while the fault is present. Operation resumes and the output is enabled when

the fault condition no longer exists.

11

CLEAR_FAULTS command.

000

No Retry. The output remains disabled until the device is restarted.

001-110 Not Used

Attempts to restart continuously, without checking if the fault is still present, until it is

5:3

2:0

Retry Setting

Not Used

111

commanded OFF (by the CONTROL pin or OPERATION command or both), bias power is

removed, or another fault condition causes the unit to shut down.

000-111 Not Used

VOUT_UV_FAULT_LIMIT (44h)

Definition: Sets the V

device is disabled.

undervoltage fault threshold. This fault is masked during ramp, before power-good is asserted or when the

OUT

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-16 Unsigned.

Type: R/W

Protectable: Yes

Default Value: 0.85 x VOUT_COMMAND pin-strap setting

Units: V

-13

Equation: VOUT UV fault limit = VOUT_UV_FAULT_LIMIT×2

Range: 0V to 7.99V

COMMAND

Format

VOUT_UV_FAULT_LIMIT (44h)

Linear-16 unsigned

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

0.85 x VOUT_COMMAND

Default Value

FN7558.3

September 14, 2015

Submit Document Feedback

38

ZL8800

VOUT_UV_FAULT_RESPONSE (45h)

Definition: Configures the V undervoltage fault response. Note that VOUT UV faults can only occur after Power-good (PG) has been

OUT

asserted. Under some circumstances this will cause the output to stay fixed below the power good threshold indefinitely. If this behavior

is undesired, use setting 80h. The retry time is the time between restart attempts.

Paged or Global: Paged

Data Length in Bytes: 1

Data Format: Bit Field.

Type: R/W

Protectable: Yes

Default Value: 80h (Shut down immediately, no retries)

Units: Retry time unit = 70ms

COMMAND

VOUT_UV_FAULT_RESPONSE (45h)

Bit Field

Format

Bit Position

Access

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

1

0

BIT

FIELD NAME

VALUE

00-01

10

DESCRIPTION

Response Behavior: the device:

• Pulls SALRT low

Not Used

Disable and Retry according to the setting in bits [5:3].

• Sets the related fault bit in the

status registers. Fault bits are

only cleared by the

7:6

11

Not Used

CLEAR_FAULTS command.

000

No Retry. The output remains disabled until the fault is cleared.

001-110 Not Used

5:3

2:0

Retry Setting

Not Used

Attempts to restart continuously, without checking if the fault is still present, until it is

commanded OFF (by the ENABLE pin or OPERATION command or both), bias power is removed,

or another fault condition causes the unit to shut down.

111

000-111 Not Used

IOUT_OC_FAULT_LIMIT (46h)

Definition: Sets the I peak overcurrent fault threshold. This limit is applied to current measurement samples taken after the Current

OUT

Sense Blanking Time has expired. A fault occurs after this limit is exceeded for the number of consecutive samples as defined in

ISENSE_CONFIG. This feature shares the OC fault bit operation (in STATUS_IOUT) and OC fault response with IOUT_AVG_OC_FAULT_LIMIT.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11.

Type: R/W

Protectable: Yes

Default Value: DA80h (20A)

Units: A

N

Equation: IOUT_OC_FAULT_LIMIT = Y×2

Range: -100A to 100A

COMMAND

Format

IOUT_OC_FAULT_LIMIT (46h)

Linear, two’s complement binary

Bit Position

Access

15

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Signed Exponent, N Signed Mantissa, Y

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Function

Default Value

1

0

1

0

1

0

1

0

FN7558.3

September 14, 2015

Submit Document Feedback

39

ZL8800

IOUT_UC_FAULT_LIMIT (4Bh)

Definition: Sets the I valley undercurrent fault threshold. This limit is applied to current measurement samples taken after the Current

OUT

Sense Blanking Time has expired. A fault occurs after this limit is exceeded for the number of consecutive sample as defined in

ISENSE_CONFIG. This feature shares the UC fault bit operation (in STATUS_IOUT) and UC fault response with IOUT_AVG_UC_FAULT_LIMIT.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11.

Type: R/W

Protectable: Yes

Default Value: -1 x IOUT_OC_FAULT_LIMIT

Units: A

N

Equation: IOUT_OC_FAULT_LIMIT = Y×2

Range: -100A to 100A

COMMAND

Format

IOUT_UC_FAULT_LIMIT (4Bh)

Linear, two’s complement binary

Bit Position

Access

15

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Signed Exponent, N Signed Mantissa, Y

-1 x IOUT_OC_FAULT_LIMIT

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Function

Default Value

OT_FAULT_LIMIT (4Fh)

Definition: The OT_FAULT_LIMIT command sets the temperature at which the device should indicate an over-temperature fault. Note

that the temperature must drop below OT_WARN_LIMIT to clear this fault.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11.

Type: R/W

Protectable: Yes

Default Value: EBE8h (+125˚C)

Units: Celsius

N

Equation: OT_FAULT_LIMIT = Y×2

Range: 0 to +175

COMMAND

Format

OT_FAULT_LIMIT (4Fh)

Linear, two’s complement binary

Bit Position

Access

15

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Signed Exponent, N Signed Mantissa, Y

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Function

Default Value

1

0

1

0

1

0

1

0

FN7558.3

September 14, 2015

Submit Document Feedback

40

ZL8800

OT_FAULT_RESPONSE (50h)

Definition: The OT_FAULT_RESPONSE command instructs the device on what action to take in response to an over-temperature fault.

The retry time is the time between restart attempts.

Paged or Global: Paged

Data Length in Bytes: 1

Data Format: Bit Field

Type: R/W

Protectable: Yes

Default Value: 80h (Shut down immediately, no retries)

Units: Retry time unit = 210ms

COMMAND

Format

OT_FAULT_RESPONSE (50h)

Bit Field

Bit Position

Access

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

1

0

BIT

7:6

FIELD NAME

VALUE

00-01

10

DESCRIPTION

Response Behavior: The device:

• Pulls SALRT low

Not Used

Disable and Retry according to the setting in bits [5:3].

• Sets the related fault bit in the

status registers. Fault bits are

only cleared by the

Output is disabled while the fault is present. Operation resumes and the output is enabled when

the fault condition no longer exists.

11

CLEAR_FAULTS command.

000

No Retry. The output remains disabled until the fault is cleared.

001-110 Not Used

5:3

2:0

Retry Setting

Not Used

Attempts to restart continuously, without checking if the fault is still present, until it is

commanded OFF (by the CONTROL pin or OPERATION command), bias power is removed, or

another fault condition causes the unit to shut down.

111

000-111 Not Used

OT_WARN_LIMIT (51h)

Definition: The OT_WARN_LIMIT command sets the temperature at which the device should indicate an over-temperature warning

alarm. In response to the OT_WARN_LIMIT being exceeded, the device: Sets the TEMPERATURE bit in STATUS_WORD, Sets the

OT_WARNING bit in STATUS_TEMPERATURE, and notifies the host.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11.

Type: R/W

Protectable: Yes

Default Value: EB70h (+110°C)

Units: Celsius

N

Equation: OT_WARN_LIMIT = Y×2

Range: 0 to 175

COMMAND

Format

OT_WARN_LIMIT (51h)

Linear, two’s complement binary

Bit Position

Access

15

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Signed Exponent, N Signed Mantissa, Y

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Function

Default Value

1

0

1

0

1

0

1

0

FN7558.3

September 14, 2015

Submit Document Feedback

41

ZL8800

UT_WARN_LIMIT (52h)

Definition: The UT_WARN_LIMIT command set the temperature at which the device should indicate an under-temperature Warning

alarm. In response to the UT_WARN_LIMIT being exceeded, the device: Sets the TEMPERATURE bit in STATUS_WORD, Sets the

UT_WARNING bit in STATUS_TEMPERATURE, and notifies the host.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11.

Type: R/W

Protectable: Yes

Default Value: DC40h (-30°C)

Units: Celsius

N

Equation: UT_WARN_LIMIT = Y×2

Range: -55 to +25

COMMAND

Format

UT_WARN_LIMIT (52h)

Linear, two’s complement binary

Bit Position

Access

15

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Signed Exponent, N Signed Mantissa, Y

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Function

Default Value

1

0

1

0

1

0

UT_FAULT_LIMIT (53h)

Definition: The UT_FAULT_LIMIT command sets the temperature, in degrees Celsius, of the unit at which it should indicate an under-

temperature fault. Note that the temperature must rise above UT_WARN_LIMIT to clear this fault.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11.

Type: R/W

Protectable: Yes

Default Value: E530h (-45°C)

Units: Celsius

N

Equation: UT_FAULT_LIMIT = Y×2

Range: -55 to +25

COMMAND

Format

UT_FAULT_LIMIT (53h)

Linear, two’s complement binary

Bit Position

Access

15

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Signed Exponent, N Signed Mantissa, Y

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Function

Default Value

1

0

1

0

1

0

1

0

FN7558.3

September 14, 2015

Submit Document Feedback

42

ZL8800

UT_FAULT_RESPONSE (54h)

Definition: Configures the under-temperature fault response as defined by the table below. The retry time is the time between restart

attempts.

Paged or Global: Paged

Data Length in Bytes: 1

Data Format: Bit Field.

Type: R/W

Protectable: Yes

Default Value: 80h (Shut down immediately, no retries)

Units: Retry time unit = 210ms

COMMAND

Format

UT_FAULT_RESPONSE (54h)

Bit Field

Bit Position

Access

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

1

0

BIT

7:6

FIELD NAME

VALUE

00-01

10

DESCRIPTION

Response Behavior: The device:

• Pulls SALRT low

Not Used

Disable and Retry according to the setting in bits [5:3].

• Sets the related fault bit in the

status registers. Fault bits are

only cleared by the

Output is disabled while the fault is present. Operation resumes and the output is enabled when

the fault condition no longer exists.

11

CLEAR_FAULTS command.

000

No Retry. The output remains disabled until the device is restarted.

001-110 Not Used

Attempts to restart continuously, without checking if the fault is still present, until it is

5:3

2:0

Retry Setting

Not Used

111

commanded OFF (by the CONTROL pin or OPERATION command), bias power is removed, or

another fault condition causes the unit to shut down.

000-111 Not Used

VIN_OV_FAULT_LIMIT (55h)

Definition: Sets the V overvoltage fault threshold.

IN

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11.

Type: R/W

Protectable: Yes

Default Value: D380h (14V)

Units: V

N

Equation: VIN_OV_FAULT_LIMIT = Y×2

Range: 0 to 19V

COMMAND

Format

VIN_OV_FAULT_LIMIT (55h)

Linear, two’s complement binary

Bit Position

Access

15

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Signed Exponent, N Signed Mantissa, Y

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Function

Default Value

1

0

1

0

1

0

FN7558.3

September 14, 2015

Submit Document Feedback

43

ZL8800

VIN_OV_FAULT_RESPONSE (56h)

Definition: Configures the V overvoltage fault response as defined by the table below. The retry time is the time between restart

IN

attempts.

Paged or Global: Paged

Data Length in Bytes: 1

Data Format: Bit Field.

Type: R/W

Protectable: Yes

Default Value: 80h (Immediate shutdown, no retry)

Units: Retry time unit = 70ms

COMMAND

Format

VIN_OV_FAULT_RESPONSE (56h)

Bit Field

Bit Position

Access

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

1

0

BIT

7:6

FIELD NAME

VALUE

00-01

10

DESCRIPTION

Response Behavior: The device:

• Pulls SALRT low

Not Used

Disable and Retry according to the setting in bits [5:3].

• Sets the related fault bit in the

status registers. Fault bits are

only cleared by the

Output is disabled while the fault is present. Operation resumes and the output is enabled when

the fault condition no longer exists.

11

CLEAR_FAULTS command.

000

No Retry. The output remains disabled until the fault is cleared.

001-110 Not Used

5:3

2:0

Retry Setting

Not Used

Attempts to restart continuously, without checking if the fault is still present, until it is

commanded OFF (by the CONTROL pin or OPERATION command), bias power is removed, or

another fault condition causes the unit to shut down.

111

000-111 Not Used

VIN_OV_WARN_LIMIT (57h)

Definition: Sets the V overvoltage warning threshold as defined by the table below. In response to the OV_WARN_LIMIT being

IN

exceeded, the device: Sets the NONE OF THE ABOVE and INPUT bits in STATUS_WORD, Sets the VIN_OV_WARNING bit in STATUS_INPUT,

and notifies the host.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11.

Type: R/W

Protectable: Yes

Default Value: D360h (13.5V)

Units: V

N

Equation: VIN_OV_FAULT_LIMIT = Y×2

Range: 0 to 19V

COMMAND

Format

VIN_OV_WARN_LIMIT (57h)

Linear, two’s complement binary

Bit Position

Access

15

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Signed Exponent, N Signed Mantissa, Y

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Function

Default Value

1

0

1

0

1

0

1

0

FN7558.3

September 14, 2015

Submit Document Feedback

44

ZL8800

VIN_UV_WARN_LIMIT (58h)

Definition: Sets the V undervoltage warning threshold. If a VIN_UV_FAULT occurs, the input voltage must rise above

IN

VIN_UV_WARN_LIMIT to clear the fault, which provides hysteresis to the fault threshold. In response to the UV_WARN_LIMIT being

exceeded, the device: Sets the NONE OF THE ABOVE and INPUT bits in STATUS_WORD, Sets the VIN_UV_WARNING bit in STATUS_INPUT,

and notifies the host.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11.

Type: R/W

Protectable: Yes

Default Value: 1.03 x VIN_UV_FAULT_LIMIT pin-strap setting

Units: V

N

Equation: VIN_UV_WARN_LIMIT = Y×2

Range: 0 to 19V

COMMAND

Format

VIN_UV_WARN_LIMIT (58h)

Linear, two’s complement binary

Bit Position

Access

15

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Signed Exponent, N Signed Mantissa, Y

1.03 x VIN_UV_FAULT_LIMIT

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Function

Default Value

VIN_UV_FAULT_LIMIT (59h)

Definition: Sets the V undervoltage fault threshold.

IN

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11.

Type: R/W

Protectable: Yes

Default Value: Pin-strap setting

Units: V

N

Equation: VIN_UV_FAULT_LIMIT = Y×2

Range: 0 to 19V

COMMAND

Format

VIN_UV_FAULT_LIMIT (59h)

Linear, two’s complement binary

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Function

Signed Exponent, N

Signed Mantissa, Y

Default Value

Pin-Strapped Value

FN7558.3

September 14, 2015

Submit Document Feedback

45

ZL8800

VIN_UV_FAULT_RESPONSE (5Ah)

Definition: Configures the V undervoltage fault response as defined by the table below. The retry time is the time between restart

IN

attempts.

Paged or Global: Paged

Data Length in Bytes: 1

Data Format: Bit Field.

Type: R/W

Protectable: Yes

Default Value: 80h (Immediate shutdown, no retries)

Units: Retry time unit = 70ms

COMMAND

Format

VIN_UV_FAULT_RESPONSE (5Ah)

Bit Field

Bit Position

Access

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

1

0

BIT

7:6

FIELD NAME

VALUE

00-01

10

DESCRIPTION

Response Behavior: The device:

• Pulls SALRT low

Not Used

Disable and Retry according to the setting in bits [5:3].

• Sets the related fault bit in the

status registers. Fault bits are

only cleared by the

Output is disabled while the fault is present. Operation resumes and the output is enabled when

the fault condition no longer exists.

11

CLEAR_FAULTS command.

000

No Retry. The output remains disabled until the fault is cleared.

001-110 Not Used

Attempts to restart continuously, without checking if the fault is still present, until it is

5:3

2:0

Retry Setting

Not Used

111

commanded OFF (by the CONTROL pin or OPERATION command), bias power is removed, or

another fault condition causes the unit to shut down.

000-111 Not Used

POWER_GOOD_ON (5Eh)

Definition: Sets the voltage threshold for power-good indication. Power-good asserts when the output voltage exceeds

POWER_GOOD_ON and de-asserts when the output voltage is less than VOUT_UV_FAULT_LIMIT.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-16 Unsigned.

Type: R/W

Protectable: Yes

Default Value: 0.9 x VOUT_COMMAND pin-strap setting

Units: V

COMMAND

Format

POWER_GOOD_ON (5Eh)

Linear, unsigned binary

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

0.9 x VOUT_COMMAND

Default Value

FN7558.3

September 14, 2015

Submit Document Feedback

46

ZL8800

TON_DELAY (60h)

Definition: Sets the delay time from when the device is enabled to the start of V

rise.

OUT

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11.

Type: R/W

Protectable: Yes

Default Value: CA80h, 5ms

Units: ms

N

Equation: TON_DELAY = Y×2

Range: 0 to 5 seconds. The minimum delay time is 3ms. Values below 3ms will result in a delay time of 3ms.

COMMAND

Format

TON_DELAY (60h)

Linear, two’s complement binary

Bit Position

Access

15

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Signed Exponent, N Signed Mantissa, Y

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Function

Default Value

1

0

1

0

1

0

1

0

TON_RISE (61h)

Definition: Sets the rise time of VOUT after ENABLE and TON_DELAY.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11.

Type: R/W

Protectable: Yes

Default Value: CA80h, 5ms

Units: ms

N

Equation: TON_RISE = Y×2

Range: 1 to 100ms. The minimum rise time is 1ms. Values below 1ms will default to 1ms. Short rise times may cause excessive input

and output currents to flow, thus triggering overcurrent faults at start-up.

COMMAND

Format

TON_RISE (61h)

Linear, two’s complement binary

Bit Position

Access

15

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Signed Exponent, N Signed Mantissa, Y

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Function

Default Value

1

0

1

0

1

0

1

0

FN7558.3

September 14, 2015

Submit Document Feedback

47

ZL8800

TOFF_DELAY (64h)

Definition: Sets the delay time from DISABLE to start of VOUT fall.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11.

Type: R/W

Protectable: Yes

Default Value: 0000h, 0ms

Units: ms

N

Equation: TON_DELAY = Y×2

Range: 0 to 5 seconds. Values less than 0.5ms will set the device to immediate off (no TOFF_FALL ramp down).

COMMAND

Format

TOFF_DELAY (64h)

Linear, two’s complement binary

Bit Position

Access

15

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Signed Exponent, N Signed Mantissa, Y

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Function

Default Value

0

TOFF_FALL (65h)

Definition: Sets the fall time for V

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11.

Type: R/W

after DISABLE and TOFF_DELAY.

OUT

Protectable: Yes

Default Value: 1 x TON_RISE

Units: ms

N

Equation: TOFF_FALL = Y×2

Range: 0 to 100ms. Although values can be set below 0.50ms, fall time accuracy cannot be guaranteed. In addition, short fall times

may cause excessive negative output current to flow, thus triggering undercurrent faults at shut-down.

COMMAND

Format

TOFF_FALL (65h)

Linear, two’s complement binary

Bit Position

Access

15

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Signed Exponent, N Signed Mantissa, Y

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Function

Default Value

1 x TON_RISE

STATUS_BYTE (78h)

Definition: The STATUS_WORD command returns two bytes of information with a summary of the unit’s fault condition. Based on the

information in these bytes, the host can get more information by reading the appropriate status registers. The low byte of the

STATUS_WORD is the same register as the STATUS_BYTE (78h) command.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Bit Field

Type: Read-only

Protectable: No

Default Value: 00h

Units: N/A

FN7558.3

September 14, 2015

Submit Document Feedback

48

ZL8800

STATUS_WORD (79h)

Definition: The STATUS_WORD command returns two bytes of information with a summary of the unit’s fault condition. Based on the

information in these bytes, the host can get more information by reading the appropriate status registers. The low byte of the

STATUS_WORD is the same register as the STATUS_BYTE (78h) command.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Bit Field

Type: Read-only

Protectable: No

Default Value: 0000h

Units: N/A

COMMAND

Format

STATUS_WORD (79h)

Bit Field

Bit Position

Access

15

R

14

R

13

R

12

R

11

R

10

R

9

R

8

R

7

R

6

R

5

R

4

R

3

R

2

R

1

R

0

R

Function

See Following Table

Default Value

0

BIT NUMBER

STATUS BIT NAME

MEANING

15

14

VOUT

IOUT

An output voltage fault or warning has occurred.

An output current or output power fault or warning has occurred.

An input voltage, input current, or input power fault or warning has

occurred.

13

INPUT

12

11

10

9

MFG_SPECIFIC

POWER_GOOD #

NOT USED

A manufacturer specific fault or warning has occurred.

The POWER_GOOD signal, if present, is negated. (Note 17)

Not Used

OTHER

A bit in STATUS_OTHER is set.

A fault type not given in bits 15:1 of the STATUS_WORD has been

detected.

8

7

6

UNKNOWN

BUSY

A fault was declared because the device was busy and unable to

respond.

This bit is asserted if the unit is not providing power to the output,

regardless of the reason, including simply not being enabled.

OFF

5

4

3

2

1

0

VOUT_OV_FAULT

IOUT_OC_FAULT

VIN_UV_FAULT

TEMPERATURE

CML

An output overvoltage fault has occurred.

An output overcurrent fault has occurred.

An input undervoltage fault has occurred.

A temperature fault or warning has occurred.

A communications, memory or logic fault has occurred.

A fault or warning not listed in bits 7:1 has occurred.

NONE OF THE ABOVE

NOTE:

17. If the POWER_GOOD# bit is set, this indicates that the POWER_GOOD signal, if present, is signaling that the output power is not good.

FN7558.3

September 14, 2015

Submit Document Feedback

49

ZL8800

STATUS_VOUT (7Ah)

Definition: The STATUS_VOUT command returns one data byte with the status of the output voltage.

Paged or Global: Paged

Data Length in Bytes: 1

Data Format: Bit Field

Type: Read-only

Protectable: No

Default Value: 00h

Units: N/A

COMMAND

Format

STATUS_VOUT (7Ah)

Bit Field

Bit Position

Access

7

R

6

R

5

R

4

R

3

R

2

R

1

R

0

R

Function

See Following Table

Default Value

0

BIT NUMBER

STATUS BIT NAME

VOUT_OV_FAULT

VOUT_OV_WARNING

VOUT_UV_WARNING

VOUT_UV_FAULT

Not Used

MEANING

7

6

Indicates an output overvoltage fault.

Indicates an output overvoltage warning.

Indicates an output undervoltage warning.

Indicates an output undervoltage fault.

Not Used

5

4

3:0

STATUS_IOUT (7Bh)

Definition: The STATUS_IOUT command returns one data byte with the status of the output current.

Paged or Global: Paged

Data Length in Bytes: 1

Data Format: Bit Field

Type: Read-only

Protectable: No

Default Value: 00h

Units: N/A

COMMAND

Format

STATUS_IOUT (7Bh)

Bit Field

Bit Position

Access

7

R

6

R

5

R

4

R

3

R

2

R

1

R

0

R

Function

See Following Table

Default Value

0

BIT NUMBER

STATUS BIT NAME

IOUT_OC_FAULT

IOUT_OC_LV_FAULT

IOUT_OC_WARNING

IOUT_UC_FAULT

Not Used

MEANING

7

6

An output overcurrent fault has occurred.

An output overcurrent and low voltage fault has occurred.

An output overcurrent warning has occurred.

An output under current fault has occurred.

Not Used

5

4

3:0

FN7558.3

September 14, 2015

Submit Document Feedback

50

ZL8800

STATUS_INPUT (7Ch)

Definition: The STATUS_INPUT command returns input voltage and input current status information.

Paged or Global: Global

Data Length in Bytes: 1

Data Format: Bit Field

Type: Read-only

Protectable: No

Default Value: 00h

Units: N/A

COMMAND

Format

STATUS_INPUT (7Ch)

Bit Field

Bit Position

Access

7

R

6

R

5

R

4

R

3

R

2

R

1

R

0

R

Function

See Following Table

Default Value

0

BIT NUMBER

STATUS BIT NAME

VIN_OV_FAULT

VIN_OV_WARNING

VIN_UV_WARNING

VIN_UV_FAULT

Not Used

MEANING

7

6

An input overvoltage fault has occurred.

An input overvoltage warning has occurred.

An input undervoltage warning has occurred.

An input undervoltage fault has occurred.

Not Used

5

4

3:0

STATUS_TEMPERATURE (7Dh)

Definition: The STATUS_TEMPERATURE command returns one byte of information with a summary of any temperature related faults or

warnings.

Paged or Global: Paged

Data Length in Bytes: 1

Data Format: Bit Field

Type: Read-only

Protectable: No

Default Value: 00h

Units: N/A

COMMAND

Format

STATUS_TEMP (7Dh)

Bit Field

Bit Position

Access

7

R

6

R

5

R

4

R

3

R

2

R

1

R

0

R

Function

See Following Table

Default Value

0

BIT NUMBER

STATUS BIT NAME

OT_FAULT

MEANING

7

6

An over-temperature fault has occurred.

An over-temperature warning has occurred.

An under-temperature warning has occurred.

An under-temperature fault has occurred.

Not Used

OT_WARNING

UT_WARNING

UT_FAULT

5

4

3:0

Not Used

FN7558.3

September 14, 2015

Submit Document Feedback

51

ZL8800

STATUS_CML (7Eh)

Definition: The STATUS_WORD command returns one byte of information with a summary of any Communications, Logic and/or

Memory errors.

Paged or Global: Global

Data Length in Bytes: 1

Data Format: Bit Field

Type: Read-only

Protectable: No

Default Value: 00h

Units: N/A

COMMAND

Format

STATUS_CML (7Eh)

Bit Field

Bit Position

Access

7

R

6

R

5

R

4

R

3

R

2

R

1

R

0

R

Function

See Following Table

Default Value

0

BIT NUMBER

MEANING

7

6

Invalid or unsupported PMBus™ command was received.

The PMBus™ command was sent with invalid or unsupported data.

A packet error was detected in the PMBus™ command.

Not Used

5

4:2

A PMBus™ command tried to write to a read-only or protected command, or a communication fault other than the ones listed in

this table has occurred.

1

0

Not Used

STATUS_MFR_SPECIFIC (80h)

Definition: The STATUS_MFR_SPECIFIC command returns one byte of information providing the status of the device’s voltage

monitoring and clock synchronization faults. Note: The VMON OV/UV warnings are set at ±10% of the VMON_XX_FAULT commands.

Paged or Global: Global

Data Length in Bytes: 1

Data Format: Bit Field

Type: Read only

Protectable: No

Default Value: 00h

Units: N/A

COMMAND

Format

STATUS_MFR_SPECIFIC (80h)

Bit Field

Bit Position

Access

7

R

6

R

5

R

4

R

3

R

2

R

1

R

0

R

Function

See Following Table

Default Value

0

BIT

7:6

5

FIELD NAME

MEANING

Not Used

VMON UV Warning

VMON OV Warning

The voltage on the VMON pin has dropped 10% below the level set by MFR_VMON_UV_FAULT

The voltage on the VMON pin has risen 10% above the level set by MFR_VMON_OV_FAULT

4

3

External Switching Period Fault Loss of external clock synchronization has occurred

2

Not Used

1

VMON UV Fault

VMON OV Fault

The voltage on the VMON pin has dropped below the level set by MFR_VMON_UV_FAULT

The voltage on the VMON pin has risen above the level set by MFR_VMON_OV_FAULT

0

FN7558.3

September 14, 2015

Submit Document Feedback

52

ZL8800

READ_VIN (88h)

Definition: Returns the input voltage reading.

Paged or Global: Global

Data Length in Bytes: 2

Data Format: Linear-11.

Type: Read-only

Protectable: No

Default Value: N/A

Units: V

N

Equation: READ_VIN = Y×2

Range: N/A

COMMAND

Format

READ_VIN (88h)

Linear-11

Bit Position

Access

15

R

14

R

13

R

12

R

11

R

10

R

9

R

8

R

7

R

6

R

5

R

4

R

3

R

2

R

1

R

0

R

Function

Signed Exponent, N

N/A N/A N/A

Signed Mantissa, Y

Default Value

N/A

READ_IIN (89h)

Definition: Returns the input current reading.

Paged or Global: Global

Data Length in Bytes: 2

Data Format: Linear-11.

Type: Read-only

Protectable: No

Default Value: N/A

Units: A

N

Equation: READ_IIN = Y×2

Range: N/A

COMMAND

Format

READ_IIN (89h)

Linear-11

Bit Position

Access

15

R

14

R

13

R

12

R

11

R

10

9

R

8

R

7

R

6

5

R

4

R

3

R

2

R

1

R

0

R

Function

Signed Exponent, N

N/A N/A N/A

Signed Mantissa, Y

Default Value N/A

N/A

READ_VOUT (8Bh)

Definition: Returns the output voltage reading.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-16 Unsigned.

Type: Read-only

Protectable: No

Default Value: N/A

-13

Equation: READ_VOUT = READ_VOUT × 2

Units: V

COMMAND

Format

READ_VOUT (8Bh)

Linear-16 Unsigned

Bit Position

Access

15

R

14

R

13

R

12

R

11

R

10

9

R

8

R

7

R

6

R

5

R

4

R

3

R

2

R

1

R

0

R

Default Value

N/A

FN7558.3

September 14, 2015

Submit Document Feedback

53

ZL8800

READ_IOUT (8Ch)

Definition: Returns the output current reading.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11.

Type: Read-only

Protectable: No

Default Value: N/A

Units: A

Equation: READ_IOUT = Y×2

N

Range: N/A

COMMAND

Format

READ_IOUT (8Ch)

Linear-11

Bit Position

Access

15

R

14

R

13

R

12

R

11

R

10

R

9

R

8

R

7

R

6

R

5

R

4

R

3

R

2

R

1

R

0

R

Function

Signed Exponent, N

N/A N/A N/A

Signed Mantissa, Y

Default Value

N/A

READ_TEMPERATURE_1 (8Dh)

Definition: Returns the temperature reading internal to the device.

Paged or Global: Global

Data Length in Bytes: 2

Data Format: Linear-11.

Type: Read-only

Protectable: No

Default Value: N/A

Units: ˚C

Equation: READ_TEMPERATURE_1 = Y×2

N

Range: N/A

COMMAND

Format

READ_INTERNAL_TEMP (8Dh)

Linear-11

Bit Position

Access

15

R

14

R

13

R

12

R

11

R

10

R

9

R

8

R

7

R

6

R

5

R

4

R

3

R

2

R

1

R

0

R

Function

Signed Exponent, N

N/A N/A N/A

Signed Mantissa, Y

N/A N/A N/A

Default Value

N/A

READ_TEMPERATURE_2 (8Eh)

Definition: Returns the temperature reading from the external temperature device connected to XTEMP.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11.

Type: Read-only

Protectable: No

Default Value: N/A

Units: ˚C

Equation: READ_TEMPERATURE_2 = Y×2

N

Range: N/A

COMMAND

Format

READ_EXTERNAL_TEMP (8Eh)

Linear-11

Bit Position

Access

15

R

14

R

13

R

12

R

11

R

10

R

9

R

8

R

7

R

6

R

5

R

4

R

3

R

2

R

1

R

0

R

Function

Signed Exponent, N

N/A N/A N/A

Signed Mantissa, Y

N/A N/A N/A

Default Value

N/A

FN7558.3

September 14, 2015

Submit Document Feedback

54

ZL8800

READ_DUTY_CYCLE (94h)

Definition: Reports the actual duty cycle of the converter during the enable state.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11.

Type: Read only

Protectable: No

Default Value: N/A

Units: %

N

Equation: READ_DUTY_CYCLE = Y×2

Range: 0 to100%

COMMAND

Format

READ_DUTY_CYCLE (94h)

Linear-11

Bit Position

Access

15

R

14

R

13

R

12

R

11

R

10

R

9

R

8

R

7

R

6

R

5

R

4

R

3

R

2

R

1

R

0

R

Function

Signed Exponent, N

N/A N/A N/A

Signed Mantissa, Y

Default Value

N/A

READ_FREQUENCY (95h)

Definition: Reports the actual switching frequency of the converter during the enable state.

Paged or Global: Global

Data Length in Bytes: 2

Data Format: Linear-11.

Default Value: N/A

Units: kHz

N

Equation: READ_FREQUENCY = Y×2

Range: N/A

COMMAND

Format

READ_FREQUENCY (95h)

Linear-11

Bit Position

Access

15

R

14

R

13

R

12

R

11

R

10

R

9

R

8

R

7

R

6

R

5

R

4

R

3

R

2

R

1

R

0

R

Function

Signed Exponent, N

N/A N/A N/A

Signed Mantissa, Y

N/A N/A N/A

Default Value

N/A

MFR_ID (99h)

Definition: MFR_ID sets a user defined identification string not to exceed 32 bytes. The sum total of characters in MFR_ID,

MFR_MODEL, MFR_REVISION, MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command cannot

exceed 128 bytes. This limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform

a RESTORE, write this command then perform a STORE/RESTORE.

Paged or Global: Global

Data Length in Bytes: user defined

Data Format: ASCII. ISO/IEC 8859-1

Type: Block R/W

Protectable: Yes

Default Value: null

Units: N/A

FN7558.3

September 14, 2015

Submit Document Feedback

55

ZL8800

MFR_MODEL (9Ah)

Definition: MFR_MODEL sets a user defined model string not to exceed 32 bytes. The sum total of characters in MFR_ID, MFR_MODEL,

MFR_REVISION, MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command cannot exceed 128 bytes.

This limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write

this command then perform a STORE/RESTORE.

Paged or Global: Global

Data Length in Bytes: user defined

Data Format: ASCII. ISO/IEC 8859-1

Type: Block R/W

Protectable: Yes

Default Value: null

Units: N/A

MFR_REVISION (9Bh)

Definition: MFR_REVISION sets a user defined revision string not to exceed 32 bytes. The sum total of characters in MFR_ID,

MFR_MODEL, MFR_REVISION, MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command cannot

exceed 128 bytes. This limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform

a RESTORE, write this command then perform a STORE/RESTORE.

Paged or Global: Global

Data Length in Bytes: user defined

Data Format: ASCII. ISO/IEC 8859-1

Type: Block R/W

Protectable: Yes

Default Value: null

Units: N/A

MFR_LOCATION (9Ch)

Definition: MFR_LOCATION sets a user defined location identifier string not to exceed 32 bytes. The sum total of characters in MFR_ID,

MFR_MODEL, MFR_REVISION, MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command cannot

exceed 128 bytes. This limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform

a RESTORE, write this command then perform a STORE/RESTORE.

Paged or Global: Global

Data Length in Bytes: user defined

Data Format: ASCII. ISO/IEC 8859-1

Type: Block R/W

Protectable: Yes

Default Value: null

Units: N/A

MFR_DATE (9Dh)

Definition: MFR_DATE sets a user defined date string not to exceed 32 bytes. The sum total of characters in MFR_ID, MFR_MODEL,

MFR_REVISION, MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command cannot exceed 128 bytes.

This limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write

this command then perform a STORE/RESTORE.

Paged or Global: Global

Data Length in Bytes: user defined

Data Format: ASCII. ISO/IEC 8859-1

Type: Block R/W

Protectable: Yes

Default Value: null

Units: N/A

FN7558.3

September 14, 2015

Submit Document Feedback

56

ZL8800

MFR_SERIAL (9Eh)

Definition: MFR_SERIAL sets a user defined serialized identifier string not to exceed 32 bytes. The sum total of characters in MFR_ID,

MFR_MODEL, MFR_REVISION, MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command cannot

exceed 128 bytes. This limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform

a RESTORE, write this command then perform a STORE/RESTORE.

Paged or Global: Global

Data Length in Bytes: User defined

Data Format: ASCII. ISO/IEC 8859-1

Type: Block R/W

Protectable: Yes

Default Value: null

Units: N/A

IC_DEVICE_ID (ADh)

Definition: Reports device identification information.

Data Length in Bytes: 4

Data Format: CUS

Type: Block Read

Protectable: No

Default Value: 49A02400h

Units: N/A

COMMAND

Format

IC_DEVICE_ID (ADh)

Block Read

Byte Position

Function

3

2

1

0

MFR code

49h

ID High Byte

A0h

ID Low Byte

24h

Reserved

00h

Default Value

IC_DEVICE_REV (AEh)

Definition: Reports device revision information.

Data Length in Bytes: 4

Data Format: CUS

Type: Block Read

Protectable: No

Default Value: 00000000h

Units: N/A

COMMAND

Format

IC_DEVICE_REV (AEh)

Block Read

Byte Position

3

2

1

0

Function

Firmware Major

00h

Firmware Minor

00h

Factory Configuration

00h

Reserved

00h

Default Value

USER_DATA_00 (B0h)

Definition: USER_DATA_00 sets a user defined data string not to exceed 32 bytes. The sum total of characters in MFR_ID, MFR_MODEL,

MFR_REVISION, MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command cannot exceed 128 bytes

This limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write

this command then perform a STORE/RESTORE.

Paged or Global: Global

Data Length in Bytes: User defined

Data Format: ASCII. ISO/IEC 8859-1

Type: Block R/W

Protectable: Yes

Default Value: null

Units: N/A

FN7558.3

September 14, 2015

Submit Document Feedback

57

ZL8800

DEADTIME_MAX (BFh)

Definition: Sets the maximum dead time value for the PWMH and PWML outputs. This limit applies during frozen or adaptive dead time

algorithm modes (see DEADTIME_CONFIG).

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Bit Field

Type: R/W

Protectable: Yes

Default Value: 3838h (56ns/56ns)

Units: ns

Range: 0 to 60ns

Reference: N/A

COMMAND

Format

DEADTIME_MAX (BFh)

Bit Field/Linear-7 Unsigned

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

0

1

0

1

0

BITS

15

PURPOSE

Not Used

VALUE

DESCRIPTION

0

H

0

L

Not Used

Limits the maximum allowed HIGH to LOW dead time when using the

adaptive dead time algorithm. dead time = Hns (signed)

14:8

7

Sets the maximum HIGH to LOW dead time

Not Used

Limits the maximum allowed LOW to HIGH dead time when using the

adaptive dead time algorithm. dead time = Lns (signed)

6:0

Sets the maximum LOW to HIGH dead time

ISENSE_CONFIG (D0h)

Definition: Configures current sense circuitry.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Bit Field

Type: R/W word

Protectable: Yes

Default Value: 4204h (256ns, 5 counts, downslope, low range)

Units: N/A

Range: N/A

COMMAND

Format

ISENSE_CONFIG (D0h)

Bit Field

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

0

1

0

1

0

1

0

FN7558.3

September 14, 2015

Submit Document Feedback

58

ZL8800

BIT

FIELD NAME

VALUE

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

000

SETTING

DESCRIPTION

0

32

64

96

128

160

192

224

256

288

320

352

384

Current Sense Blanking

Time

15:11

416

Sets the blanking time current sense blanking time in increments of 32ns

448

480

512

544

576

608

640

672

704

736

768

800

832

1

001

3

010

5

7

Sets the number of consecutive overcurrent (OC) or undercurrent (UC) events

required for a fault. An event can occur once during each switching cycle. For

example, if 5 is selected, an OC or UC event must occur for 5 consecutive

switching cycles, resulting in a delay of at least 5 switching periods.

011

10:8 Current Sense Fault Count

100

9

101

11

110

13

111

15

7:4

3:2

Not Used

0000

00

Not Used

DCR (Down Slope)

DCR (Up Slope)

Not Used

Low Range

Medium Range

High Range

Not Used

01

Current Sense Control

Selection of current sensing method (DCR based: VOUT referenced)

10

11

00

01

1:0

Current Sense Range

Low Range ±25mV, Medium Range ±35mV, High Range ±50mV

10

11

FN7558.3

September 14, 2015

Submit Document Feedback

59

ZL8800

USER_CONFIG (D1h)

Definition: Configures several user-level features. This command should be saved immediately after being written to the desired user or

default store. This is recommended when written as an individual command or as part of a series of commands in a configuration file

or script.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Bit Field

Type: R/W

Protectable: Yes

Default Value: 0402h

Units: N/A

COMMAND

Format

USER_CONFIG (D1h)

Bit Field

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

0

1

0

1

0

BIT

FIELD NAME

VALUE

SETTING

0-31d

DESCRIPTION

15:11 Minimum Duty Cycle 00000

Sets the minimum duty-cycle to 2 x (VALUE + 1)/512. Must be enabled with Bit 7

0 = PWML and PWMH are direct drive to MOSFET driver

1 = PWML is DRMOS Enable, PWMH is DRMOS PWM input

Not Used

0

Disable

Enable

Not Used

Disable

Enable

Not Used

VSET0

10

9:8

7

Enable DR MOS

Not Used

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Minimum Duty Cycle

Control

Control for minimum duty cycle

6

Not Used

0 = Uses only VSET0 to set Pin-strapped output voltage

1 = Uses only VSET1 to set Pin-strapped output voltage

5

VSET Select

VSET1

Disable

Enable

4

3

2

1

0

Margin Ratio Enable

PWML disabled state

Use VOUT_MARGIN_RATIO to program margin values when enabled

Low when disabled

High when disabled

Open Drain

Push-pull

PWML is low (off) when device is disabled (Bit 3 set to 0), or high (on) when device

is disabled (Bit 3 set to 1)

0 = PG is open-drain output

1 = PG is push-pull output

Power-good

Configuration

Disable

XTEMP Enable

Enable external temperature sensor

Enable

Disable

XTEMP Fault Select

Selects external temperature sensor to determine temperature faults

Enable

FN7558.3

September 14, 2015

Submit Document Feedback

60

ZL8800

IIN_CAL_GAIN (D2h)

Definition: Sets the effective impedance across the current sense circuit for use in calculating input current at +25°C.

Paged or Global: Global

Data Length in Bytes: 2

Data Format: Linear-11.

Type: R/W

Protectable: Yes

Default Value: C200h (2mΩ)

Units: mΩ

N

Equation: IIN_CAL_GAIN = Y×2

COMMAND

Format

IIN_CAL_GAIN (D2h)

Linear-11

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

Signed Exponent, N

Signed Mantissa, Y

Default Value

1

0

1

0

DDC_CONFIG (D3h)

Definition: Configures DDC addressing and current sharing. To operate as a 2-phase controller, set both phases to the same Rail ID, set

Phases in Rail to 2, then set each phase ID sequentially as 0 and 1. The ZL8800 will automatically equally offset the phases in the rail.

Phase spreading is done automatically as part of the DDC_CONFIG command, the INTERLEAVE command only applies to non-current

sharing rails. The ZL8800 can operate as a 2-phase controller, current sharing between it’s 2 internal phases, but does not support

current sharing with other ZL8800 devices or phases.

NOTE: The output MUST be connected to VSEN0P and VSEN0N when operating as a 2-phase controller.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Bit Field

Type: R/W

Protectable: Yes

Default Value: PMBus™ address pin-strap dependent.

Units: N/A

COMMAND

Format

DDC_CONFIG (D3h)

Bit Field

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

0

Lower 5 bits of device address

0

BIT

15:13

12:8

7:3

FIELD NAME

Phase ID

VALUE

0 to 7

SETTING

DESCRIPTION

0

Sets the output's phase position within the rail

Rail ID

0 to 31d

00

Identifies the device as part of a current sharing rail (Shared output)

Not Used

00

0

2:0

Phases In Rail

0 to 7

Identifies the number of phases on the same rail (+1)

FN7558.3

September 14, 2015

Submit Document Feedback

61

ZL8800

POWER_GOOD_DELAY (D4h)

Definition: Sets the delay applied between the output exceeding the PG threshold (POWER_GOOD_ON) and asserting the PG pin. The

delay time can range from 0ms up to 500s, in steps of 125ns. A 1ms minimum configured value is recommended to apply proper

debounce to this signal.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11.

Type: R/W

Protectable: Yes

Default Value: BA00h, 1ms

Units: ms

N

Equation: POWER_GOOD_DELAY = Y×2

Range: 0 t0 5 seconds

COMMAND

Format

POWER_GOOD_DELAY (D4h)

Linear-11

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

Signed Exponent, N

Signed Mantissa, Y

Default Value

1

0

1

0

1

0

INDUCTOR (D6h)

Definition: Informs the device of the circuit’s inductor value. This is used in adaptive algorithm calculations relating to the inductor

ripple current.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11.

Type: R/W

Protectable: Yes

Default Value: B23Dh (0.56µH)

Units: µH

N

Equation: INDUCTOR = Y×2

Range: 0 to 100µH

COMMAND

Format

INDUCTOR (D6h)

Linear-11

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

Signed Exponent, N

Signed Mantissa, Y

Default Value

1

0

1

0

1

0

1

0

1

FN7558.3

September 14, 2015

Submit Document Feedback

62

ZL8800

VOUT_MARGIN RATIO (D7h)

Definition: Percentage to set MARGIN_HIGH and MARGIN_LOW above and below VOUT_COMMAND when feature is enabled by

USER_CONFIG.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11

Type: R/W

Protectable: Yes

Default Value: 5 (CA80h)

Units: %

N

Equation: VOUT_MARGIN_RATIO = Y×2

Range: 0 to 50%

COMMAND

Format

VOUT_MARGIN_RATIO (D7h)

Linear-11

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

Signed Exponent, N

Signed Mantissa, Y

Default Value

1

0

1

0

1

0

1

0

OVUV_CONFIG (D8h)

Definition: Configures the output voltage OV and UV fault detection feature

Paged or Global: Paged

Data Length in Bytes: 1

Data Format: Bit Field

Type: R/W

Protectable: Yes

Default Value: 00h

Units: N/A

COMMAND

Format

OVUV_CONFIG (D8h)

Bit Field

Bit Position

Access

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

0

BITS

7

PURPOSE

VALUE

0

DESCRIPTION

Controls how an OV fault response shutdown sets the output

driver state

An OV fault does not enable low-side power device

An OV fault enables the low-side power device

Not Used

1

0

6:4 Not Used

Defines the number of consecutive limit violations required to

declare an OV or UV fault

3:0

N

N+1 consecutive OV or UV violations initiate a fault response

FN7558.3

September 14, 2015

Submit Document Feedback

63

ZL8800

XTEMP_SCALE (D9h)

Definition: Sets a scalar value that is used for calibrating the external temperature. The constant is applied in the equation below to

produce the read value of XTEMP via the PMBus™ command READ_EXTERNAL_TEMP.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11.

Type: R/W

Protectable: Yes

Default Value: BA00h (1.0)

Units: 1/°C





1

Equation:

READ_TEMPERATURE_2 ExternalTemperature

  XTEMP_OFFSET





XTEMP_SCALE





Range: 0.1 to 10

COMMAND

Format

XTEMP_SCALE (D9h)

Linear-11

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

Signed Exponent, N

Signed Mantissa, Y

Default Value

1

0

1

0

1

0

XTEMP_OFFSET (DAh)

Definition: Sets an offset value that is used for calibrating the external temperature. The constant is applied in the equation below to

produce the read value of XTEMP via the PMBus™ command READ_EXTERNAL_TEMP.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11.

Type: R/W

Protectable: Yes

Default Value: 0000h (0)

Units: °C



1



Equation:

READ_TEMPERATURE_2 ExternalTemperature

  XTEMP_OFFSET





XTEMP_SCALE





Range: -100 to 100

COMMAND

Format

XTEMP_OFFSET (DAh)

Linear-11

Bit Position

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Access

Function

R/W

Signed Exponent, N

Signed Mantissa, Y

Default Value

0

FN7558.3

September 14, 2015

Submit Document Feedback

64

ZL8800

TEMPCO_CONFIG (DCh)

Definition: Configures the correction factor and temperature measurement source when performing temperature coefficient correction

for current sense. TEMPCO_CONFIG values are applied as negative correction to a positive temperature coefficient.

Paged or Global: Paged

Data Length in Bytes: 1

Data Format: Bit Field

Type: R/W

Protectable: Yes

Default Value: 27h (3900ppm/°C)

Equation: To determine the hex value of the Tempco Correction factor (TC) for current scale of a power stage current sensing, first

determine the temperature coefficient of resistance for the sensing element, α. This is found with the equation:

R_REF R

R_REF(T_REFT )

 

Where:

R = Sensing element resistance at temperature “T”

R

= Sensing element resistance at reference temperature T

REF

α = Temperature coefficient of resistance for the sensing element material

T = Temperature measured by temperature sensor, in Degrees Celsius

T

= Reference temperature that α is specified at for the sensing element material

REF

After α is determined, convert the value in units of 100ppm/°C. This value is then converted to a hex value with the following equation:

 10⁶

100

TC 

Typical Values: Copper = 3900ppm/˚C (27h), silicon = 4800ppm/˚C (30h)

Range: 0 to 6300ppm/˚C

COMMAND

Format

TEMPCO_CONFIG (DCh)

Bit Field

Bit Position

Access

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

0

1

0

1

BITS

7

PURPOSE

VALUE

0

DESCRIPTION

Selects the temp sensor source for tempco correction

Selects the internal temperature sensor

Selects the XTEMP pin for temperature measurements (2N3904 Junction)

Note that XTEMP must be enabled in USER_CONFIG, bit 1.

1

Sets the tempco correction in units of 100ppm/˚C for

IOUT_CAL_GAIN

RSEN (DCR) = IOUT_CAL_GAIN x (1+TC x (T-25))

where RSEN = resistance of sense element

6:0

TC

FN7558.3

September 14, 2015

Submit Document Feedback

65

ZL8800

DEADTIME (DDh)

Definition: Sets the nonoverlap between PWM transitions using a 2-byte data field. The most significant byte controls the high-side to

low-side dead time value as a single 2’s-complement signed value in units of ns. The least-significant byte controls the low-side to

high-side dead time value. Positive values imply a non-overlap of the FET drive on-times. Negative values imply an overlap of the FET

drive on-times. The device will operate at the dead time values written to this command when adaptive dead time is disabled, between

the minimum dead time specified in DEADTIME_CONFIG and the maximum dead time specified in DEADTIME_MAX. When switching

from adaptive dead time mode to frozen mode (by writing to Bit 15 of DEADTIME_CONFIG) the frozen dead time will be whatever the

last dead time was before the device switches to frozen dead time mode.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Two 2’s complement bytes

Type: R/W

Protectable: Yes

Default Value: 1010h (16ns/16ns)

Units: ns

Range: -15ns to 60ns

COMMAND

Format

DEADTIME (DDh)

Linear-8 Signed

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

High to low-side dead time 8 bit two's complement signed

Low to high-side dead time 8 bit two's complement signed

Default Value

0

1

0

1

0

DEADTIME_CONFIG (DEh)

Definition: Configures the adaptive dead time optimization mode. Also sets the minimum dead time value for the adaptive dead time

mode range.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Bit Field

Type: R/W

Protectable: Yes

Default Value: 0808h (Adaptive dead time control, 8ns/8ns minimum dead time)

Units: N/A

COMMAND

Format

DEADTIME_CONFIG (DEh)

Bit Field/Linear-7 Unsigned

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

0

1

0

1

0

BITS

15

PURPOSE

VALUE

DESCRIPTION

0

1

Adaptive HIGH to LOW dead time control

Freeze the HIGH to LOW dead time

Sets the HIGH to LOW transition dead time mode

Sets the minimum HIGH to LOW dead time

Sets the LOW to HIGH transition dead time mode

Sets the minimum LOW to HIGH dead time

Limits the minimum allowed HIGH to LOW dead time when using

the adaptive dead time algorithm (2ns resolution)

14:8

7

0-126d

0

1

Adaptive LOW to HIGH dead time control

Freeze the LOW to HIGH dead time

Limits the minimum allowed LOW to HIGH dead time when using

the adaptive dead time algorithm (2ns resolution)

6:0

0-126d

FN7558.3

September 14, 2015

Submit Document Feedback

66

ZL8800

ASCR_CONFIG (DFh)

Definition: Allows user configuration of ASCR settings. ASCR gain and residual value are automatically set by the ZL8800 based on

input voltage and output voltage. ASCR Gain is analogous to bandwidth, ASCR Residual is analogous to damping. To improve load

transient response performance, increase ASCR Gain. To lower transient response overshoot, increase ASCR Residual. Increasing ASCR

gain can result in increased PWM jitter and should be evaluated in the application circuit. Excessive ASCR gain can lead to excessive

output voltage ripple. Increasing ASCR Residual to improve transient response damping can result in slower recovery times, but will not

affect the peak output voltage deviation. Typical ASCR Gain settings range from 100 to 1000, and ASCR Residual settings range from

10 to 90.

Paged or Global: Paged

Data Length in Bytes: 4

Data Format: Bit Field and nonsigned binary

Type: R/W

Protectable: Yes

Default Value: 015A0100h (Gain = 256d, Residual = 90d, ASCR enabled)

Units: N/A

COMMAND

Format

ASCR_CONFIG (DFh)

Bit Field/Linear-8 Unsigned

Bit Position

Access

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

R/W

Function

See Following Table

Default Value

Format

0

1

0

1

0

Linear-16 Unsigned

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

0

1

0

BITS

PURPOSE

Not Used

VALUE

0000000h

1

DESCRIPTION

31:25

Not Used

Enable

24

ASCR Enable

0

Disable

23:16

15:0

ASCR Residual Setting

ASCR Gain Setting

5Ah

ASCR residual

ASCR gain

0100h

FN7558.3

September 14, 2015

Submit Document Feedback

67

ZL8800

SEQUENCE (E0h)

Definition: Identifies the Rail DDC ID of the prequel and sequel rails when performing multirail sequencing. The device will enable its

output when its EN or OPERATION enable state, as defined by ON_OFF_CONFIG, is set and the prequel device has issued a power-good

event on the DDC bus. The device will disable its output (using the programmed delay values) when the sequel device has issued a

power-down event on the DDC bus.

The data field is a two-byte value. The most-significant byte contains the 5-bit Rail DDC ID of the prequel device. The least-significant

byte contains the 5-bit Rail DDC ID of the sequel device. The most significant bit of each byte contains the enable of the prequel or

sequel mode. This command overrides the corresponding sequence configuration set by the CONFIG pin settings.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Bit Field

Type: R/W

Protectable: Yes

Default Value: 00h (Prequel and sequel disabled)

Units: N/A

COMMAND

Format

SEQUENCE (E0h)

Bit Field

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

0

BIT

FIELD NAME

VALUE

SETTING

Disable

Enable

DESCRIPTION

Disable, no prequel preceding this rail

0

15

Prequel Enable

1

Enable, prequel to this rail is defined by bits 12:8

Not Used

14:13

12:8

Not Used

0

0-31d

0

Not Used

DDC ID

Disable

Enable

Prequel Rail DDC ID

Set to the DDC ID of the prequel rail

Disable, no sequel following this rail

Enable, sequel to this rail is defined by bits 4:0

Not Used

7

Sequel Enable

1

6:5

4:0

Not Used

0

Not Used

DDC ID

Sequel Rail DDC ID

0-31d

Set to the DDC ID of the sequel rail

FN7558.3

September 14, 2015

Submit Document Feedback

68

ZL8800

TRACK_CONFIG (E1h)

Definition: Configures the voltage tracking modes of the device. Only 1 channel can be configured to track: Channel 0, Channel 1 or the

output of a 2-phase application.

Paged or Global: Paged

Data Length in Bytes: 1

Data Format: Bit Field

Type: R/W

Protectable: Yes

Default Value: 00h

Units: N/A

COMMAND

Format

TRACK_CONFIG (E1h)

Bit Field

Bit Position

Access

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

0

BIT

7

FIELD NAME

VALUE

SETTING

Disable

Enable

Not Used

100%

DESCRIPTION

0

Tracking is disabled

Tracking is enabled

Not Used

Voltage Tracking Control

Not Used

1

6:3

2

0000

0

1

0

1

0

1

Output tracks at 100% ratio of VTRK input

Output tracks at 50% ratio of VTRK input

Output voltage is limited by target voltage

Output voltage is limited by VTRK voltage

Tracking Ratio Control

50%

Target Voltage

VTRK Voltage

Track after PG

Track always

1

0

Tracking Upper Limit

Ramp-Up Behavior

The output is not allowed to track VTRK down before power-good

The output is allowed to track VTRK down before power-good

FN7558.3

September 14, 2015

Submit Document Feedback

69

ZL8800

DDC_GROUP (E2h)

Definition: Rails (output voltages) are assigned Group numbers in order to share specified behaviors. The DDC_GROUP command

configures fault spreading group ID and enable, broadcast OPERATION group ID and enable, and broadcast VOUT_COMMAND group ID

and enable. Note that DDC Groups are separate and unique from DDC Phases and INTERLEAVE groups. Current sharing rails need to be

in the same DDC Group in order to respond to broadcast VOUT_COMMAND and OPERATION commands. Power fail event responses

(and Phases) are automatically spread in phase 0 and 1 when the ZL8800 is operating in 2-phase current sharing mode when it is

configured using DDC_CONFIG, regardless of it’s setting in DDC_GROUP.

Paged or Global: Paged

Data Length in Bytes: 3

Data Format: Bit Field

Type: R/W

Protectable: Yes

Default Value: 000000h (Ignore BROADCAST VOUT_COMMAND and OPERATION, Sequence shutdown on POWER_FAIL event)

Units: N/A

COMMAND

Format

DDC_GROUP (E2h)

Bit Field

Bit Position 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Access

R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/

W

Function

See Following Table

Default

Value

Lower 5 bits of device

address

Lower 5 bits of device

address

Lower 5 bits of device

address

0

BITS

PURPOSE

Not Used

VALUE

DESCRIPTION

23:22

00

1

Not Used

Responds to BROADCAST_VOUT_COMMAND with same Group ID

Ignores BROADCAST_VOUT_COMMAND

21

BROADCAST_VOUT_COMMAND response

0

20:16 BROADCAST_VOUT_COMMAND group ID

0-31d Group ID sent as data for broadcast BROADCAST_VOUT_COMMAND events

15:14

13

Not Used

00

1

Not Used

Responds to BROADCAST_OPERATION with same Group ID

Ignores BROADCAST_OPERATION

BROADCAST_OPERATION response

0

12:8

7:6

BROADCAST_OPERATION group ID

Not Used

0-31d Group ID sent as data for broadcast BROADCAST_OPERATION events

00

1

Not Used

Responds to POWER_FAIL events with same Group ID by shutting down immediately

Responds to POWER_FAIL events with same Group ID with sequenced shutdown

5

POWER_FAIL response

POWER_FAIL group ID

0

4:0

0-31d Group ID sent as data for broadcast POWER_FAIL events

FN7558.3

September 14, 2015

Submit Document Feedback

70

ZL8800

DEVICE_ID (E4h)

Definition: Returns the 16-byte (character) device identifier string. The format is: Part number, Major Revision, (period), Minor Revision,

Engineering version letter

Paged or Global: Global

Data Length in Bytes: 16

Data Format: ASCII. ISO/IEC 8859-1

Type: Block Read

Protectable: No

Default Value: ZL8800, current major revision, (period), current minor revision, current engineering version letter

Units: N/A

COMMAND

Format

DEVICE_ID (E4h)

Characters (Bytes)

Characters

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

Part Number

Maj. Rev.

.

Min. Rev

Engr.

*

Default Value

Z

L

8

0

*

* current revision at time of manufacture

MFR_IOUT_OC_FAULT_RESPONSE (E5h)

Definition: Configures the I overcurrent fault response as defined by the following table. The command format is the same as the

OUT

PMBus™ standard fault responses except that it sets the overcurrent status bit in STATUS_IOUT. The retry time is the time between

restart attempts.

Paged or Global: Paged

Data Length in Bytes: 1

Data Format: Bit Field

Type: R/W

Protectable: Yes

Default Value: 80h (Immediate shutdown, no retries)

Units: Retry time = 70ms

COMMAND

Format

MFR_IOUT_OC_FAULT_RESPONSE (E5h)

Bit Field

Bit Position

Access

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

1

0

BIT

7:6

FIELD NAME

VALUE

DESCRIPTION

Response Behavior: For all modes, the

device:

• Pulls SALRT low

• Sets the related fault bit in the

status registers. Fault bits are only

cleared by the CLEAR_FAULTS

command.

00

01

10

Not Used

Disable without delay and retry according to the setting in bits 5:3.

11

Not Used

000

No retry. The output remains disabled until the fault is cleared.

001-110 Not Used

5:3

2:0

Retry Setting

Not Used

Attempts to restart continuously, without checking if the fault is still present, until it is

commanded OFF (by the CONTROL pin or OPERATION command or both), bias power is

removed, or another fault condition causes the unit to shut down.

111

000-111 Not Used

FN7558.3

September 14, 2015

Submit Document Feedback

71

ZL8800

MFR_IOUT_UC_FAULT_RESPONSE (E6h)

Definition: Configures the I undercurrent fault response as defined by the following table. The command format is the same as the

OUT

PMBus™ standard fault responses except that it sets the undercurrent status bit in STATUS_IOUT. The retry time is the time between

restart attempts.

Data Length in Bytes: 1

Paged or Global: Paged

Data Format: Bit Field

Type: R/W

Protectable: Yes

Default Value: 80h (Immediate shutdown, no retries)

Units: Retry time unit = 70ms

COMMAND

Format

MFR_IOUT_UC_FAULT_RESPONSE (E6h)

Bit Field

Bit Position

Access

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

1

0

BIT

7:6

FIELD NAME

VALUE

00

DESCRIPTION

Response Behavior: For all modes, the device:

• Pulls SALRT low

• Sets the related fault bit in the status

registers. Fault bits are only cleared by the

CLEAR_FAULTS command.

Not Used

01

10

Disable without delay and retry according to the setting in bits 5:3.

Not Used

11

000

No retry. The output remains disabled until the fault is cleared.

001-110 Not Used

5:3

2:0

Retry Setting

Not Used

Attempts to restart continuously, without checking if the fault is still present, until it

is commanded OFF (by the CONTROL pin or OPERATION command or both), bias

power is removed, or another fault condition causes the unit to shut down.

111

000-111 Not Used

FN7558.3

September 14, 2015

Submit Document Feedback

72

ZL8800

IOUT_AVG_OC_FAULT_LIMIT (E7h)

Definition: Sets the I average overcurrent fault threshold. For downslope sensing, this corresponds to the average of all the current

OUT

samples taken during the (1-D) time interval, excluding the current sense blanking time (which occurs at the beginning of the 1-D

interval). For up-slope sensing, this corresponds to the average of all the current samples taken during the D time interval, excluding the

current sense blanking time (which occurs at the beginning of the D interval). This feature shares the OC fault bit operation (in

STATUS_IOUT) and OC fault response with IOUT_ OC_FAULT_LIMIT.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11.

Type: R/W

Protectable: Yes

Default Value: 0.8 x IOUT_OC_FAULT_LIMIT

Units: Amperes

N

Equation: IOUT_AVG_OC_FAULT_LIMIT = Y×2

Range: -100 to 100A

COMMAND

Format

IOUT_AVG_OC_FAULT_LIMIT (E7h)

Linear-11

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

Signed Exponent, N

Signed Mantissa, Y

0.8 x IOUT_OC_FAULT_LIMIT

Default Value

IOUT_AVG_UC_FAULT_LIMIT (E8h)

Definition: Sets the IOUT average undercurrent fault threshold. For downslope sensing, this corresponds to the average of all the current

samples taken during the (1-D) time interval, excluding the current sense blanking time (which occurs at the beginning of the 1-D

interval). For up-slope sensing, this corresponds to the average of all the current samples taken during the D time interval, excluding the

current sense blanking time (which occurs at the beginning of the D interval). This feature shares the UC fault bit operation (in

STATUS_IOUT) and UC fault response with IOUT_ UC_FAULT_LIMIT.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11.

Type: R/W

Protectable: Yes

Default Value: 0.8 x IOUT_UC_FAULT_LIMIT

Units: Amperes

N

Equation: IOUT_AVG_UC_FAULT_LIMIT = Y×2

Range: -100 to 100A

COMMAND

Format

IOUT_AVG_UC_FAULT_LIMIT (E8h)

Linear-11

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

Signed Exponent, N

Signed Mantissa, Y

0.8 x IOUT_UC_FAULT_LIMIT

Default Value

FN7558.3

September 14, 2015

Submit Document Feedback

73

ZL8800

USER_GLOBAL_CONFIG (E9h)

Definition: This command is used to set options for output voltage sensing, maximum output voltage override, SMBus time-out, and

DDC and SYNC output configurations.

Paged or Global: Global

Data Length in Bytes: 2

Data Format: Bit Field

Type: R/W

Protectable: Yes

Default Value: 0000h

Units: N/A

COMMAND

Format

USER_GLOBAL_CONFIG (E9h)

Bit Field

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

0

BITS

PURPOSE

Not Used

VALUE

DESCRIPTION

15:10

000000

Not Used

Vsense Select for monitoring and fault

detection

00

01

10

0

Output 0 uses VSEN0, Output 1 uses VSEN1

Both outputs use VSEN0

Both outputs use VSEN1

Not Used

9:8

7

6

5

4

3

Not Used

DDC output Configuration

0

DDC output open drain

DDC output push-pull

Not Used

1

Not Used

0

Disable SMBus Time-Outs

0

SMBus time-outs enabled

SMBus time-outs disabled

Not Used

1

Not Used

0

Sync I/O Control

00

01

10

11

0

Use internal clock (frequency initially set with pin-strap)

Use internal clock and output internal clock (not for use with pin-strap)

2:1

0

Use external clock

Not Used

FN7558.3

September 14, 2015

Submit Document Feedback

74

ZL8800

SNAPSHOT (EAh)

Definition: The SNAPSHOT command is a 32-byte read-back of parametric and status values. It allows monitoring and status data to be

stored to flash either during a fault condition or via a system-defined time using the SNAPSHOT_CONTROL command. Snapshot is

continuously updated in RAM and can be read using the SNAPSHOT command. When a fault occurs, the latest snapshot in RAM is

stored to flash. Snapshot data can read back by writing a 01h to the SNAPSHOT_CONTROL command, then reading SNAPSHOT.

Paged or Global: Paged

Data Length in Bytes: 32

Data Format: Bit Field

Type: Block Read

Protectable: No

Default Value: N/A

Units: N/A

BYTE NUMBER

VALUE

Not Used

PMBus™ COMMAND

Not Used

FORMAT

0000h

31:23

22

Flash Memory Status Byte

Manufacturer Specific Status Byte

CML Status Byte

N/A

Bit Field

21

STATUS_MFR_SPECIFIC (80h)

STATUS_CML (7Eh)

STATUS_TEMPERATURE (7Dh)

STATUS_INPUT (7Ch)

STATUS_IOUT (7Bh)

STATUS_VOUT (7Ah)

READ_FREQUENCY (95h)

READ_TEMPERATURE_2 (8Eh)

READ_TEMPERATURE_1 (8Dh)

READ_DUTY_CYCLE (94h)

N/A

1 Byte Bit Field

2 Byte Linear-11

2 Byte Linear-16 Unsigned

2 Byte Linear-11

20

19

Temperature Status Byte

Input Status Byte

18

17

Iout Status Byte

16

Vout Status Byte

15:14

13:12

11:10

9:8

Switching Frequency

External Temperature

Internal Temperature

Duty Cycle

7:6

Highest Measured Output Current

Output Current

5:4

READ_IOUT (8Ch)

3:2

Output Voltage

READ_VOUT (8Bh)

1:0

Input Voltage

READ_VIN (88h)

BLANK_PARAMS (EBh)

Definition: Returns a 16-byte string which indicates which parameter values were either retrieved by the last RESTORE operation or

have been written since that time. Reading BLANK_PARAMS immediately after a restore operation allows the user to determine which

parameters are stored in that store. A one indicates the parameter is not present in the store and has not been written since the

RESTORE operation.

Paged or Global: Paged

Data Length in Bytes: 16

Data Format: Bit Field

Type: Block Read

Protectable: No

Default Value: FF…FFh

Units: N/A

FN7558.3

September 14, 2015

Submit Document Feedback

75

ZL8800

LEGACY_FAULT_GROUP (F0h)

Definition: This command allows the ZL8800 to sequence and fault spread with devices other than the ZL8800 family of ICs. This

command sets which rail DDC IDs should be listened to for fault spreading information. The data sent is a 4-byte, 32-bit bit vector

where every bit represents a rail’s DDC ID. A bit set to 1 indicates a device DDC ID to which the configured device will respond upon

receiving a fault spreading event. In this vector, bit 0 of byte 0 corresponds to the rail with DDC ID 0. Following through, Bit 7 of byte 3

corresponds to the rail with DDC ID 31.

NOTE: The device/rail’s own DDC ID should not be set within the LEGACY_FAULT_GROUP command for that device/rail.

All devices in a current share rail (devices other than the ZL8800 family ICs) must shut down for the rail to report a shutdown.

If fault spread mode is enabled in USER_CONFIG, the device will immediately shut down if on of its DDC_GROUP members fail. The

device/rail will attempt its configured restart only after all devices/rails within the DDC_GROUP have cleared their faults.

If fault spread mode is disabled in USER_CONFIG, the device will perform a sequenced shutdown as defined by the SEQUENCE

command setting. The rails/devices in a sequencing set only attempt their configured restart after all faults have cleared within the

DDC_GROUP. If fault spread mode is disabled and sequencing is also disabled, the device will ignore faults from other devices and stay

enabled.

Paged or Global: Paged

Data Length in Bytes: 4

Data Format: Bit field

Type: Block R/W

Protectable: Yes

Default Value: 00000000h

Units: N/A

COMMAND

Format

LEGACY_FAULT_GROUP (F0h)

Bit Field

Bit Position

Access

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

R/W

Function

See Following Table

Default Value

Format

0

Bit Field

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

0

BIT

FIELD NAME

Fault Group

VALUE

NA

SETTING

DESCRIPTION

31:0

00000000h Identifies the devices in the fault spreading group.

FN7558.3

September 14, 2015

Submit Document Feedback

76

ZL8800

SNAPSHOT_CONTROL (F3h)

Definition: Writing a 01h will cause the device to copy the current SNAPSHOT values from NVRAM to the 32-byte SNAPSHOT command

parameter. Writing a 02h will cause the device to write the current SNAPSHOT values to NVRAM, 03h will erase all SNAPSHOT values

from NVRAM. Write (02h) and Erase (03h) may only be used when the device is disabled. All other values will be ignored.

Paged or Global: Paged

Data Length in Bytes: 1

Data Format: Bit Field

Type: R/W byte

Protectable: Yes

Default Value: N/A

Units: N/A

COMMAND

Format

SNAPSHOT_CONTROL (F3h)

Bit Field

Bit Position

Access

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

0

VALUE

01

DESCRIPTION

Read SNAPSHOT values from NVRAM

Write SNAPSHOT values to NVRAM

Erase SNAPSHOT values from NV RAM

02

03

RESTORE_FACTORY (F4h)

Definition: Restores the device to the hard-coded Factory default values and pin-strap definitions. The device retains the DEFAULT and

USER stores for restoring. Security level is changed to Level 1 following this command.

Paged or Global: Global

Data Length in Bytes: 0

Data Format: N/A

Type: Write only

Protectable: Yes

Default Value: N/A

Units: N/A

MFR_VMON_OV_FAULT_LIMIT (F5h)

Definition: Sets the VMON overvoltage fault threshold. A VMON parameter equals 16 times the voltage applied to the VMON pin. The

VMON overvoltage warn limit is automatically set to 90% of this fault value.

Paged or Global: Global

Data Length in Bytes: 2

Data Format: Linear-11.

Type: R/W

Protectable: Yes

Default Value: D300h (12V)

Units: V

N

Equation: MFR_VMON_OV_FAULT_LIMIT = Y×2

Range: 0 to 19V

COMMAND

Format

MFR_VMON_OV_FAULT_LIMIT (F5h)

Linear-11

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

Signed Exponent, N

Signed Mantissa, Y

Default Value

1

0

1

0

1

0

FN7558.3

September 14, 2015

Submit Document Feedback

77

ZL8800

MFR_VMON_UV_FAULT_LIMIT (F6h)

Definition: Sets the VMON undervoltage fault threshold. A VMON parameter equals 16x the voltage applied to the VMON pin. The VMON

undervoltage warn limit is automatically set to 110% of this fault value.

Paged or Global: Global

Data Length in Bytes: 2

Data Format: Linear-11.

Type: R/W

Protectable: Yes

Default Value: CA40h (4.5V)

Units: V

N

Equation: MFR_VMON_UV_FAULT_LIMIT = Y x 2

Range: 0 to 19V

COMMAND

Format

MFR_VMON_UV_FAULT_LIMIT (F6h)

Linear-11

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

Signed Exponent, N

Signed Mantissa, Y

Default Value

1

0

1

0

1

0

1

0

MFR_READ_VMON (F7h)

Definition: Reads the VMON voltage.

Paged or Global: Global

Data Length in Bytes: 2

Data Format: Linear-11.

Type: Read only

Protectable: No

Default Value: N/A

Units: V

N

Equation: MFR_READ_VMON = Y x 2

Range: 0 to 19V

COMMAND

Format

MFR_READ_VMON (F7h)

Linear-11

Bit Position

Access

15

14

13

R/W

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

Signed Exponent, N

N/A N/A N/A

Signed Mantissa, Y

N/A N/A N/A

Default Value

N/A

FN7558.3

September 14, 2015

Submit Document Feedback

78

ZL8800

VMON_OV_FAULT_RESPONSE (F8h)

Definition: Configures the VMON overvoltage fault response as defined by the following table. The retry time is the time between restart

attempts

Paged or Global: Global

Data Length in Bytes: 1

Data Format: Bit Field.

Type: R/W

Protectable: Yes

Default Value: 80h (Immediate Shutdown, no retries)

Units: Retry time unit = 70ms

COMMAND

Format

VMON_OV_FAULT_RESPONSE (F8h)

Bit Field

Bit Position

Access

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

1

0

BIT

7:6

FIELD NAME

VALUE

DESCRIPTION

00

01

10

Not Used

Disable without delay and retry according to the setting in bits 5:3.

Response Behavior: The device:

• Pulls SALRT low

• Sets the related fault bit in the

status registers. Fault bits are only

cleared by the CLEAR_FAULTS

command.

Output is disabled while the fault is present. Operation resumes and the output is enabled

when the fault condition no longer exists.

11

000

No Retry. The output remains disabled until the fault is cleared.

001-110 Not Used

5:3

2:0

Retry Setting

Not Used

Attempts to restart continuously, without checking if the fault is still present, until it is

commanded OFF (by the CONTROL pin or OPERATION command or both), bias power is

removed, or another fault condition causes the unit to shut down.

111

000-111 Not Used

FN7558.3

September 14, 2015

Submit Document Feedback

79

ZL8800

VMON_UV_FAULT_RESPONSE (F9h)

Definition: Configures the VMON undervoltage fault response as defined by the following table. Note: The retry time is the time between

restart attempts

Paged or Global: Global

Data Length in Bytes: 1

Data Format: Bit Field.

Type: R/W

Protectable: Yes

Default Value: 80h (Immediate shutdown, no retries)

Units: Retry time unit = 70ms

COMMAND

Format

VMON_UV_FAULT_RESPONSE (F9h)

Bit Field

Bit Position

Access

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

1

0

BIT

7:6

FIELD NAME

VALUE

DESCRIPTION

Response Behavior: The device:

• Pulls SALRT low

• Sets the related fault bit in the

status registers. Fault bits are only

cleared by the CLEAR_FAULTS

command.

00

01

10

Not Used

Disable without delay and retry according to the setting in bits 5:3.

Output is disabled while the fault is present. Operation resumes and the output is enabled

when the fault condition no longer exists.

11

000

No Retry. The output remains disabled until the fault is cleared.

001-110 Not Used

5:3

2:0

Retry Setting

Not Used

Attempts to restart continuously, without checking if the fault is still present, until it is

commanded OFF (by the CONTROL pin or OPERATION command or both), bias power is

removed, or another fault condition causes the unit to shut down.

111

000-111 Not Used

SECURITY_LEVEL (FAh)

Definition: The device provides write protection for individual commands. Each bit in the UNPROTECT parameter controls whether its

corresponding command is writeable (commands are always readable). If a command is not writeable, a password must be entered in

order to change its parameter (i.e., to enable writes to that command). There are two types of passwords, public and private. The public

password provides a simple lock-and-key protection against accidental changes to the device. It would typically be sent to the device in

the application prior to making changes. Private passwords allow commands marked as non-writeable in the UNPROTECT parameter to

be changed. Private passwords are intended for protecting default-installed configurations and would not typically be used in the

application. Each store (USER and DEFAULT) can have its own UNPROTECT string and private password. If a command is marked as

non-writeable in the DEFAULT UNPROTECT parameter (its corresponding bit is cleared), the private password in the DEFAULT Store must

be sent in order to change that command. If a command is writeable according to the Default UNPROTECT parameter, it may still be

marked as non-writeable in the User Store UNPROTECT parameter. In this case, the User private password can be sent to make the

command writeable.

The device supports four levels of security. Each level is designed to be used by a particular class of users, ranging from module

manufacturers to end users, as discussed in the following. Levels 0 and 1 correspond to the public password. All other levels require a

private password. Writing a private password can only raise the security level. Writing a public password will reset the level down to 0 or

1.

Figure 12 shows the algorithm used by the device to determine if a particular command write is allowed.

FN7558.3

September 14, 2015

Submit Document Feedback

80

ZL8800

Write

Attempted

Always

Writeable

?

Y

N

Read

Only

?

Y

N

Security

Level == 3

?

Y

N

Default

UNPROTECT

== 0

Y

?

N

Security

Level == 2

?

Y

N

User

UNPROTECT

== 0

?

Y

N

Security

Level == 1

?

Write

Prohibited

Write

Allowed

N

Y

FIGURE 12. ALGORITHM USED TO DETERMINE WHEN A COMMAND IS WRITEABLE

Security Level 3 – Module Vendor

Level 3 is intended primarily for use by Module vendors to protect device configurations in the Default Store. Clearing a UNPROTECT bit

in the Default Store implies that a command is writeable only at Level 3 and above. The device’s security level is raised to Level 3 by

writing the private password value previously stored in the Default Store. To be effective, the module vendor must clear the UNPROTECT

bit corresponding to the STORE_DEFAULT_ALL and RESTORE_DEFAULT commands. Otherwise, Level 3 protection is ineffective since

the entire store could be replaced by the user, including the enclosed private password.

Security Level 2 – User

Level 2 is intended for use by the end user of the device. Clearing a UNPROTECT bit in the User Store implies that a command is

writeable only at Level 2 and above. The device’s security level is raised to Level 2 by writing the private password value previously

stored in the User Store. To be effective, the user must clear the UNPROTECT bit corresponding to the STORE_USER_ALL,

RESTORE_DEFAULT_ALL, STORE_DEFAULT_ALL, and RESTORE_DEFAULT commands. Otherwise, Level 2 protection is ineffective since

the entire store could be replaced, including the enclosed private password.

Security Level 1 – Public

Level 1 is intended to protect against accidental changes to ordinary commands by providing a global write-enable. It can be used to

protect the device from erroneous bus operations. It provides access to commands whose UNPROTECT bit is set in both the Default and

User Store. Security is raised to Level 1 by writing the public password stored in the User Store using the PUBLIC_PASSWORD

command. The public password stored in the Default Store has no effect.

FN7558.3

September 14, 2015

Submit Document Feedback

81

ZL8800

Security Level 0 - Unprotected

Level 0 implies that only commands which are always writeable (e.g., PUBLIC_PASSWORD) are available. This represents the lowest

authority level and hence the most protected state of the device. The level can be reduced to 0 by using PUBLIC_PASSWORD to write

any value which does not match the stored public password.

Paged or Global: Global

Data Length in Bytes: 1

Data Format: Hex

Type: Read Byte

Protectable: No

Default Value: 01h

Units: N/A

Reference: AN2031 - Writing Configuration Files for Intersil Digital Power

PRIVATE_PASSWORD (FBh)

Definition: Sets the private password string.

Paged or Global: Global

Data Length in Bytes: 9

Data Format: ASCII. ISO/IEC 8859-1

Type: Block R/W

Protectable: No

Default Value: 000000000000000000h

Units: N/A

Reference: AN2031 - Writing Configuration Files for Intersil Digital Power

PUBLIC_PASSWORD (FCh)

Definition: Sets the public password string.

Paged or Global: Global

Data Length in Bytes: 4

Data Format: ASCII. ISO/IEC 8859-1

Type: Block R/W

Protectable: No

Default Value: 00000000h

Units: N/A

Reference: AN2031 - Writing Configuration Files for Intersil Digital Power

UNPROTECT (FDh)

Definition: Sets a 256-bit (32-byte) parameter which identifies which commands are to be protected against write-access at lower

security levels. Each bit in this parameter corresponds to a command according to the command’s code. The command with a code of

00h (PAGE) is protected by the least-significant bit of the least-significant byte, followed by the command with a code of 01h and so

forth. Note that all possible commands have a corresponding bit regardless of whether they are protectable or supported by the device.

Clearing a command’s UNPROTECT bit indicates that write-access to that command is only allowed if the device’s security level has

been raised to an appropriate level. The UNPROTECT bits in the DEFAULT store require a security level 3 or greater to be writeable. The

UNPROTECT bits in the USER store require a security level of 2 or higher.

Data Length in Bytes: 32

Paged or Global: Global

Data Format: Custom

Type: Block R/W

Protectable: No

Default Value: FF…FFh

Units: N/A

Reference: AN2031 - Writing Configuration Files for Intersil Digital Power

FN7558.3

September 14, 2015

Submit Document Feedback

82

ZL8800

Firmware Revision History

FIRMWARE REVISION CODE

CHANGE DESCRIPTION

NOTE

1.04

Initial Release

Not recommended for a new design

1. Fix to start-up routine to improve SA pin read

performance at cold temperatures.

2. Improved fault retry performance.

3. Improved DDC compatibility with previous generations

of Intersil controllers and modules.

1.06

Recommended for a new design

4. Addition of the LEGACY_FAULT_GROUP command to

allow for fault spreading over Intersil’s DDC bus with

previous generation of controllers and modules.

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you

have the latest revision.

DATE

REVISION

FN7558.3

CHANGE

September 14, 2015

-Added Related Literature section on page 1.

-Added Key Differences table to page 1.

-Updated Ordering Information table on page 8 by adding ZL8800ALBFT and ZL8800ALBFTK part numbers,

added FIRMWARE REVISION column, and added Note 5.

-Added LEGACY_FAULT_GROUP command to “PMBus™ Command Summary” on page 27 and in the

Command descriptions on page 76.

-Changed reference to 30ms to 70ms, and 20 to 30ms to 60 to 70ms in “Start-Up Procedure” on page 15.

-Added detail to TON_DELAY Range description on page 47.

-Added detail to TON_RISE Range description on page 47.

-Added detail to TOFF_DELAY Range description on page 48.

-Added Firmware Revision History section.

November 11, 2013

October 10, 2013

FN7558.2

FN7558.1

Added “™” to ChargeMode - page 1 title, 3rd paragraph and trademark statement bottom of page.

The maximum, ramp-up time and ramp-down time changed from 200ms to 100ms: pages 10, 47, 48.

The maxiumum soft-start delay, turn-off delay and power-good delay changed on pages 47, 48 and 62 to 5

seconds to match the limits in the EC table (page 10).

The 2nd table on page 60. The location and size of the bit field for minimum duty cycle changed from 2 bits

in location 9:8 to 5 bits in location 15:11.

September 18, 2013

FN7558.0

Initial Release

About Intersil

Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products

address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.

For the most updated datasheet, application notes, related documentation and related parts, please see the respective product

information page found at www.intersil.com.

You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.

Reliability reports are also available from our website at www.intersil.com/support.

For additional products, see www.intersil.com/en/products.html

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted

in the quality certifications found at www.intersil.com/en/support/qualandreliability.html

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time

without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be

accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN7558.3

September 14, 2015

Submit Document Feedback

83

ZL8800

Package Outline Drawing

L44.7x7B

44 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 0, 10/09

5.00 TYP

40X 0.50

7.00

A

6

B

44

PIN #1

INDEX

AREA

34

1

6

33

PIN 1

INDEX

AREA

5.20 ±0.1

EXP. DAP

23

11

44X 0.25 4

0.10 M C A B

(4X)

0.15

22

12

SIDE VIEW

TOP VIEW

5.20 ±0.1 EXP. DAP

BOTTOM VIEW

44X 0.55 ±0.1

( 6.65 )

SEE DETAIL "X"

( 5.20)

0.10C

C

1.00 MAX

0.08C

SIDE VIEW

( 6.65 )

( 5.20 )

( 40X 0.50)

5

C

0.2 REF

(44X .25)

0 . 00 MIN.

0 . 05 MAX.

( 44 X 0.75)

TYPICAL RECOMMENDED LAND PATTERN

DETAIL "X"

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

3.

Unless otherwise specified, tolerance : Decimal ± 0.05

4. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

Tiebar shown (if present) is a non-functional feature.

5.

6.

The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

Complies to JEDEC MO220 VKKD-1.

7.

FN7558.3

September 14, 2015

Submit Document Feedback

84


型号：	ZL8800-2CH-DEMO1Z
厂家：	Intersil
描述：	Dual Channel/Dual Phase PMBusâ¢ ChargeModeâ¢ Control DC/DC Digital Controller
文件：	总84页 (文件大小：1240K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ZL8800-2CH-DEMO1Z [INTERSIL]

相关型号：

ZL8800-2PH-DEMO1Z

ZL8800-2PH-DEMO1Z

ZL8800ALAFT

ZL8800ALAFT

ZL8800ALAFT7A

ZL8800ALAFTK

ZL8800ALAFTK

ZL8800ALBFT

ZL8800ALBFT

ZL8800ALBFT7A

ZL8800ALBFTK

ZL8800ALBFTK