IPS0551SPBF [INFINEON]
Buffer/Inverter Based Peripheral Driver, 100A, PSSO2, SMD-220;
| 型号： | IPS0551SPBF |
| 厂家： | 
Infineon |
| 描述： | Buffer/Inverter Based Peripheral Driver, 100A, PSSO2, SMD-220 驱动 接口集成电路 |
| 文件： | 总10页 (文件大小：105K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet No. PD60160-B
IPS0551T
FULLY PROTECTED POWER MOSFET SWITCH
Product Summary
Features
• Over temperature shutdown
• Over current shutdown
• Active clamp
• Low current & logic level input
• E.S.D protection
R
6.0mΩ (max)
ds(on)
clamp
V
40V
Ishutdown
100A
Description
T T
on/ off
4µs
The IPS0551T is a fully protected three terminal SMART
POWER MOSFET that features over-current, over-tem-
perature, ESD protection, and drain to source active
®
clamp. This device combines a HEXFET POWER
MOSFET and a gate driver. It offers full protection and
high reliability required in harsh environments. The driver
allows short switching times and provides efficient protec-
tionbyturningOFFthepowerMOSFETwhentemperature
exceeds 165oC or when the drain current reaches 100A.
The device restarts once the input is cycled. The ava-
lanche capability is significantly enhanced by the active
clamp and covers most inductive load demagnetiza-
tions.
Package
SUPER SMD220
SUPER TO220
Typical Connection
L o a d
D
S
R
in s e rie s
( if n e e d e d )
IN
c o n tr o l
L o g ic s ig n a l
(Refer to lead assignment for correct pin configuration)
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1
IPS0551T
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters
are referenced to SOURCE lead. (T
print with 70 µm copper thickness.
= 25oC unless otherwise specified). PCB mounting uses the standard foot-
Ambient
Symbol Parameter
Min.
Max.
Units
Test Conditions
V
Maximum drain to source voltage
—
37
ds
in
V
V
Maximum input voltage
-0.3
-10
7
I+
Maximum IN current
+10
mA
in
(1)
I
Diode max. continuous current
sd cont.
(rth=60oC/W)
(rth=5oC/W)
—
—
—
2.8
35
A
(1)
I
Diode max. pulsed current
100
sd pulsed
(1)
P
d
Maximum power dissipation
(rth=60oC/W)
Electrostatic discharge voltage (Human Body)
Electrostatic discharge voltage (Machine Model)
Max. storage temperature
—
—
2
4
W
ESD1
ESD2
C=100pF, R=1500Ω,
kV
—
0.5
150
+150
300
C=200pF, R=0Ω, L=10µH
T
T
T
-55
-40
—
stor.
oC
max. Max. junction temperature
j
Lead temperature (soldering, 10 seconds)
lead
Thermal Characteristics
Symbol Parameter
Min. Typ. Max. Units Test Conditions
R
R
R
R
1
2
3
4
Thermal resistance free air
—
—
—
—
60
60
35
0.7
—
—
th
th
th
th
Thermal resistance to PCB min footprint
Thermal resistance to PCB 1" sq. footprint
Thermal resistance junction to case
oC/W
—
Recommended Operating Conditions
These values are given for a quick design. For operation outside these conditions, please consult the application notes.
Symbol Parameter
Min. Max.
Units
V
V
V
Continuous drain to source voltage
High level input voltage
Low level input voltage
—
4
18
ds (max)
IH
IL
6
V
0
0.5
I
Continuous drain current
ds
Tamb=85oC
(
o
o
o
TAmbient = 85 C, IN = 5V, rth = 80 C/W, Tj = 125 C)
—
—
0.1
—
0
8
35
0.5
1
A
o
o
o
(
TAmbient = 85 C, IN = 5V, rth = 5 C/W, Tj = 125 C)
R
in
Recommended resistor in series with IN pin
kΩ
µ
S
T
Max recommended rise time for IN signal (see fig. 2)
Max. frequency in short circuit condition (Vcc = 14V)
r-in (max)
(2)
F -I
r sc
1
kHz
(1) Limited by junction temperature (pulsed current limited also by internal wiring)
(2) Operation at higher switching frequencies is possible. See Appl. Notes.
2
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IPS0551T
Static Electrical Characteristics
(T = 25oC and Vcc = 14V unless otherwise specified. Standard footprint 70µm of copper thickness)
j
Symbol Parameter
Min. Typ. Max. Units Test Conditions
ON state resistance T = 25oC
—
—
0
4.5
6.0
R
ds(on)
j
o
@Tj=25 C
ON state resistance T = 150oC
j
7.5
V
= 5V, I = 10A
ds
mΩ
µA
in
R
8.8
ds(on)
o
@Tj=150 C
Idss
@Tj=25 C
Drain to source leakage current
Drain to source clamp voltage 1
0.01
25
—
Vcc = 14V, Tj = 25oC
o
V clamp 1
I
= 20mA (see Fig.3 & 4)
d
I=35A -t<100us
37
—
—
40
43
0.85
V clamp 2 Drain to source clamp voltage 2
48
1
I
I
I
V
in
V
V
V
Body diode forward voltage
= 35A,
= 0V
d
sd
V
= 1 mA
IN to source clamp voltage
7
8.0
1.8
90
9.5
2.2
in
d
in clamp
th
=
,
IN threshold voltage
1.0
25
50
50mA Vds = 14V
,
I
I
Input supply current (normal operation)
Input supply current (protection mode)
300
400
V
V
= 5V
= 5V
in on
in
µA
130
in, off
in
over-current triggered
Switching Electrical Characteristics
V
= 14V, Resistive Load = 0.4Ω, Rinput = 50Ω, 100µs pulse, T = 25oC, (unless otherwise specified).
j
cc
Symbol Parameter
Min. Typ. Max. Units Test Conditions
T
T
T
T
T
Turn-on delay time
Rise time
0.25
0.25
—
1
1
15
4
4
4
—
8
on
r
rf
See figure 2
Time to 130% final R
Turn-off delay time
Fall time
µs
ds(on)
1.5
0.5
—
off
f
in
See figure 2
2
5
Q
nC
V
in
= 5V
Total gate charge
200
—
Protection Characteristics
Symbol Parameter
Min. Typ. Max. Units Test Conditions
T
Over temperature threshold
—
165
—
oC
See fig. 1
sd
I
Over current threshold
IN protection reset threshold
Time to reset protection
60
1.5
2
100
1.9
10
150
2.8
A
V
See fig. 1
sd
V
reset
T
40
µs
V
= 0V, Tj = 25oC
reset
in
100
1200
EOI_OT Short circuit energy (cf application note)
400
µJ
V
cc
= 14V
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IPS0551T
Functional Block Diagram
All values are typical
DRAIN
37 V
Ω
100 kΩ
200
IN
S
Q
Q
R
8V
I sense
T > 165°c
I > Isd
µ
80 A
SOURCE
Lead Assignments
2 ( D )
1 2 3
In D S
1 2 3
In D S
SUPER SMD220
(Advanced Information)
SUPER TO220
4
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IPS0551T
5 V
0 V
Vin
1900%%
Tr-in
t > T reset
t < T reset
Ids
I shutdown
Isd
90 %
10 %
Td on
Td off
tf
tr
T
T shutdown
Tsd
(165 °c)
Figure 2 - IN rise time & switching time definitions
Figure 1 - Timing diagram
T clamp
Vin
L
V load
Rem : V load is negative
during demagnetization
+
14 V
-
R
Ids
Vds clamp
D
S
Vin
IN
Vds
Ids
( Vcc )
5 v
0 v
Vds
(
see Appl . Notes to evaluate power dissipation )
Figure 3 - Active clamp waveforms
Figure 4 - Active clamp test circuit
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5
IPS0551T
All curves are typical values with standard footprint. Operating in the shaded area is not recommended.
12
200%
11
180%
160%
10
9
140%
120%
100%
80%
60%
40%
20%
0%
8
7
6
5
4
3
2
1
0
Tj = 150oC
Tj = 25oC
0
1
2
3
4
5
6
7
8
-50 -25
0
25 50 75 100 125 150 175
Figure 5 - Rds
(mΩ) Vs Input Voltage (V)
Figure 6 - Normalised Rds
(on)
(%) Vs T (oC)
j
(on)
40
40
35
30
25
20
15
10
5
toff delay
fall time
ton delay
130% rdson
rise time
35
30
25
20
15
10
5
0
0
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
Figure 7 - Turn-ON Delay Time, Rise Time & Time
to 130% final Rds(on) (us) Vs Input Voltage (V)
Figure 8 - Turn-OFF Delay Time & Fall Time (us)
Vs Input Voltage (V)
6
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IPS0551T
1 0 0
1 0
1
1 0 0
1 0
1
delay off
fall time
delay on
rise time
130% rdson
1 0
1 0 0
1 0 0 0
10
100
1000
Figure 9 - Turn-ON Delay Time, Rise Time & Time
Figure 10 - Turn-OFF Delay Time & Fall Time (us)
to 130% final Rds(on) (us) Vs IN Resistor (Ω)
Vs IN Resistor (Ω)
100
90
80
70
60
50
40
30
20
10
0
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
Isd 25°C
Ilim 25°C
0
1
2
3
4
5
6
7
8
9
-50 -25
0
25 50 75 100 125 150
Figure 12 - Over-current (A) Vs Temperature (oC)
Figure 11 - Current Iim. & Ishutdown (A) Vs Vin (V)
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IPS0551T
1000
100
10
rth = 1 °C /W (c a s e t o a m b ie n t )
T=25°C free air/ std. footprint
T=100°C free air/ std. footprint
rth = 5 °C /W
rth = 1 5 °C /W
100
90
80
70
60
50
40
30
20
10
0
rth = 3 0 °C /W: 1 '' fo o tp rin t
rth = 6 0°C / W: s t d . fo o t p rin t
Current path capability should
be above this curve
Load characteristic should
be below this curve
-50
0
50
100
150
200
1
Figure 14 - Ids (A) Vs Protection Resp. Time (s)
Figure 13 - Max.Cont. Ids (A) Vs
Amb. Temperature (oC)
1 .0 0 E+0 2
single pulse
1000
100
10
10 Hz rth=60°C/W dT=25°C
100Hz rth=60°C/W dT=25°C
1 .0 0 E+0 1
1 .0 0 E+0 0
1 .0 0 E-0 1
1 .0 0 E-0 2
Single pulse
rth free air / std. fooprint
rth 1 inch² footprint
rth infinite heatsink
1
0.1
0 .0 0 1
0 .0 1
0 .1
1
1 0
Figure 16 - Transient Thermal Imped. (oC/W)
Vs Time (s)
Figure 15 - Iclamp (A) Vs Inductive Load (mH)
8
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IPS0551T
200
180
160
140
120
100
80
16
14
12
10
8
Treset
rise time
fall time
6
60
4
Iin,on
Iin,off
40
2
20
0
0
-50 -25
0
25 50 75 100 125 150
-50 -25
0
25 50 75 100 125 150
Figure 17 - Inputcurrent (µA) Vs Junction (oC)
Figure 18 - Turn-on, Turn-off and Treset (µS) Vs Tj (oC)
120%
115%
110%
105%
100%
95%
90%
Vds clamp @ Isd
85%
Vin clamp @ 10mA
80%
-50 -25
0
25 50 75 100 125 150
Figure 19 - Vin clamp1 & Vin clamp2 (%) Vs Tj (oC)
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IPS0551T
Case outline Super TO220
9.00 [.354]
8.00 [.315]
11.00 [.433]
10.00 [.394]
B
A
5.00 [.196]
4.00 [.158]
0.25 [.010]
B
A
1.50 [.059]
0.50 [.020]
13.50 [.531]
12.50 [.493]
4
15.00 [.590]
14.00 [.552]
1
2
3
LEAD ASSIGNMENTS
MOS F E T
IGBT
4.00 [.157]
3.50 [.138]
14.50 [.570]
13.00 [.512]
1 - GATE
1 - GATE
2 - DRAIN
3 - SOURCE
4 - DRAIN
2 - COLLECTOR
3 - EMIT TER
4 - COLLECTOR
1.00 [.039]
0.70 [.028]
4X
1.30 [.051]
0.90 [.036]
3X
1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994.
2. CONT ROL L ING DI ME NS I ON: MI L L I ME T E R.
3.00 [.118]
2.50 [.099]
2.55 [.100]
2X
0.25 [.010]
B
A
3. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES].
4. OUT L INE CONF ORMS T O JE DE C OUT L INE T O-273AA.
01-3073 02
Case outline Super SMD220
IRGB-012-012
5
6/22/2001
10
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