IR3521 [INFINEON]
XPHASE3TM AMD SVID CONTROL IC; XPHASE3TM AMD SVID控制IC
| 型号： | IR3521 |
| 厂家： | 
Infineon |
| 描述： | XPHASE3TM AMD SVID CONTROL IC |
| 文件： | 总45页 (文件大小：470K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IR3521
DATA SHEET
XPHASE3TM AMD SVID CONTROL IC
DESCRIPTION
The IR3521 Control IC combined with an xPHASE3TM Phase IC provides a full featured and flexible way to
implement a complete AMD SVID power solution. It provides outputs for both the VDD core and VDDNB
auxiliary planes required by the CPU. The IR3521 provides overall system control and interfaces with any
number of Phase ICs each driving and monitoring a single phase. The xPHASE3TM architecture results in a
power supply that is smaller, less expensive, and easier to design while providing higher efficiency than
conventional approaches.
FEATURES
2 converter outputs for the AMD processor VDD core and VDDNB auxiliary planes
Supports High Speed (HS) I2C Serial communications
PSI_L serial commands are communicated to a programmable number of phase ICs
0.5% overall system set point accuracy
High speed error amplifiers with wide bandwidth of 20MHz and fast slew rate of 10V/us
Remote sense amplifiers provide differential sensing and require less than 50uA bias current
Programmable Dynamic VID Slew Rates
Programmable VID Offset (VDD output only)
Programmable output impedance (VDD output only)
Programmable Dynamic OC for IDD_Spike
Programmable per phase switching frequency of 250kHz to 1.5MHz
Hiccup over current protection with delay during normal operation
Central over voltage detection and communication to phase ICs through IIN (ISHARE) pin
OVP disabled during dynamic VID down to prevent false triggering
Over voltage signal to system with over voltage detection during powerup and normal operation
Detection and protection of open remote sense lines
Gate Drive and IC bias linear regulator control with programmable output voltage and UVLO
Small thermally enhanced 32L MLPQ (5mm x 5mm) package
ORDERING INFORMATION
Device
Package
Order Quantity
3000 per reel
IR3521MTRPBF
32 Lead MLPQ (5 x 5 mm body)
32 Lead MLPQ (5 x 5 mm body)
IR3521MPBF (Samples Only)
100 piece strips
Page 1
V3.03
IR3521
APPLICATION CIRCUIT
12V
To Converters
12V
To Phase IC
VCCL & GATE
DRIVE BIAS
Q3
VCCL
CVCCL9
RVCCLFB1 RVCCLFB2
PHSIN
Phase Clock Input to
Last Phase IC of VDD
RVCCLDRV
2 wire
Digital
Daisy Chain
Bus to VDD
& VDDNB
PHSOUT
CLKOUT
PGOOD
SVC
EPAD
Phase ICs
Power Saving
Indicator to
VDD Phase ICs
1
2
3
4
5
6
7
8
24
PSI_L
SVD
PWROK
ENABLE
SVD
PSI_L
ROSC
ROSC
23
22
21
20
19
18
17
PWROK
ENABLE
IIN2
VDRP1
IIN1
IR3521
CONTROL
IC
ISHARE1
CSS/DEL2
RVDAC2
CSS/DEL1
CVDAC1
SS/DEL2
VDAC2
OCSET2
EAOUT2
SS/DEL1
VDAC1
OCSET1
EAOUT1
CVDAC2
RVDAC1
3 Wire Analog
Control Bus
to VDD Phase
ICs
ROCSET1
ROCSET2
VDAC1
EAOUT1
CDRP1
RDRP1
Load Line NTC
Thermistor;
Locate close to
VDD Power Stage
RCP2 CCP21
RFB22 CFB2
RFB21
CFB1
RFB12
CCP11
RCP1
RTHERMISTOR1
CCP22
RFB11
CCP12
To VDD
VDD SENSE +
RFB13
Remote
VDD SENSE -
Sense
EAOUT2
3 Wire Analog
Control Bus to
VDDNB Phase
ICs
VDAC2
ISHARE2
VDDNB SENSE -
VDDNB SENSE +
To VDDNB
Remote
Sense
Figure 1 – IR3521 Application Circuit
Page 2
V3.03
IR3521
PIN DESCRIPTION
PIN# PIN SYMBOL
PIN DESCRIPTION
1
2
3
SVD
SVD (Serial VID Data) is a bidirectional signal that is an input and open drain output
for both master (AMD processor) and slave (IR3521), requires an external bias
voltage and should not be floated
System wide Power Good signal and input to the IR3521. When asserted, the
IR3521 output voltage is programmed through the SVID interface protocol.
Connecting this pin to VCCL enables VFIX mode.
Enable input. A logic low applied to this pin puts the IC into fault mode. A logic high
on the pin enables the converter and causes the SVC and SVD input states to be
decoded and stored, determining the 2-bit Boot VID. Do not float this pin as the logic
state will be undefined.
PWROK
ENABLE
4
5
6
IIN2
Output 2 average current input from the output 2 phase IC(s). This pin is also used
to communicate over voltage condition to the output 2 phase ICs.
Programs output 2 startup and over current protection delay timing. Connect an
external capacitor to LGND to program.
Output 2 reference voltage programmed by the SVID inputs and error amplifier non-
inverting input. Connect an external RC network to LGND to program dynamic VID
slew rate and provide compensation for the internal buffer amplifier.
Programs the output 2 constant converter output current limit and hiccup over-
current threshold through an external resistor tied to VDAC2 and an internal current
source from this pin. Over-current protection can be disabled by connecting a
resistor from this pin to VDAC2 to program the threshold higher than the possible
signal into the IIN2 pin from the phase ICs but no greater than 5V (do not float this
pin as improper operation will occur).
SS/DEL2
VDAC2
7
OCSET2
8
9
EAOUT2
FB2
Output of the output 2 error amplifier.
Inverting input to the Output 2 error amplifier.
10
11
12
13
14
15
16
VOUT2
VOSEN2+
VOSEN2-
VOSEN1-
VOSEN1+
VOUT1
FB1
Output 2 remote sense amplifier output.
Output 2 remote sense amplifier input. Connect to output at the load.
Output 2 remote sense amplifier input. Connect to ground at the load.
Output 1 remote sense amplifier input. Connect to ground at the load.
Output 1 remote sense amplifier input. Connect to output at the load.
Output 1 remote sense amplifier output.
Inverting input to the output 1 error amplifier. Converter output voltage can be
increased from the VDAC1 voltage with an external resistor connected between
VOUT1 and this pin (there is an internal current sink at this pin).
Output of the output 1 error amplifier.
Programs the output 1 constant converter output current limit and hiccup over-
current threshold through an external resistor tied to VDAC1 and an internal current
source from this pin. Over-current protection can be disabled by connecting a
resistor from this pin to VDAC1 to program the threshold higher than the possible
signal into the IIN1 pin from the phase ICs but no greater than 5V (do not float this
pin as improper operation will occur).
17
18
EAOUT1
OCSET1
19
VDAC1
Output 1 reference voltage programmed by the SVID inputs and error amplifier non-
inverting input. Connect an external RC network to LGND to program dynamic VID
slew rate and provide compensation for the internal buffer amplifier.
Page 3
V3.03
IR3521
PIN#
20
PIN
SYMBOL
PIN DESCRIPTION
SS/DEL1
Programs output 1 startup and over current protection delay timing. Connect an
external capacitor to LGND to program.
21
IIN1
Output 1 average current input from the output 1 phase IC(s). This pin is also used
to communicate over voltage condition to phase ICs.
22
VDRP1
Output 1 Buffered IIN1 signal. Connect an external RC network to FB1 to program
converter output impedance.
23
ROSC/OVP Connect a resistor to LGND to program oscillator frequency and OCSET1, OCSET2,
FB1, FB2, VDAC1, and VDAC2 bias currents. Oscillator frequency equals switching
frequency per phase. The pin voltage is 0.6V during normal operation and higher
than 1.6V if over-voltage condition is detected.
24
25
PSI_L
CLKOUT
Digital output to communicate the systems power state to phase ICs PSI_L pin.
Clock output at switching frequency multiplied by phase number. Connect to CLKIN
pins of phase ICs.
26
PHSOUT
Phase clock output at switching frequency per phase. Connect to PHSIN pin of the
first phase IC.
27
28
PHSIN
VCCL
Feedback input of phase clock. Connect to PHSOUT pin of the last phase IC.
Output of the voltage regulator, and power input for clock oscillator circuitry. Connect
a decoupling capacitor to LGND. No external power rail connection is allowed.
Non-inverting input of the voltage regulator error amplifier. Output voltage of the
regulator is programmed by the resistor divider connected to VCCL.
Output of the VCCL regulator error amplifier to control external transistor. The pin
senses 12V power supply through a resistor.
Open collector output that drives low during startup and under any external fault
condition. And it monitors output voltages, if any of the voltage planes fall out of
spec, it will drive low. Connect external pull-up. ( Output voltage out of spec is
defined as 350mV to 240mV below VDAC voltage )
29
30
31
VCCLFB
VCCLDRV
PGOOD
32
SVC
SVC (Serial VID Clock) is an open drain output of the processor and input to
IR3521, requires an external bias voltage and should not be floated
Local ground for internal circuitry and IC substrate connection.
EPAD
LGND
Page 4
V3.03
IR3521
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed below may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications are not implied. All voltages are absolute voltages referenced to the
LGND pin.
Operating Junction Temperature……………..0 to 150oC
Storage Temperature Range………………….-65oC to 150oC
ESD Rating………………………………………HBM Class 1C JEDEC Standard
MSL Rating………………………………………2
Reflow Temperature…………………………….260oC
PIN #
1
2
3
4
5
6
7
8
PIN NAME
SVD
PWROK
ENABLE
IIN2
SS/DEL2
VDAC2
OCSET2
EAOUT2
FB2
VOUT2
VOSEN2+
VOSEN2-
VOSEN1-
VOSEN1+
VOUT1
FB1
EAOUT1
OCSET1
VDAC1
SS/DEL1
IIN1
VDRP1
ROSC/OVP
PSI_L
VMAX
8V
8V
3.5V
8V
8V
3.5V
8V
8V
8V
8V
VMIN
ISOURCE
1mA
1mA
1mA
5mA
1mA
1mA
1mA
25mA
1mA
5mA
5mA
5mA
5mA
5mA
5mA
1mA
25mA
1mA
1mA
1mA
5mA
35mA
1mA
1mA
100mA
10mA
1mA
1mA
1mA
1mA
1mA
1mA
20mA
ISINK
10mA
1mA
1mA
1mA
1mA
1mA
1mA
10mA
1mA
25mA
1mA
1mA
1mA
1mA
25mA
1mA
10mA
1mA
1mA
1mA
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.5V
-0.5V
-0.5V
-0.5V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
n/a
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
EPAD
8V
1.0V
1.0V
8V
8V
8V
8V
8V
3.5V
8V
8V
1mA
1mA
1mA
8V
8V
VCCL+ 0.3V
8V
20mA
100mA
10mA
1mA
20mA
1mA
50mA
20mA
1mA
CLKOUT
PHSOUT
PHSIN
8V
8V
8V
VCCL
VCCLFB
VCCLDRV
PGOOD
SVC
3.5V
10V
VCCL + 0.3V
8V
LGND
n/a
1mA
Page 5
V3.03
IR3521
RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN
4.75V ≤ VCCL ≤ 7.5V, -0.3V ≤ VOSEN-x ≤ 0.3V, 0 oC ≤ TJ ≤ 100 oC, 7.75 kΩ ≤ ROSC ≤ 50 kΩ, CSS/DELx = 0.1uF
ELECTRICAL CHARACTERISTICS
The electrical characteristics table shows the spread of values guaranteed within the recommended operating conditions (unless
otherwise specified). Typical values (TYP) represent the median values, which are related to 25°C.
PARAMETER
SVID Interface
TEST CONDITION
MIN
TYP
MAX
UNIT
SVC & SVD Input Thresholds
Threshold Increasing
0.8025
570
150
-5
0.90
650
250
0
0.9975
750
400
5
V
Threshold Decreasing
Threshold Hysteresis
0V ≤ V(x) ≤ 3.5V, SVD not asserted
I(SVD)= 3mA
mV
mV
uA
mV
ns
Bias Current
SVD Low Voltage
20
300
160
SVD Fall Time, CSVD=400 pF
70-30% VDDIO, 1.425V ≤ VDDIO ≤ 1.9V,
1.7MHz operation, Note 1
3.4MHz operation
20
10
40
SVD Fall Time, CSVD=100 pF
Pulse width input filter
20
80
ns
ns
Note 1
20
20
<100
PSI_L OUTPUT
Output Voltage
I(PSI_L) = 3mA
150
10
300
20
mV
Pull-up Resistance (to VCCL)
6
kΩ
Oscillator
PHSOUT Frequency
-10%
See
Figure 2
0.600
+10%
kHz
ROSC Voltage
0.57
0.630
1
V
V
CLKOUT High Voltage
I(CLKOUT)= -10 mA, measure V(VCCL) –
V(CLKOUT).
CLKOUT Low Voltage
PHSOUT High Voltage
I(CLKOUT)= 10 mA
1
1
V
V
I(PHSOUT)= -1 mA, measure V(VCCL) –
V(PHSOUT)
PHSOUT Low Voltage
I(PHSOUT)= 1 mA
1
V
PHSIN Threshold Voltage
Compare to V(VCCL)
30
50
70
%
VDRP1 Buffer Amplifier
Input Offset Voltage
Source Current
V(VDRP1) – V(IIN1), 0.5V ≤ V(IIN) ≤ 3.3V
-8
2
0
8
mV
mA
0.5V ≤ V(IIN1) ≤ 3.3V
0.5V ≤ V(IIN1) ≤ 3.3V
Note 1
30
0.6
Sink Current
0.2
0.4
8
mA
Unity Gain Bandwidth
Slew Rate
MHz
V/s
A
Note 1
4.7
-0.2
IIN Bias Current
-2
1
Remote Sense Differential Amplifiers
Unity Gain Bandwidth
Note 1
3.0
-3
6.4
0
9.0
3
MHz
mV
Input Offset Voltage
0.5V≤ V(VOSENx+) - V(VOSENx-) ≤ 1.6V,
Note 2
Source Current
0.5V≤ V(VOSENx+) - V(VOSENx-) ≤ 1.6V
0.5
2
1
1.7
18
8
mA
mA
V/us
uA
uA
V
Sink Current
0.5V≤ V(VOSENx+) - V(VOSENx-) ≤ 1.6V
0.5V≤ V(VOSENx+) - V(VOSENx-) ≤ 1.6V
TBS V < V(VOSENx+) < 1.6V
-0.3V ≤ VOSENx- ≤ 0.3V, All VID Codes
V(VCCL)=7V
12
4
Slew Rate
2
VOSEN+ Bias Current
VOSEN- Bias Current
VOSEN+ Input Voltage Range
Low Voltage
30
30
50
50
5.5
250
1
V(VCCL) =7V
mV
V
High Voltage
V(VCCL) – V(VOUTx)
0.5
Page 6
V3.03
IR3521
PARAMETER
Soft Start and Delay
Start Delay
TEST CONDITION
MIN
TYP
MAX UNIT
Measure Enable to EAOUTx activation
Measure Enable activation to PGOOD
V(IINx) – V(OCSETx) = 500 mV
1
3
2.9
8
3.5
13
ms
ms
us
V
Start-up Time
OC Delay Time
85
0.7
170
1.4
325
1.9
SS/DELx to FBx Input Offset
Voltage
With FBx = 0V, adjust V(SS/DELx) until
EAOUTx drives high
Charge Current
-30
-50
47
-70
A
A
OC Delay/VID Off Discharge
Currents
Note 1
Fault Discharge Current
2.5
7
4.5
10
6.5
12
A
uA/uA
V
Hiccup Duty Cycle
I(Fault) / I(Charge)
Charge Voltage
3.5
3.9
80
4.2
Delay Comparator Threshold
Relative to Charge Voltage, SS/DELx
rising Note 1
mV
Delay Comparator Threshold
Relative to Charge Voltage, SS/DELx
falling Note 1
120
mV
Delay Comparator Hysteresis
Discharge Comp. Threshold
Note 1
40
mV
mV
150
200
300
Over-Current Comparators
Input Offset Voltage
OCSET Bias Current
1V ≤ V(OCSETx) ≤ 3.3V
-35
-5%
0
35
+5%
mV
A
Vrosc(V)*100
0/Rosc(KΩ)
2048-4096 Count Threshold
1024-2048 Count Threshold
Adjust ROSC value to find threshold
Adjust ROSC value to find threshold
16
20
kΩ
kΩ
Error Amplifiers
System Set-Point Accuracy
(Deviation from Table 1, 2, and
3 per test circuit in Figures 2A
& 2B)
VID ≥ 1V
-0.5
-5
0.5
+5
+8
%
0.8V ≤ VID < 1V
0.5V ≤ VID < 0.8V
mV
mV
-8
Input Offset Voltage
Measure V(FBx) – V(VDACx)). Note 2
-1
0
1
mV
Vrosc(V)*1000
/Rosc(KΩ)
FB1 Bias Current
-5%
+5%
A
FB2 Bias Current
DC Gain
-1
100
20
0
1
A
dB
Note 1
Note 1
Note 1
110
30
135
40
Bandwidth
MHz
V/s
mA
mA
mV
mV
mV
Slew Rate
5.5
0.4
5.0
500
12
20
Sink Current
Source Current
Maximum Voltage
Minimum Voltage
0.85
8.5
780
120
300
1
12.0
950
250
600
Measure V(VCCL) – V(EAOUTx)
Open Voltage Loop Detection
Threshold
Open Voltage Loop Detection
Delay
Measure V(VCCL) - V(EAOUT), Relative
to Error Amplifier maximum voltage.
Measure PHSOUT pulse numbers from
V(EAOUTx) = V(VCCL) to PGOOD = low.
125
8
Pulses
Enable Input
Blanking Time
Noise Pulse < 100ns will not register an
ENABLE state change. Note 1
75
250
400
ns
VDAC References
3050*Vrosc(V)
/ ROSC(kΩ)
2650*Vrosc(V)
/ ROSC(kΩ)
Source Currents
Includes I(OCSETx)
Includes I(OCSETx)
-8%
-8%
+8%
+8%
A
A
Sink Currents
PGOOD Output
Under Voltage Threshold -
Voutx Decreasing
Reference to VDACx
-365
-315
-265
mV
Page 7
V3.03
IR3521
PARAMETER
TEST CONDITION
MIN
TYP
MAX UNIT
Under Voltage Threshold - Voutx
Increasing
Reference to VDACx
-325
-275
-225
mV
Under Voltage Threshold Hysteresis
5
53
150
0
110
300
10
mV
mV
Output Voltage
I(PGOOD) = 4mA
V(PGOOD) = 5.5V
Leakage Current
A
VCCL Activation Threshold
I(PGOOD) = 4mA, V(PGOOD) =
300mV
1.73
3.5
V
Over Voltage Protection (OVP) Comparators
Threshold at Power-up
1.60
220
-20
1.73
1.83
V
Voutx Threshold Voltage
Compare to V(VDACx)
Compare to V(VDACx)
260
285
mV
mV
OVP Release Voltage during Normal
Operation
3
25
Threshold during Dynamic VID down
1.8
25
1.85
50
1.9
75
V
Dynamic VID Detect Comparator Threshold Note 1
mV
ns
Propagation Delay to IIN
Measure time from V(Voutx) >
90
180
V(VDACx) (250mV overdrive) to
V(IINx) transition to > 0.9 *
V(VCCL).
OVP High Voltage
Measure V(VCCL)-V(ROSC/OVP)
0
0
1.2
0.2
V
V
OVP Power-up High Voltage
V(VCCLDRV)=1.8V. Measure
V(VCCL)-V(ROSC/OVP)
Propagation Delay to OVP
Measure time from V(Voutx) >
V(VDACx) (250mV overdrive) to
V(ROSC/OVP) transition to >1V.
150
5
300
nS
IIN Pull-up Resistance
15
Ω
Open Sense Line Detection
Sense Line Detection Active Comparator
Threshold Voltage
Sense Line Detection Active Comparator
Offset Voltage
VOSEN+ Open Sense Line Comparator
Threshold
VOSEN- Open Sense Line Comparator
Threshold
150
29
200
62.5
89.0
0.40
500
250
90
mV
mV
%
V(Voutx) < [V(VOSENx+) –
V(LGND)] / 2
Compare to V(VCCL)
86.5
0.36
200
91.5
0.44
700
V
Sense Line Detection Source Currents
V(Voutx) = 100mV
uA
VCCL Regulator Amplifier
Reference Feedback Voltage
VCCLFB Bias Current
VCCLDRV Sink Current
UVLO Start Threshold
UVLO Stop Threshold
Hysteresis
1.15
-1
1.2
0
1.25
1
V
uA
mA
%
10
40
Compare to V(VCCL)
Compare to V(VCCL)
Compare to V(VCCL)
89.0
81.0
7.0
93.5
85.0
8.25
97.0
89.0
9.5
%
%
ENABLE, PWROK Inputs
Threshold Increasing
Threshold Decreasing
Threshold Hysteresis
Bias Current
1.3
0.8
470
-5
1.65
0.99
620
0
1.9
1.2
770
5
V
V
mV
uA
V
0V ≤ V(x) ≤ 3.5V, SVC not asserted
PWROK VFIX Mode Threshold
3.3
V
(VCCL
+3.3)(V) / 2
VC
CL
General
VCCL Supply Current
3.5
10
15
mA
Note 1: Guaranteed by design, but not tested in production Note 2: VDACx Outputs are trimmed to compensate for Error & Amp
Remote Sense Amp input offset.
Page 8
V3.03
IR3521
PHSOUT FREQUENCY VS RROSC CHART
PHSOUT FREQUENCY vs. RROSC
1600
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
5
10
15
20
25
30
35
40
45
50
55
RROSC (KOhm)
Figure 2 - Phout Frequency vs. RROSC chart
System Fault Table
Response Open Open
Open
UVLO
Over
Disable
VID_OFF
SVID
SS Latch
SS discharge below 0.2V
Single Single
OC
Before
OC
After
UVLO
(Vout)
No
No
Single
Daisy Sense Voltage (VCCL)
Voltage
EN Fault Latch
Recycle Enable
Latch
Reset
UV & EN Latch
Recycle VCCL then Enable
Outputs
Affected
Both
Single
Both
Both
Both
Disables
EA
SS/DELx
Discharge
Yes
No
No
Yes
Yes
Flags
PGood
Delays
32
Clock
Pulses
No
8
No
No
250ns
Blanking
Time
No
PHSOUT
Pulses*
SS/DELx
Discharge
Threshold
No
PHSOUT
Pulses
No
Additional
Flagged
Response
Yes,
No
IINx and
Rosc pins
pulled-up to
VCCL
* Pulse number range depends on Rosc value selected (See Specifications Table)
Page 9
V3.03
IR3521
SYSTEM SET POINT TEST
The converter output voltage is determined by the system set point voltage which is the voltage that appears at
the FBx pins when the converter is in regulation. The set point voltage includes error terms for the VDAC digital-
to-analog converters, Error Amp input offsets, and Remote Sense input offsets. The voltage appearing at the
VDACx pins is not the system set point voltage. System set point voltage test circuits for Outputs 1 and 2 are
shown in Figures 3A and 3B.
ERROR
IR3521
AMPLIFIER
VDAC1
BUFFER
AMPLIFIER
EAOUT1
FB1
+
-
+
-
ISOURCE
ISINK
"FAST"
VDAC
VDAC1
OCSET1
ROCSET1
IFB1
IOCSET1
IROSC
IROSC
RVDAC1
CVDAC1
ROSC BUFFER
AMPLIFIER
CURRENT
SOURCE
GENERATOR
IROSC
1.2V
LGND
+
-
RROSC
ROSC
VOUT1
EAOUT
SYSTEM
REMOTE SENSE
AMPLIFIER
SET POINT
VOSNS-
VOLTAGE
VOSEN1+
VOSEN1-
+
-
Figure 3A - Output 1 System Set Point Test Circuit
ERROR
IR3521
AMPLIFIER
VDAC2
BUFFER
AMPLIFIER
EAOUT2
+
-
FB2
+
-
ISOURCE
"FAST"
VDAC
VDAC2
OCSET2
ISINK
ROCSET2
IOCSET2
IROSC
RVDAC2
CVDAC2
ROSC BUFFER
AMPLIFIER
CURRENT
SOURCE
GENERATOR
IROSC
1.2V
LGND
+
-
RROSC
ROSC
VOUT2
EAOUT
SYSTEM
REMOTE SENSE
AMPLIFIER
SET POINT
VOSNS-
VOLTAGE
VOSEN2+
VOSEN2-
+
-
Figure 3B - Output 2 System Set Point Test Circuit
Page 10
V3.03
IR3521
SYSTEM THEORY OF OPERATION
PWM Control Method
The PWM block diagram of the xPHASE3TM architecture is shown in Figure 4. Feed-forward voltage mode control
with trailing edge modulation is used to provide system control. A voltage type error amplifier with high-gain and
wide-bandwidth, located in the Control IC, is used for the voltage control loop. The feed-forward control is
performed by the phase ICs as a result of sensing the input voltage (FET’s drain voltage). The PWM ramp slope
will change with the input voltage and automatically compensate for changes in the input voltage. The input voltage
can change due to variations in the silver box output voltage or due to the wire and PCB-trace voltage drop related
to changes in load current.
GATE DRIVE
VOLTAGE
VIN
IR35121CONTROL IC
PHSOUT
IR3505 PHASE IC
VCC
CLOCK GENERATOR
CLKOUT
CLKIN
PHSIN
CLK
D
Q
VCCH
PWM
LATCH
GATEH
CBST
PHSOUT
PHSIN
VOSNS1+
VOUT1
S
PWM
COMPARATOR
SW
RESET
DOMINANT
COUT
-
R
VCCL
EAIN
+
GND
ENABLE
GATEL
PGND
REMOTE SENSE
AMPLIFIER
+
-
+
BODY
BRAKING
COMPARATOR
VID6-
VOSNS1-
RAMP
DISCHARGE
CLAMP
VOUT1
VDAC1
LGND
SHARE ADJUST
ERROR AMPLIFIER
ERROR
AMPLIFIER
+
VDAC
CURRENT
SENSE
AMPLIFIER
+
+
-
EAOUT1
VID6
VID6
+
ISHARE
DACIN
-
CSIN+
CSIN-
-
3K
RCP1
CCS RCS
VID6
VID6+
+
-
CCP14
RFB12
CFB2
RFB11
CCP13
FB1
IFB1
IROSC
RDRP1
CDRP2
VDRP1 AMP
+
PHSOUT
CLKIN
IR3505 PHASE IC
VDRP1
IIN1
VCC
-
CLK
D
Q
VCCH
Output
1
Only
PWM
LATCH
GATEH
CBST
PHSIN
EAIN
S
PWM
SW
RESET
COMPARATOR
DOMINANT
-
R
VCCL
+
ENABLE
GATEL
PGND
+
BODY
BRAKING
COMPARATOR
VID6-
RAMP
DISCHARGE
CLAMP
SHARE ADJUST
ERROR AMPLIFIER
+
CURRENT
SENSE
AMPLIFIER
+
VID6
VID6
+
ISHARE
DACIN
-
CSIN+
CSIN-
-
3K
CCS RCS
VID6
VID6+
+
-
Figure 4 - PWM Block Diagram
Frequency and Phase Timing Control
The oscillator (system clock) is located in the Control IC and is programmable from 250 kHz to 9 MHZ by an
external resistor. The control IC clock signal (CLKOUT) is connected to CLKIN of all the phase ICs. The phase
timing of the phase ICs is controlled by the daisy chain loop. The control IC phase clock output (PHSOUT) is
connected to the phase clock input (PHSIN) of the first phase IC, and PHSOUT of the first phase IC is connected to
PHSIN of the second phase IC, etc. The last phase IC (PHSOUT) is connected back to PHSIN of the control IC to
complete the loop. During power up, the control IC sends out clock signals from both CLKOUT and PHSOUT pins
and detects the feedback at PHSIN pin to determine the phase number and monitor any fault in the daisy chain
loop. Figure 5 shows the phase timing for a four phase converter.
Page 11
V3.03
IR3521
Control IC CLKOUT
(Phase IC CLKIN)
Control IC PHSOUT
(Phase IC1 PHSIN)
Phase IC1
PWM Latch SET
Phase IC 1 PHSOUT
(Phase IC2 PHSIN)
Phase IC 2 PHSOUT
(Phase IC3 PHSIN)
Phase IC 3 PHSOUT
(Phase IC4 PHSIN)
Phase IC4 PHSOUT
(Control IC PHSIN)
Figure 5 Four Phase Oscillator Waveforms
PWM Operation
The PWM comparator is located in the phase IC. Upon receiving the falling edge of a clock, the PWM latch is set
and the PWM ramp amplitude begins to increase prompting the low side driver is turned off. After the non-overlap
time (GATEL < 1.0V), the high side driver is turned on. When the PWM ramp voltage exceeds the error amplifier’s
output voltage, the PWM latch is reset. This also turns off the high side driver, turns on the low side driver after the
non-overlap time and the PWM ramp discharged current is clamped which quickly discharges the internal capacitor
to the output voltage of share adjust amplifier, in phase IC, until the next clock pulse.
The PWM latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in
response to a load step decrease. Phases can overlap and go up to 100% duty cycle in response to a load step
increase with turn-on gated by the clock pulses. An error amplifier output voltage greater than the common mode
input range of the PWM comparator results in 100% duty cycle regardless of the voltage of the PWM ramp. This
arrangement guarantees the error amplifier is always in control and can demand 0 to 100% duty cycle as required.
It also favors response to a load step decrease which is appropriate given the low output to input voltage ratio of
most systems. The inductor current will increase much more rapidly than decrease in response to load transients.
This control method is designed to provide “single cycle transient response” where the inductor current changes in
response to load transients within a single switching cycle maximizing the effectiveness of the power train and
minimizing the output capacitor requirements. An additional advantage of the architecture is that differences in
ground or input voltage at the phases have no effect on operation since the PWM ramps are referenced to VDAC.
Figure 6 depicts PWM operating waveforms under various conditions.
Page 12
V3.03
IR3521
PHASE IC
CLOCK
PULSE
EAIN
PWMRMP
GATEH
GATEL
VDAC
STEADY-STATE
OPERATION
DUTY CYCLE INCREASE
DUE TO LOAD
INCREASE
DUTY CYCLE DECREASE
DUE TO VIN INCREASE
(FEED-FORWARD)
DUTY CYCLE DECREASE DUE TO LOAD
DECREASE (BODY BRAKING) OR FAULT
(VCC UV, OCP, VID FAULT)
STEADY-STATE
OPERATION
Figure 6 PWM Operating Waveforms
Body BrakingTM
In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in
response to a load step decrease is;
L*(IMAX IMIN
)
TSLEW
VO
The slew rate of the inductor current can be significantly increased by turning off the synchronous rectifier in
response to a load step decrease. The switch node voltage is then forced to decrease until conduction of the
synchronous rectifier’s body diode occurs. This increases the voltage across the inductor from Vout to Vout +
VBODYDIODE
.
The minimum time required to reduce the current in the inductor in response to a load transient
decrease is now;
L*(IMAX IMIN
VO VBODYDIODE
)
TSLEW
Since the voltage drop in the body diode is often higher than output voltage, the inductor current slew rate can be
increased by 2X or more. This patent pending technique is referred to as “body braking” and is accomplished
through the “body braking comparator” located in the phase IC. If the error amplifier’s output voltage drops below
the VDAC voltage or a programmable voltage, this comparator turns off the low side gate driver.
Lossless Average Inductor Current Sensing
Inductor current can be sensed by connecting a series resistor and a capacitor network in parallel with the inductor
and measuring the voltage across the capacitor, as shown in Figure 7. The equation of the sensing network is,
1
RL sL
1 sRCSCCS
vC (s) vL (s)
iL (s)
1 sRCSCCS
Usually the resistor Rcs and capacitor Ccs are chosen so that the time constant of Rcs and Ccs equals the time
constant of the inductor which is the inductance L over the inductor DCR (RL). If the two time constants match, the
voltage across Ccs is proportional to the current through L, and the sense circuit can be treated as if only a sense
resistor with the value of RL was used. The mismatch of the time constants does not affect the measurement of
inductor DC current, but affects the AC component of the inductor current.
Page 13
V3.03
IR3521
L
v
L
L
R
R
L
i
O
V
CS
CS
C
O
C
Current
Sense Amp
c
vCS
CSOUT
Figure 7 Inductor Current Sensing and Current Sense Amplifier
The advantage of sensing the inductor current versus high side or low side sensing is that actual output current
being delivered to the load is obtained rather than peak or sampled information about the switch currents. The
output voltage can be positioned to meet a load line based on real time information. Except for a sense resistor in
series with the inductor, this is the only sense method that can support a single cycle transient response. Other
methods provide no information during either load increase (low side sensing) or load decrease (high side sensing).
An additional problem associated with peak or valley current mode control for voltage positioning is that they suffer
from peak-to-average errors. These errors will show in many ways but one example is the effect of frequency
variation. If the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and
the output impedance of the converter will drop by about 10%. Variations in inductance, current sense amplifier
bandwidth, PWM prop delay, any added slope compensation, input voltage, and output voltage are all additional
sources of peak-to-average errors.
Current Sense Amplifier
A high speed differential current sense amplifier is located in the phase IC, as shown in Figure 7. Its gain is
nominally 34 at 25ºC, and the 3850 ppm/ºC increase in inductor DCR should be compensated in the voltage loop
feedback path.
The current sense amplifier can accept positive differential input up to 50mV and negative up to -10mV before
clipping. The output of the current sense amplifier is summed with the DAC voltage and sent to the control IC and
other phases through an on-chip 3Kꢀ resistor connected to the ISHARE pin. The ISHARE pins of all the phases are
tied together and the voltage on the share bus represents the average current through all the inductors and is used
by the control IC for voltage positioning and current limit protection.
Average Current Share Loop
Current sharing between phases of the converter is achieved by the average current share loop in each phase IC.
The output of the current sense amplifier is compared with average current at the share bus. If current in a phase is
smaller than the average current, the share adjust amplifier of the phase will pull down the starting point of the PWM
ramp thereby increasing its duty cycle and output current; if current in a phase is larger than the average current,
the share adjust amplifier of the phase will pull up the starting point of the PWM ramp thereby decreasing its duty
cycle and output current. The current share amplifier is internally compensated so that the crossover frequency of
the current share loop is much slower than that of the voltage loop and the two loops do not interact.
Page 14
V3.03
IR3521
IR3521 THEORY OF OPERATION
Block Diagram
The Block diagram of the IR3521 is shown in Figure 8. The following discussions are applicable to either output
plane unless otherwise specified.
Serial VID Control
The two Serial VID Interface (SVID) pins SVC and SVD are used to program the Boot VID voltage upon assertion of
ENABLE while PWROK is de-asserted. See Table 1 for the 2-bit Boot VID codes. Both VDAC1 and VDAC2
voltages will be programmed to the Boot VID code until PWROK is asserted. The Boot VID code is stored by the
IR3521 to be utilized again if PWROK is de-asserted.
Serial VID communication from the processor is enabled after the PWROK is asserted. Addresses and data are
serially transmitted in 8-bit words. The IR3521 has three fixed addresses to control VDAC1, VDAC2, or both
VDAC1 and VDAC2 (See Table 6 for addresses). The first data bit of the SVID data word represents the PSI_L bit
and if pulled low will force all phase ICs, connected to the PSI_L pin, in to a power-saving mode. The remaining
data bits SVID[6:0] select the desired VDACx regulation voltage as defined in Table 3. SVID[6:0] are the inputs to
the Digital-to-Analog Converter (DAC) which then provides an analog reference voltage to the transconductance
type buffer amplifier. This VDACx buffer provides a system reference on the VDACx pin. The VDACx voltage along
with error amplifier and remote sense differential amplifier input offsets are post-package trimmed to provide a
0.5% system set-point accuracy, as measured in Figures 3A and 3B. VDACx slew rates are programmable by
properly selecting external series RC compensation networks located between the VDACx and the LGND pins. The
VDACx source and sink currents are derived off the external oscillator frequency setting resistor, RROSC. The
programmable slew rate enables the IR3521 to smoothly transition the regulated output voltage throughout VID
transitions. This results in power supply input and output capacitor inrush currents along with output voltage
overshoot to be well controlled.
The two Serial VID Interface (SVID) pins SVC and SVD can also program the VFIX VID voltage upon assertion of
ENABLE while PWROK is equal to VCCL. See Table 2 for the 2-bit VFIX VID codes. Both VDAC1 and VDAC2
voltages will be programmed to the VFIX code.
The SVC and SVD pins require external pull-up biasing and should not be floated.
Output 1 (VDD) Adaptive Voltage Positioning
The IR3521 provides Adaptive Voltage Positioning (AVP) on the output1 plane only. AVP helps reduces the peak
to peak output voltage excursions during load transients and reduces load power dissipation at heavy load. The
circuitry related to the voltage positioning is shown in Figure 9. Resistor RFB1 is connected between the error
amplifiers inverting input pin FB1 and the remote sense differential amplifier output, VOUT1. An internal current sink
on the FB1 pin along with RFB1 provides programmability of a fixed offset voltage above the VDAC1 voltage. The
offset voltage generated across RFB1 forces the converter’s output voltage higher to maintain a balance at the error
amplifiers inputs. The FB1 sink current is derived by the external resistor RROSC that programs the oscillator
frequency.
The VDRP1 pin voltage is a buffered reproduction of the IIN1 pin which is connected to the current share bus
ISHARE. The voltage on ISHARE represents the system average inductor current information. At each phase IC,
an RC network across the inductor provides current information which is gained up 32.5X and then added to the
VDACX voltage. This phase current information is provided on the ISHARE bus via a 3K resistor in the phase ICs.
Page 15
V3.03
IR3521
POR
VDD
SELECT MODE
DISABLE
D
.
Q
250nS
BLANKING
ENABLE
-
+
VCCLDRV
VCCLFB
VCCL-UVLO
OVLATCH
VCCL REGULATOR
AMPLIFIER
Q
ENABLE
FLT2
OV FAULT LATCH
1.65V
1V
COMPARATOR
SSCL FS2
+
DLY OUT2
OV1-2
S
SET
Q
VOUT2 VID OFF
-
DISABLE
UV2
DOMINANT
SSCL FS1
R
1.2V
0.94
0.86
UV1
VOUT1 VID OFF
DLY OUT1
VCCLDRV
+
-
PGOOD
FLT1
VCCL UVLO
400k
OV1 FAULT LATCH
VCCL UVL
COMPARATOR
SS/DEL CLEARED
FAULT LATCH2
SS/DEL CLEARED
FAULT LATCH1
SELECT MODE
DISABLE
VCCL UVLO
OC2 AFTER VRRDY
OC2 Bf VRRDY
SELECT MODE
DISABLE
VCCL UVLO
SSCL FS2
SSCL FS1
S
Q
Q
SET
S
SET
DOMINANT
OC1 AFTER VRRDY
OC1 Bf VRRDY
INTERNAL
DIS
CIRCUIT
BIAS
DOMINANT
VCCL
R
UV CLEARED
FAULT LATCH2
R
UV CLEARED
FAULT LATCH1
OPEN DAISY
OPEN SENSE2
OPEN CONTROL2
OPEN DAISY
OPEN SENSE1
OPEN CONTROL1
S
Q
Q
S
SET
SET
DOMINANT
DOMINANT
R
R
80mV
120mV
80mV
120mV
DELAY
COMPARATOR
POWER-UP
OK LATCH
DELAY
COMPARATOR
POWER-UP
OK LATCH
PHSOUT
IROSC
DIS
PHSOUT
IROSC
DIS
COUTER
DIS
OC DELAY
OC DELAY
+
+
COUTER
DLY OUT2
DLY OUT1
DIS
DIS
DIS
S
Q
Q
S
-
-
3.9V
3.9V
RESET
DOMINANT
RESET
DOMINANT
reset
reset
DISCHARGE
COMPARATOR
-
DISCHARGE
COMPARATOR
R
Q
Q
R
U?
FLT1
FLT2
ICHG
50uA
-
+
ICHG
50uA
DCHG1
DCHG2
+
0.2V
0.2V
DIS
AND2
SS/DEL2
SS/DEL1
VDRP1
DIS
IDCHG
4.5uA
FLT2
DCHG2
DCHG1
FLT1
IDCHG2
47uA
IDCHG1
47uA
IDCHG
4.5uA
VCCL
VCCL
OV1
PHSOUT
-
+
PHSOUT
OV2
OC LIMIT
DIS
8
Delay
DIS
DIS
Pulse
Pulse
8
OC LIMIT
DIS
Delay
VDRP
AMPLIFIER
DIS
COMPARATOR
COMPARATOR
+
+
IIN1
IIN2
-
-
OCSET1
OCSET2
OPEN CONTROL
1.08V
1.08V
OPEN CONTROL
IOCSET
IROSC
VCCL
IROSC
LOOP COMPARATOR
IOCSET
LOOP COMPARATOR
-
+
VCCL
-
+
FLT1
DISABLE2
DISABLE1
DLY OUT2
1.4V
1.4V
+
+
-
+
+
-
SOFT
START
CLAMP
SOFT
START
CLAMP
EAOUT1
FB1
EAOUT2
FB2
VDAC1
+
-
+
-
VDAC2
DLY OUT1
ERROR
AMPLIFIER
ERROR
AMPLIFIER
FLT2
IROSC
OVER VOLTAGE
COMPARATOR
275mV
IFB
260mV
260mV
VRRDY
275mV
315mV
VOUT2 UV
COMPARATOR
-
+
-
+
VRRDY
VOUT1 UV
+
315mV
COMPARATOR
OVER VOLTAGE
COMPARATOR
UV2
OVLATCH
VDAC1
+
OVLATCH
-
UV1
1.6V
1.6V
-
DYNAMIC VID2 DOWN
DETECT COMPARATOR
DYNAMIC VID1 DOWN
DETECT COMPARATOR
VDAC2
U?
+
+
OV2
OV1
-
-
DETECTION PULSE2
DETECTION PULSE1
25k
50mV
50mV
AND2
VOUT2
VOUT1
25k
25k
25k
25k
+
-
+
60mV
60mV
VOSEN2+
VOSEN2-
VOSEN1+
VOSEN1-
25k
-
IVOSEN2-
IVOSEN2+ REMOTE SENSE
REMOTE SENSE
IVOSEN1-
IVOSEN-
VCCL
IVOSEN1+
+
-
+
-
AMPLIFIER
AMPLIFIER
25k
25k
IVOSEN-
VCCL
VIDSEL
VIDSEL
VCCL
DETECTION PULSE2
VCCL
200mV
-
-
DETECTION PULSE1
200mV
+
+
4
OPEN SENSE
4
OPEN SENSE
VCCL RESET
VCCL RESET
VCCL*0.9
VCCL*0.9
LINE DETECT
COMPARATORS
LINE DETECT
COMPARATORS
EN
EN
-
+
-
+
0.4V
OPEN SENSE LINE2
OPEN SENSE LINE1
0.4V
EN
EN
-
+
-
+
+
-
+
ISOURCE
ISINK
ISOURCE
ISINK
IROSC
IROSC
VDAC1
VDAC2
-
VDAC BUFFER
AMPLIFIER
VDAC BUFFER
AMPLIFIER
OPEN DAISY
FAULT
VCCL UVLO
SVID to SVID
SVID to Metal
Metal to SVID
VID3
CHAIN
Vout1 VID
On-The-Fly
High to Low
READ
&
STORE PRE-PWROK
Low to High
2
VDD
BIT VID
VID7
VID3
VID3
DVID2
CURRENT
SOURCE
GENERATOR
SVID to SVID
SVID to Metal
Metal to SVID
IROSC
Vout2 VID
On-The-Fly
High to Low
VID0
EVNAIBLDE3D
SVID
CLOCK
MEMORY
ROSC BUFFER
AMPLIFIER
Connection to VCCL
High to Low
VFIXVID3
PWROK
Mode
PHSIN
D/A
CONVERTER
Back to PRE-PWROK
VIDVID3
BIT
+
-
2
VID3
EPAD
ROSC
SVC
PHSOUT
CLKOUT
SVC
SVD
0.6V
SVI (Seriel VID Interface)
VID3
SVD
VID3
PHSIN
VID7
VID3
CLKOUT
PHSOUT
VCCL- 1.2V
VCCL
OV2
OV1
10k
OV1_2
PSI_L
Figure 8 Block Diagram
Page 16
V3.03
IR3521
Control IC
VDAC1
Phase IC
VDAC1
Current Sense
Amplifier
CSIN+
CSIN-
+
ISHARE
VDAC
Error
-
Amplifier
3k
+
EA OUT1
FB1
-
RFB1
IFB
VDRP
RDRP1
Amplifier
Phase IC
VDRP1
Current Sense
-
+
Amplifier
CSIN+
CSIN-
+
IIN1
ISHARE
VDAC
-
3k
VOUT1
Remote
Sense
Amplifier
VOSEN1+
VOSEN1-
+
-
Figure 9 Adaptive voltage positioning
Control IC
VDAC1
VDAC1
Error
Amplifier
+
EA OUT1
RFB11
-
RFB12
Rt
IFB
FB1
VDRP
RDRP1
Amplifier
VDRP1
IIN1
-
+
VOUT1
Remote
Sense
Amplifier
VOSEN1+
VOSEN1-
+
-
Figure 10 Temperature compensation of Output1 inductor DCR
Page 17
V3.03
IR3521
Output 1 (VDD) Adaptive Voltage Positioning (continued)
The voltage difference between VDRP1 and FB1 represents the gained up average current information. Placing a
resistor RDRP1 between VDRP1 and FB1 converts the gained up current information (in the form of a voltage) into a
current forced onto the FB1 pin. This current, which can be calculated using (VDRP1-VDAC1) / RDRP1, will vary the
offset voltage produced across RFB1. Since the error amplifier will force the loop to maintain FB1 to equal the
VDAC1 reference voltage, the output regulation voltage will be varied. When the load current increases, the
adaptive positioning voltage V(VDRP1) increases accordingly. (VDRP1-VDAC1) / RDRP1 increases the voltage drop
across the feedback resistor RFB1, and makes the output voltage lower proportional to the load current. The
positioning voltage can be programmed by the resistor RDRP1 so that the droop impedance produces the desired
converter output impedance. The offset and slope of the converter output impedance are referenced to VDAC1 and
are not affected by changes in the VDAC1 voltage.
Output1 Inductor DCR Temperature Compensation
A negative temperature coefficient (NTC) thermistor can be used for output1 inductor DCR temperature
compensation. The thermistor should be placed close to the output1 inductors and connected in parallel with the
feedback resistor, as shown in Figure 10. The resistor in series with the thermistor is used to reduce the nonlinearity
of the thermistor.
Remote Voltage Sensing
VOSENX+ and VOSENX- are used for remote sensing and connected directly to the load. The remote sense
differential amplifiers are high speed, have low input offset and low input bias currents to ensure accurate voltage
sensing and fast transient response.
Start-up Sequence
The IR3521 has a programmable soft-start function to limit the surge current during the converter start-up. A
capacitor connected between the SS/DELX and LGND pins controls soft start timing, over-current protection delay
and hiccup mode timing. Constant current sources and sinks control the charge and discharge rates of the
SS/DELX.
Figure 11 depicts the SVID start-up sequence. If the ENABLE input is asserted and there are no faults, the SS/DELX
pin will begin charging, the pre-PWROK 2 bit Boot VID codes are read and stored, and both VDAC pins transition to
the pre-PWROK Boot VID code. The error amplifier output EAOUTX is clamped low until SS/DELX reaches 1.4V.
The error amplifier will then regulate the converter’s output voltage to match the V(SS/DELX)-1.4V offset until the
converter output reaches the 2-bit Boot VID code. The SS/DELX voltage continues to increase until it rises above
the threshold of Delay Comparator where the PGOOD output is allowed to go high. The SVID interface is activated
upon PWROK assertion and the VDACX along with the converter output voltage will change in response to any
SVID commands.
VCCL under voltage, over current, or a low signal on the ENABLE input immediately sets the fault latch, which
causes the EAOUT pin to drive low, thereby turning off the phase IC drivers. The PGOOD pin also drives low and
SS/DELX discharges to 0.2V. If the fault has cleared, the fault latch will be reset by the SS/DELX discharge
comparator allowing another soft start charge cycle to occur.
Other fault conditions, such as output over voltage, open VOSNS sense lines, or an open phase timing daisy chain
set a different group of fault latches that can only be reset by cycling VCCL power. These faults discharge
SS/DELX, pull down EAOUTX and drive PGOOD low.
SVID OFF codes turn off the converter by discharging SS/DELX and pulling down EAOUTx but do not drive PGOOD
low. Upon receipt of a non-off SVID code the converter will re-soft start and transition to the voltage represented by
the SVID code as shown in Figure 11.
The converter can be disabled by pulling the SS/DELx pins below 0.6V.
Page 18
V3.03
IR3521
VCC
(12V)
ENABLE
2-Bit Boot VID
READ STORE
SVID
TRANSITION
2-Bit Boot
VID On-Hold
SVID OFF COMMAND
SVID OFF COMMAND
SVID ON COMMAND
SVC
SVD
&
SVID
TRANSITION
2-Bit Boot VID
READ STORE
2-Bit Boot
VID On-Hold
SVID ON COMMAND
&
SVID set voltage
2-Bit Boot
VID Voltage
SVID programmed voltage
0.8V
0.5V
VDACx
4.0V
3.92V
1.4V
1.4V
SS/DEL
EAOUT
VOUT
PGOOD
PWROK
VID ON
THE FLY
PROCESSION
START
DELAY
NORMAL
OPERATION
SVID OFF TRANSISTION
SVID ON TRANSISTION
STARTUP
TIME
Figure 11 SVID Start-up Sequence Transitions
Page 19
V3.03
IR3521
Serial VID Interface Protocol and VID-on-the-fly Transition
The IR3521 supports the AMD SVI bus protocol and the AMD Server and desktop SVI wire protocol which are
based on High-Speed I2C. SVID commands from an AMD processor are communicated through SVID bus pins
SVC and SVD. The SVC pin of the IR3521 does not have an open drain output since AMD SVID protocol does not
support slave clock stretching.
The IR3521 transitions from a 2-bit Boot VID mode to SVI mode upon assertion of PWROK. The SMBus send byte
protocol is used by the IR3521 VID-on-the-fly transactions. The IR3521 will wait until it detects a start bit which is
defined as an SVD falling edge while SVC is high. A 7bit address code plus one write bit (low) should then follow
the start bit. This address code will be compared against an internal address table and the IR3521 will reply with an
acknowledge ACK bit if the address is one of the three stored addresses otherwise the ACK bit will not be sent out.
The SVD pin is pulled low by the IR3521 to generate the ACK bit. Table 4 has the list of addresses recognized by
the IR3521.
The processor should then transmit the 8-bit data word immediately following the ACK bit. The first data bit (bit 7),
of the SVID data word, represents the Power State Indicator (PSI) bit which is passed on to the phase ICs via the
IR3521 PSI_L pin. PSI_L is pulled high by an internal 10K resistor to VCCL when data bit 7 of an SVID command
is high. A low, on this bit (bit 7), will pull the PSL_pin low and trigger all connected, predetermine, phase ICs to turn
off. If transitioning from one phase to multiple phases, the last phase IC, or returning phase IC, should be left on to
ensure the fastest possible clock frequency calibration. A shorter calibration time will help minimize droop at the
VDD output when leaving PSI_L mode. The remaining data bits SVID[6:0] select the desired VDACx regulation
voltage as defined in Table 3. The IR3521 replies again with an ACK bit once the data is received. If the received
data is not a VID-OFF command, the IR3521 immediately changes the DAC analog outputs to the new target.
VDAC1 and VDAC2 then slew to the new VID voltages. See Figure 12 for a send byte example.
Table 1 – 2-bit Boot VID codes
Table 2 – VFIX mode 2 bit VID Codes
SVC
SVD
Output Voltage(V)
SVC
SVD
Output Voltage(V)
0
0
1
1
0
1
0
1
1.4
1.2
1.0
0.8
0
0
1
1
0
1
0
1
1.1
1.0
0.9
0.8
Figure 12 Send Byte Example
Page 20
V3.03
IR3521
Table 3 - AMD 7 BIT SVID CODES
SVID [6:0] Voltage (V) SVID [6:0] Voltage (V)
SVID [6:0] Voltage (V)
SVID [6:0] Voltage (V)
000_0000
000_0001
000_0010
000_0011
000_0100
000_0101
000_0110
000_0111
000_1000
000_1001
000_1010
000_1011
000_1100
000_1101
000_1110
000_1111
001_0000
001_0001
001_0010
001_0011
001_0100
001_0101
001_0110
001_0111
001_1000
001_1001
001_1010
001_1011
001_1100
001_1101
001_1110
001_1111
1.5500
1.5375
1.5250
1.5125
1.5000
1.4875
1.4750
1.4625
1.4500
1.4375
1.4250
1.4125
1.4000
1.3875
1.3750
1.3625
1.3500
1.3375
1.3250
1.3125
1.3000
1.2875
1.2750
1.2625
1.2500
1.2375
1.2250
1.2125
1.2000
1.1875
1.1750
1.1625
010_0000
010_0001
010_0010
010_0011
010_0100
010_0101
010_0110
010_0111
010_1000
010_1001
010_1010
010_1011
010_1100
010_1101
010_1110
010_1111
011_0000
011_0001
011_0010
011_0011
011_0100
011_0101
011_0110
011_0111
011_1000
011_1001
011_1010
011_1011
011_1100
011_1101
011_1110
011_1111
1.1500
1.1375
1.1250
1.1125
1.1000
1.0875
1.0750
1.0625
1.0500
1.0375
1.0250
1.0125
1.0000
0.9875
0.9750
0.9625
0.9500
0.9375
0.9250
0.9125
0.9000
0.8875
0.8750
0.8625
0.8500
0.8375
0.8250
0.8125
0.8000
0.7875
0.7750
0.7625
100_0000
100_0001
100_0010
100_0011
100_0100
100_0101
100_0110
100_0111
100_1000
100_1001
100_1010
100_1011
100_1100
100_1101
100_1110
100_1111
101_0000
101_0001
101_0010
101_0011
101_0100
101_0101
101_0110
101_0111
101_1000
101_1001
101_1010
101_1011
101_1100
101_1101
101_1110
101_1111
0.7500
0.7375
0.7250
0.7125
0.7000
0.6875
0.6750
0.6625
0.6500
0.6375
0.6250
0.6125
0.6000
0.5875
0.5750
0.5625
0.5500
0.5375
0.5250
0.5125
0.5000
0.5000
0.5000
0.5000
0.5000
0.5000
0.5000
0.5000
0.5000
0.5000
0.5000
0.5000
110_0000
110_0001
110_0010
110_0011
110_0100
110_0101
110_0110
110_0110
110_1000
110_1001
110_1010
110_1011
110_1100
110_1101
110_1110
110_1111
111_0000
111_0001
111_0010
111_0011
111_0100
111_0101
111_0110
111_0111
111_1000
111_1001
111_1010
111_1011
111_1100
111_1101
111_1110
111_1111
0.5000
0.5000
0.5000
0.5000
0.5000
0.5000
0.5000
0.5000
0.5000
0.5000
0.5000
0.5000
0.5000
0.5000
0.5000
0.5000
0.5000
0.5000
0.5000
0.5000
0.5000
0.5000
0.5000
0.5000
0.5000
0.5000
0.5000
0.5000
OFF
OFF
OFF
OFF
Table 4 - SVI Send Byte Address Table
SVI Address [6:0] + Wr
110xx100b
Description
Set VID only on Output 1
Set VID only on Output 2
110xx010b
110xx110b
Set VID on both Output 1 and Output 2
Note: ‘x’ in the above Table 4 means the bit could be either ‘1’ or ‘0’.
Page 21
V3.03
IR3521
Over-Current Hiccup Protection after Soft Start
The over current limit threshold is set by a resistor connected between OCSETX and VDACX pins. Figure 13 shows
the hiccup over-current protection with delay after PGOOD is asserted. The delay is required since over-current
conditions can occur as part of normal operation due to load transients or VID transitions.
If the IINX pin voltage, which is proportional to the average current plus VDACX voltage, exceeds the OCSETx
voltage after PGOOD is asserted, it will initiate the discharge of the capacitor at SS/DELX through the discharge
current 47uA. If the over-current condition persists long enough for the SS/DELX capacitor to discharge below the
120mV offset of the delay comparator, the fault latch will be set which will then pull the error amplifier’s output low to
stop phase IC switching and will also de-asserting the PGOOD signal. The SS/DEL capacitor will then continue to
be discharged by a 4.5 uA current until it reaches 200 mV where the fault latch will reset to allow another soft start
cycle to occur. The output current is not controlled during the delay time. If an over-current condition is again
encountered during the soft start cycle, the over-current action will repeat and the converter will be in hiccup mode.
ENABLE
INTERNAL
OC DELAY
4.0V
3.92V
3.87V
SS/DEL
EA
1.4V
VOUT
PGOOD
OCP THRESHOLD
IOUT
HICCUP OVER-CURRENT
PROTECTION (OUTPUT
SHORTED)
OVER-CURRENT
PROTECTION
(OUTPUT SHORTED)
NORMAL
START-UP
NORMAL
START-UP
OCP
DELAY
NORMAL
OPERATION
START-UP WITH
OUTPUT SHORTED
POWER-DOWN
(OUTPUT
NORMAL
SHORTED)
OPERATION
Figure 13 Hiccup over-current waveforms
Linear Regulator Output (VCCL)
The IR3521 has a built-in linear regulator controller, and only an external NPN transistor is needed to create a
linear regulator. The output voltage of the linear regulator can be programmed between 4.75V and 7.5V [?] by the
resistor divider at VCCLFB pin. The regulator output powers the gate drivers and other circuits of the phase ICs
along with circuits in the control IC, and the voltage is usually programmed to optimize the converter efficiency. The
linear regulator can be compensated by a 4.7uF capacitor at the VCCL pin. As with any linear regulator, due to
stability reasons, there is an upper limit to the maximum value of capacitor that can be used at this pin and it’s a
function of the number of phases used in the multiphase architecture and their switching frequency. Figure 14
shows the stability plots for the linear regulator with 5 phases switching at 750 kHz.
For powering the IR3521 and up to two phase ICs an NPN transistor in a SOT-23 package could be used. For a
larger number of phase ICs an NPN transistor in DPAK package is recommended. .
VCCL voltage must be regulated by a closed control loop based on the IR3521’s VCCL regulator controller in order
to keep both VCCLDRV and VCCLFB voltages in the operating points that would support correct UVLO operation.
No external power rail can be connected to VCCL pin.”
Page 22
V3.03
IR3521
Figure 14 VCCL regulator stability with 5 phases and PHSOUT equals 750 kHz
VCCL Under Voltage Lockout (UVLO)
The IR3521 does not directly monitor VCC for under voltage lockout but instead monitors the system VCCL supply
voltage since this voltage is used for the gate drive. As VCC begins to rise during power up, the VCCLDRV pin will
be high impedance therefore allowing VCCL to roughly follow VCC-NPNVBE until VCCL is above 94% of the voltage
set by resistor divider at VCCLFB pin. At this point, the OVX and UV CLEARED fault latches will be released. If
VCCL voltage drops below 86% of the set value, the SS/DEL CLEARED fault latch will be set.
VID OFF Codes
SVID OFF codes of 111_1100, 111_1101, 111_1110, and 111_1111 turn off the converter by pulling down EAOUTX
voltage and discharging SS/DELX through the 50uA discharge current, but do not drive PGOOD low. Upon receipt
of a non-off SVID code the converter will turn on and transition to the voltage represented by the SVID as shown in
Figure 10.
Power Good (PGOOD)
The PGOOD pin is an open-collector output and should have an external pull-up resistor. During soft start, PGOOD
remains low until the output voltage is in regulation and SS/DELX is above 3.9V. The PGOOD pin becomes low if
ENABLE is low, VCCL is below 86% of target, an over current condition occurs for at least 1024 PHSOUT clocks
prior to PGOOD, an over current condition occurs after PGOOD and SS/DELX discharges to the delay threshold, an
open phase timing daisy chain condition occurs, VOSNS lines are detected open, VOUTX is 315mV below VDACX,
or if the error amp is sensed as operating open loop for 8 PHSOUT cycles. A high level at the PGOOD pin indicates
that the converter is in operation with no fault and ensures the output voltage is within the regulation.
PGOOD monitors the output voltage. If any of the voltage planes fall out of regulation, PGOOD will become low, but
the VR continues to regulate its output voltages. The PWROK input may or may not de-assert prior to the voltage
planes falling out of specification. Output voltage out of spec is defined as 315mV to 275mV below nominal voltage.
VID on-the-fly transition which is a voltage plane transitioning between one voltage associated with one VID code
and a voltage associated with another VID code is not considered to be out of specification.
A PWROK de-assert while ENABLE is high results in all planes regulating to the previously stored 2-bit Boot VID. If
the 2-bit Boot VID is higher than the VID prior to PWROK de-assertion, this transition will NOT be treated as VID on-
the-fly and if either of the two outputs is out of spec high, PGOOD will be pulled down.
Page 23
V3.03
IR3521
Open Voltage Loop Detection
The output voltage range of error amplifier is continuously monitored to ensure the voltage loop is in regulation. If
any fault condition forces the error amplifier output above VCCL-1.08V for 8 PHSOUT switching cycles, the fault
latch is set. The fault latch can only be cleared by cycling the power to VCCL.
Load Current Indicator Output
The VDRP pin voltage represents the average current of the converter plus the DAC voltage. The load current
information can be retrieved by using a differential amplifier to subtract VDAC1 voltage from the VDRP1 voltage.
Enable Input
Pulling the ENABLE pin below 0.8V sets the Fault Latch. Forcing ENABLE to a voltage above 1.94V results in the
pre-PWROK 2 bit VID codes off the SVD and SVC pins to be read and stored. SS/DELX pins are also allowed to
begin their power-up cycles.
Over Voltage Protection (OVP)
Output over-voltage might occur due to a high side MOSFET short or if the output voltage sense path is
compromised. If the over-voltage protection comparators sense that either VOUTX pin voltage exceeds VDACX by
260mV, the over voltage fault latch is set which pulls the error amplifier output low to turn off the converter power
stage. The IR3521 communicates an OVP condition to the system by raising the ROSC/OVP pin voltage to within
V(VCCL) – 1.2 V. An OVP condition is also communicated to the phase ICs by forcing the IIN pin (which is tied to
the ISHARE bus and ISHARE pins of the phase ICs) to VCCL as shown in Figure 15. In each phase IC, the OVP
circuit overrides the normal PWM operation to ensure the low side MOSFET turn-on within approximately 150ns.
The low side MOSFET will remain on until the ISHARE pins fall below V(VCCL) - 800mV. An over voltage fault
condition is latched in the IR3521 and can only be cleared by cycling the power to VCCL.
During dynamic VID down at light to no load, false OVP triggering is prevented by increasing the OVP threshold to a
fixed 1.85V whenever a dynamic VID is detected and the difference between output voltage and the fast internal
VDAC is more than 50mV, as shown in Figure 16. The over-voltage threshold is changed back to VDAC+125mV if
the difference between output voltage and the fast internal VDAC is less than 50mV.
The overall system must be considered when designing for OVP. In many cases the over-current protection of the
AC-DC or DC-DC converter supplying the multiphase converter will be triggered thus providing effective protection
without damage as long as all PCB traces and components are sized to handle the worst-case maximum current. If
this is not possible, a fuse can be added in the input supply to the multiphase converter.
Page 24
V3.03
IR3521
OUTPUT
VOLTAGE
(Vout)
OVP
THRESHOLD
VCCL-800 mV
IIN
(PHASE IC
ISHARE)
GATEH
(PHASE IC)
GATEL
(PHASE IC)
FAULT
LATCH
ERROR
AMPLIFIER
OUTPUT
VDAC
(EAOUT)
AFTER
OVP
NORMAL OPERATION
OVP CONDITION
Figure 15 - Over-voltage protection during normal operation
VID
VDAC
OV
THRESHOLD
1.85V
VDAC + 260mV
OUTPUT
VOLTAGE
(VO)
VDAC
50mV
50mV
NORMAL
OPERATION
NORMAL
OPERATION
VID DOWN
LOW VID
VID UP
Figure 16 Over-voltage protection during dynamic VID
Page 25
V3.03
IR3521
Open Remote Sense Line Protection
If either remote sense line VOSENX+ or VOSENX- is open, the output of Remote Sense Amplifier (VOUTX) drops.
The IR3521 continuously monitors the VOUTX pin and if VOUTX is lower than 200 mV, two separate pulse currents
are applied to the VOSENX+ and VOSENX- pins to check if the sense lines are open. If VOSENX+ is open, a voltage
higher than 90% of V(VCCL) will be present at VOSENX+ pin and the output of Open Line Detect Comparator will
be high. If VOSENX- is open, a voltage higher than 400mV will be present at VOSENX- pin and the Open Line
Detect Comparator output will be high. With either sense line open, the Open Sense Line Fault Latch will be set to
force the error amplifier output low and immediately shut down the converter. SS/DELX will be discharged and the
Open Sense Fault Latch can only be reset by cycling the power to VCCL.
Open Daisy Chain Protection
The IR3521 checks the daisy chain every time it powers up. It starts a daisy chain pulse on the PHSOUT pin and
detects the feedback at PHSIN pin. If no pulse comes back after 32 CLKOUT pulses, the pulse is restarted again. If
the pulse fails to come back the second time, the Open Daisy Chain fault is registered, and SS/DELX is not allowed
to charge. The fault latch can only be reset by cycling the power to VCCL.
After powering up, the IR3521 monitors PHSIN pin for a phase input pulse equal or less than the number of phases
detected. If PHSIN pulse does not return within the number of phases in the converter, another pulse is started on
PHSOUT pin. If the second started PHSOUT pulse does not return on PHSIN, an Open Daisy Chain fault is
registered.
Phase Number Determination
After a daisy chain pulse is started, the IR3521 checks the timing of the input pulse at PHSIN pin to determine the
phase number.
Page 26
V3.03
IR3521
APPLICATIONS INFORMATION
CVCC8
Q4
VGATE
12V
V2EA
RVCCLFB1
RVCCLFB2
CVCCL10
RVCCLDRV
VDDNB
CONVERTER
CIN6
ISHARE2
Q64
15
CCS9
1
2
3
4
5
VDAC2
RCS6
IOUT
SW
GATEH
BOOST
VCCL
NC2
VDDNBSEN+
VDDNB SENSE+
14
CBST62
13
VDDPWRGD
U311
PSI
L12
IR3507
PHSIN
DACIN
LGND
PHSIN
SVC
VDDNB+
12
PHSOUT
CLKOUT
Q63
11
COUTNB
VDDNB-
EPAD
VDDNBSEN-
CVCCL12
VDDNB SENSE-
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
SVD
SVD
PSI_L
ROSC
ROSC
PWROK
PWROK
ENABLE
IIN2
RDRP11
ENABLE
CDRP1
VDRP1
IIN1
RDRP12
CVCC12
VDD 5-PHASE
CONVERTER
IR3521
CONTROL
IC
CSS/DEL2
CSS/DEL1
SS/DEL2
VDAC2
OCSET2
EAOUT2
SS/DEL1
VDAC1
OCSET1
EAOUT1
CVDAC2
CVDAC1
RVDAC2
RVDAC1
CIN1
ROCSET2
ROCSET1
VDAC
VDDEA
V2EA
Q16
CCP11
RCP1
CCS8
1
2
3
4
5
15
14
13
12
11
RCS1
IOUT
PSI
SW
GATEH
BOOST
VCCL
NC2
VDDSEN+
VDD SENSE+
VDD+
U345
CCP12
CBST2
L9
RCP2
CCP22
IR3507
DACIN
LGND
PHSIN
RFB11
RFB12
COUT
CCP21
Q15
CFB2
CFB1
RFB22
VDD-
RTHERM1
RFB21
RFB13
CVCCL14
CVCC7
VDDSEN-
CLOSE TO
POWER
STAGE
VDD SENSE-
VDDSEN+
VDDSEN-
CIN2
VDDNBSEN-
VDDNBSEN+
Q24
1
2
3
4
5
15
CCS7
RCS2
IOUT
PSI
SW
14
U343
GATEH
CBST9
L8
13
12
11
IR3507
DACIN
LGND
PHSIN
BOOST
VCCL
NC2
Q23
CVCCL15
CVCC11
CIN3
U344
1
2
3
4
5
15
CCS12
RCS3
IOUT
PSI
SW
14
13
12
11
U105
GATEH
BOOST
VCCL
NC2
CBST7
L10
IR3507
DACIN
LGND
PHSIN
U318
CVCCL13
CVCC10
CIN4
Q43
CCS10
1
2
3
4
5
15
IOUT
PSI
SW
RCS4
14
U346
GATEH
CBST6
L11
13
12
11
IR3507
DACIN
LGND
PHSIN
BOOST
VCCL
NC2
Q44
CVCCL11
CVCC9
CIN5
U341
1
2
3
4
5
15
CCS11
IOUT
PSI
SW
RCS5
14
13
12
11
U347
GATEH
BOOST
VCCL
NC2
CBST8
L7
IR3507
DACIN
LGND
PHSIN
U342
CVCCL16
Figure 17 IR3521 \ IR3507 Five Phases – One Phase Dual Outputs AMD SVID Converter
Page 27
V3.03
IR3521
DESIGN PROCEDURES - IR3521 AND IR3508 CHIPSET
IR3521 EXTERNAL COMPONENTS
All the output components are selected using one output but suitable for both unless otherwise specified.
Oscillator Resistor RRosc
The IR3521 generates square wave pulses to synchronize the phase ICs. The switching frequency of the each
phase converter equals the PHSOUT frequency, which is set by the external resistor RROSC (use Figure 2 to
determine the RROSC value). The CLKOUT frequency equals the switching frequency multiplied by the phase
number.
Soft Start Capacitor CSS/DEL
The Soft Start capacitor CSS/DEL programs four different time parameters: soft start delay time, soft start time,
PGOOD delay time and over-current fault latch delay time after PGOOD.
SS/DEL pin voltage controls the slew rate of the converter output voltage, as shown in Figure 11. Once the ENABLE
pin rises above 1.65V, there is a soft-start delay time TD1 during which SS/DEL pin is charged from zero to 1.4V.
Once SS/DEL reaches 1.4V the error amplifier output is released to allow the soft start. The soft start time, TD2,
represents the time during which converter voltage rises from zero to pre-PWROK VID voltage and the SS/DEL pin
voltage rises from 1.4V to pre-PWROK VID voltage plus 1.4V. PGOOD delay time TD3 is the time period from VR
reaching the pre-PWROK VID voltage to the PGOOD signal assertion.
Calculate CSS/DEL based on the required soft start time TD2.
TD2*50*106
TD2* ICHG
(1)
CSS / DEL
VprePWROK
VprePWROK
The soft start delay time TD1 and PGOOD delay time TD3 are determined by equation (2) and (3) respectively.
C
SS / DEL *1.4
C
SS / DEL *1.4
50*106
(2)
TD1
TD3
ICHG
CSS / DEL * (3.92 VprePWROK 1.4) CSS / DEL *(3.92 VprePWROK 1.4)
(3)
50 *106
ICHG
Once CSS/DEL is chosen, use equation (4) to calculate the maximum over-current fault latch delay time tOCDEL.
CSS / DEL *0.12 CSS / DEL *0.12
(4)
tOCDEL
47 *106
IDISCHG
VDAC Slew Rate Programming Capacitor CVDAC and Resistor RVDAC
The slew rate of VDAC down-slope SRDOWN can be programmed by the external capacitor CVDAC as defined in (5),
where ISINK is the VDAC buffer sink current. The resistor RVDAC is used to compensate VDAC circuit and is
determined by (6). The up and down slow are equal due to symmetrical sink and source capabilities of the VDAC
buffer.
Page 28
V3.03
IR3521
ISINK
(5)
(6)
CVDAC
SRDOWN
3.2 1015
RVDAC 0.5
2
CVDAC
Over Current Setting Resistor ROCSET
The inductor DC resistance is utilized to sense the inductor current. The copper wire of inductor has a constant
temperature coefficient of 3850 ppm/°C, and therefore the maximum inductor DCR can be calculated from (7), where
RL_MAX and RL_ROOM are the inductor DCR at maximum temperature, TL_MAX, and room temperature, TL_ROOM,
respectively.
RL _ MAX RL _ ROOM [1 3850*106 (TL _ MAX TL _ ROOM )]
(7)
The total input offset voltage (VCS_TOFST), of the phase IC’s current sense amplifier, is the sum of input offset
(VCS_OFST) of the amplifier itself and that created by the amplifier input bias current flowing through the current sense
resistor RCS.
VCS _ TOFST VCS _ OFST ICSIN RCS
(8)
The over-current limit is set by the external resistor ROCSET as defined in (9). ILIMIT is the required over-current limit.
IOCSET is the bias current of OCSET pin and can be calculated with the equation located in the ELECTRICAL
CHARACTERISTICS Table. GCS is the gain of the current sense amplifier. KP is the ratio of inductor peak current
over the average current in each phase and can be calculated using equation (10).
ILIMIT
ROCSET [
RL _ MAX (1 KP ) VCS _ TOFST ]GCS / IOCSET
(9)
n
(VI VO )VO /(LVI fSW 2)
IO / n
(10)
KP
VCCL Programming Resistor RVCCLFB1 and RVCCLFB2
Since VCCL voltage is proportional to the MOSFET gate driver loss and inversely proportional to the MOSFET
conduction loss, the optimum voltage should be chosen to maximize the converter efficiency. VCCL linear
regulator consists of an external NPN transistor, a ceramic capacitor and a programmable resistor divider. Pre-
select RVCCLFB1, and calculate RVCCLFB2 from (11).
R
VCCLFB1 *1.23
RVCCLFB2
(11)
VCCL 1.23
No Load Offset Setting Resistor RFB11, RFB13, RTHERM1 and Adaptive Voltage Positioning Resistor
RDRP11 for Output1
Define RFB_R as the effective offset resistor at room temperature equals to RFB11//(RFB13+RTHERM1). Given the
offset voltage VO_NLOFST (offset above the DAC voltage) and calculating the sink current from the FB1 pin IFB1, using
the equation in the ELECTRICAL CHARACTERISTICS Table, the effective offset resistor value, RFB1, can be
determined from equation (12).
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VO _ NLOFST
RFB _ R
(12)
IFB1
Adaptive voltage positioning lowers the converter voltage by RO*IO, where RO is the required output impedance of
the converter. Pre-select feedback resistor RFB, and calculate the droop resistor RDRP,
RFB _ R RL _ ROOM *GCS
(13)
RDRP11
n RO
Calculate the desired effective feedback resistor at the maximum temperature RFB_M using (14)
RDRP11 RO *n
GCS RL _ MAX
RFB _ M
(14)
A negative temperature constant (NTC) thermistor RTHERM1 is required to sense the temperature of the power stage
for the inductor DCR thermal compensation. Pre-select the value of RTHERM. RTHERM must be bigger than RFB_R at
room temperature but also bigger than RFB_M at the maximum allowed temperature. RTMAX1 is defined as the NTC
thermistor resistance at maximum allowed temperature, TMAX. RTMAX1 is calculated from (15).
1
1
RTMAX1 RTHERM1 *EXP[BTHERM1 *(
)]
(15)
TL _ MAX T_ ROOM
Select the series resistor RFB13 by using equation (16). RFB13 is incorporated to linearize the NTC thermistor which
has non-linear characteristics in the operational temperature range.
(RTHERM 1 RTMAX 1)2 4 * (RTHERM 1 * RTMAX 1 (RTHERM 1 RTMAX 1) * RFB _ R * RFB _ M /(RFB _ R RFB _ M )) (RTHERM 1 RTMAX 1
)
(16)
RFB13
2
Use equation (17) to determine RFB11.
1
1
1
(17)
RFB11 RFB _ R RFB13 RTHERM1
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IDD Dynamic OC Limit Capacitor
The latest AMD processors require two over current limits: one for normal thermal design current (TDC) operation and
the other for system IDD_Spike. TDC over-current is set by following instructions outlined in the Over Current Setting
Resistor Rocset section. IDD_Spike occur when the load current exceeds the TDC for a very short duration (10 ms).
Figure 18 shows the boundaries of an event. The current over a moving average of 10 ms does not exceed the TDC
limit. Higher IDD-Spike will last for a shorter duration.
OCP-IDDSpike
IDDSpike
OCP-TDC
TDC
1
2
3
4
5
6
7
8
9
10
Time (ms)
Figure 18 Showing IDD_Spike Boundaries
The IDD_Spike over current threshold can be implemented by incorporation a properly sized capacitor between
the OCSET (18) and the IN1 (21) pins (see Figure 19).
Phase IC IOUT
1
Phase IC IOUT
2
High-pass filter
IIN
CIDDSpike
Phase IC IOUT
3
OCSET1
VDAC
Control IC
OCSET
comparator
ROCSET
RVDAC
Phase IC
4
IOUT
CVDAC
Figure 19 CIDDSpike and ROCSET form a High Pass Filter
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When a step load is applied, the capacitor acts as a short-circuit, at that instant, and pushes the OCSET signal up by
∆V (i.e. change in IIN) instantaneously. After an increase in its level, the OCP signal starts decaying exponentially
towards its original value. The rate of decay is determined by the RC time constant. The VR will enter hiccup mode
when the OCSET signal falls below the IIN value. The following equation (18) is use to calculate the ideal capacitor
value:
tspike _ oc
CIDD _ Spike
,
(18)
Ispike IOC
Ispike ITDC
ROC In
where,
tspike_oc = IDD_Spike OC time (choose >1.5ms),
Roc = OC resistor (TDC),
Ispike = IDD_Spike Max,
IOC = TDC OC Threshold,
ITDC = Thermal Design Current.
The following graph shows a dynamic OC response with tspike set for 1.5ms.
tspike_oc
IDD_Spike OC Threshold
IDD_Spike Boundary
OC Threshold
TDC
Figure 20 Showing Dynamic OC Response
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IR3508 EXTERNAL COMPONENTS
Inductor Current Sensing Capacitor CCS and Resistor RCS
The DC resistance of the inductor is utilized to sense the inductor current. Usually the resistor RCS and capacitor
CCS in parallel with the inductor are chosen to match the time constant of the inductor, and therefore the voltage
across the capacitor CCS represents the inductor current. If the two time constants are not the same, the AC
component of the capacitor voltage is different from that of the real inductor current. The time constant mismatch
does not affect the average current sharing among the multiple phases, but affect the current signal ISHARE as well
as the output voltage during the load current transient if adaptive voltage positioning is adopted.
Measure the inductance L and the inductor DC resistance RL. Pre-select the capacitor CCS and calculate RCS as
follows.
L RL
(19)
RCS
CCS
Bootstrap Capacitor CBST
Depending on the duty cycle and gate drive current of the phase IC, a capacitor in the range of 0.1uF to 1uF is
needed for the bootstrap circuit.
Decoupling Capacitors for Phase IC
0.1uF-1uF decoupling capacitors are required at VCC and VCCL pins of phase ICs.
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VOLTAGE LOOP COMPENSATION
The adaptive voltage positioning (AVP) is usually adopted in the computer applications to improve the transient
response and reduce the power loss at heavy load. Like current mode control, the adaptive voltage positioning
loop introduces extra zero to the voltage loop and splits the double poles of the power stage, which make the
voltage loop compensation much easier.
Adaptive voltage positioning lowers the converter voltage by RO*IO, where RO is the required output impedance of
the converter.
The selection of compensation types depends on the output capacitors used in the converter. For the applications
using Electrolytic, Polymer or AL-Polymer capacitors and running at lower frequency, type II compensation shown
in Figure 21(a) is usually enough. While for the applications using only ceramic capacitors and running at higher
frequency, type III compensation shown in Figure 21(b) is preferred.
For applications where AVP is not required, the compensation is the same as for the regular voltage mode
control. For converter using Polymer, AL-Polymer, and ceramic capacitors, which have much higher ESR zero
frequency, type III compensation is required as shown in Figure 18(b) with RDRP and CDRP removed.
CCP1
CCP1
RFB
CFB
RCP
CCP
VO+
RCP
CCP
RFB1
FB
-
EAOUT
RFB
EAOUT
VO+
FB
VDAC
-
RDRP
+
VDRP
EAOUT
EAOUT
VDAC
RDRP
CDRP
+
VDRP
(a) Type II compensation
(b) Type III compensation
Figure 21 Voltage loop compensation network
Type II Compensation for AVP Applications
Determine the compensation at no load, the worst case condition. Choose the crossover frequency fc between
1/10 and 1/5 of the switching frequency per phase. Assume the time constant of the resistor and capacitor across
the output inductors matches that of the inductor, and determine RCP and CCP from (20) and (21), where LE and
CE are the equivalent inductance of output inductors and the equivalent capacitance of output capacitors
respectively.
(2 fC )2 LE CE RFB 5
VI * 1 (2 * fC *C * RC )2
(20)
RCP
10 LE CE
(21)
CCP
RCP
CCP1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise.
A ceramic capacitor between 10pF and 220pF is usually enough.
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Type III Compensation for AVP Applications
Determine the compensation at no load, the worst case condition. Assume the RC, resistor and capacitor across
the output inductors, and L/DCR time constant matches, the crossover frequency and phase margin of the voltage
loop can be estimated by (22) and (23), where RLE is the equivalent resistance of inductor DCR.
RDRP
(22)
(23)
fC1
2 *CE GCS * RFB RLE
180
C1 90 A tan(0.5)
Choose the desired crossover frequency fc around fc1, estimated by (22), or choose fc between 1/10 and 1/5 of
the switching frequency per phase. The components should be selected to ensure the close loop gain slope is
-20dB /Dec around the crossover frequency. Choose resistor RFB1 according to (24), and determine CFB and
CDRP from (25) and (26).
1
2
2
3
RFB1
RFB
to
RFB1
RFB
(24)
(25)
1
CFB
4 fC RFB1
(RFB RFB1) CFB
(26)
CDRP
RDRP
RCP and CCP have limited effect on the crossover frequency, and are used only to fine tune the crossover
frequency and transient load response. Determine RCP and CCP from (27) and (28).
(2 fC )2 LE CE RFB 5
(27)
(28)
RCP
VI
10 LE CE
CCP
RCP
CCP1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise.
A ceramic capacitor between 10pF and 220pF is usually enough.
Type III Compensation for Non-AVP Applications
Resistor RDRP and capacitor CDRP are not needed. Choose the crossover frequency fc between 1/10 and 1/5 of
the switching frequency per phase and select the desired phase margin θc. Calculate K factor from (29), and
determine the component values based on (30) to (34),
C
K tan[ (
4
1.5)]
(29)
(30)
(31)
(32)
180
(2 LE CE fC )2 5
VI K
RCP RFB
K
CCP
2 fC RCP
1
CCP1
2 fC K RCP
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K
(33)
(34)
CFB
2 fC RFB
1
RFB1
2 fC K CFB
CURRENT SHARE LOOP COMPENSATION
The internal compensation of current share loop ensures that crossover frequency of the current share loop is at least
one decade lower than that of the voltage loop so that the interaction between the two loops is eliminated.
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DESIGN EXAMPLE – AMD FIVE + ONE PHASE DUAL OUTPUT CONVERTER (FIGURE 17)
SPECIFICATIONS
Input Voltage: VI=12 V
DAC Voltage: VDAC=1.2 V
No Load Output Voltage Offset for output1: VO_NLOFST=15 mV
Output1 Current: IO1=95 ADC
Output2 Current: IO1=20 ADC
Output1 Over Current Limit: Ilimit1=115 ADC
Output2 Over Current Limit: Ilimit2= 25 ADC
Output Impedance: RO1=0.3 mꢀ
Dynamic VID Slew Rate: SR=3.25mV/uS
Over Temperature Threshold: TMAX=110 ºC
POWER STAGE
Phase Number: n1=5, n2=1
Switching Frequency: fSW=520 kHz
Output Inductors: L1=120 nH, L2=220 nH, RL1= 0.52mꢀ, RL2= 0.47mꢀ
Output Capacitors: POSCAPs, C=470uF, RC= 8mꢀ, Number Cn1=9, Cn2=5
IR3500 EXTERNAL COMPONENTS
Oscillator Resistor RROSC
Once the switching frequency is chosen, RROSC can be determined from Figure 2. For switching frequency of
520kHz per phase, choose ROSC=23.2kꢀ.
Soft Start Capacitor CSS/DEL
Determine the soft start capacitor from the required soft start time.
2*103 *50*106
TD2* ICHG
CSS / DEL
0.1uF
Vboot
1.0
The soft start delay time is
0.1*106 *1.1
50*106
CSS / DEL *1.1
TD1
2.2mS
ICHG
The PGOOD delay time is
0.1*106 *(3.92 11.1)
C
SS / DEL *(3.92 Vboot 1.1)
TD3
3.6mS
50*106
ICHG
The maximum over current fault latch delay time is
0.1*106 *0.12
47 *106
C
SS / DEL *0.12
tOCDEL
0.638mS
IDISCHG
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VDAC Slew Rate Programming Capacitor CVDAC and Resistor RVDAC
ISINK
45.2 106
3.2*103
, Choose CVDAC=22nF
14.1nF
CVDAC
SRDOWN
3.2 1015
RVDAC 0.5
7.1Ohm
2
CVDAC
Over Current Setting Resistor ROCSET
The output1 over current limit is 115A and the output2 over current limit is 25A. From the electrical characteristics
table can get the bias current of OCSET pin (IOCSET) is 26uA with ROSC=23.2 kꢀ. The total current sense
amplifier input offset voltage is around 0mV, Calculate constant KP, the ratio of inductor peak current over average
current in each phase,
(VI VO )VO /(L VI fSW 2) (12 1.2)1.2 /(120*109 12520*103 2)
KP1
KP 2
0.38
ILIMIT / n
115 / 5
(12 1.2)1.2 /(220*109 12520*103 2)
0.19
25
ILIMIT
ROCSET 1 [
RL (1 KP ) VCS _TOFST ]GCS / IOCSET
n
115
(
0.52*103 1.38)*34 /(26*106 ) 21.6k
5
ILIMIT
ROCSET 2 [
RL (1 KP ) VCS _ TOFST ]GCS / IOCSET
n
25
( 0.47*103 1.19)*34 /(26*106 ) 18.4k
1
VCCL Programming Resistor RVCCLFB1 and RVCCLFB2
Choose VCCL=7V to maximize the converter efficiency. Pre-select RVCCLFB1=20kꢀ, and calculate RVCCLFB2.
VCCLFB1 *1.23 20*103 *1.23
R
RVCCLFB2
4.26k
VCCL 1.23
7 1.23
No Load Offset Setting Resistor RFB11, RFB13, RTHERM1 and Adaptive Voltage Positioning Resistor
RDRP11 for Output1
Define RFB_R is the effective offset resistor at room temperature equals to RFB11//(RFB13+RTHERM1). Given the
offset voltage VO_NLOFST above the DAC voltage, calculate the sink current from the FB1 pin IFB1= 26uA using
the equation in the ELECTRICAL CHARACTERISTICS Table, then the effective offset resistor value RFB_R1 can
be determined by:
15*103
26*106
VO _ NLOFST
RFB _ R1
577Ohm
I FB1
Adaptive voltage positioning lowers the converter voltage by RO*IO, where RO is the required output impedance of
the converter. Pre-select feedback resistor RFB, and calculate the droop resistor RDRP,
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577*0.52*103 *34
5*0.3*103
RFB _ R RL _ ROOM *GCS
RDRP1
6.7KOhm
n RO
In the case of thermal compensation is required, use equation (14) to (17) to select the RFB network resistors.
IR3508 EXTERNAL COMPONENTS
Inductor Current Sensing Capacitor CCS and Resistor RCS
Choose CCS1=Ccs2=0.1uF, and calculate RCS,
L RL 120*109 /(0.52*103)
RCS1
2.3k
0.1*106
CCS
L RL 220*109 /(0.47*103)
RCS 2
4.7k
0.1*106
CCS
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LAYOUT GUIDELINES
The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB
layout, therefore minimizing the noise coupled to the IC.
Dedicate at least one middle layer for a ground plane LGND.
Connect the ground tab under the control IC to LGND plane through a via.
Separate analog bus (EAIN, DACIN and ISHARE) from digital bus (CLKIN, PHSIN, and PHSOUT) to reduce
the noise coupling.
Place VCCL decoupling capacitor VCCL as close as possible to VCCL and LGND pins.
Place the following critical components on the same layer as control IC and position them as close as
possible to the respective pins, ROSC, ROCSET, RVDAC, CVDAC, and CSS/DEL. Avoid using any via for
the connection.
Place the compensation components on the same layer as control IC and position them as close as possible
to EAOUT, FB, VO and VDRP pins. Avoid using any via for the connection.
Use Kelvin connections for the remote voltage sense signals, VOSNS+ and VOSNS-, and avoid crossing over
the fast transition nodes, i.e. switching nodes, gate drive signals and bootstrap nodes.
Avoid analog control bus signals, VDAC, IIN, and especially EAOUT, crossing over the fast transition nodes.
Separate digital bus, CLKOUT, PHSOUT and PHSIN from the analog control bus and other compensation
components.
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PCB METAL AND COMPONENT PLACEMENT
Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should
be ≥ 0.2mm to prevent shorting.
Lead land length should be equal to maximum part lead length + 0.3 mm outboard extension + 0.05mm
inboard extension. The outboard extension ensures a large and inspectable toe fillet, and the inboard
extension will accommodate any part misalignment and ensure a fillet.
Center pad land length and width should be equal to maximum part pad length and width. However, the
minimum metal to metal spacing should be ≥ 0.17mm for 2 oz. Copper (≥ 0.1mm for 1 oz. Copper and ≥
0.23mm for 3 oz. Copper)
Four 0.30mm diameter vias shall be placed in the center of the pad land and connected to ground to
minimize the noise effect on the IC.
No pcb traces should be routed nor vias placed under any of the 4 corners of the IC package. Doing so
can cause the IC to rise up from the pcb resulting in poor solder joints to the IC leads.
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SOLDER RESIST
The solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. The solder
resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all Non
Solder Mask Defined (NSMD). Therefore pulling the S/R 0.06mm will always ensure NSMD pads.
The minimum solder resist width is 0.13mm.
At the inside corner of the solder resist where the lead land groups meet, it is recommended to provide a
fillet so a solder resist width of ≥ 0.17mm remains.
The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto
the copper of 0.06mm to accommodate solder resist mis-alignment. In 0.5mm pitch cases it is allowable
to have the solder resist opening for the land pad to be smaller than the part pad.
Ensure that the solder resist in-between the lead lands and the pad land is ≥ 0.15mm due to the high
aspect ratio of the solder resist strip separating the lead lands from the pad land.
Four vias in the land pad should be tented or plugged from bottom boardside with solder resist.
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STENCIL DESIGN
The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands.
Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mm
pitch devices the leads are only 0.25mm wide, the stencil apertures should not be made narrower;
openings in stencils < 0.25mm wide are difficult to maintain repeatable solder release.
The stencil lead land apertures should therefore be shortened in length by 80% and centered on the lead
land.
The land pad aperture should be striped with 0.25mm wide openings and spaces to deposit
approximately 50% area of solder on the center pad. If too much solder is deposited on the center pad
the part will float and the lead lands will be open.
The maximum length and width of the land pad stencil aperture should be equal to the solder resist
opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the
lead lands when the part is pushed into the solder paste.
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PACKAGE INFORMATION
32L MLPQ (5 x 5 mm Body) θJA =24.4 oC/W, θJC =0.86 oC/W
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Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.
www.irf.com
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