AS7C33256PFS32A2-133TQI [ISSI]
Standard SRAM, 256KX32, 10ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100;
| 型号： | AS7C33256PFS32A2-133TQI |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Standard SRAM, 256KX32, 10ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100 静态存储器 |
| 文件： | 总14页 (文件大小：384K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 2002
Preliminary
AS7C33256PFS32A
AS7C33256PFS36A
®
3.3V 256K × 32/36 pipeline burst synchronous SRAM
Features
• Organization: 262,144 words x 32 or 36 bits
• Fast clock speeds to 166 MHz in LVTTL/LVCMOS
• Fast clock to data access: 3.5/3.8/4.0/5.0 ns
• Fast OE access time: 3.5/3.8/4.0/5.0 ns
• Fully synchronous register-to-register operation
• Single register “Flow-through” option
• Single-cycle deselect
- Dual-cycle deselect also available (AS7C33256PFD32A/
AS7C33256PFD36A)
• Pentium®1compatible architecture and timing
• Asynchronous output enable control
• Available in100-pin TQFP and 119-pin BGA packages
• Byte write enables
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate VDDQ
• 30 mW typical standby power in power down mode
• NTD™1 pipeline architecture available
(AS7C33256NTD32A/ AS7C33256NTD36A)
• Available in both 2 chip enable and 3 chip enable
- 2 CE part number is AS7C33256PFS32A2 or AS7C33256PFS36A2
®
1 Pentium is a registered trademark of Intel Corporation. NTD™ is a
trademark of Alliance Semiconductor Corporation. All trademarks
mentioned in this document are the property of their respective
owners.
Logic block diagram
LBO
Burst logic
CLK
ADV
ADSC
CLK
CE
CLR
256K × 32/36
Memory
ADSP
18
16
18
18
array
D
CE
CLK
Q
A[17:0]
Address
register
36/32
36/32
BWE
GWE
d
D
Q
Q
Q
Q
DQ
d
Byte write
BW
registers
CLK
D
DQ
c
BW
c
Byte write
registers
CLK
D
DQ
b
BW
b
Byte write
registers
CLK
D
DQ
a
4
BW
a
Byte write
registers
CLK
D
CE0
CE1
CE2
OE
Output
registers
CLK
Q
Q
Input
registers
CLK
Enable
register
CE
CLK
D
Enable
delay
Power
down
ZZ
register
CLK
36/32
DQ[a:d]
OE
FT
Selection guide
–166
–150
–133
7.5
133
4
–100
10
Units
ns
Minimum cycle time
6
6.6
150
3.8
450
110
30
Maximum pipelined clock frequency
166
3.5
475
130
30
100
5
MHz
ns
Maximum pipelined clock access time
Maximum operating current
425
100
30
325
90
mA
mA
mA
Maximum standby current
Maximum CMOS standby current (DC)
30
4/15/02; v.1.9
Alliance Semiconductor
P. 1 of 14
Copyright ©Alliance Semiconductor. All rights reserved.
AS7C33256PFS32A
AS7C33256PFS36A
®
Pin Arrangement for TQFP 3 Chip Enable
DQP /NC
b
DQP /NC
c
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQ
b
DQ
c
2
DQ
DQ
3
b
c
V
V
4
DDQ
SSQ
DDQ
SSQ
c
V
V
5
DQ
DQ
6
b
DQ
b
DQ
c
7
DQ
b
DQ
c
8
DQ
DQ
9
b
c
SSQ
V
V
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SSQ
DDQ
V
DQ
DQ
c
DDQ
DQ
b
c
DQ
b
V
FT
SS
NC
VDD
ZZ
V
DD
TQFP 14 × 20 mm
NC
V
SS
DQ
DQ
a
d
DQ
a
DQ
d
V
V
DDQ
SSQ
a
DDQ
V
V
SSQ
d
DQ
DQ
DQ
a
DQ
d
DQ
a
DQ
d
DQ
DQ
a
SSQ
DDQ
a
d
SSQ
V
V
V
V
DDQ
DQ
DQ
a
DQ
DQ
d
d
DQP /NC
a
DQP /NC
d
Note: Pins 1, 30, 51, 80 are NC for ×32
Pin Arrangement for TQFP 2 Chip Enable
DQP /NC
b
DQP /NC
c
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQ
b
DQ
c
2
DQ
DQ
3
b
c
V
V
4
DDQ
SSQ
DDQ
SSQ
c
V
V
5
DQ
DQ
6
b
DQ
b
DQ
c
7
DQ
b
DQ
c
8
DQ
DQ
9
b
c
SSQ
V
V
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SSQ
DDQ
V
DQ
DQ
c
DDQ
DQ
b
c
DQ
b
V
FT
SS
NC
VDD
ZZ
V
DD
TQFP 14 × 20 mm
NC
V
SS
DQ
DQ
DQ
d
a
d
DQ
a
V
V
DDQ
SSQ
a
DDQ
V
V
SSQ
d
DQ
DQ
DQ
a
DQ
d
DQ
a
DQ
d
DQ
DQ
a
SSQ
DDQ
a
d
SSQ
V
V
V
V
DDQ
DQ
DQ
a
DQ
d
DQ
d
DQP /NC
d
DQP /NC
a
Note: Pins 1, 30, 51, 80 are NC for ×32
4/15/02; v.1.9
Alliance Semiconductor
P. 2 of 14
AS7C33256PFS32A
AS7C33256PFS36A
®
1
Ball assignment for 119-ball BGA
1
2
3
4
5
A
6
A
A
A
7
A
B
C
D
E
VDDQ
NC
A
A
ADSP
ADSC
VDD
NC
VDDQ
NC
CE1
A
A
A
NC
A
A
NC
DQC
DQC
VDDQ
DQC
DQC
VDDQ
DQd
DQd
VDDQ
DQd
DQPc
DQc
DQc
DQc
DQc
VDD
DQd
DQd
DQd
DQd
VSS
VSS
VSS
BWc
VSS
NC
VSS
BWd
VSS
VSS
VSS
LBO
A
VSS
VSS
VSS
BWb
VSS
NC
VSS
BWa
VSS
VSS
VSS
FT
DQpb DQb
CE0
OE
DQb
DQb
DQb
DQb
VDD
DQa
DQa
DQa
DQa
DQPa
A
DQb
VDDQ
DQb
DQb
VDDQ
DQa
DQa
VDDQ
DQa
DQa
NC
F
G
H
J
ADV
GWE
VDD
CLK
NC
K
L
M
N
P
BWE
A12
A02
VDD
A
DQd DQPd
R
T
U
NC
NC
A
NC
NC
A
NC
ZZ
VDDQ
NC
NC
NC
NC
VDDQ
1 Note 2D, 2P, 6D and 6P are NC for x32
2 A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter
if burst is desired.
4/15/02; v.1.9
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P. 3 of 14
AS7C33256PFS32A
AS7C33256PFS36A
®
Functional description
The AS7C33256PFS32A and AS7C33256PFS36A are high-performance CMOS 8-Mbit synchronous Static Random Access Memory (SRAM)
devices organized as 262,144 words x 32 or 36 bits, and incorporate a two-stage register-register pipeline for highest frequency on any given
technology.
Timing for these devices is compatible with existing Pentium® synchronous cache specifications. This architecture is suited for ASIC, DSP
1
(TMS320C6X), and PowerPC™ -based systems in computing, datacomm, instrumentation, and telecommunications systems.
Fast cycle times of 6/6.6/7.5/10 ns with clock access times (t ) of 3.5/3.8/4.0/5.0 ns enable 166, 150, 133 and 100 MHz bus frequencies.
CD
Two-chip enable and three-chip enable (CE) inputs permit versatility and easy memory expansion. Burst operation is initiated in one of two
ways: the controller address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally
generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register
when ADSP is sampled Low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation the data accessed
by the current address, registered in the address registers by the positive edge of CLK, are carried to the data-out registers and driven on the
output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on all subsequent
clock edges. Address is incremented internally for the next access of the burst when ADV is sampled Low, and both address strobes are High.
Burst mode is selectable with the LBO input. With LBO unconnected or driven High, burst operations use a Pentium® count sequence. With
LBO driven LOW, the device uses a linear count sequence suitable for PowerPC™ and many other applications.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 32/
36 bits regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is High, one or more bytes may be written by asserting
BWE and the appropriate individual byte BWn signal(s).
BWn is ignored on the clock edge that samples ADSP Low, but is sampled on all subsequent clock edges. Output buffers are disabled when BWn
is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled Low. Address is incremented internally to
the next burst address if BWn and ADV are sampled Low.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow.
• ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.
• WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP High).
• Master chip enable CE0 blocks ADSP, but not ADSC.
AS7C33256PFS32A and AS7C33256PFS36A family operates from a core 3.3V power supply. I/Os use a separate power supply that can operate
at 2.5V or 3.3V. These devices are available in a 100-pin 14 × 20 mm TQFP package and in a 119-pin 14 × 20 mm BGA package.
Capacitance
Parameter
Input capacitance
I/O capacitance
Symbol
CIN
Signals
Address and control pins
I/O pins
Test conditions
VIN = 0V
Max
5
Unit
pF
CI/O
VIN = VOUT = 0V
7
pF
Write enable truth table (per byte)
GWE
BWE
BWn
WEn
T
L
X
L
X
L
H
T
H
H
L
X
H
F*
F*
H
ꢀꢁꢂꢃꢄX = Don’t Care, L = Low, H = High, T = True, F = False; *= Valid read; n = a, b, c, d; WE, WEn = internal write signal.
Burst order table
Interleaved Burst Order
Linear Burst Order
LBO=0
LBO=1
Starting Address 00
First increment 01
Second increment 10
Third increment 11
01
00
11
10
10
11
00
01
11
10
01
00
Starting Address 00
First increment 01
Second increment 10
Third increment 11
01
10
11
00
10
11
00
01
11
00
01
10
™
1 PowerPC is a trademark International Business Machines Corporation.
4/15/02; v.1.9
Alliance Semiconductor
P. 4 of 14
AS7C33256PFS32A
AS7C33256PFS36A
®
Signal descriptions
Signal
I/O Properties Description
CLK
I
I
CLOCK
SYNC
SYNC
Clock. All inputs except OE, FT, ZZ, LBO are synchronous to this clock.
Address. Sampled when all chip enables are active and ADSC or ADSP are asserted.
Data. Driven as output when the chip is enabled and OE is active.
A0–A17
DQ[a,b,c,d] I/O
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is
inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more information.
CE0
I
I
I
SYNC
SYNC
SYNC
Synchronous chip enables. Active HIGH and active Low, respectively. Sampled on clock
edges when ADSC is active or when CE0 and ADSP are active.
CE1, CE2
ADSP
Address strobe processor. Asserted LOW to load a new bus address or to enter standby
mode.
ADSC
ADV
I
I
SYNC
SYNC
Address strobe controller. Asserted LOW to load a new address or to enter standby mode.
Advance. Asserted LOW to continue burst read/write.
Global write enable. Asserted LOW to write all 32/36 bits. When High, BWE and BW[a:d]
control write enable.
GWE
BWE
I
I
SYNC
SYNC
Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a:d] inputs.
Write enables. Used to control write of individual bytes when GWE = HIGH and BWE =
Low. If any of BW[a:d] is active with GWE = HIGH and BWE = LOW the cycle is a write
cycle. If all BW[a:d] are inactive the cycle is a read cycle.
BW[a,b,c,d]
I
SYNC
Asynchronous output enable. I/O pins are driven when OE is active and the chip is in read
mode.
OE
I
I
ASYNC
STATIC
Count mode. When driven High, count sequence follows Intel XOR convention. When
driven Low, count sequence follows linear convention. This signal is internally pulled High.
LBO
Flow-through mode.When low, enables single register flow-through mode. Connect to
FT
ZZ
I
I
STATIC
ASYNC
VDD if unused or for pipelined operation.
Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
Absolute maximum ratings
Parameter
Symbol
VDD, VDDQ
VIN
Min
–0.5
–0.5
–0.5
–
Max
+4.6
Unit
V
Power supply voltage relative to GND
Input voltage relative to GND (input pins)
Input voltage relative to GND (I/O pins)
Power dissipation
VDD + 0.5
VDDQ + 0.5
1.8
V
VIN
V
PD
W
mA
oC
oC
DC output current
IOUT
–
50
Storage temperature (plastic)
Temperature under bias
Tstg
–65
–65
+150
Tbias
+135
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions may affect reliability.
4/15/02; v.1.9
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P. 5 of 14
AS7C33256PFS32A
AS7C33256PFS36A
®
Synchronous truth table
1
CE0
H
L
CE1
X
L
CE2 ADSP ADSC ADV WEn
OE Address accessed
CLK
Operation
Deselect
DQ
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z2
Hi−Z
Hi−Z2
Hi−Z
Q
X
X
X
H
H
L
X
L
L
X
L
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
F
X
X
X
X
X
L
NA
NA
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
Deselect
L
L
H
L
NA
Deselect
L
X
X
H
H
H
H
X
X
X
X
X
X
X
X
H
X
X
X
X
X
L
NA
Deselect
L
H
L
NA
Deselect
L
X
X
L
External
External
External
External
Next
Begin read
Begin read
Begin read
Begin read
Cont. read
Cont. read
Suspend read
Suspend read
Cont. read
Cont. read
Suspend read
Suspend read
Begin write
Cont. write
Cont. write
Suspend write
Suspend write
L
L
L
H
L
L
L
H
H
H
H
H
H
X
X
X
X
H
H
X
H
X
L
L
L
F
H
L
X
X
X
X
H
H
H
H
L
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
H
H
L
F
L
F
H
L
Next
Hi−Z
Q
H
H
L
F
Current
Current
Next
F
H
L
Hi−Z
Q
F
L
F
H
L
Next
Hi−Z
Q
H
H
X
L
F
Current
Current
External
Next
F
H
X
X
X
X
X
Hi−Z
D3
T
T
T
T
T
X
H
X
H
X
X
X
X
H
H
H
H
D
L
Next
D
H
H
Current
Current
D
D
1 See “Write enable truth table” on page 4 for more information.
2 Q in flow through mode.
3 For WRITE operation following a READ, OE must be HIGH before the input data set up time and held HIGH throughout the input hold time.
Key: X = Don’t Care, L = Low, H = High.
Recommended operating conditions
Parameter
Symbol
VDD
VSS
Min
3.135
0.0
Nominal
Max
3.465
0.0
Unit
3.3
0.0
3.3
0.0
2.5
0.0
–
Supply voltage
V
VDDQ
VSSQ
VDDQ
VSSQ
VIH
3.135
0.0
3.465
0.0
3.3V I/O supply voltage
2.5V I/O supply voltage
V
V
V
2.35
0.0
2.9
0.0
2.0
–0.52
VDD + 0.3
0.8
Address and
control pins
VIL
–
Input voltages1
VIH
2.0
–
VDDQ + 0.3
0.8
I/O pins
V
VIL
–0.52
0
–
Ambient operating temperature
TA
–
70
°C
1 Input voltage ranges apply to 3.3V I/O operation. For 2.5V I/O operation, contact factory for input specifications.
2 V min = –2.0V for pulse width less than 0.2 × t
IL
.
RC
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Alliance Semiconductor
P. 6 of 14
AS7C33256PFS32A
AS7C33256PFS36A
®
TQFP thermal resistance
Description
Conditions
Symbol
Ty pi c a l
40
Units
°C/W
°C/W
1–layer
4–layer
θ
Thermal resistance
JA
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51
(junction to ambient)1
θ
22
JA
JC
Thermal resistance
θ
8
°C/W
(junction to top of case)1
1 This parameter is sampled.
DC electrical characteristics
–166
–150
–133
–100
Parameter
Symbol
Test conditions
VDD = Max, VIN = GND to VDD
OE ≥ VIH, VDD = Max,
Min Max Min Max Min Max Min Max Unit
Input leakage
current1
|ILI|
–
–
–
2
2
–
–
–
2
2
–
–
–
2
2
–
–
–
2
2
µA
µA
Output leakage
current
|ILO
|
VOUT = GND to VDD
2
Operating power
supply current
ICC
CE0 = VIL, CE1 = VIH, CE2 = VIL,
f = fMax, IOUT = 0 mA
475
450
425
325 mA
(Pipelined)
2
ICC
Operating power
supply current
CE0 = VIL, CE1 = VIH, CE2 = VIL,
f = fMax, IOUT = 0 mA
–
325
–
325
–
300
–
300 mA
90
(Flow-
through)
ISB
Deselected, f = fMax, ZZ ≤ VIL
–
–
130
30
–
–
110
30
–
–
100
30
–
–
Deselected, f = 0, ZZ ≤ 0.2V
all VIN ≤ 0.2V or ≥ VDD – 0.2V
Standby power
supply current
ISB1
30
mA
Deselected, f = f , ZZ
≥
V
– 0.2V
Max
DD
ISB2
–
30
–
30
–
30
–
30
All VIN ≤ VIL or ≥ VIH
VOL
IOL = 8 mA, VDDQ = 3.465V
IOH = –4 mA, VDDQ = 3.135V
–
0.4
–
–
0.4
–
–
0.4
–
–
0.4
V
Output voltage
VOH
2.4
2.4
2.4
2.4
–
1 LBO pin has an internal pull-up and input leakage = 10 µA.
2 I given with no output loading. I increases with faster cycles times and greater output loading.
CC
CC
DC electrical characteristics for 2.5V I/O operation
–166
–150
–133
–100
Parameter
Symbol
|ILO
Test conditions
Min Max Min Max Min Max Min Max Unit
Output leakage
current
OE ≥ VIH, VDD = Max,
VOUT = GND to VDD
|
–1
1
–1
1
–1
1
–1
1
µA
V
VOL
IOL = 2 mA, VDDQ = 2.65V
IOH = –2 mA, VDDQ = 2.35V
–
0.7
–
–
0.7
–
–
0.7
–
–
0.7
–
Output voltage
VOH
1.7
1.7
1.7
1.7
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P. 7 of 14
AS7C33256PFS32A
AS7C33256PFS36A
®
Timing characteristics over operating range
–166
–150
–133
–100
Parameter
Symbol Min Max Min Max Min Max Min Max Unit Notes1
Clock frequency
fMax
tCYC
–
6
166
–
–
150
–
–
133
–
–
100 MHz
Cycle time (pipelined mode)
6.6
10
-
7.5
12
-
10
12
-
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Cycle time (flow-through mode)
tCYCF
10
-
–
–
–
Clock access time (pipelined mode)- 3.3V VDDQ tCD 3.3V
Clock access time (pipelined mode)- 2.5V VDDQ tCD 2.5V
3.5
4.0
9
3.8
4.3
10
3.8
–
4.0
4.5
10
4.0
–
5.0
5.0
12
5.0
–
-
-
-
-
Clock access time (flow-through mode)
Output enable LOW to data valid
Clock HIGH to output Low Z
Data output invalid from clock HIGH
Output enable LOW to output Low Z
Output enable HIGH to output High Z
Clock HIGH to output High Z
Output enable HIGH to invalid output
Clock HIGH pulse width
tCDF
tOE
tLZC
tOH
–
–
–
–
–
3.5
–
–
–
–
0
0
0
0
2,3,4
2
1.5
0
–
1.5
0
–
1.5
0
–
1.5
0
–
tLZOE
tHZOE
tHZC
tOHOE
tCH
–
–
–
–
2,3,4
2,3,4
2,3,4
–
3.5
3.5
–
–
3.8
3.8
–
–
4.0
4.0
–
–
4.5
5.0
–
–
–
–
–
0
0
0
0
2.4
2.4
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
–
2.5
2.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
1.5
1.5
0.5
0.5
0.5
–
2.5
2.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
1.5
1.5
0.5
0.5
0.5
–
3.5
3.5
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
2.0
2.0
2.0
0.5
0.5
0.5
–
5
5
Clock LOW pulse width
tCL
–
–
–
–
Address setup to clock HIGH
Data setup to clock HIGH
tAS
–
–
–
–
6
tDS
–
–
–
–
6
Write setup to clock HIGH
tWS
–
–
–
–
6,7
6,8
6
Chip select setup to clock HIGH
Address hold from clock HIGH
Data hold from clock HIGH
Write hold from clock HIGH
Chip select hold from clock HIGH
ADV setup to clock HIGH
tCSS
–
–
–
–
tAH
–
–
–
–
tDH
–
–
–
–
6
tWH
tCSH
tADVS
–
–
–
–
6,7
6,8
6
–
–
–
–
–
–
–
–
ADSP setup to clock HIGH
tADSPS 1.5
tADSCS 1.5
tADVH 0.5
tADSPH 0.5
tADSCH 0.5
–
–
–
–
6
ADSC setup to clock HIGH
–
–
–
–
6
ADV hold from clock HIGH
ADSP hold from clock HIGH
ADSC hold from clock HIGH
1 See “Notes” on page 12
–
–
–
–
6
–
–
–
–
6
–
–
–
–
6
4/15/02; v.1.9
Alliance Semiconductor
P. 8 of 14
AS7C33256PFS32A
AS7C33256PFS36A
®
Key to switching waveforms
Rising input
Falling input
Undefined/don’t care
Timing waveform of read cycle
t
t
CYC
CL
t
CH
CLK
t
ADSPS
t
ADSPH
ADSP
ADSC
t
ADSCS
t
ADSCH
t
AS
LOAD NEW ADDRESS
A3
t
AH
A1
A2
Address
t
WS
t
WH
GWE, BWE
t
CSS
t
CSH
CE0, CE2
CE1
t
ADVS
t
ADVH
ADV
OE
t
CD
t
HZOE
t
OH
ADV INSERTS WAIT STATES
t
HZC
Q(A1)
Q(A2)
Q(A2Ý01)
Q(A2Ý10)
Q(A2Ý11)
Q(A3)
Q(A3Ý01) Q(A3Ý10)
D
OUT
(pipelined mode)
t
OE
t
LZOE
Q(A1)
Q(A2Ý01)
Q(A2Ý10)
Q(A2Ý11) Q(A3) Q(A3Ý01) Q(A3Ý10) Q(A3Ý11)
D
OUT
(flow-through mode)
t
HZC
Note: Ý = XOR when LBO= HIGH/No Connect; Ý = ADD when LBO = LOW.
BW[a:d] is don’t care.
4/15/02; v.1.9
Alliance Semiconductor
P. 9 of 14
AS7C33256PFS32A
AS7C33256PFS36A
®
Timing waveform of write cycle
t
t
CYC
t
CH
CL
CLK
t
ADSPS
t
ADSPH
ADSP
t
ADSCS
t
ADSCH
ADSC
ADSC LOADS NEW ADDRESS
A3
t
AS
t
AH
A1
A2
Address
t
WS
t
WH
BWE
BW[a:d]
t
CSS
t
CSH
CE0, CE2
CE1
t
ADV SUSPENDS BURST
ADVS
t
ADVH
ADV
OE
t
DS
t
DH
D(A1)
D(A2)
D(A2Ý01)
D(A2Ý01) D(A2Ý10) D(A2Ý11)
D(A3)
D(A3Ý01) D(A3Ý10)
Data In
Note: Ý = XOR when LBO = HIGH/No Connect; Ý = ADD when LBO = LOW.
4/15/02; v.1.9
Alliance Semiconductor
P. 10 of 14
AS7C33256PFS32A
AS7C33256PFS36A
®
Timing waveform of read/write cycle
t
t
CYC
t
CH
CL
CLK
t
ADSPS
t
ADSPH
ADSP
t
AS
t
AH
A2
A3
A1
Address
t
WS
t
WH
GWE
CE0, CE2
CE1
t
ADVS
t
ADVH
ADV
OE
t
DS
t
DH
D(A2)
D
IN
t
t
t
t
LZOE
HZOE
OH
LZC
t
t
OE
CD
Q(A1)
Q(A3)
Q(A3Ý01)
Q(A3Ý10)
Q(A3Ý11)
D
OUT
(pipeline mode)
t
CDF
Q(A3Ý11)
Q(A1)
Q(A3Ý01)
Q(A3Ý10)
D
OUT
(flow-through mode)
Note: Ý = XOR when LBO = HIGH/No Connect; Ý = ADD when LBO = LOW.
4/15/02; v.1.9
Alliance Semiconductor
P. 11 of 14
AS7C33256PFS32A
AS7C33256PFS36A
®
AC test conditions
• Output load: see Figure B, except for t , t
, t
, t , see Figure C.
LZC LZOE HZOE HZC
• Input pulse level: GND to 3V. See Figure A.
Thevenin equivalent:
• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.5V.
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
319Ω / 1667Ω
Z = 50
Ω
50
Ω
0
D
OUT
V = 1.5V
+3.0V
D
L
OUT
90%
10%
90%
10%
5 pF*
for 3.3V I/O;
353Ω / 1538Ω
30 pF*
= V
/2
DDQ
GND
*including scope
and jig capacitance
GND
for 2.5V I/O
Figure A: Input waveform
Figure B: Output load (A)
Figure C: Output load (B)
Notes
1
2
3
4
5
6
For test conditions, see AC Test Conditions, Figures A, B, C.
This parameter measured with output load condition in Figure C.
This parameter is sampled, but not 100% tested.
t
is less than t
; and t
HZC
is less than t at any given temperature and voltage.
LZC
HZOE
LZOE
tCH measured as HIGH above V and tCL measured as LOW below V .
IH IL
This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must meet
the setup and hold times for all rising edges of CLK when chip is enabled.
Write refers to GWE, BWE, BW[a:d].
7
8
Chip select refers to CE0, CE1, CE2.
4/15/02; v.1.9
Alliance Semiconductor
P. 12 of 14
AS7C33256PFS32A
AS7C33256PFS36A
®
Package Dimensions
100-pin Quad Flat Pack (TQFP)
TQFP
c
Min
0.05
Max
0.15
A1 A2
L1
L
Hd
D
A1
A2
b
1.35
1.45
0.22
0.38
b
e
0.09
0.20
c
13.90
19.90
14.10
20.10
D
E
0.65 nominal
e
15.90
21.90
0.45
16.10
22.10
0.75
Hd
He
L
α
He
E
1.00 nominal
L1
0°
7°
α
Dimensions in millimeters
119-ball BGA (ball grid array)
All measurements are in
mm.
Min
Typ
Max
-
1.27
-
A
B
13.90 14.00 14.10
7.62
21.90 22.00 22.10
-
-
B1
C
-
0.60
-
20.32
0.75
-
-
C1
D
0.90
1.70
-
E
-
0.56
0.60
E1
E2
0.50
0.70
4/15/02; v.1.9
Alliance Semiconductor
P. 13 of 14
AS7C33256PFS32A
AS7C33256PFS36A
®
Ordering information
Package
–166 MHz
–150 MHz
–133 MHz
–100 MHz
AS7C33256PFS32A-
166TQC
AS7C33256PFS32A-
150TQC
AS7C33256PFS32A-
133TQC
AS7C33256PFS32A-
100TQC
x32 TQC
x32 TQI
AS7C33256PFS32A-
166TQI
AS7C33256PFS32A-
150TQI
AS7C33256PFS32A-
133TQI
AS7C33256PFS32A-
100TQI
AS7C33256PFS36A-
166TQC
AS7C33256PFS36A-
150TQC
AS7C33256PFS36A-
133TQC
AS7C33256PFS36A-
100TQC
x36 TQC
AS7C33256PFS36A-
166TQI
AS7C33256PFS36A-
150TQI
AS7C33256PFS36A-
133TQI
AS7C33256PFS36A-
100TQI
x36 TQI
AS7C33256PFS32A2-
166BC
AS7C33256PFS32A2-
150BC
AS7C33256PFS32A2-
133BC
AS7C33256PFS32A2-
100BC
x32 BC
AS7C33256PFS32A2-
166BI
AS7C33256PFS32A2-
150BI
AS7C33256PFS32A2-
133BI
AS7C33256PFS32A2-
100BI
x32 BI
AS7C33256PFS36A2-
166BC
AS7C33256PFS36A2-
150BC
AS7C33256PFS36A2-
133BC
AS7C33256PFS36A2-
100BC
x36 BC
AS7C33256PFS36A2-
166BI
AS7C33256PFS36A2-
150BI
AS7C33256PFS36A2-
133BI
AS7C33256PFS36A2-
100BI
x36 BI
AS7C33256PFS32A2-
166TQC
AS7C33256PFS32A2-
150TQC
AS7C33256PFS32A2-
133TQC
AS7C33256PFS32A2-
100TQC
x32 TQC (2 CE)
x32 TQI (2 CE)
x36 TQC (2 CE)
AS7C33256PFS32A2-
166TQI
AS7C33256PFS32A2-
150TQI
AS7C33256PFS32A2-
133TQI
AS7C33256PFS32A2-
100TQI
AS7C33256PFS36A2-
166TQC
AS7C33256PFS36A2-
150TQC
AS7C33256PFS36A2-
133TQC
AS7C33256PFS36A2-
100TQC
AS7C33256PFS36A2-
166TQI
AS7C33256PFS36A2-
150TQI
AS7C33256PFS36A2-
133TQI
AS7C33256PFS36A2-
100TQI
x36 TQI (2 CE)
Part numbering guide
AS7C
33
256
PF
S
32/36
A
blank or 2
–XXX
TQ or B
C/I
1
2
3
4
5
6
7
8
9
10
11
1. Alliance Semiconductor SRAM prefix
2. Operating voltage: 33=3.3V
3. Organization: 256=256K
4. Pipeline-Flowthrough (each device has both options)
5. Deselect: S=Single cycle deselect
6. Organization: 32=x32; 36=x36
7. Production version: A=first production version
8. Blank = the default:3 CE (chip enable), 2 = 2 CE (2 chip enable)
9. Clock speed (MHz)
10. Package type: TQ=TQFP or B=BGA
11. Operating temperature: C=Commercial (
0°
C to 70
°
C); I=Industrial (-40
°
C to 85° C)
4/15/02; v.1.9
Alliance Semiconductor
P. 14 of 14
© Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks
of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data
contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development,
significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide,
any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties
related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in
Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not
convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-
supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes
all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
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