AS7C33512PFS16A-150TQC [ISSI]
Standard SRAM, 512KX16, 10ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100;
| 型号： | AS7C33512PFS16A-150TQC |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Standard SRAM, 512KX16, 10ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100 静态存储器 |
| 文件： | 总13页 (文件大小：268K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 2003
AS7C33512PFS16A
AS7C33512PFS18A
®
3.3V 512K × 16/18 pipelined burst synchronous SRAM
Features
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/ O operation with separate V
• Organization: 524,288 words × 16 or 18 bits
• Fast clock speeds to 166 MHz in LVTTL/ LVCMOS
• Fast clock to data access: 3.5/ 3.8/ 4.0/ 5.0 ns
• Fast OEaccess time: 3.5/ 3.8/ 4.0/ 5.0 ns
• Fully synchronous register-to-register operation
• Single register “flow-through” option
• Single-cycle deselect
DDQ
• 30 mW typical standby power in power down mode
1
• NTD™ pipeline architecture available
(AS7C33512NTD16A/ AS7C33512NTD18A)
• Asynchronous output enable control
• Available in 100-pin TQFP
• Byte write enables
1. NTD™ is a trademark of Alliance Semiconductor Corporation. All
trademarks mentioned in this document are the property of their respec-
tive owners.
Logic block diagram
Pin arrangement for TQFP
LBO
CLK
CLK
CE
CLR
ADV
ADSC
ADSP
Burst logic
512K × 16/ 18
A
NC
NC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
VDDQ
2
Memory
array
2
2
19
NC
3
19 17
19
AddresQs
register
V
D
A[18:0]
VDDQ
4
V
5
SSQ
SSQ
CS
NC
NC
NC
6
DQpa/ NC
DQa
7
CLK
DQb
DQb
8
DQa
9
16/ 18
16/ 18
V
V
10
11
SSQ
SSQ
VDDQ
DQa
DQa
VSS
V
DDQ
GWE
BW
b
D
Q
DQb
DQb 12
DQb 13
FT 14
Byte Write
registers
TQFP 14 × 20mm
BWE
VDD
NC
VDD
ZZ
15
CLK
NC 16
17
D
Q
DQa
V
SS
2
BW
a
Byte Write
DQa
DQa
VDDQ
DQb 18
DQb 19
VDDQ 20
registers
CLK
V
V
21
SSQ
DSQSQb 22
CE0
CE1
CE2
OE
DEnableQ
register
Input
DQa
DQa
NC
Output
DQb 23
registers
registers
DQpb/ NC 24
NC 25
CE
NC
CLK
CLK
CLK
V
V
26
27
SSQ
SSQ
VDDQ
NC
V
DEnableQ
DDQ
NC 28
NC 29
NC 30
Power
down
delay
ZZ
NC
register
NC
CLK
OE
16/ 18
DQ[a,b]
Note: Pins 24 and 74 are NC for x 16.
FT
Selection guide
–166
6
–150
6.6
–133
7.5
133
4
–100
10
Units
ns
Minimum cycle time
Maximum pipelined clock frequency
Maximum pipelined clock access time
Maximum operating current
166
3.5
475
130
30
150
3.8
100
5
MHz
ns
450
110
30
425
100
30
325
90
mA
mA
mA
Maximum standby current
Maximum CMOS standby current (DC)
30
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Alliance Semiconductor
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Copyright © Alliance Semiconductor. All rights reserved.
AS7C33512PFS16A
AS7C33512PFS18A
®
Functional description
The AS7C33512PFS16A and AS7C33512PFS18A are high performance CMOS 8-Mbit synchronous Static Random Access Memory (SRAM)
devices organized as 524,288 words × 16 or 18 bits and incorporate a pipeline for highest frequency on any given technology.
Fast cycle times of 6/ 6.6/ 7.5/ 10 ns with clock access times (t ) of 3.5/ 3.8/ 4.0/ 5.0 ns enable 166, 150, 133 and 100 MHz bus frequencies.
CD
Three chip enable inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC),
or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register.
When ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation the data accessed
by the current address, registered in the address registers by the positive edge of CLK, are carried to the data-out registers and driven on the
output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted but is sampled on all subsequent
clock edges. Address is incremented internally for the next access of the burst when ADV is sampled low and both address strobes are high.
Burst mode is selectable with the LBO input. With LBO unconnected or driven high, burst operations use an interleaved count sequence. With
LBO driven low the device uses a linear count sequence.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 16
or 18 bits regardless of the state of individual BW[a:b] inputs. Alternately, when GWE is high, one or more bytes may be written by asserting
BWE and the appropriate individual byte BWn signal(s).
BWn is ignored on the clock edge that samples ADSP low, but is sampled on all subsequent clock edges. Output buffers are disabled when BWn
is sampled low (regardless of OE). Data is clocked into the data input register when BWn is sampled low. Address is incremented internally to
the next burst address if BWn and ADV are sampled low.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow.
•
•
ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC
WE signals are sampled on the clock edge that samples ADSC low (and ADSP high).
.
• Master chip select CE0 blocks ADSP, but not ADSC
.
The AS7C33512PFS16A and AS7C33512PFS18A operate from a 3.3V supply. I/ Os use a separate power supply that can operate at 2.5V or 3.3V.
These devices are available in a 100-pin 14×20 mm TQFP.
Capacitance
Parameter
Input capacitance
I/ O capacitance
Symbol
Signals
Address and control pins
I/ O pins
Test conditions
IN = 0V
IN = VOUT = 0V
Max
5
Unit
pF
C
V
IN
C
V
7
pF
I/ O
Write enable truth table (per byte)
GWE
BWE
X
BWn
X
WEn
L
T
T
H
L
L
H
H
X
F*
F*
H
L
H
Key: X = don’t care, L = low, H = high, T = true, F = false; * = valid read; n = a,b; WE, WEn = internal write signal
Burst order
Interleaved Burst Order LBO=1
Linear Burst Order LBO=0
A1 A0 A1 A0 A1 A0 A1 A0
A1 A0 A1 A0 A1 A0 A1 A0
Starting Address 0 0
First increment 0 1
Second increment 1 0
Third increment 1 1
0 1
0 0
1 1
1 0
1 0
1 1
0 0
0 1
1 1
1 0
0 1
0 0
Starting Address 0 0
First increment 0 1
Second increment 1 0
Third increment 1 1
01
1 0
1 1
0 0
0 1
1 1
0 0
0 1
1 0
1 0
1 1
0 0
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AS7C33512PFS16A
AS7C33512PFS18A
®
Signal descriptions
Signal
I/ O
Properties
CLOCK
SYNC
Description
CLK
I
I
Clock. All inputs except OE, FT, ZZ, LBO are synchronous to this clock.
Address. Sampled when all chip enables are active and ADSC or ADSP are asserted.
Data. Driven as output when the chip is enabled and OE is active.
A0–A18
DQ[a,b]
I/ O
SYNC
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When
CE0 is inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more
information.
CE0
I
SYNC
Synchronous chip enables. Active high and active low, respectively. Sampled on clock
edges when ADSC is active or when CE0 and ADSP are active.
CE1, CE2
ADSP
I
I
SYNC
SYNC
Address strobe (processor). Asserted low to load a new address or to enter standby
mode.
Address strobe (controller). Asserted low to load a new address or to enter standby
mode.
ADSC
ADV
I
I
I
SYNC
SYNC
SYNC
Burst advance. Asserted low to continue burst read/ write.
Global write enable. Asserted low to write all 16 or 18 bits. When high, BWE and
BW[a,b] control write enable.
GWE
Byte write enable. Asserted low with GWE = high to enable effect of BW[a,b]
inputs.
BWE
BW[a,b]
OE
I
I
I
I
SYNC
SYNC
Write enables. Used to control write of individual bytes when GWE = high and
BWE = low. If any of BW[a,b] is active with GWE = high and BWE = low the cycle
is a write cycle. If all BW[a,b] are inactive, the cycle is a read cycle.
Asynchronous output enable. I/ O pins are driven when OE is active and the chip is
in read mode.
ASYNC
STATIC
Count mode. When driven high, count sequence follows Intel XOR convention.
When driven low, count sequence follows linear convention. This signal is internally
pulled high.
LBO
Flow-through mode.When low, enables single register flow-through mode. Connect
to VDD if unused or for pipelined operation.
FT
I
I
STATIC
ASYNC
Snooze. Places device in low power mode; data is retained. Connect to GND if
unused.
ZZ
Absolute maximum ratings
Parameter
Symbol
Min
–0.5
–0.5
–0.5
–
Max
+4.6
Unit
V
Power supply voltage relative to GND
Input voltage relative to GND (input pins)
Input voltage relative to GND (I/ O pins)
Power dissipation
VDD, VDDQ
V
VDD + 0.5
VDDQ + 0.5
1.8
V
IN
V
V
IN
PD
W
DC output current
IOUT
Tstg
–
50
mA
° C
° C
Storage temperature (plastic)
Temperature under bias
–65
–65
+150
Tbias
+135
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional oper-
ation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions may affect reliability.
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AS7C33512PFS16A
AS7C33512PFS18A
®
Synchronous truth table
Address
accessed
1
CE0
H
L
CE1
X
L
CE2 ADSP ADSC ADV
WEn
X
X
X
X
X
X
X
F
OE
X
X
X
X
X
L
CLK
Operation
Deselect
DQ
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z2
Hi−Z
Hi−Z2
Hi−Z
Q
X
X
X
H
H
L
X
L
L
X
L
X
X
X
X
X
X
X
X
X
L
NA
NA
L to H
L to H
L to H
L to H
L to H
Lto H
Lto H
Lto H
Lto H
Lto H
L to H
L to H
L to H
Lto H
L to H
L to H
L to H
Lto H
L to H
L to H
L to H
L to H
Deselect
L
L
H
L
NA
Deselect
L
X
X
H
H
H
H
X
X
X
X
X
X
X
X
H
X
X
X
X
X
L
NA
Deselect
L
H
L
NA
Deselect
L
X
X
L
External
External
External
External
Next
Begin read
Begin read
Begin read
Begin read
Cont. read
Cont. read
Suspend read
Suspend read
Cont. read
Cont. read
Suspend read
Suspend read
Begin write
Cont. write
Cont. write
Suspend write
Suspend write
L
L
L
H
L
L
L
H
H
H
H
H
H
X
X
X
X
H
H
X
H
X
L
L
L
F
H
L
X
X
X
X
H
H
H
H
L
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
H
H
L
F
L
F
H
L
Next
Hi−Z
Q
H
H
L
F
Current
Current
Next
F
H
L
Hi−Z
Q
F
L
F
H
L
Next
Hi−Z
Q
H
H
X
L
F
Current
Current
External
Next
F
H
X
X
X
X
X
Hi−Z
D3
T
T
T
T
T
X
H
X
H
X
X
X
X
H
H
H
H
D
L
Next
D
H
H
Current
Current
D
D
Key: X = don’t care, L = low, H = high.
1
2
3
See “Write enable truth table” on page 2 for more information.
Q in flow-through mode
For WRITE operation following a READ, OE must be high before the input data set up time and held high throughout the input hold time.
Recommended operating conditions
Parameter
Symbol
Min
3.135
0.0
Nominal
Max
3.465
0.0
Unit
VDD
3.3
0.0
3.3
0.0
2.5
0.0
–
Supply voltage
V
V
SS
VDDQ
3.135
0.0
3.465
0.0
3.3V I/ O supply
voltage
V
V
V
V
SSQ
VDDQ
2.35
0.0
2.9
2.5V I/ O supply
voltage
V
0.0
SSQ
V
2.0
–0.52
VDD + 0.3
0.8
Address and
control pins
IH
V
–
IL
Input voltages1
V
2.0
–
VDDQ + 0.3
0.8
IH
I/ O pins
V
V
–0.52
0
–
IL
Ambient operating temperature
TA
–
70
° C
1 Input voltage ranges apply to 3.3V I/ O operation. For 2.5V I/ O operation, contact factory for input specifications.
2 V min = –2.0V for pulse width less than 0.2 × t
IL
.
RC
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AS7C33512PFS16A
AS7C33512PFS18A
®
TQFP thermal resistance
Description
Conditions
Symbol
Typical
40
Units
° C/ W
° C/ W
1-layer
4-layer
θ
Thermal resistance
JA
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/ JESD51
(junction to ambient)1
θ
22
JA
JC
Thermal resistance
θ
8
° C/ W
(junction to top of case)1
1 This parameter is sampled.
DC electrical characteristics for 3.3V I/ O operation
–166
–150
–133
–100
Parameter
Symbol
Test conditions
Min Max Min Max Min Max Min Max Unit
Input leakage
current1
| ILI|
VDD = Max, VIN = GND to VDD
–
–
–
2
2
–
–
–
2
2
–
–
–
2
2
–
–
–
2
2
µA
µA
Output leakage
current
OE ≥ V , VDD = Max,
IH
| ILO
|
VOUT = GND to VDD
2
Operating power
supply current
ICC
CE0 = V , CE1 = V , CE2 = V ,
IL
IH
IL
475
450
425
325 mA
f = fMax, IOUT = 0 mA
(Pipelined)
2
ICC
Operating power
supply current
CE0 = V , CE1 = V , CE2 = V ,
IL
IH
IL
–
325
–
325
–
300
–
300 mA
90
(Flow-
f = fMax, IOUT = 0 mA
Through)
ISB
Deselected, f = fMax, ZZ ≤ V
–
–
130
30
–
–
110
30
–
–
100
30
–
–
IL
Deselected, f = 0, ZZ ≤ 0.2V
all V ≤ 0.2V or ≥ VDD – 0.2V
Standby power
supply current
ISB1
30
mA
IN
Deselected, f = f , ZZ
≥
V
– 0.2V
Max
DD
ISB2
–
30
–
30
–
30
–
30
All V ≤ V or ≥ V
IN
IL
IH
V
IOL = 8 mA, VDDQ = 3.465V
IOH = –4 mA, VDDQ = 3.135V
–
0.4
–
–
0.4
–
–
0.4
–
–
0.4
V
OL
Output voltage
V
2.4
2.4
2.4
2.4
–
OH
1 LBO pin has an internal pull-up and input leakage = ±10 µA.
2 I given with no output loading. I increases with faster cycle times and greater output loading.
CC CC
DC electrical characteristics for 2.5V I/ O operation
–166
–150
–133
–100
Parameter
Symbol
| ILO
Test conditions
OE ≥ V , VDD = Max,
Min Max Min Max Min Max Min Max Unit
Output leakage
current
IH
|
–1
1
–1
1
–1
1
–1
1
µA
V
VOUT = GND to VDD
V
IOL = 2 mA, VDDQ = 2.65V
IOH = –2 mA, VDDQ = 2.35V
IOL = 1mA, VDDQ = 2.65V
IOH = –1 mA, VDDQ = 2.35V
–
0.7
–
–
0.7
–
–
0.7
–
–
0.7
–
OL
V
1.7
–
1.7
–
1.7
–
1.7
–
OH
Output voltage
V
0.4
–
0.4
–
0.4
–
0.4
–
OL
V
V
2.0
2.0
2.0
2.0
OH
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AS7C33512PFS16A
AS7C33512PFS18A
®
Timing characteristics for 3.3 V I/ O operation
–166
–150
–133
–100
Parameter
Symbol Min Max Min Max Min Max Min Max Unit Notes1
Clock frequency
fMax
tCYC
tCYCF
tCD
–
6
166
–
–
6.6
10
-
150
–
–
7.5
12
-
133
–
–
10
12
-
100 MHz
Cycle time (pipelined mode)
–
–
ns
ns
Cycle time (flow-through mode)
Clock access time (pipelined mode)
Clock access time (flow-through mode)
Output enable low to data valid
10
-
–
–
–
3.5
9
3.8
10
3.8
–
4.0
10
4.0
–
5.0 ns
12 ns
5.0 ns
tCDF
tOE
tLZC
tOH
–
–
–
–
–
3.5
–
–
–
–
Clock high to output low Z
0
0
0
0
–
–
ns
ns
2,3,4
2
Data output invalid from clock high (Pipelined Mode)
1.5
–
1.5
–
1.5
–
1.5
tOHF
Data Output invalid from clock high (Flow-through
Mode)
3.0
–
3.0
–
3.0
–
3.0
ns
2
Output enable low to output low Z
Output enable high to output high Z
Clock high to output high Z
Output enable high to invalid output
Clock high pulse width
tLZOE
tHZOE
tHZC
tOHOE
tCH
0
–
3.5
3.5
–
0
–
3.8
3.8
–
0
–
4.0
4.0
–
0
–
ns
2,3,4
2,3,4
2,3,4
–
–
–
–
4.5 ns
5.0 ns
–
–
–
–
0
0
0
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.4
2.3
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
1.5
–
2.5
2.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
1.5
1.5
0.5
0.5
0.5
–
2.5
2.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
1.5
1.5
0.5
0.5
0.5
–
3.5
3.5
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
2.0
2.0
2.0
0.5
0.5
0.5
5
5
Clock low pulse width
tCL
–
–
–
Address setup to clock high
Data setup to clock high
tAS
–
–
–
6
tDS
–
–
–
6
Write setup to clock high
Chip select setup to clock high
Address hold from clock high
Data hold from clock high
Write hold from clock high
Chip select hold from clock high
ADV setup to clock high
tWS
–
–
–
6,7
6,8
6
tCSS
–
–
–
tAH
–
–
–
tDH
–
–
–
6
tWH
tCSH
tADVS
tADSPS
–
–
–
6,7
6,8
6
–
–
–
–
–
–
ADSP setup to clock high
–
–
–
6
ADSC setup to clock high
tADSCS 1.5
–
–
–
6
ADV hold from clock high
ADSP hold from clock high
ADSC hold from clock high
1 See “Notes on page 11.
tADVH
0.5
0.5
–
–
–
6
tADSPH
–
–
–
6
tADSCH 0.5
–
–
–
6
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Alliance Semiconductor
6 of 13
AS7C33512PFS16A
AS7C33512PFS18A
®
.
Timing characteristics for 2.5 V I/ O operation
–166
–150
–133
–100
Parameter
Symbol Min Max Min Max Min Max Min Max Unit Notes1
Clock frequency
fMax
tCYC
tCYCF
tCD
–
6
166
–
–
6.6
10
-
150
–
–
7.5
12
-
133
–
–
10
12
-
100 MHz
Cycle time (pipelined mode)
–
–
ns
ns
Cycle time (flow-through mode)
Clock access time (pipelined mode)
Clock access time (flow-through mode)
Output enable low to data valid
10
-
–
–
–
3.8
9
4.0
10
3.8
–
4.2
10
4.0
–
5.0 ns
12 ns
5.0 ns
tCDF
tOE
tLZC
tOH
–
–
–
–
–
3.5
–
–
–
–
Clock high to output low Z
0
0
0
0
–
–
ns
ns
2,3,4
2
Data output invalid from clock high (Pipelined Mode)
1.5
–
1.5
–
1.5
–
1.5
tOHF
Data Output invalid from clock high (Flow-through
Mode)
3.0
–
3.0
–
3.0
–
3.0
ns
ns
2
Output enable low to output low Z
Output enable high to output high Z
Clock high to output high Z
Output enable high to invalid output
Clock high pulse width
tLZOE
tHZOE
tHZC
tOHOE
tCH
0
–
3.5
3.5
–
0
–
3.8
3.8
–
0
–
4.0
4.0
–
0
–
2,3,4
2,3,4
2,3,4
–
–
–
–
4.5 ns
5.0 ns
–
–
–
–
0
0
0
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.4
2.3
1.7
1.7
1.7
1.7
0.7
0.7
0.7
0.7
1.7
1.7
–
2.5
2.5
1.7
1.7
1.7
1.7
0.7
0.7
0.7
0.7
1.7
1.7
1.7
0.7
0.7
0.7
–
2.5
2.5
1.7
1.7
1.7
1.7
0.7
0.7
0.7
0.7
1.7
1.7
1.7
0.7
0.7
0.7
–
3.5
3.5
2.0
2.0
2.0
2.0
0.7
0.7
0.7
0.7
2.0
2.0
2.0
0.7
0.7
0.7
5
5
Clock low pulse width
tCL
–
–
–
Address setup to clock high
Data setup to clock high
tAS
–
–
–
6
tDS
–
–
–
6
Write setup to clock high
Chip select setup to clock high
Address hold from clock high
Data hold from clock high
Write hold from clock high
Chip select hold from clock high
ADV setup to clock high
tWS
–
–
–
6,7
6,8
6
tCSS
–
–
–
tAH
–
–
–
tDH
–
–
–
6
tWH
tCSH
tADVS
tADSPS
–
–
–
6,7
6,8
6
–
–
–
–
–
–
ADSP setup to clock high
–
–
–
6
ADSC setup to clock high
tADSCS 1.7
–
–
–
6
ADV hold from clock high
ADSP hold from clock high
ADSC hold from clock high
1 See “Notes on page 11.
tADVH
0.7
0.7
–
–
–
6
tADSPH
–
–
–
6
tADSCH 0.7
–
–
–
6
5/ 9/ 03, v.1.8.1
Alliance Semiconductor
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AS7C33512PFS16A
AS7C33512PFS18A
®
Key to switching waveforms
Rising input
Falling input
Undefined/ don’t care
Timing waveform of read cycle
t
t
CYC
CL
t
CH
CLK
t
ADSPS
t
ADSPH
ADSP
ADSC
t
ADSCS
t
ADSCH
t
AS
LOAD NEW ADDRESS
A3
t
AH
A1
A2
Address
t
WS
t
WH
GWE, BWE
t
CSS
t
CSH
CE0, CE2
CE1
t
ADVS
t
ADVH
ADV
OE
t
CD
t
HZOE
t
OH
ADV INSERTS WAIT STATES
t
HZC
Q(A1)
Q(A2)
Q(A2Ý01)
Q(A2Ý10)
Q(A2Ý11)
Q(A3)
Q(A3Ý01) Q(A3Ý10)
D
OUT
(pipelined mode)
t
OE
t
LZOE
Q(A1)
Q(A2Ý01)
Q(A2Ý10)
Q(A2Ý11) Q(A3) Q(A3Ý01) Q(A3Ý10) Q(A3Ý11)
D
OUT
(flow-through mode)
t
HZC
Note: Ý = XOR when LBO = high/ no connect; Ý = ADD when LBO = low.
BW[a:b] is don’t care.
5/ 9/ 03, v.1.8.1
Alliance Semiconductor
8 of 13
AS7C33512PFS16A
AS7C33512PFS18A
®
Timing waveform of write cycle
t
t
CYC
t
CH
CL
CLK
t
ADSPS
t
ADSPH
ADSP
t
ADSCS
t
ADSCH
ADSC
ADSC LOADS NEW ADDRESS
A3
t
AS
t
AH
A1
A2
Address
t
WS
t
WH
BWE
BWa,b
t
CSS
t
CSH
CE0, CE2
CE1
t
ADV SUSPENDS BURST
ADVS
t
ADVH
ADV
OE
t
DS
t
DH
D(A1)
D(A2)
D(A2Ý01)
D(A2Ý01)
D(A2Ý10) D(A2Ý11)
D(A3)
D(A3Ý01)
D(A3Ý10)
Data In
Note: Ý = XOR when LBO = high/ no connect; Ý = ADD when LBO = low.
5/ 9/ 03, v.1.8.1
Alliance Semiconductor
9 of 13
AS7C33512PFS16A
AS7C33512PFS18A
®
Timing waveform of read/ write cycle
t
t
CYC
t
CH
CL
CLK
t
ADSPS
t
ADSPH
ADSP
t
AS
t
AH
A2
A3
A1
Address
t
WS
t
WH
.
.
GWE
CE0, CE2
CE1
t
ADVS
t
ADVH
ADV
OE
t
DS
t
DH
D(A2)
D
IN
t
t
t
t
LZOE
HZOE
OH
LZC
t
t
OE
CD
Q(A1)
Q(A3)
Q(A3Ý01)
Q(A3Ý10)
Q(A3Ý11)
D
OUT
(pipelined mode)
t
CDF
Q(A3Ý11)
Q(A1)
Q(A3Ý01)
Q(A3Ý10)
D
OUT
(flow-through mode)
Note: Ý = XOR when LBO = high/ no connect; Ý = ADD when LBO = low.
5/ 9/ 03, v.1.8.1
Alliance Semiconductor
10 of 13
AS7C33512PFS16A
AS7C33512PFS18A
®
AC test conditions
• Output load: see Figure B, except for t , t
, t
, t , see Figure C.
LZC LZOE HZOE HZC
• Input pulse level: GND to 3V. See Figure A.
Thevenin equivalent:
• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.5V.
+3.3V for 3.3V I/ O;
/ +2.5V for 2.5V I/ O
319Ω / 1667Ω
Z = 50
Ω
50
Ω
0
D
OUT
V = 1.5V
+3.0V
D
L
OUT
5 pF*
90%
10%
90%
10%
for 3.3V I/ O;
353Ω / 1538Ω
30 pF*
= V / 2
DDQ
GND
*including scope
and jig capacitance
GND
for 2.5V I/ O
Figure C: Output load (B)
Figure A: Input waveform
Figure B: Output load (A)
Notes:
1) For test conditions, see “AC Test Conditions”, Figures A, B, and C
2) This parameter measured with output load condition in Figure C.
3) This parameter is sampled but not 100% tested.
4) t
is less than t
, and t
is less than t
at any given temperature and voltage.
HZOE
LZOE
HZC
LZC
5) t is measured high above V , and t is measured as low below V
CH IH CL IL
6) This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must meet
the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled.
7) Write refers to GWE, BWE, and BW[a,b].
8) Chip select refers to CE0, CE, and CE2.
5/ 9/ 03, v.1.8.1
Alliance Semiconductor
11 of 13
AS7C33512PFS16A
AS7C33512PFS18A
®
Package dimensions: 100-pin quad flat pack (TQFP)
Hd
TQFP
D
Min
0.05
Max
0.15
A1
A2
b
b
e
1.35
1.45
α
0.22
0.38
0.09
0.20
c
13.80
19.80
14.20
20.20
D
He
E
E
0.65 nominal
e
A2
c
15.80
21.80
0.45
16.20
22.20
0.75
Hd
He
L
L1
L
A1
1.00 nominal
L1
0°
7°
α
Dimensions in millimeters
5/ 9/ 03, v.1.8.1
Alliance Semiconductor
12 of 13
AS7C33512PFS16A
AS7C33512PFS18A
®
Ordering information
Package
–166 MHz
–150 MHz
–133 MHz
–100 MHz
AS7C33512PFS16A-
166TQC
AS7C33512PFS16A-
150TQC
AS7C33512PFS16A-
133TQC
AS7C33512PFS16A-
100TQC
x16 TQFP
x16 TQFP
x18 TQFP
x18 TQFP
AS7C33512PFS16A-
166TQI
AS7C33512PFS16A-
150TQI
AS7C33512PFS16A-
133TQI
AS7C33512PFS16A-
100TQI
AS7C33512PFS18A-
166TQC
AS7C33512PFS18A-
150TQC
AS7C33512PFS18A-
133TQC
AS7C33512PFS18A-
100TQC
AS7C33512PFS18A-
166TQI
AS7C33512PFS18A-
150TQI
AS7C33512PFS18A-
133TQI
AS7C33512PFS18A-
100TQI
Part numbering guide
AS7C
33
512
PF
S
16 or 18
A
–XXX
TQ
C/ I
1
2
3
4
5
6
7
8
9
10
1. Alliance Semiconductor SRAM prefix
2. Operating voltage: 33 = 3.3V
3. Organization: 512
= 512K
4. Pipelined/ flow-through mode (each device works in both modes)
5. Deselect: S = single cycle deselect
6. Organization: 16 = x 16, 18 = x 18
7. Production version: A = first production version
8. Clock speed (MHz)
9. Package type: TQ = TQFP
10. Operating temperature: C = commercial (0° C to 70° C); I = industrial (-40° C to 85° C)
5/ 9/ 03, v.1.8.1
Alliance Semiconductor
13 of 13
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contained herein represents Alliance's best data and/ or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development,
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