IC24C64B-3Z [ISSI]
EEPROM, 8KX8, Serial, CMOS, PDSO8, TSSOP-8;
| 型号： | IC24C64B-3Z |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | EEPROM, 8KX8, Serial, CMOS, PDSO8, TSSOP-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总12页 (文件大小：54K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
IS24C32A
IS24C64A/B
ISSI
65,536 bit/32,768 bit
2-WIRE SERIAL CMOS EEPROM
ADVANCEDINFORMATION
JANUARY2004
FEATURES
DESCRIPTION
The IS24C32A and IS24C64A/B are electrically
• Two-Wire Serial Interface
erasable PROM devices that use the standard 2-
wire interface for communications. The IS24C32A
and IS24C64A/B contain a memory array of 32K-
bits (4K x 8) and 64K-bits (8K x 8), respectively.
Each device is organized into 32 byte pages for
page write mode.
–Bi-directional data transfer protocol
• 400 KHz (I2C Protocol) Compatibility
• Low Power CMOS Technology
–Standby Current less than 6 µA (5.0V)
–Read Current less than 2 mA (5.0V)
–Write Current less than 3 mA (5.0V)
• Flexible Voltage Operation
This EEPROM is offered in wide operating volt-
ages of 1.8V to 5.5V (IS24Cxx-2) and 2.5V to 5.5V
(IS24Cxx-3) to be compatible with most application
voltages. ISSI designed this device family to be a
practical, low-power 2-wire EEPROM solution.
The devices are available in 8-pin PDIP, 8-pin
SOIC and 8-pin TSSOP packages.
–Vcc = 1.8V to 5.5V for –2 version
–Vcc = 2.5V to 5.5V for –3 version
• Hardware Data Protection
–IS24C32A/64A: WP protects entire array
–IS24C64B: WP protects top quarter of array
• Sequential Read Feature
The IS24C32A/64A/64B maintains compatibility
with the popular 2-wire bus protocol, so it is easy
to use in applications implementing this bus type.
The simple bus consists of the Serial Clock wire
(SCL) and the Serial Data wire (SDA). Using the
bus, a Master device such as a microcontroller is
usually connected to one or more Slave devices
such as this device. The bit stream over the SDA
line includes a series of bytes, which identifies a
particular Slave device, an instruction, an address
within that Slave device, and a series of data, if
appropriate. The IS24C32A/64A/64B has a Write
Protect pin (WP) to allow blocking of any write
instruction transmitted over the bus.
• Filtered Inputs for Noise Suppression
• 8-pin PDIP, 8-pin SOIC and 8-pin TSSOP
packages
• Self time write cycle with auto clear
5 ms @ 2.5V
• Organization:
–IS24C32A: 4Kx8 (128 pages of 32 bytes)
–IS24C64A/B: 8Kx8 (256 pages of 32 bytes)
• 32 Byte Page Write Buffer
• High Reliability
–Endurance: 1,000,000 Cycles
–Data Retention: 100 Years
• Commercial and Industrial temperature ranges
Copyright © 2004 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCEDINFORMATION Rev. 00A
1
01/26/04
IS24C32A
®
IS24C64A/B
ISSI
FUNCTIONAL BLOCK DIAGRAM
HIGH VOLTAGE
8
Vcc
GENERATOR,
TIMING & CONTROL
5
6
7
SDA
SCL
WP
CONTROL
LOGIC
EEPROM
ARRAY
SLAVE ADDRESS
REGISTER &
COMPARATOR
1
2
3
WORD ADDRESS
COUNTER
A0
A1
A2
Y
DECODER
ACK
Clock
DI/O
DATA
REGISTER
4
GND
>
nMOS
PIN DESCRIPTIONS
PIN CONFIGURATION
8-Pin DIP, SOIC, and TSSOP
A0-A2
SDA
SCL
WP
Address Inputs
Serial Address/Data I/O
A0
A1
1
2
3
4
8
7
6
5
VCC
WP
Serial Clock Input
Write Protect Input
Power Supply
Ground
Vcc
A2
SCL
SDA
GND
GND
SCL
This input clock pin is used to synchronize the data
transfer to and from the device.
withthe24C16.Whenpinsarehardwired,asmanyaseight
32K/64K devices may be addressed on a single bus
system.Whenthepinsarenothardwired,thedefaultvalues
of A0, A1, and A2 are zero.
SDA
The SDA is a Bi-directional pin used to transfer addresses
anddataintoandoutofthedevice. TheSDApinisanopen
drain output and can be wire-Ored with other open drain
or open collector outputs. The SDA bus requires a pullup
resistor to Vcc.
WP
WPistheWriteProtectpin. WithIS24C32A/64A, iftheWP
pinistiedtoVcc, theentirearraybecomesWriteProtected
(Read only). With IS24C64B, if WP is tied to Vcc, the top
quarterofthearray(1800h-1FFFh)becomesWriteProtected.
When WP is tied to GND or left floating, normal read/write
operations are allowed to the device.
A0, A1, A2
The A0, A1 and A2 are the device address inputs that are
hardwired or left not connected for hardware compatibility
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCEDINFORMATION Rev. 00A
01/26/04
IS24C32A
®
IS24C64A/B
ISSI
DEVICE OPERATION
Stop Condition
IS24C32A/64A/64B features serial communication and
supports a bi-directional 2-wire bus transmission protocol.
The Stop condition is defined as a Low to High transition of
SDAwhenSCLisHigh. AlloperationsmustendwithaStop
condition.
2-WIRE BUS
Acknowledge (ACK)
Thetwo-wirebusisdefinedasaSerialDataline(SDA),and
a Serial Clock line (SCL). The protocol defines any device
that sends data onto the SDA bus as a transmitter, and the
receiving devices as a receiver. The bus is controlled by a
Master device that generates the SCL, controls the bus
access, andgeneratestheStopandStartconditions. The
IS24C32A/64A/64B is the Slave device on the bus.
After a successful data transfer, each receiving device is
required to generate an ACK. The Acknowledging device
pulls down the SDA line.
Reset
The IS24C32A/64A/64B contains a reset function in case
the 2-wire bus transmission is accidentally interrupted
(eg. a power loss), or needs to be terminated mid-stream.
The reset is caused when the Master device creates a
Start condition. To do this, it may be necessary for the
Master device to monitor the SDA line, which may cycle
the SCL up to nine times. (For each clock signal
transition to High, the Master checks for a High level on
SDA.)
The Bus Protocol:
– Data transfer may be initiated only when the bus is not
busy
– During a data transfer, the data line must remain stable
whenevertheclocklineishigh. Anychangesinthedata
line while the clock line is high will be interpreted as a
Start or Stop condition.
Standby Mode
The state of the data line represents valid data after a Start
condition.Thedatalinemustbestableforthedurationofthe
High period of the clock signal. The data on the SDA line
may be changed during the Low period of the clock signal.
Thereisoneclockpulseperbitofdata. Eachdatatransfer
isinitiatedwithaStartconditionandterminatedwithaStop
condition.
Power consumption is reduced in standby mode. The
IS24C32A/64A/64Bwillenterstandbymode: a)AtPower-
up, and remain in it until SCL or SDA toggles; b) Following
the Stop signal if a no write operation is initiated; or c)
Followinganyinternalwriteoperation.
Start Condition
The Start condition precedes all commands to the device
andisdefinedasaHightoLowtransitionofSDAwhenSCL
isHigh.TheEEPROMmonitorstheSDAandSCLlinesand
will not respond until the Start condition is met.
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCEDINFORMATION Rev. 00A
3
01/26/04
IS24C32A
®
IS24C64A/B
ISSI
WRITE OPERATION
Byte Write
DEVICE ADDRESSING
The Master begins a transmission by sending a Start
condition. The Master then sends the address of the
particular Slave devices it is requesting. The Slave
(Fig. 5) address is 8 bits.
In the Byte Write mode, the Master device sends the Start
condition and the Slave address information (with the R/W
settoZero)totheSlavedevice. AftertheSlavegenerates
an ACK, the Master sends the two byte address that is to
be written into the address pointer of the IS24C32A/64A/
64B. After receiving another ACK from the Slave, the
Master device transmits the data byte to be written into the
address memory location. The IS24C32A/64A/64B
acknowledges once more and the Master generates the
Stop condition, at which time the device begins its internal
programmingcycle. Whilethisinternalcycleisinprogress,
the device will not respond to any request from the Master
device.
The four most significant bits of the address are fixed as
1010 for the IS2432A/64A/64B.
ThenextthreebitsoftheSlaveaddressareA0,A1,andA2,
andareusedincomparisonwiththehard-wiredinputvalues
ontheA0,A1,andA2pins. UptoeightIS24C32A/64A/64B
units may share the 2-wire bus.
The last bit of the Slave address specifies whether a Read
or Write operation is to be performed. When this bit is set
to1,aReadoperationisselected,andwhensetto0,aWrite
operation is selected.
Page Write
After the Master transmits the Start condition and Slave
address byte (Fig. 5), the appropriate 2-wire Slave
(eg.IS24C64A)willrespondwithACKontheSDAline. The
Slave will pull down the SDA on the ninth clock cycle,
signalingthatitreceivedtheeightbitsofdata.Theselected
EEPROM then prepares for a Read or Write operation by
monitoring the bus.
The IS24C32A/64A/64B is capable of 32-byte Page-Write
operation.APage-Writeisinitiatedinthesamemannerasa
ByteWrite,butinsteadofterminatingtheinternalWritecycle
afterthefirstdatawordistransferred,theMasterdevicecan
transmit up to 31 more bytes. After the receipt of each data
word, the EEPROM responds immediately with an ACK on
SDAline,andthefivelowerorderdatawordaddressbitsare
internally incremented by one, while the higher order bits of
the data word address remain constant. If a byte address is
incremented from the last byte of a page, it returns to the
first byte of that page. If the Master device should transmit
more than 32 bytes prior to issuing the Stop condition, the
addresscounterwill“rollover,”andthepreviouslywrittendata
will be overwritten. Once all 32 bytes are received and the
Stop condition has been sent by the Master, the internal
programming cycle begins. At this point, all received data is
written to the IS24C32A/64A/64B inasingle Writecycle. All
inputs are disabled until completion of the internal Write
cycle.
Acknowledge (ACK) Polling
The disabling of the inputs can be used to take advantage
of the typical Write cycle time. Once the Stop condition is
issued to indicate the end of the host's Write operation, the
IS24C32A/64A/64B initiates the internal Write cycle. ACK
polling can be initiated immediately. This involves issuing
theStartconditionfollowedbytheSlaveaddressforaWrite
operation. If the EEPROM is still busy with the Write
operation, no ACK will be returned. If the IS24C32A/64A/
64B has completed the Write operation, an ACK will be
returnedandthehostcanthenproceedwiththenextRead
orWriteoperation.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCEDINFORMATION Rev. 00A
01/26/04
IS24C32A
®
IS24C64A/B
ISSI
READ OPERATION
Random Address Read
Read operations are initiated in the same manner as Write
operations, except that the (R/W) bit of the Slave address
issetto“1”. TherearethreeReadoperationoptions:current
addressread, randomaddressreadandsequentialread.
Selective Read operations allow the Master device to
select at random any memory location for a Read
operation. The Master device first performs a 'dummy'
Write operation by sending the Start condition, Slave
address and byte address of the location it wishes to read.
After the IS24C32A/64A/64B acknowledges the byte
address,theMasterdeviceresendstheStartconditionand
the Slave address, this time with the R/W bit set to
one. TheEEPROMthenrespondswithitsACKandsends
the data requested. The Master device does not send an
ACKbutwillgenerateaStopcondition. (RefertoFigure9.
RandomAddressReadDiagram.)
Current Address Read
TheIS24C32A/64A/64Bcontainsaninternaladdresscounter
which maintains the address of the last byte accessed,
incrementedbyone. Forexample,ifthepreviousoperation
iseitheraReadorWriteoperationaddressedtotheaddress
locationn, theinternaladdresscounterwouldincrementto
address location n+1. When the EEPROM receives the
Slave Addressing Byte with a Read operation (R/W bit set
to“1”),itwillrespondanACKandtransmitthe8-bitdatabyte
stored at address location n+1. The Master should not
acknowledge the transfer but should generate a Stop
condition so the IS24C32A/64A/64B discontinues
transmission. If 'n' is the last byte of the memory, then the
datafromlocation'0'willbetransmitted. (RefertoFigure8.
CurrentAddressReadDiagram.)
Sequential Read
Sequential Reads can be initiated as either a Current
Address Read or Random Address Read. After the
IS24C32A/64A/64Bsendsinitialbytesequence,theMaster
device now responds with an ACK indicating it requires
additionaldatafromtheIS24C32A/64A/64B.TheEEPROM
continues to output data for each ACK received. The
MasterdeviceterminatesthesequentialReadoperationby
pulling SDA High (no ACK) indicating the last data word to
be read, followed by a Stop condition.
Thedataoutputissequential, withthedatafromaddressn
followed by the data from address n+1, n+2 ... etc. The
addresscounterincrementsbyoneautomatically,allowing
the entire memory contents to be serially read during
sequential Read operation. When the memory address
boundary of 8191 for IS24C64A/B or 4095 for IS24C32A
(dependingonthedevice)isreached,theaddresscounter
“rollsover”toaddress0,andthedevicecontinuestooutput
data. (Refer to Figure 10. Sequential Read Diagram).
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCEDINFORMATION Rev. 00A
5
01/26/04
IS24C32A
®
IS24C64A/B
ISSI
Figure 1. Typical System Bus Configuration
Vcc
SDA
SCL
Master
Transmitter/
Receiver
IS24C32A/64A/64B
Figure 2. Output Acknowledge
SCL from
Master
1
8
9
Data Output
from
Transmitter
t
AA
tAA
Data Output
from
ACK
Receiver
Figure 3. START and STOP Conditions
SCL
SDA
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCEDINFORMATION Rev. 00A
01/26/04
IS24C32A
®
IS24C64A/B
ISSI
Figure 4. Data Validity Protocol
Data Change
SCL
SDA
Data Stable
Data Stable
Figure 5. Slave Address
BIT
7
6
5
4
3
2
1
0
1
0
1
0
A2 A1 A0
R/W
Figure 6. Byte Write
S
W
R
I
T
E
S
T
O
P
T
A
R
T
Device
Address
Data
Word Address
Word Address
SDA
Bus
Activity
A
C
K
A
C
K
A
C
K
A
C
K
#
* * *
M
S
B
L
S
B
M
S
B
* = Don't care bits
# = Don't care bit for 24C32A
R/W
Figure 7. Page Write
S
T
A
R
T
W
R
I
S
T
Device
Address
O
T
E
Data (n)
Data (n+1)
Data (n+31)
Word Address (n) Word Address (n)
A
P
SDA
Bus
Activity
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
C
K
#
* * *
M
S
B
L
S
B
* = Don't care bits
# = Don't care bit for 24C32A
R/W
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCEDINFORMATION Rev. 00A
7
01/26/04
IS24C32A
®
IS24C64A/B
ISSI
Figure 8. Current Address Read
S
T
A
R
T
R
E
A
D
S
T
O
P
Device
Address
Data
SDA
Bus
Activity
A
C
K
M
S
B
L
S
B
N
O
A
C
K
R/W
Figure 9. Random Address Read
S
T
A
R
T
W
R
I
T
E
S
T
R
E
A
D
S
T
A
Device
Address
Device
Address
Word
Address (n)
Word
Address (n)
O
R
T
Data n
P
SDA
Bus
Activity
A
C
K
A
C
K
A
A
C
K
C
#
* * *
K
M
S
B
L
S
B
N
O
A
C
K
* = Don't care bits
# = Don't care bit for 24C32A
R/W
DUMMY WRITE
Figure 10. Sequential Read
R
E
A
D
S
T
O
P
Device
Address
Data Byte n
Data Byte n+1
Data Byte n+2
Data Byte n+X
SDA
Bus
Activity
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
R/W
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCEDINFORMATION Rev. 00A
01/26/04
IS24C32A
®
IS24C64A/B
ISSI
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
–0.5 to +6.25
–0.5 to Vcc + 0.5
–55 to +125
–65 to +150
5
Unit
V
VS
SupplyVoltage
VP
Voltage on Any Pin
TemperatureUnderBias
StorageTemperature
OutputCurrent
V
TBIAS
TSTG
IOUT
°C
°C
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extendedperiodsmayaffectreliability.
OPERATING RANGE (IS24C64A/B-2 and IS24C32A-2)
Range
AmbientTemperature
0°C to +70°C
VCC
Commercial
Industrial
1.8V to 5.5V
1.8V to 5.5V
–40°Cto+85°C
OPERATING RANGE (IS24C64A/B-3 and IS24C32A-3)
Range
AmbientTemperature
0°C to +70°C
VCC
Commercial
Industrial
2.5V to 5.5V
2.5V to 5.5V
–40°Cto+85°C
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
Input Capacitance
Output Capacitance
6
8
COUT
VOUT = 0V
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 5.0V.
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCEDINFORMATION Rev. 00A
9
01/26/04
IS24C32A
®
IS24C64A/B
ISSI
AC WAVEFORMS
Figure 11. Bus Timing
t
R
t
F
t
HIGH
t
LOW
t
SU:STO
SCL
t
BUF
t
SU:STA
tHD:DAT
t
HD:STA
tSU:DAT
SDAIN
t
AA
tDH
SDAOUT
WP
t
SU:WP
t
HD:WP
Figure 12. Write Cycle Timing
SCL
ACK
SDA
t
WR
WORD n
STOP
Condition
START
Condition
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCEDINFORMATION Rev. 00A
01/26/04
IS24C32A
®
IS24C64A/B
ISSI
DC ELECTRICAL CHARACTERISTICS
Commercial (TA = 0oC to +70oC), Industrial (TA = -40oC to +85oC)
Symbol Parameter
Test Conditions
Min.
—
Max.
Unit
V
VOL1
VOL2
VIH
Output Low Voltage
VCC = 1.8V, IOL = 0.15 mA
VCC = 2.5V, IOL = 3 mA
0.2
0.4
Output Low Voltage
Input High Voltage
—
V
VCC X 0.7 VCC + 0.5
V
VIL
Input Low Voltage
–1.0
—
VCC X 0.3
V
ILI
Input Leakage Current
Output Leakage Current
VIN = VCC max.
3
3
µA
µA
ILO
—
Notes: VIL min and VIH max are reference only and are not tested.
POWER SUPPLY CHARACTERISTICS
Commercial (TA = 0oC to +70oC), Industrial (TA = -40oC to +85oC)
Symbol Parameter
Test Conditions
Min.
—
Max.
2.0
3.0
1
Unit
mA
mA
µA
ICC1
ICC2
ISB1
ISB2
Vcc Operating Current
Read at 400 KHz (Vcc = 5V)
Write at 400 KHz (Vcc = 5V)
Vcc = 1.8V
Vcc Operating Current
Standby Current
—
—
Standby Current
Vcc = 2.5V
—
2
µA
ISB3
Standby Current
Vcc = 5.0 V
—
6
µA
AC ELECTRICAL CHARACTERISTICS
Commercial (TA = 0oC to +70oC) Industrial (TA = -40oC to +85oC)
1.8V-5.5V
Min. Max.
2.5V-5.5V
Min. Max.
4.5V-5.5V
Symbol Parameter
Min. Max. Unit
fSCL
SCL Clock Frequency
Noise Suppression Time(1)
0
—
4.7
4
100
100
—
—
—
—
—
—
—
—
—
—
—
—
0
400
50
—
0
—
1000 KHz
T
—
50
—
ns
µs
µs
µs
µs
µs
µs
µs
ns
ns
µs
µs
ns
ns
ns
ns
ms
tLow
Clock Low Period
1.2
0.6
1.2
0.6
0.6
0.6
0.6
100
0
0.6
0.4
0.5
0.25
0.25
0.25
0.25
100
0
tHigh
Clock High Period
—
—
tBUF
Bus Free Time Before New Transmission(1)
Start Condition Setup Time
Stop Condition Setup Time
Start Condition Hold Time
Stop Condition Hold Time
Data In Setup Time
4.7
4
—
—
tSU:STA
tSU:STO
tHD:STA
tHD:STO
tSU:DAT
tHD:DAT
tSU:WP
tHD:WP
tDH
—
—
4
—
—
4
—
—
4
—
—
100
0
—
—
Data In Hold Time
—
—
WP pin Setup Time
4
0.6
1.2
50
—
0.6
1.2
50
—
WP pin Hold Time
4.7
—
—
Data Out Hold Time (SCL Low to SDA Data Out Change) 100
—
—
tAA
Clock to Output (SCL Low to SDA Data Out Valid)
SCL and SDA Rise Time(1)
SCL and SDA Fall Time(1)
Write Cycle Time
100 3500
50
900
300
300
10
50
400
300
100
5
tR
—
—
—
1000
300
10
—
—
tF
—
—
tWR
—
—
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCEDINFORMATION Rev. 00A
11
01/26/04
IS24C32A
®
IS24C64A/B
ISSI
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Voltage
Frequency Range
PartNumber Package
100 KHz
100 KHz
100 KHz
400 KHz
400 KHz
400 KHz
1.8V
to 5.5V
IS24C32A-2P 300-mil Plastic DIP
IS24C32A-2G Small Outline (JEDEC STD)
1.8V
to 5.5V
IS24C64A-2P 300-mil Plastic DIP
IS24C64A-2G Small Outline (JEDEC STD)
1.8V
to 5.5V
IS24C64B-2P 300-mil Plastic DIP
IS24C64B-2G Small Outline (JEDEC STD)
2.5V
to 5.5V
IS24C32A-3P 300-mil Plastic DIP
IS24C32A-3G Small Outline (JEDEC STD)
2.5V
to 5.5V
IS24C64A-3P 300-mil Plastic DIP
IS24C64A-3G Small Outline (JEDEC STD)
2.5V
IS24C64B-3P 300-mil Plastic DIP
to 5.5V
IS24C64B-3G Small Outline (JEDEC STD)
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Voltage
Frequency Range
PartNumber Package
100 KHz
100 KHz
100 KHz
400 KHz
400 KHz
400 KHz
1.8V
to 5.5V
IS24C32A-2PI 300-mil Plastic DIP
IS24C32A-2GI Small Outline (JEDEC STD)
1.8V
to 5.5V
IS24C64A-2PI 300-mil Plastic DIP
IS24C64A-2GI Small Outline (JEDEC STD)
1.8V
to 5.5V
IS24C64B-2PI 300-mil Plastic DIP
IS24C64B-2GI Small Outline (JEDEC STD)
2.5V
to 5.5V
IS24C32A-3PI 300-mil Plastic DIP
IS24C32A-3GI Small Outline (JEDEC STD)
2.5V
to 5.5V
IS24C64A-3PI 300-mil Plastic DIP
IS24C64A-3GI Small Outline (JEDEC STD)
2.5V
IS24C64B-3PI 300-mil Plastic DIP
to 5.5V
IS24C64B-3GI Small Outline (JEDEC STD)
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCEDINFORMATION Rev. 00A
01/26/04
相关型号：
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