IC43R16160L-5T_技术文档

IC43R16160

Document Title

4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM

Revision History

Revision No

0A

History

Draft Date

Remark

Initial Draft

January 13,2004

Preliminary

The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and

products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.

Integrated Circuit Solution Inc.

DDR001-0A 01/13/2004

1

IC43R16160

PRELIMINARY

4M Words x 16 Bits x 4 Banks (256-MBIT)

DDR SYNCHRONOUS DYNAMIC RAM

5

6

7

DDR266

DDR333

7.5ns

DDR400

7.5ns

Clock Cycle Time (t_CK2

Clock Cycle Time (t_CK2.5

Clock Cycle Time (t_CK3

)

7.5ns

)

7ns

-

6ns

5ns

6ns

-

)

System Frequency (f_{CK max}

)

143MHz

200MHz

166MHz

Features

Description

■ High speed data transfer rates with system frequency

up to 200 MHz

The ICSI IC43R16160 is a four bank DDR DRAM

organized as 4 banks x 4Mbit x 16. The IC43R16160

achieves high speed data transfer rates by employing a

chip architecture that prefetches multiple bits and then

synchronizes the output data to a system clock.

■ Data Mask for Write Control

■ Four Banks controlled by BA0 & BA1

■ Programmable CAS Latency: 2, 2.5, 3

■ Programmable Wrap Sequence: Sequential

or Interleave

■ Programmable Burst Length:

2, 4, 8 for Sequential Type

2, 4, 8 for Interleave Type

■ Automatic and Controlled Precharge Command

■ Power Down Mode

■ Auto Refresh and Self Refresh

■ Refresh Interval: 8192 cycles/64 ms

■ Available in 66-pin 400 mil TSOP

■ SSTL-2 Compatible I/Os

All of the control, address, circuits are synchronized with

the positive edge of an externally supplied clock. I/O

transactionsareocurringonbothedgesofDQS. Operating

the four memory banks in an interleaved fashion allows

random access operation to occur at a higher rate than is

possible with standard DRAMs. A sequential and gapless

data rate is possible depending on burst length, CAS

latency and speed grade of the device.

■ Double Data Rate (DDR)

■ Bidirectional Data Strobe (DQS) for input and output

data, active on both edges

■ On-Chip DLL aligns DQ and DQs transitions with CK

transitions

■ Differential clock inputs CK and CK

■ Power Supply 2.5V ± 0.2V

■ Power Supply 2.6V ± 0.1V for DDR400

Device Usage Chart

CK Cycle Time (ns)

Power

Std.

Operation

Temperature

Range

Package Outline

Temperature

Mark

JESEC 66TSOP II

-5

-6

-7

L

0°C to 70°C

•

Blank

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors

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Integrated Circuit Solution Inc.

DDR001-0A 01/13/2004

IC43R16160

66 Pin Plastic TSOP-II

PIN CONFIGURATION

Top View

VDD

DQ0

VDDQ

DQ1

DQ2

VSSQ

DQ3

DQ4

VDDQ

DQ5

DQ6

VSSQ

DQ7

NC

VDDQ

LDQS

NC

VDD

NC

LDM

WE

CAS

RAS

CS

1

2

3

4

5

6

7

8

VSS

DQ15

VSSQ

DQ14

DQ13

VDDQ

DQ12

DQ11

VSSQ

DQ10

DQ9

VDDQ

DQ8

NC

VSSQ

UDQS

NC

VREF

VSS

UDM

CK

CKE

NC

A12

A11

A9

A8

A7

A6

A5

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

NC

BA0

BA1

AP/A10

A0

A1

A2

A3

VDD

A4

VSS

Pin Names

CK, CK

Differential Clock Input

Clock Enable

DQ’s

Data Input/Output

CKE

DM (UDM, LDM)

V_DD

Data Mask

CS

Chip Select

Power

(+2.5V and +2.6V for DDR400)

RAS

Row Address Strobe

Column Address Strobe

Write Enable

V_SS

Ground

CAS

V_DDQ

Power for I/O’s

(+2.5V and +2.6V for DDR400)

WE

DQS (UDQS, LDQS)

A₀–A₁₂

Data Strobe (Bidirectional)

Address Inputs

V_SSQ

NC

Ground for I/O’s

Not connected

BA0, BA1

Bank Select

VREF

Reference Voltage for Inputs

Integrated Circuit Solution Inc.

DDR001-0A 01/13/2004

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IC43R16160

Block Diagram

16M x 16

Row Addresses

Column Addresses

A0 - A8, AP, BA0, BA1

A0 - A12, BA0, BA1

Row address

buffer

Column address

counter

Column address

buffer

Refresh Counter

Row decoder

Memory array

Bank 0

Memory array

Bank 1

Memory array

Bank 2

Memory array

Bank 3

8192 x 256

x32 bit

8192 x 256

x 32 bit

8192 x 256

x 32 bit

8192 x 256

x 32 bit

Control logic & timing generator

Input buffer

Output buffer

DQ₀-DQ₁₅

CK, CK

DQS

DLL

Strobe

Gen.

Data Strobe

Capacitance*

Absolute Maximum Ratings*

Operating temperature range ..................0 to 70 °C

Storage temperature range ................-55 to 150 °C

T = 0 to 70°C, V = 2.5V 0.2V, V = 2.6V 0.1V

A

CC

for DDR400, f = 1 Mhz

V

Supply Voltage Relative to V .....-1V to +3.6V

DD

SS

Input Capacitance

Symbol Min Max Unit

Supply Voltage Relative to V

DDQ

SS

......................................................-1V to +3.6V

VREF and Inputs Voltage Relative to V

BA0, BA1, CKE, CS, RAS, (CAS,

A0-A11, WE)

C_INI

2

3.0 pF

SS

......................................................-1V to +3.6V

I/O Pins Voltage Relative to V

Input Capacitance (CK, CK)

Data & DQS I/O Capacitance

Input Capacitance (DM)

C_IN2

C_OUT

C_IN3

2

4

SS

5

pF

..........................................-0.5V to V

+0.5V

DDQ

Power dissipation .......................................... 1.6 W

Data out current (short circuit)...................... 50 mA

5.0 pF

*Note: Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage of the device.

Exposure to absolute maximum rating conditions for

extended periods may affect device reliability.

*Note: Capacitance is sampled and not 100% tested.

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Integrated Circuit Solution Inc.

DDR001-0A 01/13/2004

IC43R16160

Signal Pin Description

Type Signal Polarity

Function

CK

Positive The system clock input. All inputs except DQs and DMs are sampled on the rising

Input Pulse

Edge

edge of CK.

Activates the CK signal when high and deactivates the CK signal when low, thereby

initiates either the Power Down mode, or the Self Refresh mode.

CKE

Input Level Active High

Input Pulse Active Low

CS

enables the command decoder when low and disables the command decoder

CS

when high. When the command decoder is disabled, new commands are ignored

but previous operations continue.

RAS CAS

,

WE

When sampled at the positive rising edge of the clock, CAS, RAS, and WE define

the command to be executed by the SDRAM.

Input Pulse Active Low

Input/

Active on both edges for data input and output.

Edge aligned to output data

DQS

Pulse Active High Center aligned to input data

Output

During a Bank Activate command cycle, A0-A12 defines the row address (RA0-

RA12) when sampled at the rising clock edge.

During a Read or Write command cycle, A0-A8 defines the column address (CA0-

CA8) when sampled at the rising clock edge.

In addition to the column address, A10(=AP) is used to invoke autoprecharge

operation at the end of the burst read or write cycle. If A10 is high, autoprecharge is

selected and BA0, BA1 defines the bank to be precharged. If A10 is low,

autoprecharge is disabled. During a Precharge command cycle, A10(=AP) is used in

conjunction with BA0 and BA1 to control which bank(s) to precharge. If A10 is high,

all four banks will be precharged simultaneously regardless of state of BA0 and BA1.

A0 - A12 Input Level

_

BA0,

Input Level

BA1

_

Selects which bank is to be active.

Input/

Output

DQx

Level

Data Input/Output pins operate in the same manner as on conventional DRAMs.

In Write mode, DM has a latency of zero and operates as a word mask by allowing

DM,

LDM,

UDM

Input Pulse Active High input data to be written if it is low but blocks the write operation if is high for LDM

corresponds to data on DQ0-DQ7, UDM corresponds to data on DQ8-DQ15.

VDD,VSS Supply

Power and ground for the input buffers and the core logic.

VDDQ

Supply

VSSQ

Isolated power supply and ground for the output buffers to provide improved noise

immunity.

_

VREF

Input Level

SSTL Reference Voltage for Inputs

Integrated Circuit Solution Inc.

DDR001-0A 01/13/2004

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IC43R16160

Mode Register Set (MRS)

The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs

CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to

make DDR SDRAM useful for a variety of different applications. The default value of the mode register is not

defined, therefore the mode register must be written after EMRS setting for proper DDR SDRAM operation.

The mode register is written by asserting low on CS, RAS, CAS, WE and BA (The DDR SDRAM should be

0

in all bank precharge with CKE already high prior to writing into the mode register). The state of address pins

A ~ A in the same cycle as CS, RAS, CAS, WE and BA0 low is written in the mode register. Two clock

0

12

cycles are required to meet t

spec. The mode register contents can be changed using the same com-

MRD

mand and clock cycle requirements during operation as long as all banks are in the idle state. The mode reg-

ister is divided into various fields depending on functionality. The burst length uses A ~ A , addressing mode

0

2

uses A , CAS latency (read latency from column address) uses A ~ A . A is a Mosel Vitelic specific test

3

4

6

7

mode during production test. A is used for DLL reset. A must be set to low for normal MRS operation. Refer

8

7

to the table for specific codes for various burst length, addressing modes and CAS latencies.

1. MRS can be issued only at all banks precharge state.

2. Minimum tRP is required to issue MRS command.

to

Address Bus

A

12

A3

BA1

BA

0

A

2

A

1

A0

I/O DLL

Extended Mode Register

Mode Register

0

RFU : Must be set "0"

MRS

0

RFU

DLL TM

BT Burst Length

CAS Latency

A

0

1

I/O Strength

Full

A

0

1

0

DLL Enable

Enable

A

0

1

3

Burst Type

Sequential

Interleave

A₇

A

8

DLL Reset

No

mode

Normal

Test

0

1

0

Half

Disable

1

Yes

Burst Length

CAS Latency

Latency

BA

0

A

n

~ A

0

A

0

1

6

A

5

A

0

1

0

1

0

1

0

1

4

Latency

Reserve

2

A

2

A

1

A

0

Sequential

Reserve

2

Interleave

Reserve

2

(Existing)MRS Cycle

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Extended Funtions(EMRS)

4

3

8

Reserve

2.5

Reserve

* RFU(Reserved for future use)

should stay "0" during MRS

cycle.

Reserve

Mode Register Set

0

1

2

3

4

5

6

7

8

CK,CK

*1

Mode

Register Set

Precharge

All Banks

Any

Command

*2

RP

t_MRD

tCK

t

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Integrated Circuit Solution Inc.

DDR001-0A 01/13/2004

IC43R16160

Mode Register Set Timing

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

t

MRD

RP

CK

CK, CK

Pre- All

MRS/EMRS

ANY

Command

Mode Register set (MRS) or Extended Mode Register Set (EMRS) can be issued only when all banks are in the idle state.

If a MRS command is issued to reset the DLL, then an additional 200 clocks must occur prior to issuing any new command

to allow time for the DLL to lock onto the clock.

Burst Mode Operation

Burst Mode Operation is used to provide a constant flow of data to memory locations (Write cycle), or from

memory locations (Read cycle). Two parameters define how the burst mode will operate: burst sequence and

burst length. These parameters are programmable and are determined by address bits A —A during the

0

3

Mode Register Set command. Burst type defines the sequence in which the burst data will be delivered or

stored to the SDRAM. Two types of burst sequence are supported: sequential and interleave. The burst

length controls the number of bits that will be output after a Read command, or the number of bits to be input

after a Write command. The burst length can be programmed to values of 2, 4, or 8. See the Burst Length

and Sequence table below for programming information.

Burst Length and Sequence

Burst Length

Starting Length (A , A , A )

Sequential Mode

0, 1

Interleave Mode

0, 1

2

1

0

xx0

xx1

x00

x01

x10

x11

000

001

010

011

100

101

110

111

2

1, 0

0, 1, 2, 3

1, 2, 3, 0

1, 0, 3, 2

4

2, 3, 0, 1

3, 0, 1, 2

3, 2, 1, 0

0,1, 2, 3, 4, 5, 6, 7

1, 2, 3, 4, 5, 6, 7, 0

2, 3, 4, 5, 6, 7, 0, 1

3, 4, 5, 6, 7, 0, 1, 2

4, 5, 6, 7, 0, 1, 2, 3

5, 6, 7, 0, 1, 2, 3, 4

6, 7, 0, 1, 2, 3, 4, 5

7, 0, 1, 2, 3, 4, 5, 6

0,1, 2, 3, 4, 5, 6, 7

1, 0, 3, 2, 5, 4, 7, 6

2, 3, 0, 1, 6, 7, 4, 5

3, 2, 1, 0, 7, 6, 5, 4

4, 5, 6, 7, 0, 1, 2, 3

5, 4, 7, 6, 1, 0, 3, 2

6, 7, 4, 5, 2, 3, 0, 1

7, 6, 5, 4, 3, 2, 1, 0

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Integrated Circuit Solution Inc.

DDR001-0A 01/13/2004

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IC43R16160

Bank Activate Command

The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising

edge of the clock. The DDR SDRAM has four independent banks, so two Bank Select addresses (BA and

0

BA ) are supported. The Bank Activate command must be applied before any Read or Write operation can

1

be executed. The delay from the Bank Activate command to the first Read or Write command must meet or

exceed the minimum RAS to CAS delay time (t

min). Once a bank has been activated, it must be pre-

RCD

charged before another Bank Activate command can be applied to the same bank. The minimum time interval

between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay

time (t

min).

RRD

Bank Activation Timing

(CAS Latency = 2; Burst Length = Any)

T0

T1

T2

T3

Tn

t_RC

Tn+1

Tn+2

Tn+3

Tn+4

Tn+5

t_RP(min)

t_RRD(min)

t

(min)

RAS

t_RCD(min)

CK, CK

BA/Address

Bank/Row

Activate/A

Bank/Col

Read/A

Bank/Row

Activate/A

Bank/Row

Bank

Pre/A

Activate/B

Command

Begin Precharge Bank A

Read Operation

With the DLL enabled, all devices operating at the same frequency within a system are ensured to have

the same timing relationship between DQ and DQS relative to the CK input regardless of device density, pro-

cess variation, or technology generation.

The data strobe signal (DQS) is driven off chip simultaneously with the output data (DQ) during each read

cycle. The same internal clock phase is used to drive both the output data and data strobe signal off chip to

minimize skew between data strobe and output data. This internal clock phase is nominally aligned to the

input differential clock (CK, CK) by the on-chip DLL. Therefore, when the DLL is enabled and the clock fre-

quency is within the specified range for proper DLL operation, the data strobe (DQS), output data (DQ), and

the system clock (CK) are all nominally aligned.

Since the data strobe and output data are tightly coupled in the system, the data strobe signal may be de-

layed and used to latch the output data into the receiving device. The tolerance for skew between DQS and

DQ (t_DQSQ) is tighter than that possible for CK to DQ (t_AC) or DQS to CK (t_DQSCK).

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Integrated Circuit Solution Inc.

DDR001-0A 01/13/2004

IC43R16160

Output Data (DQ) and Data Strobe (DQS) Timing Relative to the Clock (CK)

During Read Cycles

(CAS Latency = 2.5; Burst Length = 4)

T4

T0

T1

T2

T3

CK, CK

READ

NOP

Command

t

(max)

DQSCK

t

(min)

DQSCK

DQS

DQ

t

(max)

AC

t

(min)

AC

D

3

0

1

2

The minimum time during which the output data (DQ) is valid is critical for the receiving device (i.e., a mem-

ory controller device). This also applies to the data strobe during the read cycle since it is tightly coupled to

the output data. The minimum data output valid time (t_DV) and minimum data strobe valid time (t_DQSV) are de-

rived from the minimum clock high/low time minus a margin for variation in data access and hold time due to

DLL jitter and power supply noise.

Integrated Circuit Solution Inc.

DDR001-0A 01/13/2004

9

IC43R16160

Output Data and Data Strobe Valid Window for DDR Read Cycles

(CAS Latency = 2; Burst Length = 2)

T4

T0

T1

T2

T3

CK, CK

READ

NOP

Command

DQS

t

(min)

DQSV

D

1

DQ

0

t

(min)

DV

Read Preamble and Postamble Operation

Prior to a burst of read data and given that the controller is not currently in burst read mode, the data strobe

signal (DQS), must transition from Hi-Z to a valid logic low. The is referred to as the data strobe “read pream-

ble” (t_RPRE). This transition from Hi-Z to logic low nominally happens one clock cycle prior to the first edge of

valid data.

Once the burst of read data is concluded and given that no subsequent burst read operations are initiated,

the data strobe signal (DQS) transitions from a logic low level back to Hi-Z. This is referred to as the data

strobe “read postamble” (t_RPST). This transition happens nominally one-half clock period after the last edge of

valid data.

Consecutive or “gapless” burst read operations are possible from the same DDR SDRAM device with no

requirement for a data strobe “read” preamble or postamble in between the groups of burst data. The data

strobe read preamble is required before the DDR device drives the first output data off chip. Similarly, the

data strobe postamble is initiated when the device stops driving DQ data at the termination of read burst cycles.

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DDR001-0A 01/13/2004

IC43R16160

Data Strobe Preamble and Postamble Timings for DDR Read Cycles

(CAS Latency = 2; Burst Length = 2)

T4

T0

T1

T2

T3

CK, CK

READ

NOP

Command

t

(max)

RPRE

t

(min)

RPRE

t

(min)

RPST

DQS

DQ

t

(max)

RPST

t

(min)

DQSQ

D

0

1

t

(max)

DQSQ

Consecutive Burst Read Operation and Effects on the Data Strobe Preamble and Postamble

Burst Read Operation (CAS Latency = 2; Burst Length = 4)

CK, CK

NOP

Read

NOP

Read

NOP

Command

DQS

A

B

D0 D1 D2 D3 D0 D1 D2 D3

DQ

A

B

Burst Read Operation (CAS Latency = 2; Burst Length = 4)

CK, CK

NOP

Read

NOP

Read

NOP

Command

DQS

A

B

D0 D1 D2 D3

B B B B

DQ

A

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IC43R16160

Auto Precharge Operation

The Auto Precharge operation can be issued by having column address A₁₀high when a Read or Write

command is issued. If A₁₀is low when a Read or Write command is issued, then normal Read or Write burst

operation is executed and the bank remains active at the completion of the burst sequence. When the Auto

Precharge command is activated, the active bank automatically begins to precharge at the earliest possible

moment during the Read or Write cycle once t_RAS(min) is satisfied.

Read with Auto Precharge

If a Read with Auto Precharge command is initiated, the DDR SDRAM will enter the precharge operation

N-clock cycles measured from the last data of the burst read cycle where N is equal to the CAS latency pro-

grammed into the device. Once the autoprecharge operation has begun, the bank cannot be reactivated until

the minimum precharge time (t_RP) has been satisfied.

Read with Autoprecharge Timing

(CAS Latency = 2; Burst Length = 4)

T0

T1

T2

T3

t

T4

T5

T6

t (min)

T7

T8

T9

(min)

RAS

P

CK, CK

Command

DQS

ACT

NOP

R w/AP

NOP

BA

NOP

D

3

DQ

0

1

2

Begin Autoprecharge

Earliest Bank A reactivate

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DDR001-0A 01/13/2004

IC43R16160

Read with Autoprecharge Timing as a Function of CAS Latency

(CAS Latency = 2, 2.5, Burst Length = 4)

T0

T1

T2

T3

(min)

T4

T5

T6

T7

T8

T9

t

(min)

RAS

RP

CK, CK

BA

NOP

RAP

NOP

BA

NOP

Command

DQS

DQ

D

3

0

1

2

CAS Latency=2

DQS

DQ

D

3

0

1

2

CAS Latency=2.5

Integrated Circuit Solution Inc.

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IC43R16160

Precharge Timing During Read Operation

For the earliest possible Precharge command without interrupting a Read burst, the Precharge command

may be issued on the rising clock edge which is CAS latency (CL) clock cycles before the end of the Read

burst. A new Bank Activate (BA) command may be issued to the same bank after the RAS precharge time

(t_RP). A Precharge command can not be issued until t_RAS(min) is satisfied.

Read with Precharge Timing as a Function of CAS Latency

(CAS Latency = 2, 2.5, 3; Burst Length = 4)

T0

T1

T2

T3

(min)

T4

T5

T6

T7

T8

T9

t

(min)

RAS

RP

CK, CK

BA

NOP

Read

NOP

Pre

NOP

BA

NOP

Command

A

DQS

DQ

D

3

0

1

2

CAS Latency=2

DQS

DQ

D

3

0

1

2

CAS Latency=2.5

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Integrated Circuit Solution Inc.

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IC43R16160

Burst Stop Command

The Burst Stop command is valid only during burst read cycles and is initiated by having RAS and CAS

high with CS and WE low at the rising edge of the clock. When the Burst Stop command is issued during a

burst Read cycle, both the output data (DQ) and data strobe (DQS) go to a high impedance state after a delay

(L_BST) equal to the CAS latency programmed into the device. If the Burst Stop command is issued during a

burst Write cycle, the command will be treated as a NOP command.

Read Terminated by Burst Stop Command Timing

(CAS Latency = 2, 2.5, 3; Burst Length = 4)

T0

T1

T2

T3

T4

T5

T6

CK, CK

Read

BST

NOP

Command

L

BST

DQS

DQ

CAS Latency = 2

D

1

0

L

BST

DQS

DQ

CAS Latency = 2.5

D

1

0

Integrated Circuit Solution Inc.

DDR001-0A 01/13/2004

15

IC43R16160

Read Interrupted by a Precharge

A Burst Read operation can be interrupted by a precharge of the same bank. The Precharge command to

Output Disable latency is equivalent to the CAS latency.

Read Interrupted by a Precharge Timing

(CAS Latency = 2, 2.5, 3; Burst Length = 8)

T0

T1

T2

T3

(min)

T4

T5

T6

T7

T8

T9

t

(min)

RAS

RP

CK, CK

BA

NOP

Read

NOP

Pre

NOP

BA

NOP

Command

A

DQS

DQ

D

3

0

1

2

CAS Latency=2

DQS

DQ

D

3

0

1

2

CAS Latency=2.5

Burst Write Operation

The Burst Write command is issued by having CS, CAS, and WE low while holding RAS high at the rising

edge of the clock. The address inputs determine the starting column address. The memory controller is re-

quired to provide an input data strobe (DQS) to the DDR SDRAM to strobe or latch the input data (DQ) and

data mask (DM) into the device. During Write cycles, the data strobe applied to the DDR SDRAM is required

to be nominally centered within the data (DQ) and data mask (DM) valid windows. The data strobe must be

driven high nominally one clock after the write command has been registered. Timing parameters t_DQSS(min)

and t_DQSS(max) define the allowable window when the data strobe must be driven high.

Input data for the first Burst Write cycle must be applied one clock cycle after the Write command is

registered into the device (WL=1). The input data valid window is nominally centered around the midpoint of

the data strobe signal. The data window is defined by DQ to DQS setup time (t_QDQSS) and DQ to DQS hold

time (t_QDQSH). All data inputs must be supplied on each rising and falling edge of the data strobe until the burst

length is completed. When the burst has finished, any additional data supplied to the DQ pins will be ignored.

Write Preamble and Postamble Operation

Prior to a burst of write data and given that the controller is not currently in burst write mode, the data strobe

signal (DQS), must transition from Hi-Z to a valid logic low. This is referred to as the data strobe “write preamble”.

This transition from Hi-Z to logic low nominally happens on the falling edge of the clock after the write com-

mand has been registered by the device. The preamble is explicitly defined by a setup time (t_WPRES(min)) and

hold time (t_WPREH(min)) referenced to the first falling edge of CK after the write command.

16

Integrated Circuit Solution Inc.

DDR001-0A 01/13/2004

IC43R16160

Burst Write Timing

(CAS Latency = Any; Burst Length = 4)

T4

T0

T1

T2

T3

CK, CK

WRITE

NOP

Command

t_WPREH

t_WPST

t_WPRES

t_QDQSS

t_DQSS

DQS(nom)

DQ(nom)

t_QDQSH

t_QDQSS

t_QDQSH

D₀

D₁

D₂

D₃

t_WPREH(min)

_WPRES(min)

t

DQS(min)

DQ(min)

t_DQSS(min)

D₀

D₁

D₂

D₃

t_WPRES(max)

t

_WPREH(max)

DQS(max)

DQ(max)

t

_DQSS(max)

D₀

D₁

D₂

D₃

Once the burst of write data is concluded and given that no subsequent burst write operations are initiated,

the data strobe signal (DQS) transitions from a logic low level back to Hi-Z. This is referred to as the data

strobe “write postamble”. This transition happens nominally one-half clock period after the last data of the

burst cycle is latched into the device.

Integrated Circuit Solution Inc.

DDR001-0A 01/13/2004

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IC43R16160

Write Interrupted by a Precharge

A Burst Write can be interrupted before completion of the burst by a Precharge command, with the only

restriction being that the interval that separates the commands be at least one clock cycle.

Write Interrupted by a Precharge Timing

(CAS Latency = 2; Burst Length = 8)

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

CK, CK

Command

DQS

Write

Pre

NOP

A

t

WR

D

6

DQ

0

1

2

3

4

5

DM

Data is masked

by DM input

Data is masked

by Precharge Command

DQS input ignored

Write with Auto Precharge

If A is high when a Write command is issued, the Write with auto Precharge function is performed. Any

10

new command to the same bank should not be issued until the internal precharge is completed. The internal

precharge begins after keeping t

(min.).

WR

Write with Auto Precharge Timing

(CAS Latency = Any; Burst Length = 4)

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

t_RAS(min)

CK, CK

BA

NOP

WAP

NOP

BA

Command

DQS

DQ

t_WR(min)

t_RP(min)

D₀

D₁D₂D₃

Begin Autoprecharge

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Integrated Circuit Solution Inc.

DDR001-0A 01/13/2004

IC43R16160

Precharge Timing During Write Operation

Precharge timing for Write operations in DRAMs requires enough time to satisfy the write recovery require-

ment. This is the time required by a DRAM sense amp to fully store the voltage level. For DDR SDRAMs, a

timing parameter (t_WR) is used to indicate the required amount of time between the last valid write operation

and a Precharge command to the same bank.

The “write recovery” operation begins on the rising clock edge after the last DQS edge that is used to strobe

in the last valid write data. “Write recovery” is complete on the next 2nd rising clock edge that is used to strobe

in the Precharge command.

Write with Precharge Timing

(

CAS Latency = Any; Burst Length = 4)

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

t_RP(min)

T10

t_RAS(min)

CK, CK

BA

NOP

Write

NOP

Pre

NOP

BA

NOP

t_WR

Command

A

DQS

DQ

D₀

D₁D₂D₃

t

WR

DQS

DQ

D₀

D₁D₂D₃

Integrated Circuit Solution Inc.

DDR001-0A 01/13/2004

19

IC43R16160

Data Mask Function

The DDR SDRAM has a Data Mask function that is used in conjunction with the Write cycle, but not the

Read cycle. When the Data Mask is activated (DM high) during a Write operation, the Write is blocked (Mask

to Data Latency = 0).

When issued, the Data Mask must be referenced to both the rising and falling edges of Data Strobe.

Data Mask Timing

(CAS Latency = Any; Burst Length = 8)

T9

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK, CK

Write

NOP

Command

t

DMDQSS

DQS

DQ

t

DMDQSH

D

7

0

1

2

3

4

5

6

DM

Burst Interruption

Read Interrupted by a Read

A Burst Read can be interrupted before completion of the burst by issuing a new Read command to any

bank. When the previous burst is interrupted, the remaining addresses are overridden with a full burst length

starting with the new address. The data from the first Read command continues to appear on the outputs until

the CAS latency from the interrupting Read command is satisfied. At this point, the data from the interrupting

Read command appears on the bus. Read commands can be issued on each rising edge of the system clock.

It is illegal to interrupt a Read with autoprecharge command with a Read command.

Read Interrupted by a Read Command Timing

(CAS Latency = 2; Burst Length = 4)

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

CK, CK

Command

DQS

Read

NOP

A

B

DA0 DA1 DB0 DB1 DB2 DB3

DQ

20

Integrated Circuit Solution Inc.

DDR001-0A 01/13/2004

IC43R16160

Read Interrupted by a Write

To interrupt a Burst Read with a Write command, a Burst Stop command must be asserted to stop the burst

read operation and 3-state the DQ bus. Additionally, control of the DQS bus must be turned around to allow

the memory controller to drive the data strobe signal (DQS) into the DDR SDRAM for the write cycles. Once

the Burst Stop command has been issued, a Write command can not be issued until a minimum delay or

latency (L_BST) has been satisfied. This latency is measured from the Burst Stop command and is equivalent

to the CAS latency programmed into the mode register. In instances where CAS latency is measured in half

clock cycles, the minimum delay (L_BST) is rounded up to the next full clock cycle (i.e., if CL=2 then L_BST=2, if

CL=2.5 then L_BST=3). It is illegal to interrupt a Read with autoprecharge command with a Write command.

Read Interrupted by Burst Stop Command Followed by a Write Command Timing

(CAS Latency = 2; Burst Length = 4)

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

CK, CK

Command

DQS

Read

BST

NOP

Write

NOP

D

3

DQ

0

1

0

1

2

L

BST

Write Interrupted by a Write

A Burst Write can be interrupted before completion by a new Write command to any bank. When the pre-

vious burst is interrupted, the remaining addresses are overridden with a full burst length starting with the new

address. The data from the first Write command continues to be input into the device until the Write Latency

of the interrupting Write command is satisfied (WL=1) At this point, the data from the interrupting Write com-

mand is input into the device. Write commands can be issued on each rising edge of the system clock. It is

illegal to interrupt a Write with autoprecharge command with a Write command.

Write Interrupted by a Write Command Timing

(CAS Latency = Any; Burst Length = 4)

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

CK, CK

Command

DQS

Write

NOP

A

B

DA0 DA1 DB0 DB1 DB2 DB3

DM0 DM1 DM0 DM1 DM2 DM3

DQ

DM

Write Latency

Integrated Circuit Solution Inc.

DDR001-0A 01/13/2004

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IC43R16160

Write Interrupted by a Read

A Burst Write can be interrupted by a Read command to any bank. If a burst write operation is interrupted

prior to the end of the burst operation, then the last two pieces of input data prior to the Read command must

be masked off with the data mask (DM) input pin to prevent invalid data from being written into the memory

array. Any data that is present on the DQ pins coincident with or following the Read command will be masked

off by the Read command and will not be written to the array. The memory controller must give up control of

both the DQ bus and the DQS bus at least one clock cycle before the read data appears on the outputs in

order to avoid contention. In order to avoid data contention within the device, a delay is required (t_CDLR) from

the last valid data input before a Read command can be issued to the device. It is illegal to interrupt a Write

with autoprecharge command with a Read command.

Write Interrupted by a Read Command Timing

(CAS Latency = 2; Burst Length = 8)

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

CK, CK

Command

DQS

Write

NOP

Read

NOP

D

NOP

t

WTR

D

7

DQ

0

1

2

3

4

5

0

1

2

3

4

5

6

DM

Data is masked

by DM input

Data is masked

by Read command

DQS input ignored

Auto Refresh

The Auto Refresh command is issued by having CS, RAS, and CAS held low with CKE and WE high at the

rising edge of the clock. All banks must be precharged and idle for a t_RP(min) before the Auto Refresh com-

mand is applied. No control of the address pins is required once this cycle has started because of the internal

address counter. When the Auto Refresh cycle has completed, all banks will be in the idle state. A delay be-

tween the Auto Refresh command and the next Activate command or subsequent Auto Refresh command

must be greater than or equal to the t_RFC(min). Commands may not be issued to the device once an Auto

Refresh cycle has begun. CS input must remain high during the refresh period or NOP commands must be

registered on each rising edge of the CK input until the refresh period is satisfied.

Auto Refresh Timing

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

t

RFC

RP

CK, CK

Pre All

Auto Ref

NOP

ANY

Command

High

CKE

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DDR001-0A 01/13/2004

IC43R16160

Self Refresh

A self refresh command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising

edge of the clock (CK). Once the self refresh command is initiated, CKE must be held low to keep the device

in self refresh mode. During the self refresh operation, all inputs except CKE are ignored. The clock is inter-

nally disabled during self refresh operation to reduce power consumption. The self refresh is exited by sup-

plying stable clock input before returning CKE high, asserting deselect or NOP command and then asserting

CKE high for longer than t

after self refresh exit.

for locking of DLL. The auto refresh is required before self refresh entry and

SREX

• •

CK, CK

• •

Stable Clock

NOP

Self

Refresh

Auto

Refresh

Command

• •

CKE

• •

tSREX

Power Down Mode

The power down mode is entered when CKE is low and exited when CKE is high. Once the power down

mode is initiated, all of the receiver circuits except clock, CKE and DLL circuit are gated off to reduce power

consumption. All banks should be in idle state prior to entering the precharge power down mode and CKE

should be set high at least 1tck+tIS prior to row active command. During power down mode, refresh opera-

tions cannot be performed, therefore the device cannot remain in power down mode longer than the refresh

period (t

) of the device.

REF

CK, CK

• •

precharge

Precharge

power

down

power

down

Exit

• •

Precharge

Active

NOP

Read

Command

CKE

Entry

• •

Active

power down

Entry

Active

power down

Exit

Integrated Circuit Solution Inc.

DDR001-0A 01/13/2004

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IC43R16160

TRUTH TABLE 1 – CKE

(Notes: 1-4)

CKEn-1 CKEn

CURRENT STATE

Power-Down

COMMANDn

ACTIONn

Maintain Power-Down

Maintain Self Refresh

NOTES

X

L

Self Refresh

Power-Down

Self Refresh

DESELECT or NOP

Exit Power-Down

Exit Self Refresh

L

H

5

All Banks Idle

Bank(s) Active

All Banks Idle

DESELECT or NOP

AUTO REFRESH

See Truth Table 2

Precharge Power-Down Entry

Active Power-Down Entry

Self Refresh Entry

H

L

H

NOTE:

1. CKE is the logic state of CKE at clock edge n; CKE was the state of CKE at the previous clock edge.

n

n-1

2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.

3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn.

4. All states and sequences not shown are illegal or reserved.

t

5. DESELECT or NOP commands should be issued on any clock edges occurring during the XSR period.

A minimum of 200 clock cycles is needed before applying a read command, for the DLL to lock.

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DDR001-0A 01/13/2004

IC43R16160

TRUTH TABLE 2 – Current State Bank n - Command to Bank n

(Notes: 1-6; notes appear below and on next page)

CURRENT STATE

/CS

H

L

/RAS /CAS /WE

COMMAND/ACTION

NOTES

X

H

L

X

H

L

X

H

L

DESELECT (NOP/continue previous operation)

NO OPERATION (NOP/continue previous operation)

ACTIVE (select and activate row)

Any

L

Idle

L

AUTO REFRESH

7

L

MODE REGISTER SET

L

H

L

H

L

READ (select column and start READ burst)

WRITE (select column and start WRITE burst)

PRECHARGE (deactivate row in bank or banks)

READ (select column and start new READ burst)

PRECHARGE (truncate READ burst, start PRECHARGE)

BURST TERMINATE

10

8

Row Active

L

H

L

H

L

H

L

10

8

Read (Auto Precharge

Disabled)

L

H

L

H

L

9

L

H

L

READ (select column and start READ burst)

WRITE (select column and start new WRITE burst)

10, 11

10

Write (Auto Precharge

Disabled)

L

H

L

PRECHARGE (truncate WRITE burst, start PRECHARGE) 8, 11

NOTE:

t

1. This table applies when CKE was HIGH and CKE is HIGH (see Truth Table 1) and after XSR

n-1

n

has been met (if the previous state was self refresh).

2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown

are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.

3. Current state definitions:

t

Idle: The bank has been precharged, and RP has been met.

t

Row Active: A row in the bank has been activated, and RCD has been met.

No data bursts/accesses and no register accesses are in progress.

Read: A READ burst has been initiated, with AUTO PRECHARGE disabled,

and has not yet terminated or been terminated.

Write: A WRITE burst has been initiated, with AUTO PRECHARGE disabled,

and has not yet terminated or been terminated.

4. The following states must not be interrupted by a command issued to the same bank. DESELECT or NOP com-

mands,

or allowable commands to the other bank should be issued on any clock edge occurring during these states.

Allowable commands to the other bank are determined by its current state and Truth Table 2, and according to

Truth Table 3.

t

Precharging: Starts with registration of a PRECHARGE command and ends when RP is

t

met. Once RP is met, the bank will be in the idle state.

Integrated Circuit Solution Inc.

DDR001-0A 01/13/2004

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IC43R16160

NOTE: (continued)

t

Row Activating: Starts with registration of an ACTIVE command and ends when RCD is

t

met. Once RCD is met, the bank will be in the “row active” state.

Read w/Auto-Precharge Enabled: Starts with registration of a READ command with AUTO PRECHARGE

t

enabled and ends when RP has been met. Once RP is met, the bank will

be in the idle state.

Write w/Auto-Precharge Enabled: Starts with registration of a WRITE command with AUTO PRECHARGE

t

enabled and ends when RP has been met. Once RP is met, the bank will

be in the idle state.

5. The following states must not be interrupted by any executable command; DESELECT or NOP commands must be

applied on each positive clock edge during these states.

Refreshing: Starts with registration of an AUTO REFRESH command and ends when

t

RC is met. Once RFC is met, the DDR SDRAM will be in the “all banks

idle” state.

Accessing Mode Register: Starts with registration of a MODE REGISTER SET command and ends

t

when MRD has been met. Once MTC is met, the DDR SDRAM will be in

the “all banks idle” state.

Precharging All: Starts with registration of a PRECHARGE ALL command and ends when

t

RP is met. Once RP is met, all banks will be in the idle state.

6. All states and sequences not shown are illegal or reserved.

7. Not bank-specific; requires that all banks are idle and no bursts are in progress.

8. May or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging.

9. Not bank-specific; BURST TERMINATE affects the most recent READ burst, regardless of bank.

10. READs or WRITEs listed in the Command/Action column include READs or WRITEs with AUTO PRECHARGE

enabled and READs or WRITEs with AUTO PRECHARGE disabled.

11. Requires appropriate DM masking.

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Integrated Circuit Solution Inc.

DDR001-0A 01/13/2004

IC43R16160

TRUTH TABLE 3 – Current State Bank n - Command to Bank m

(Notes: 1-6; notes appear below and on next page)

CURRENT STATE /CS /RAS /CAS /WE

COMMAND/ACTION

NOTES

H

L

X

L

X

H

X

L

X

H

X

H

L

X

H

X

H

L

DESELECT (NOP/continue previous operation)

NO OPERATION (NOP/continue previous operation)

Any Command Otherwise Allowed to Bank m

ACTIVE (select and activate row)

READ (select column and start READ burst)

WRITE (select column and start WRITE burst)

PRECHARGE

Any

Idle

H

L

7

Row Activating,

Active, or Precharging

L

H

L

H

L

ACTIVE (select and activate row)

READ (select column and start new READ burst)

PRECHARGE

Read

(Auto-Precharge

Disabled)

H

L

7

H

L

H

L

ACTIVE (select and activate row)

READ (select column and start READ burst)

WRITE (select column and start new WRITE burst)

PRECHARGE

Write

(Auto- Precharge

Disabled)

H

L

7, 8

7

L

H

L

H

L

ACTIVE (select and activate row)

READ (select column and start new READ burst)

WRITE (select column and start WRITE burst)

PRECHARGE

H

L

3a, 7

Read

(With Auto-Precharge)

L

3a, 7, 9

H

L

H

L

ACTIVE (select and activate row)

READ (select column and start READ burst)

WRITE (select column and start new WRITE burst)

PRECHARGE

H

L

3a, 7

Write

(With Auto-Precharge)

L

H

L

NOTE:

t

1. This table applies when CKE was HIGH and CKE is HIGH (see Truth Table 1) and after XSR has been met

n-1

n

(if the previous state was self refresh).

2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the

commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given

command is allowable). Exceptions are covered in the notes below.

3. Current state definitions:

t

Idle: The bank has been precharged, and RP has been met.

t

Row Active: A row in the bank has been activated, and RCD has been met. No data

bursts/accesses and no register accesses are in progress.

Read: A READ burst has been initiated, with AUTO PRECHARGE disabled, and

has not yet terminated or been terminated.

Write: A WRITE burst has been initiated, with AUTO PRECHARGE disabled, and

has not yet terminated or been terminated.

Integrated Circuit Solution Inc.

DDR001-0A 01/13/2004

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IC43R16160

NOTE: (continued)

Read with Auto Precharge Enabled: See following text

Write with Auto Precharge Enabled: See following text

3a. The Read with Auto Precharge Enabled or Write with Auto Precharge Enabled states can each be broken

into two parts: the access period and the precharge period. For Read with Auto Precharge, the precharge

period is defined as if the same burst was executed with Auto Precharge disabled and then followed with the

earliest possible PRECHARGE command that still accesses all of the data in the burst. For Write with Auto

Precharge, the precharge period begins when tWR ends, with tWR measured as if Auto Precharge was

disabled. The access period starts with registration of the command and ends where the precharge period

t

(or RP) begins.

During the precharge period of the Read with Auto Precharge Enabled or Write with Auto Precharge Enabled

states, ACTIVE, PRECHARGE, READ and WRITE commands to the other bank may be applied; during the

access period, only ACTIVE and PRECHARGE commands to the other bank may be applied. In either case, all

other related limitations apply (e.g. contention between READ data and WRITE data must be avoided).

4. AUTO REFRESH and MODE REGISTER SET commands may only be issued when all banks are idle.

5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the

current state only.

6. All states and sequences not shown are illegal or reserved.

7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with AUTO PRECHARGE

enabled and READs or WRITEs with AUTO PRECHARGE disabled.

8. Requires appropriate DM masking.

9. A WRITE command may be applied after the completion of data output.

28

Integrated Circuit Solution Inc.

DDR001-0A 01/13/2004

IC43R16160

Simplified State Diagram

Power

Applied

Power

On

Precharge

PREALL

Self

Refresh

REFS

REFSX

MRS

Auto

MRS

REFA

Idle

EMRS

Refresh

CKEL

CKEH

Active

Power

Down

ACT

Precharge

Power

Down

CKEH

CKEL

Burst Stop

Row

Active

Read

Write

Read

Write A

Read A

Read

Write

Read A

Write A

Read

A

PRE

Write

A

Read

A

PRE

Precharge

PREALL

PRE

Automatic Sequence

Command Sequence

PREALL = Precharge All Banks

MRS = Mode Register Set

EMRS = Extended Mode Register Set

REFS = Enter Self Refresh

REFSX = Exit Self Refresh

REFA = Auto Refresh

CKEL = Enter Power Down

CKEH = Exit Power Down

ACT = Active

Write A = Write with Autoprecharge

Read A = Read with Autoprecharge

PRE = Precharge

Integrated Circuit Solution Inc.

DDR001-0A 01/13/2004

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IC43R16160

DC Operating Conditions & Specifications

DC Operating Conditions

Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)

Parameter

Supply voltage (for device with a nominal V_DDof 2.5V)

Supply voltage (V_DDof 2.6V for DDR400 device)

I/O Supply voltage

Symbol

V_DD

Min

2.3

Max

2.7

Unit

Note

V_DD

2.5

2.7

V_DDQ

V_REF

V_TT

2.3

2.7

V

I/O Supply voltage for DDR400 device

I/O Reference voltage

2.5

2.7

0.49*VDDQ

V_REF-0.04

V_REF+0.15

-0.3

0.51*VDDQ

V_REF+0.04

V_DDQ+0.3

V_REF-0.15

V_DDQ+0.3

V_DDQ+0.6

2

V

1

2

I/O Termination voltage(system)

Input logic high voltage

V

V_IH(DC)

V_IL(DC)

V_IN(DC)

V_ID(DC)

I_I

V

Input logic low voltage

V

Input Voltage Level, CK and CK inputs

Input Differential Voltage, CK and CK inputs

Input leakage current

-0.3

V

0.3

V

3

-2

uA

mA

Output leakage current

I_OZ

-5

5

Output High Current (V_OUT= 1.95V)

Output Low Current (V_OUT= 0.35V)

I_OH

-16.8

16.8

I_OL

Notes: 1. V_REFis expected to be equal to 0.5*V_DDQof the transmitting device, and to track variations in the DC level of the same. Peak-

to-peak noise on V_REFmay not exceed 2% of the DC value

2.V_TTis not applied directly to the device. V_TTis a system supply for signal termination resistors, is expected to be set equal to

V_REF, and must track variations in the DC level of V_REF

3. V_IDis the magnitude of the difference between the input level on CK and the input level on CK.

DC operating condition

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Integrated Circuit Solution Inc.

DDR001-0A 01/13/2004

IC43R16160

IDD Max Specifications and Conditions

(0°C < TA < 70°C, VDDQ=2.5V+ 0.2V, VDD=2.5 +0.2V, for DDR400 device VDDQ=2.6V+ 0.1V, VDD=2.6 +0.1V

Version

-6

Conditions

Symbol

-5

-7

Unit

Operating current - One bank Active-Precharge; tRC=tRCmin;tCK=133Mhz for

DDR266, 166Mhz for DDR333; DQ,DM and DQS inputs chang-ing twice per clock

cycle; address and control inputs changing once per clock cycle

IDD0

120

110

100

mA

Operating current - One bank operation; One bank open, BL=4

IDD1

160

30

140

25

120

20

mA

Percharge power-down standby current; All banks idle; power - down mode; CKE

=< VIL(max); tCK=133Mhz for DDR266; Vin = Vref for DQ,DQS and DM

IDD2P

Precharge Floating standby current; CS# > =VIH(min);All banks idle; CKE > =

VIH(min); tCK=133Mhz for DDR266; Address and other control inputs changing once

per clock cycle; Vin = Vref for DQ,DQS and DM

IDD2F

IDD2Q

IDD3P

52

50

30

45

44

25

38

37

20

mA

Precharge Quiet standby current; CS# > = VIH(min); All banks idle; CKE > =

VIH(min); tCK =133Mhz for DDR266; Address and other control inputs stable with

keeping >= VIH(min) or =<VIL(max); Vin = Vref for DQ ,DQS and DM

Active power - down standby current; one bank active; power-down mode; CKE=<

VIL (max); tCK =133Mhz for DDR266, 166MHZ for DDR333; Vin = Vref for DQ,DQS

and DM

Active standby current; CS# >= VIH(min); CKE>=VIH(min); one bank active; active -

precharge; tRC=tRASmax; tCK =133Mhz for DDR266, 166Mhz for DDR333; DQ, DQS

and DM inputs changing twice per clock cycle; address and other control inputs

changing once per clock cycle

IDD3N

IDD4R

90

80

70

mA

Operating current - burst read; Burst length = 2; reads; continguous burst; One bank

active; address and control inputs changing once per clock cycle; CL=2 at tCK =

133Mhz for DDR266, CL=2.5 at tCK=166Mhz for DDR333; 50% of data changing at

every burst; lout = 0 m A

270

250

230

210

190

170

Operating current - burst write; Burst length = 2; writes; continuous burst; One bank

active address and control inputs changing once per clock cycle; CL=2 at tCK =

133Mhz for DDR266 ; DQ, DM and DQS inputs changing twice per clock cycle, 50% of

input data changing at every burst

IDD4W

IDD5

Auto refresh current; tRC = tRFC(min) - 10*tCK for DDR266 at 133Mhz, 12*tCK for

DDR333; distributed refresh

210

3

200

3

190

3

mA

Self refresh current; CKE =< 0.2V; External clock should be on; tCK =133Mhz for

DDR266, 166Mhz for DDR333.

IDD6

(nomal)

Self refresh current; (Low Power)

(L)

1.8

mA

Operating current - Four bank operation; Four bank interleaving with BL=4

IDD7

400

350

300

Integrated Circuit Solution Inc.

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IC43R16160

AC Operating Conditions & Timming Specification

AC Operating Conditions

Parameter/Condition

Symbol

VIH(AC)

VIL(AC)

VID(AC)

VIX(AC)

Min

Max

Unit

V

Note

Input High (Logic 1) Voltage, DQ, DQS and DM signals

Input Low (Logic 0) Voltage, DQ, DQS and DM signals.

Input Differential Voltage, CK and CK inputs

VREF + 0.31

1

2

3

4

VREF - 0.31

VDDQ+0.6

V

0.7

V

Input Crossing Point Voltage, CK and CK inputs

0.5*VDDQ-0.2

0.5*VDDQ+0.2

V

Note:

1.Vih(max) = 4.2V. The overshoot voltage duration is < 3ns at VDD.

2. Vil(min) = -1.5V. The undershoot voltage duration is < 3ns at VSS.

3. VID is the magnitude of the difference between the input level on CK and the input on CK.

4. The value of V_IXis expected to equal 0.5*V_DDQof the transmitting device and must track variations in the DC level of the same.

ELECTRICAL CHARACTERISTICS AND AC TIMING for PC400/PC333/PC266/PC200 -Abso-

lute Specifications

(Notes: 1-5, 14-17) (0°C < T < 70°C; V Q = +2.5V ±0.2V, +2.5V ±0.2V for DDR400 device V Q = +2.6V ±0.1V, +2.5V

A

DD

±0.1V)

AC CHARACTERISTICS

PARAMETER

-5

-6

-7

SYMBOL

MIN

-0.65

0.45

5

MAX

0.65

0.55

10

MIN

-0.7

0.45

-

MAX

0.7

MIN

-0.75

0.45

-

MAX UNITS NOTES

^tAC

^TCH

^TCL

^tCK(3)

^tCK(2.5)

^tCK(2)

Access window of DQs from CK/

CK high-level width

CK

0.75

ns

^tCK

ns

0.55

12

0.55

12

30

48

CK low-level width

Clock cycle time

CL = 3

CL = 2.5

6

10

6

12

7

12

ns

7.5

10

7.5

12

7.5

12

ns

DQ and DM input hold time relative

to DQS

^tDH

^tDS

0.40

1.75

-0.6

0.45

1.75

-0.6

0.50

1.75

-0.75

0.35

ns

26,31

31

DQ and DM input setup time

relative to DQS

DQ and DM input pulse width (for

each input)

^tDIPW

^tDQSCK

^tDQSH

^tDQSL

^tDQSQ

^tDQSS

^tDSS

Access window of DQS from

0.6

0.75

CK/

CK

^tCK

ns

DQS input high pulse width

DQS input low pulse width

0.35

DQS-DQ skew, DQS to last DQ

valid, per group, per access

0.4

0.45

1.25

0.5

25,26

Write command to first DQS

latching transition

^tCK

0.72

0.2

1.25

0.75

0.2

0.75

0.2

1.25

DQS falling edge to CK rising -

setup time

32

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DDR001-0A 01/13/2004

IC43R16160

-5

-6

-7

AC CHARACTERISTICS

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS NOTES

DQS falling edge from CK rising -

hold time

^tDSH

^tCK

0.2

0.75

^tCH

^tCL

^tCH

^tCL

^tCH

^tCL

^tHP

^tHZ

Half clock period

ns

^tCK

34

18

14

Data-out high-impedance window

from CK/CK

-0.65

0.6

0.65

-0.7

0.75

0.8

0.7

-0.75

0.9

1

0.75

Data-out low-impedance window

from CK/CK

^tLZ

Address and control input hold

time (fast slew rate)

^tIH_F

^tIS_F

^tIH_s

Address and control input setup

time (fast slew rate)

0.6

Address and control input hold

time (slow slew rate)

0.7

Address and control input setup

time (slow slew rate)

^tIS_s

0.7

0.8

1

LOAD MODE REGISTER

command cycle time

^tMRD

2.00

^t

HP

-^tQHS

2.00

^t

HP

-^tQHS

^t

HP

-^tQHS

DQ-DQS hold, DQS to first DQ to

non-valid,per access

^tQH

^tQHS

^tRAS

ns

25,26

Data hold skew factor

0.5

0.6

0.75

ACTIVE to PRECHARGE com-

mand

40

70,000

42

120,000

45

120,000

35

43

ACTIVE to READ with Auto pre-

charge command

^tRAS(MIN) - (burst length * ^tCK/2)

^tRAP

^tRC

ns

ACTIVE to ACTIVE/AUTO RE-

FRESH command period

60

65

^tRFC

^tRCD

^tRP

AUTO REFRESH command period

ACTIVE to READ or WRITE delay

PRECHARGE command period

DQS read preamble

70

15

72

18

75

15

ns

46

15

18

15

ns

^tRPRE

^tRPST

^tCK

0.9

0.4

1.1

0.6

0.9

0.4

1.1

0.6

0.9

0.4

1.1

0.6

DQS read postamble

ACTIVE bank a to ACTIVE bank b

command

^tRRD

10

12

15

ns

^tWPRE

^tCK

ns

DQS write preamble

0.25

0

0.25

0

0.25

0

^tWPRES

DQS write preamble setup time

20,21

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IC43R16160

-5

-6

-7

AC CHARACTERISTICS

PARAMETER

SYMBOL

^tWPST

^tWR

MIN

0.4

15

MAX

MIN

0.4

15

MAX

MIN

0.4

15

MAX

UNITS NOTES

^tCK

19

DQS write postamble

Write recovery time

0.6

ns

Internal WRITE to READ

command delay

^tWTR

^tCK

2

^tQH - ^tDQSQ

Data valid output window

na

ns

25

^tREFI

^tVTD

Average periodic refresh interval

Terminating voltage delay to VDD

7.8

us

ns

0

Exit SELF REFRESH to non-

READ command

^tXSNR

^tCK

200

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SLEW RATE DERATING VALUES

(Notes: 14; notes appear on page 36) 0°C T

+70°C; V

= +2.5V ±0.2V, V = +2.5V ±0.2V for

A

DDQ DD

DDR400 V

= +2.6V ±0.1V, V = +2.6V ±0.1V)

DD

DDQ

ADDRESS / COMMAND

t

SLEW RATE

0.500V / ns

0.400V / ns

0.300V / ns

0.200V / ns

∆ IS

∆ IH

UNITS

ps

NOTES

14

0

+50

ps

14

+100

+150

+100

+150

ps

14

ps

14

SLEW RATE DERATING VALUES

(Note: 31; notes appear on page 37) (0°C T

+70°C; V

= +2.5V ±0.2V, V = +2.5V ±0.2V for

DDQ DD

A

DDR400 V

= +2.6V ±0.1V, V = +2.6V ±0.1V)

DD

DDQ

Date, DQS, DM

t

SLEW RATE

0.500V / ns

0.400V / ns

0.300V / ns

0.200V / ns

∆ DS

∆ DH

UNITS

ps

NOTES

31

0

+75

ps

31

+150

+225

+150

+225

ps

31

ps

31

NOTES:

1. All voltages referenced to VSS.

2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal

reference/supply voltage levels, but the related specifications and device operation are guaranteed for the

full voltage range specified.

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IC43R16160

3. Outputs measured with equivalent load:

V_TT

50Ω

Reference

Output

(V_OUT

Point

)

30pF

NOTES: (continued)

4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input

timing is still referenced to VREF (or to the crossing point for CK/CK), and parameter specifications

are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate

for the input signals used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC).

5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will

effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long

as the signal does not ring back above [below] the DC input LOW [HIGH] level).

6. VREF is expected to equal VDDQ/2 of the transmit-ting device and to track variations in the DC level

of the same. Peak-to-peak noise (non-common mode) on VREF may not exceed ±2 percent of the DC value.

Thus, from VDDQ/2, VREF is allowed ±25mV for DC error and an additional ±25mV for AC noise.

7. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected

to be set equal to VREF and must track variations in the DC level of VREF.

8. VID is the magnitude of the difference between the input level on CK and the input level on CK.

9. The value of VIX is expected to equal VDDQ/2 of the transmitting device and must track varia-tions in the

DC level of the same.

10. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle

time at CL = 2 for -6, -7 .

11. Enables on-chip refresh and address counters.

12. IDD specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate.

13. This parameter is sampled. VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V, VREF = VSS, f = 100 MHz, T A = 25°C,

VOUT(DC) = VDDQ/2, VOUT (peak to peak) = 0.2V. DM input is grouped with I/O pins, reflecting the fact that they

are matched in loading.

t

14. Command/Address input slew rate = 0.5V/ns. For -5, -6, -7 and -75 with slew rates 1V/ns and faster, IS and IH

t

are reduced to 900ps. If the slew rate is less than 0.5V/ns, timing must be derated: IS and IH has an additional 50ps

per each 100mV/ns reduction in slew rate from the 500mV/ns. If the slew rate exceeds 4.5V/ns, functionality is un-

certain.

15. The CK/CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK cross; the input

reference level for signals other than CK/CK is VREF.

16. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes,

CKE •0.3 x VDDQ is recognized as LOW.

17. The output timing reference level, as measured at the timing reference point indicated in Note 3, is VTT.

t

18. HZ and LZ transitions occur in the same access time windows as valid data transitions. These parameters

are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins

driving (LZ).

19. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this

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Integrated Circuit Solution Inc.

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IC43R16160

parameter, but system performance (bus turnaround) will degrade accordingly.

20. This is not a device limit. The device will operate with a negative value, but system performance could be

degraded due to bus turnaround.

21. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS

going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous

t

WRITE was in progress, DQS could be HIGH during this time, depending on DQSS.

t

22. MIN ( RC or RFC) for IDD measurements is the smallest multiple of CK that meets the minimum absolute value

t

for the respective parameter. RAS (MAX) for IDD measurements is the largest multiple of CK that

meets the maximum absolute value for RAS.

t

NOTES: (continued)

23. The refresh period 64ms. This equates to an average refresh rate of 7.8µs.

24. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maximum amount for any

given device.

t

25. The valid data window is derived by achieving other specifications - HP ( CK/2), DQSQ, and QH

t

( QH = HP - QHS). The data valid window derates directly porportional with the clock duty cycle and a practical data

valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55. Functionality is uncertain

when operating beyond a 45/55 ratio.

26. Referenced to x16 = LDQS with DQ0-DQ7; and UDQS with DQ8-DQ15.

27. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command

t

period ( RFC [MIN]) else CKE is LOW (i.e., during standby).

28. To maintain a valid level, the transitioning edge of the input must:

a) Sustain a constant slew rate from the current AC level through to the target AC level, VIL(AC) or VIH(AC).

b) Reach at least the target AC level.

c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC).

29. The Input capacitance per pin group will not differ by more than this maximum amount for any given device..

30. CK and CK input slew rate must be •1V/ns.

31. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/DM/DQS slew rate is less

t

than 0.5V/ns, timing must be derated: 50ps must be added to DS and DH for each 100mv/ns reduction in slew rate.

If slew rate exceeds 4V/ns, functionality is uncertain.

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IC43R16160

32. VDD must not vary more than 4% if CKE is not active while any bank is active.

NOTES: (continued)

33. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary by the same amount.

t

34. HP min is the lesser of CL minimum and CH minimum actually applied to the device CK and CK/ inputs,

collectively during bank active.

t

35. READs and WRITEs with auto precharge are not allowed to be issued until RAS(MIN) can be satisfied prior

to the internal precharge com-mand being issued.

36. Applies to x16. First DQS (LDQS or UDQS) to transition to last DQ (DQ0-DQ15) to transition valid.

t

Initial JEDEC specifications suggested this to be same as DQSQ.

37. Normal Output Drive Curves:

a) The full variation in driver pull-down current from minimum to maximum process, temperature and voltage

will lie within the outer bounding lines of the V-I curve of Figure A.

b) The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but no

guaranteed, to lie within the inner bounding lines of the V-I curve of Figure A.

c) The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie

within the outer bounding lines of the V-I curve of Figure B.

d)The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not

guaranteed, to lie within the inner bounding lines of the V-I curve of Figure B.

e) The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be

between .71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0 Volt, and at the same voltage

and temperature.

f) The full variation in the ratio of the nominal pull-up to pull-down current should be unity ±10%, for device

drain-to-source voltages from 0.1V to 1.0 Volt.

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38. Reduced Output Drive Curves:

a) The full variation in driver pull-down current from minimum to maximum process, tem-perature and voltage

will lie within the outer bounding lines of the V-I curve of Figure C.

b) The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not

guaranteed, to lie within the inner bounding lines of the V-I curve of Figure C.

c) The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie

within the outer bounding lines of the V-I curve of Figure D.

d)The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not

guaranteed, to lie within the inner bounding lines of the V-I curve of Figure D.

e) The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between

.71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0 V, and at the same voltage.

f) The full variation in the ratio of the nominal pull-up to pull-down current should be unity ±10%, for device

drain-to-source voltages from 0.1V to 1.0 V.

39. The voltage levels used are derived from the referenced test load. In practice, the voltage levels obtained from

a properly terminated bus will provide significantly different voltage values.

40. VIH overshoot: VIH(MAX) = VDDQ+1.5V for a pulse width •3ns and the pulse width can not be greater than 1/3

of the cycle rate. VIL undershoot: VIL(MIN) = -1.5V for a pulse width •3ns and the pulse width can not be greater than

1/3 of the cycle rate.

41. VDD and VDDQ must track each other.

42. During initialization, VDDQ, VTT, and VREF must be equal to or less than VDD + 0.3V. Alternatively, VTT may

be 1.35V maximum during power up, even if VDD /VDDQ are 0 volts, provided a minimum of 42 ohms of series re-

sistance is used between the VTT supply and the input pin.

43. tRAP •t RCD.

44. Random addressing changing 50% of data changing at every transfer.

45. Random addressing changing 100% of data changing at every transfer.

46. CKE must be active (high) during the entire time a refresh command is executed. That is, from the time the AUTO

REFRESH command is registered, CKE must be active at each rising clock edge, until tREF later.

47. IDD2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic level. IDD2Q is similar to IDD2F

except IDD2Q specifies the address and control inputs to remain stable. Although IDD2F, IDD2N, and IDD2Q are

similar, IDD2F is “worst case.”

48. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed

Integrated Circuit Solution Inc.

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IC43R16160

IBIS: I/V Characteristics for Input and Output Buffers

Normal strength driver

1. The nominal pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of Figure a.

2. The full variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer

bounding lines the of the V-I curve of Figure a.

Maximum

160

140

120

TypicalꢀHigh

100

80

TypicalꢀLow

60

Minimum

40

20

0

0.0

0.5

1.0

1.5

2.0

2.5

Vout(V)

3. The nominal pullup V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of below Figure b.

4. The Full variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the outer

bounding lines of the V-I curve of Figure b.

0.0

0.5

1.0

1.5

2.0

2.5

0

-20

Minumum

-40

TypicalꢀLow

-60

-80

-100

-120

-140

-160

-180

-200

-220

TypicalꢀHigh

Maximum

V_DDQꢀ—ꢀVout(V)

5. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source

voltage from 0 to VDDQ/2

6. The Full variation in the ratio of the nominal pullup to pulldown current should be unity ±10%, for device drain to source voltages from

0 to VDDQ/2

I/V characteristics for input/output buffers:Pull up(above) and pull down(below)

Pulldown Current (mA)

Pullup Current (mA)

Voltage (V)

0.1

Typical Low Typical High

6.0 6.8

Minimum

4.6

Maximum

9.6

Typical Low Typical High

-6.1 -7.6

Minimum

-4.6

Maximum

-10.0

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IC43R16160

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

12.2

18.1

24.1

29.8

34.6

39.4

43.7

47.5

51.3

54.1

56.2

57.9

59.3

60.1

60.5

61.0

61.5

62.0

62.5

62.9

63.3

63.8

64.1

64.6

64.8

65.0

13.5

20.1

26.6

33.0

39.1

44.2

49.8

55.2

60.3

65.2

69.9

74.2

78.4

82.3

85.9

89.1

92.2

95.3

97.2

99.1

100.9

101.9

102.8

103.8

104.6

105.4

9.2

18.2

26.0

-12.2

-18.1

-24.0

-29.8

-34.3

-38.1

-41.1

-41.8

-46.0

-47.8

-49.2

-50.0

-50.5

-50.7

-51.0

-51.1

-51.3

-51.5

-51.6

-51.8

-52.0

-52.2

-52.3

-52.5

-52.7

-52.8

-14.5

-21.2

-9.2

-20.0

-29.8

13.8

18.4

23.0

27.7

32.2

36.8

39.6

42.6

44.8

46.2

47.1

47.4

47.7

48.0

48.4

48.9

49.1

49.4

49.6

49.8

49.9

50.0

50.2

50.4

50.5

-13.8

-18.4

-23.0

-27.7

-32.2

-36.0

-38.2

-38.7

-39.0

-39.2

-39.4

-39.6

-39.9

-40.1

-40.2

-40.3

-40.4

-40.5

-40.6

-40.7

-40.8

-40.9

-41.0

-41.1

-41.2

33.9

-27.7

-38.8

41.8

-34.1

-46.8

49.4

-40.5

-54.4

56.8

-46.9

-61.8

63.2

-53.1

-69.5

69.9

-59.4

-77.3

76.3

-65.5

-85.2

82.5

-71.6

-93.0

88.3

-77.6

-100.6

-108.1

-115.5

-123.0

-130.4

-136.7

-144.2

-150.5

-156.9

-163.2

-169.6

-176.0

-181.3

-187.6

-192.9

-198.2

93.8

-83.6

99.1

-89.7

103.8

108.4

112.1

115.9

119.6

123.3

126.5

129.5

132.4

135.0

137.3

139.2

140.8

-95.5

-101.3

-107.1

-112.4

-118.7

-124.0

-129.3

-134.6

-139.9

-145.2

-150.5

-155.3

-160.1

Pull down and pull up current values

Temperature (Tambient)

Typical

Minimum

25°C

70°C

Maximum 0°C

Vdd/Vddq

Typical

Minimum

2.5V

2.3V

Maximum 2.7V

Integrated Circuit Solution Inc.

DDR001-0A 01/13/2004

41

IC43R16160

The above characteristics are specified under best, worst and normal process variation/conditions

Half strength driver

1. The nominal pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of Figure c.

2. The full variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer

bounding lines the of the V-I curve of Figure c.

90

Maximum

80

70

60

TypicalꢀHigh

50

40

TypicalꢀLow

Minimum

30

20

10

0

0.0

1.0

2.0

Vout(V)

3. Thenominal pullup V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of below Figure d.

4. The Full variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the outer

bounding lines of the V-I curve of Figure d.

0.0

0.5

1.0

1.5

2.0

2.5

0

-10

-20

Minumum

-30

-40

-50

-60

TypicalꢀLow

TypicalꢀHigh

-70

-80

-90

Maximum

V_DDQꢀ—ꢀVout(V)

5. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source

voltage from 0 to VDDQ/2

6. The Full variation in the ratio of the nominal pullup to pulldown current should be unity ±10%, for device drain to source voltages

from 0 to VDDQ/2

I/V characteristics for input/output buffers:Pull up(above) and pull down(below)

42

Integrated Circuit Solution Inc.

DDR001-0A 01/13/2004

IC43R16160

Pulldown Current (mA)

Pullup Current (mA)

Voltage (V) Typical Low Typical High

Minimum

2.6

Maximum

5.0

Typical Low Typical High

Minimum

-2.6

Maximum

-5.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

3.4

3.8

-3.5

-4.3

6.9

7.6

5.2

9.9

-6.9

-8.2

-5.2

-9.9

10.3

13.6

16.9

19.6

22.3

24.7

26.9

29.0

30.6

31.8

32.8

33.5

34.0

34.3

34.5

34.8

35.1

35.4

35.6

35.8

36.1

36.3

36.5

36.7

36.8

11.4

15.1

18.7

22.1

25.0

28.2

31.3

34.1

36.9

39.5

42.0

44.4

46.6

48.6

50.5

52.2

53.9

55.0

56.1

57.1

57.7

58.2

58.7

59.2

59.6

7.8

14.6

19.2

23.6

28.0

32.2

35.8

39.5

43.2

46.7

50.0

53.1

56.1

58.7

61.4

63.5

65.6

67.7

69.8

71.6

73.3

74.9

76.4

77.7

78.8

79.7

-10.3

-13.6

-16.9

-19.4

-21.5

-23.3

-24.8

-26.0

-27.1

-27.8

-28.3

-28.6

-28.7

-28.9

-29.0

-29.2

-29.3

-29.5

-29.6

-29.7

-29.8

-29.9

-12.0

-15.7

-19.3

-22.9

-26.5

-30.1

-33.6

-37.1

-40.3

-43.1

-45.8

-48.4

-50.7

-52.9

-55.0

-56.8

-58.7

-60.0

-61.2

-62.4

-63.1

-63.8

-64.4

-65.1

-65.8

-7.8

-14.6

-19.2

-23.6

-28.0

-32.2

-35.8

-39.5

-43.2

-46.7

-50.0

-53.1

-56.1

-58.7

-61.4

-63.5

-65.6

-67.7

-69.8

-71.6

-73.3

-74.9

-76.4

-77.7

-78.8

-79.7

10.4

13.0

15.7

18.2

20.8

22.4

24.1

25.4

26.2

26.6

26.8

27.0

27.2

27.4

27.7

27.8

28.0

28.1

28.2

28.3

28.4

28.5

28.6

-10.4

-13.0

-15.7

-18.2

-20.4

-21.6

-21.9

-22.1

-22.2

-22.3

-22.4

-22.6

-22.7

-22.8

-22.9

-23.0

-23.1

-23.2

-23.3

Pull down and pull up current values

Temperature (Tambient)

Typical 25°C

Minimum 70°C

Maximum 0°C

Vdd/Vddq

Typical 2.5V

Minimum 2.3V

Maximum 2.7V

Integrated Circuit Solution Inc.

DDR001-0A 01/13/2004

43

IC43R16160

The above characteristics are specified under best, worst and normal process variation/conditions

DATA INPUT (WRITE) TIMING

t

DSL DSH

DQS

t

DS

DI

n

DQ

DM

t

DH

t

DS

t

DH

DON'T CARE

DI n = Data In for column n

Burst Length = 4 in the case shown

3 subsequent elements of Data In are applied in the programmed

order following DI n

DATA OUTPUT (READ) TIMING

t

DQSQ

nom

t

DQSQ

max

t

DQSQ

max

DQS

DQ

t

DQSQ

min

DQSQ

min

1. tDQSQ max occurs when DQS is the earliest among DQS and DQ signals to transition.

2. tDQSQ min occurs when DQS is the latest among DQS and DQ signals to transition.

3. tDQSQ nom, shown for reference, occurs when DQS transitions in the center among DQ signal transitions.

DQS, DQ

t

DV

Burst Length = 4 in the case shown

44

Integrated Circuit Solution Inc.

DDR001-0A 01/13/2004

IC43R16160

INITIALIZE AND MODE REGISTER SETS

VDD

VDDQ

t

VTD

VTT

(system*)

VREF

t

CK

t

CL

CH

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

/CK

CK

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

t

IH

IS

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

CKE

LVCMOS LOW LEVEL

((

))

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

t

IS IH

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

COMMAND

DM

NOP

PRE

EMRS

MRS

PRE

AR

MRS

ACT

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

t

IS IH

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

A0-A9, A11

A10

CODE

RA

BA

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

t

IS IH

( (

) )

( (

) )

ALL BANKS

( (

) )

( (

) )

( (

) )

( (

) )

CODE

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

t

IS IH

t

IS IH

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

BA0=H,

BA1=L

BA0=L,

BA1=L

BA0=L,

BA1=L

BA0, BA1

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

High-Z

((

))

((

))

((

))

((

))

((

))

((

))

DQS

DQ

High-Z

((

))

((

))

((

))

((

))

((

))

((

))

T = 200µs

t

MRD

RP

RFC

Power-up:

VDD and

CLK stable

Extended

Mode

Register

Set

200 cycles of CLK**

Load

Mode

Register

(with A8 = L)

Load

Mode

Register,

Reset DLL

(with A8 = H)

DON'T CARE

*

= VTT is not applied directly to the device, however tVTD must be greater than or equal to zero to avoid device latch-up.

** = tMRD is required before any command can be applied, and 200 cycles of CK are required before a READ command can be applied.

The two Auto Refresh commands may be moved to follow the first MRS, but precede the second PRECHARGE ALL command.

Integrated Circuit Solution Inc.

DDR001-0A 01/13/2004

45

IC43R16160

POWER-DOWN MODE

t

CL

CK

CH

( (

) )

/CK

CK

( (

) )

t

IS

t

IS

IS IH

CKE

( (

) )

t

IS IH

( (

) )

COMMAND

VALID*

NOP

VALID

( (

) )

t

IS IH

( (

) )

ADDR

DQS

VALID

( (

) )

( (

) )

( (

) )

( (

) )

DQ

DM

( (

) )

( (

) )

( (

) )

Enter

Power-Down

Mode

Exit

Power-Down

Mode

DON'T CARE

No column accesses are allowed to be in progress at the time Power-Down is entered

* = If this command is a PRECHARGE (or if the device is already in the idle state) then the Power-Down

mode shown is Precharge Power Down. If this command is an ACTIVE (or if at least one row is already

active) then the Power-Down mode shown is Active Power Down.

46

Integrated Circuit Solution Inc.

DDR001-0A 01/13/2004

IC43R16160

AUTO REFRESH MODE

t

CL

CK

CH

( (

) )

( (

) )

( (

) )

( (

) )

/CK

CK

t

IS

IH

( (

) )

( (

) )

( (

) )

( (

) )

CKE

VALID

NOP

VALID

NOP

t

IS IH

( (

) )

( (

) )

( (

) )

( (

) )

COMMAND

NOP

PRE

NOP

AR

NOP

AR

NOP

ACT

( (

) )

( (

) )

( (

) )

( (

) )

A0-A8

A9, A11

A10

RA

( (

) )

( (

) )

( (

) )

( (

) )

ALL BANKS

ONE BANK

( (

) )

( (

) )

RA

BA

( (

) )

( (

) )

t

IS IH

( (

) )

( (

) )

( (

) )

( (

) )

BA0, BA1

DQS

*Bank(s)

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

DQ

DM

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

t

RC

RP

RC

DON'T CARE

* = "Don't Care", if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active (i.e. must precharge all active banks)

PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address, AR = AUTOREFRESH

NOP commands are shown for ease of illustration; other valid commands may be possible at these times

DM, DQ and DQS signals are all "Don't Care"/High-Z for operations shown

Integrated Circuit Solution Inc.

DDR001-0A 01/13/2004

47

IC43R16160

SELF REFRESH MODE

t

CK

clock must be stable before

exiting Self Refresh mode

( (

) )

t

CH

CL

t

( (

) )

/CK

CK

( (

) )

( (

) )

t

IS

IS IH

( (

) )

CKE

( (

) )

t

IS IH

( (

) )

( (

) )

COMMAND

NOP

AR

NOP

VALID

( (

) )

( (

) )

t

IS IH

( (

) )

( (

) )

ADDR

DQS

VALID

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

DQ

DM

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

t

XSNR/

tXSRD**

t

RP*

Enter

Self Refresh

Mode

Exit

Self Refresh

Mode

DON'T CARE

* = Device must be in the "All banks idle" state prior to entering Self Refresh mode

** = tXSNR is required before any non-READ command can be applied, and tXSRD (200 cycles of CLK)

are required before a READ command can be applied.

48

Integrated Circuit Solution Inc.

DDR001-0A 01/13/2004

IC43R16160

READ - WITHOUT AUTO PRECHARGE

t

CK

CH

CL

/CK

CK

t

IS IH

IH

CKE

VALID

NOP

VALID

NOP

VALID

NOP

StartꢀAutoprecharge

t

IS IH

COMMAND

NOP

READ

NOP

PRE

NOP

ACT

t

IS IH

x4:A0-A9

x8:A0-A8

x16:A0-A7

Col

n

RA

x4:A11

x8:A9, A11

x16:A8, A9, A11

t

IS IH

ALL BANKS

A10

RA

DIS AP

ONE BANK

t

IS IH

BA0, BA1

DM

Bank

x

*Bank

x

Bank x

t

CL = 2

RP

Case 1:

tAC/tDQSCK = min

t

DQSCK

min

t

RPST

t

RPRE

DQS

DQ

t

HZ

LZ

min

DO

n

t

LZ

AC

min

Case 2:

tAC/tDQSCK = max

t

DQSCK

max

t

RPST

RPRE

DQS

DQ

t

HZ

LZ

max

DO

n

t

LZ

AC

max

DON'T CARE

DO

n = Data Out from column n

Burst Length = 4 in the case shown

3 subsequent elements of Data Out are provided in the programmed order following DO

DIS AP = Disable Autoprecharge

n

* = "Don't Care", if A10 is HIGH at this point

PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address

NOP commands are shown for ease of illustration; other commands may be valid at these times

Integrated Circuit Solution Inc.

DDR001-0A 01/13/2004

49

IC43R16160

READ - WITH AUTO PRECHARGE

t

CK

CH

CL

/CK

CK

t

IS IH

IH

CKE

VALID

NOP

VALID

NOP

VALID

NOP

t

IS IH

COMMAND

NOP

READ

NOP

PRE

NOP

ACT

t

IS IH

x4:A0-A9

x8:A0-A8

x16:A0-A7

Col

n

RA

x4:A11

x8:A9, A11

x16:A8, A9, A11

t

IS IH

ALL BANKS

ONE BANK

A10

RA

DIS AP

t

IS IH

BA0, BA1

DM

Bank

x

*Bank

x

Bank x

t

CL = 2

RP

Case 1:

tAC/tDQSCK = min

t

DQSCK

min

t

RPST

t

RPRE

DQS

t

HZ

LZ

min

DO

n

DQ

t

LZ

AC

min

Case 2:

tAC/tDQSCK = max

t

DQSCK

max

t

RPST

RPRE

DQS

t

HZ

LZ

max

DO

n

DQ

t

LZ

AC

max

DON'T CARE

DO

n = Data Out from column n

Burst Length = 4 in the case shown

3 subsequent elements of Data Out are provided in the programmed order following DO

DIS AP = Disable Autoprecharge

n

* = "Don't Care", if A10 is HIGH at this point

PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address

NOP commands are shown for ease of illustration; other commands may be valid at these times

50

Integrated Circuit Solution Inc.

DDR001-0A 01/13/2004

IC43R16160

BANK READ ACCESS

t

CL

CK

CH

/CK

CK

t

IS

IH

CKE

t

IS IH

COMMAND

NOP

ACT

NOP

READ

NOP

PRE

NOP

ACT

t

IS IH

x4:A0-A9

x8:A0-A8

x16:A0-A7

RA

Col

n

RA

x4:A11

x8:A9, A11

x16:A8, A9, A11

RA

t

IS IH

ALL BANKS

ONE BANK

A10

RA

DIS AP

t

IS IH

BA0, BA1

Bank

x

Bank

x

*Bank

x

Bank x

t

RC

t

RAS

CL = 2

t

RCD

t

RP

DM

Case 1:

tAC/tDQSCK = min

t

DQSCK

min

t

RPST

t

RPRE

DQS

DQ

t

HZ

LZ

min

DO

n

t

AC

LZ

min

Case 2:

tAC/tDQSCK = max

t

DQSCK

max

t

RPST

RPRE

DQS

DQ

t

HZ

LZ

max

DO

n

t

LZ

AC

max

DON'T CARE

DO

n = Data Out from column n

Burst Length = 4 in the case shown

3 subsequent elements of Data Out are provided in the programmed order following DO

DIS AP = Disable Autoprecharge

n

* = "Don't Care", if A10 is HIGH at this point

PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address

NOP commands are shown for ease of illustration; other commands may be valid at these times

Note that tRCD > tRCD MIN so that the same timing applies if Autoprecharge is enabled (in which case tRAS would be limiting)

Integrated Circuit Solution Inc.

DDR001-0A 01/13/2004

51

IC43R16160

WRITE - WITHOUT AUTO PRECHARGE

t

CL

CK

CH

/CK

CK

t

IS IH

IH

CKE

VALID

NOP

t

IS IH

COMMAND

NOP

WRITE

NOP

PRE

NOP

ACT

t

IS IH

x4:A0-A9

x8:A0-A8

x16:A0-A7

Col

n

RA

x4:A11

x8:A9, A11

x16:A8, A9, A11

t

IS IH

ALL BANKS

ONE BANK

A10

RA

BA

DIS AP

t

IS IH

BA0, BA1

Bank

x

*Bank x

t

RP

t

DSH

Case 1:

DSH

tDQSS = min

t

WR

t

DQSH

t

WPST

DQSS

DQS

t

WPRES

t

DQSL

t

WPRE

DI

n

DQ

DM

t

Case 2:

tDQSS = max

DSS

t

DQSH

t

WPST

DQSS

DQS

t

WPRES

t

DQSL

t

WPRE

DI

n

DQ

DM

DON'T CARE

DI n = Data In for column n

Burst Length = 4 in the case shown

3 subsequent elements of Data In are applied in the programmed order following DI n

DIS AP = Disable Autoprecharge

* = "Don't Care", if A10 is HIGH at this point

PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address

NOP commands are shown for ease of illustration; other valid commands may be possible at these times

52

Integrated Circuit Solution Inc.

DDR001-0A 01/13/2004

IC43R16160

WRITE - WITH AUTO PRECHARGE

t

CL

CK

CH

/CK

CK

t

IS IH

CKE

VALID

NOP

VALID

NOP

VALID

NOP

t

IS IH

COMMAND

NOP

WRITE

NOP

ACT

t

IS IH

x4:A0-A9

x8:A0-A8

x16:A0-A7

Col

n

RA

x4:A11

x8:A9, A11

x16:A8, A9, A11

EN AP

A10

RA

BA

t

IS IH

BA0, BA1

Bank x

t

DAL

t

DSH

Case 1:

DSH

tDQSS = min

t

DQSH

t

WPST

DQSS

DQS

t

WPRES

t

DQSL

t

WPRE

DI

n

DQ

DM

t

Case 2:

DSS

tDQSS = max

t

DQSH

t

WPST

DQSS

DQS

t

WPRES

t

DQSL

t

WPRE

DI

n

DQ

DM

DON'T CARE

DI

n = Data In for column n

Burst Length = 4 in the case shown

3 subsequent elements of Data In are applied in the programmed order following DI

EN AP = Enable Autoprecharge

n

ACT = ACTIVE, RA = Row Address, BA = Bank Address

NOP commands are shown for ease of illustration; other valid commands may be possible at these times

Integrated Circuit Solution Inc.

DDR001-0A 01/13/2004

53

IC43R16160

BANK WRITE ACCESS

t

CL

CK

CH

/CK

CK

t

IS

IH

CKE

t

IS IH

COMMAND

NOP

ACT

NOP

WRITE

NOP

PRE

t

IS IH

x4:A0-A9

x8:A0-A8

x16:A0-A7

RA

Col

n

x4:A11

x8:A9, A11

RA

x16:A8, A9, A11

t

IS IH

ALL BANKS

ONE BANK

A10

DIS AP

t

IS IH

BA0, BA1

Bank

x

Bank

x

*Bank x

t

RAS

t

WR

RCD

t

DSH

Case 1:

DSH

tDQSS = min

t

DQSH

t

WPST

DQSS

DQS

t

WPRES

t

DQSL

t

WPRE

DI

n

DQ

DM

t

Case 2:

tDQSS = max

DSS

t

DQSH

t

WPST

DQSS

DQS

t

WPRES

t

DQSL

t

WPRE

DI

n

DQ

DM

DON'T CARE

DI

n = Data In for column n

Burst Length = 4 in the case shown

3 subsequent elements of Data In are applied in the programmed order following DI

DIS AP = Disable Autoprecharge

n

* = "Don't Care", if A10 is HIGH at this point

PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address

NOP commands are shown for ease of illustration; other valid commands may be possible at these times

54

Integrated Circuit Solution Inc.

DDR001-0A 01/13/2004

IC43R16160

Package Diagram

66-Pin TSOP-II (400 mil)

Units : Millimeters

#66

#34

(10•)

#1

#33

0.125 ^+0.075

-0.035

(1.50)

22.22 0.10

(10•)

0.10 MAX

0.25TYP

(0.71)

0.65TYP

0.65 0.08

0.30 0.08

[

]

0.075 MAX

NOTE

1. (

0 ~8

) IS REFERENCE

Integrated Circuit Solution Inc.

DDR001-0A 01/13/2004

55

IC43R16160

ORDERING INFORMATION (Pb-free Package)

Commercial Range: 0^οC to 70^οC

Frequency

Speed (ns) Order Part No.

Package

200MHz

5

IC43R16160-5T

IC43R16160-5TG

400mil TSOP-2

400mil TSOP-2(Pb-free)

166MHz

6

IC43R16160-6T

IC43R16160-6TG

400mil TSOP-2

400mil TSOP-2(Pb-free)

143MHz

7

IC43R16160-7T

IC43R16160-7TG

400mil TSOP-2

400mil TSOP-2(Pb-free)

Integrated Circuit Solution Inc.

HEADQUARTER:

NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,

HSIN-CHU, TAIWAN, R.O.C.

TEL: 886-3-5780333

Fax: 886-3-5783000

BRANCH OFFICE:

7F, NO. 106, SEC. 1, HSIN-TAI 5^THROAD,

HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.

TEL: 886-2-26962140

FAX: 886-2-26962252

http://www.icsi.com.tw

56

Integrated Circuit Solution Inc.

DDR001-0A 01/13/2004


型号：	IC43R16160L-5T
厂家：	INTEGRATED SILICON SOLUTION, INC
描述：	DRAM, 动态存储器
文件：	总56页 (文件大小：754K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IC43R16160L-5T [ISSI]

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