IS25LP128-JLLE_技术文档

IS25LP032/064/128

GENERAL DESCRIPTION

The IS25LP032/064/128 Serial Flash memory offers a versatile storage solution with high flexibility and

performance in a simplified pin count package. ISSI’s “Industry Standard Serial Interface” Flash are for systems

that require limited space, a low pin count, and low power consumption. The IS25LP032/064/128 is accessed

through a 4-wire SPI Interface consisting of a Serial Data Input (Sl), Serial Data Output (SO), Serial Clock

(SCK), and Chip Enable (CE#) pins, which can also be configured to serve as multi-I/O (see pin descriptions).

The device supports Dual and Quad I/O as well as standard, Dual Output, and Quad Output SPI. Clock

frequencies of up to 133MHz allow for equivalent clock rates of up to 532MHz (133MHz x 4) allowing more than

66Mbytes/s of data throughput. The IS25xP series of Flash adds support for DTR (Double Transfer Rate)

commands that transfer addresses and read data on both edges of the clock. These transfer rates can

outperform 16-bit Parallel Flash memories allowing for efficient memory access to support XIP (execute in

place) operation.

The memory array is organized into programmable pages of 256-bytes. This family supports page program

mode where 1 to 256 bytes of data are programmed in a single command. QPI (Quad Peripheral Interface)

supports 2-cycle instruction further reducing instruction times. Pages can be erased in groups of 4K-byte

sectors, 32K-byte blocks, 64K-byte blocks, and/or the entire chip. The uniform sector and block architecture

allows for a high degree of flexibility so that the device can be utilized for a broad variety of applications

requiring solid data retention.

GLOSSARY

Standard SPI

In this operation, a 4-wire SPI Interface is utilized, consisting of Serial Data Input (Sl), Serial Data Output (SO),

Serial Clock (SCK), and Chip Enable (CE#) pins. Instructions are sent via the SI pin to encode instructions,

addresses, or input data to the device on the rising edge of SCK. The DO pin is used to read data or to check the

status of the device on the falling edge of SCK. This device supports SPI bus operation modes (0,0) and (1,1).

Mutil I/O SPI

Multi-I/O operation utilizes an enhanced SPI protocol to allow the device to function with Dual Output, Dual Input

and Output, and Quad Input and Output capability. Executing these instructions through SPI mode will achieve

double or quadruple the transfer bandwidth for READ and PROGRAM operations.

Quad I/O QPI

The IS25LP032/064/128 enables QPI protocol by issuing an “Enter QPI mode (35h)” command. The QPI mode

uses four IO pins for input and output to decrease SPI instruction overhead and increase output bandwidth. SI

and SO pins become bidirectional IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3 respectively

during QPI mode. Issuing an “Exit QPI (F5h) command will cause the device to exit QPI mode. Power Reset or

Hardware/Software Reset can also return the device into the standard SPI mode.

DTR

In addition to SPI and QPI features, IS25LP032/064/128 also supports SPI DTR READ. SPI DTR allows high

data throughput while running at lower clock frequencies. SPI DTR READ mode uses both rising and falling

edges of the clock to drive output, resulting in reducing the dummy cycles by half.

Programmable drive strength and Selectable burst setting.

The IS25LP032/064/128 offers programmable output drive strength and selectable burst (wrap) length features

to increase the efficiency and performance of READ operations. The driver strength and burst setting features

are controlled by setting the READ registers. A total of six different drive strengths and four different burst sizes

(8/16/32/64 Bytes) are available for selection.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

3

10/03/2014

IS25LP032/064/128

TABLE OF CONTENTS

1. PIN CONFIGURATION.................................................................................................................................6

2. PIN DESCRIPTIONS....................................................................................................................................7

3. BLOCK DIAGRAM........................................................................................................................................8

4. SPI MODES DESCRIPTION ........................................................................................................................9

5. SYSTEM CONFIGURATION......................................................................................................................11

5.1 BLOCK/SECTOR ADDRESSES ..........................................................................................................11

6. REGISTERS ...............................................................................................................................................12

6.1 STATUS REGISTER ............................................................................................................................12

6.2 FUNCTION REGISTER........................................................................................................................15

6.3 READ REGISTERS..............................................................................................................................16

7. PROTECTION MODE.................................................................................................................................18

7.1 HARDWARE WRITE PROTECTION....................................................................................................18

7.2 SOFTWARE WRITE PROTECTION ....................................................................................................18

8. DEVICE OPERATION ................................................................................................................................19

8.1 NORMAL READ OPERATION (NORD, 03h).......................................................................................21

8.2 FAST READ OPERATION (FRD, 0Bh)................................................................................................23

8.3 HOLD OPERATION..............................................................................................................................25

8.4 FAST READ DUAL I/O OPERATION (FRDIO, BBh) ...........................................................................25

8.5 FAST READ DUAL OUTPUT OPERATION (FRDO, 3Bh)...................................................................28

8.6 FAST READ QUAD I/O OPERATION (FRQIO, EBh) ..........................................................................30

8.7 PAGE PROGRAM OPERATION (PP, 02h)..........................................................................................33

8.8 QUAD INPUT PAGE PROGRAM OPERATION (PPQ, 32h/38h) ........................................................35

8.9 ERASE OPERATION ...........................................................................................................................36

8.10 SECTOR ERASE OPERATION (SER, D7h/20h)...............................................................................37

8.11 BLOCK ERASE OPERATION (BER32K:52h, BER64K:D8h) ............................................................38

8.12 CHIP ERASE OPERATION (CER, C7h/60h).....................................................................................40

8.13 WRITE ENABLE OPERATION (WREN, 06h) ....................................................................................41

8.14 WRITE DISABLE OPERATION (WRDI, 04h).....................................................................................42

8.15 READ STATUS REGISTER OPERATION (RDSR, 05h) ...................................................................43

8.16 WRITE STATUS REGISTER OPERATION (WRSR, 01h).................................................................44

8.17 READ FUNCTION REGISTER OPERATION (RDFR, 48h)...............................................................45

8.18 WRITE FUNCTION REGISTER OPERATION (WRFR, 42h).............................................................46

8.19 ENTER QUAD PERIPHERAL INTERFACE (QPI) MODE OPERATION (QIOEN,35h; QIODI,F5h) .47

8.20 PROGRAM/ERASE SUSPEND & RESUME......................................................................................48

8.21 DEEP POWER DOWN (DP, B9h) ......................................................................................................49

8.22 RELEASE DEEP POWER DOWN (RDPD, ABh)...............................................................................50

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

4

10/03/2014

IS25LP032/064/128

8.23 SET READ PARAMETERS OPERATION (SRP, C0h) ......................................................................51

8.24 READ PRODUCT IDENTIFICATION (RDID, ABh) ............................................................................53

8.25 READ PRODUCT IDENTIFICATION BY JEDEC ID OPERATION (RDJDID, 9Fh; RDJDIDQ, AFh) 55

8.26 READ DEVICE MANUFACTURER AND DEVICE ID OPERATION (RDMDID, 90h)........................56

8.27 READ UNIQUE ID NUMBER (RDUID, 4Bh) ......................................................................................57

8.28 READ SFDP OPERATION (RDSFDP, 5Ah) ......................................................................................58

8.29 NO OPERATION (NOP, 00h).............................................................................................................58

8.30 SOFTWARE RESET (RESET-ENABLE (RSTEN, 66h) AND RESET (RST, 99h)) AND HARDWARE

RESET........................................................................................................................................................59

8.31 SECURITY INFORMATION ROW......................................................................................................60

8.32 INFORMATION ROW ERASE OPERATION (IRER, 64h).................................................................61

8.33 INFORMATION ROW PROGRAM OPERATION (IRP, 62h) .............................................................62

8.34 INFORMATION ROW READ OPERATION (IRRD, 68h) ...................................................................63

8.35 FAST READ DTR MODE OPERATION (FRDTR, 0Dh).....................................................................64

8.36 FAST READ DUAL IO DTR MODE OPERATION (FRDDTR, BDh) ..................................................66

8.37 FAST READ QUAD IO DTR MODE OPERATION (FRQDTR, EDh) .................................................69

8.38 SECTOR LOCK/UNLOCK FUNCTIONS............................................................................................72

9. ELECTRICAL CHARACTERISTICS...........................................................................................................74

9.1 ABSOLUTE MAXIMUM RATINGS ⁽¹⁾...................................................................................................74

9.2 OPERATING RANGE...........................................................................................................................74

9.3 DC CHARACTERISTICS......................................................................................................................74

9.4 AC MEASUREMENT CONDITIONS ....................................................................................................75

9.5 AC CHARACTERISTICS......................................................................................................................76

9.6 SERIAL INPUT/OUTPUT TIMING........................................................................................................78

9.7 POWER-UP AND POWER-DOWN ......................................................................................................80

9.8 PROGRAM/ERASE PERFORMANCE.................................................................................................81

9.9 RELIABILITY CHARACTERISTICS .....................................................................................................81

10.

PACKAGE TYPE INFORMATION.........................................................................................................82

10.1 8-Pin JEDEC 208mil Broad Small Outline Integrated Circuit (SOIC) Package (JB) ........................82

10.2 8-Contact Ultra-Thin Small Outline No-Lead (WSON) Package 6x5mm (JK)..................................83

10.3 8-Contact Ultra-Thin Small Outline No-Lead (WSON) Package 8x6mm (JL)..................................84

10.4 8-Pin 208mil VSOP Package (JF) ....................................................................................................85

10.5 16-lead Plastic Small Outline package (300 mils body width) (JM)..................................................86

10.6 24-Ball Thin Profile Fine Pitch BGA 6x8mm (JG).............................................................................87

ORDERING INFORMATION- Valid Part Numbers................................................................................88

11.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

5

10/03/2014

IS25LP032/064/128

1. PIN CONFIGURATION

CE#

Vcc

1

2

8

7

Vcc

8

CE# 1

HOLD# (IO3) ⁽¹⁾

SO (IO1)

HOLD# (IO3) ⁽¹⁾

SCK

2

7

6

5

WP# (IO2)

GND

3

4

SCK

WP# (IO2)

GND

3

4

6

5

SI (IO0)

8-pin WSON 6x5mm

8-pin WSON 8x6mm

8-pin SOIC 208mil

8-pin VSOP 208mil

Top View, Balls Facing Down

(1)

HOLD# (IO3)

Vcc

SCK

16

1

2

3

4

5

6

7

8

A1

NC

B1

A2

NC

B2

A3

NC

B3

A4

NC

SI (IO0)

NC

15

14

13

12

11

10

9

B4

NC

C1

NC

D1

NC

E1

SCK

C2

GND

C3

VCC

C4

NC

CE#

D2

NC

D3

WP#(IO2)

D4

NC

(1)

SO(IO1) SI(IO0) HOLD#(IO3)

NC

E2

NC

F2

E3

NC

F3

E4

NC

F4

NC

F1

GND

WP# (IO2)

CE#

NC

SO (IO1)

16-pin SOIC 300mil

24-ball TFBGA 6x8mm

Note1: For RESET# pin option instead of HOLD# pin, call Factory.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

6

10/03/2014

IS25LP032/064/128

2. PIN DESCRIPTIONS

SYMBOL

TYPE

DESCRIPTION

Chip Enable: The Chip Enable (CE#) pin enables and disables the devices

operation. When CE# is high the device is deselected and output pins are in a high

impedance state. When deselected the devices non-critical internal circuitry power

down to allow minimal levels of power consumption while in a standby state.

When CE# is pulled low the device will be selected and brought out of standby

mode. The device is considered active and instructions can be written to, data read,

and written to the device. After power-up, CE# must transition from high to low

before a new instruction will be accepted.

CE#

INPUT

Keeping CE# in a high state deselects the device and switches it into its low power

state. Data will not be accepted when CE# is high.

Serial Data Input, Serial Output, and IOs (SI, SO, IO0, and IO1):

This device supports standard SPI, Dual SPI, and Quad SPI operation. Standard SPI

instructions use the unidirectional SI (Serial Input) pin to write instructions,

addresses, or data to the device on the rising edge of the Serial Clock (SCK).

Standard SPI also uses the unidirectional SO (Serial Output) to read data or status

from the device on the falling edge of the serial clock (SCK).

SI (IO0),

SO (IO1)

INPUT/OUTPUT

In Dual and Quad SPI mode, SI and SO become bidirectional IO pins to write

instructions, addresses or data to the device on the rising edge of the Serial Clock

(SCK) and read data or status from the device on the falling edge of SCK. Quad SPI

instructions use the WP# and HOLD# pins as IO2 and IO3 respectively.

Write Protect/Serial Data IO (IO2): The WP# pin protects the Status Register from

being written. When the WP# is low the status registers are write-protected and vice-

versa for high. When the QE bit is set to “1”, the WP# pin (Write Protect) function is

not available since this pin is used for IO2.

WP# (IO2)

HOLD# or RESET#/Serial Data IO (IO3): When the QE bit of Status Register is set

to “1”, HOLD# pin or RESET# is not available since it becomes IO3. When QE=0 the

pin acts as HOLD# or RESET#.

RESET# pin can be selected with dedicated parts (Call Factory).

The HOLD# pin allows the device to be paused while it is selected. It pauses serial

communication by the master device without resetting the serial sequence. The

HOLD# pin is active low. When HOLD# is in a low state and CE# is low, the SO pin

will be at high impedance. Device operation can resume when HOLD# pin is brought

to a high state.

HOLD# or

RESET# (IO3)

INPUT/OUTPUT

RESET# pin is a hardware RESET signal. When RESET# is driven HIGH, the

memory is in the normal operating mode. When RESET# is driven LOW, the memory

enters reset mode and output is High-Z. If RESET# is driven LOW while an internal

WRITE, PROGRAM, or ERASE operation is in progress, data may be lost.

SCK

Vcc

INPUT

POWER

GROUND

Unused

Serial Data Clock: Synchronized Clock for input and output timing operations.

Power: Device Core Power Supply

GND

NC

Ground: Connect to ground when referenced to Vcc

NC: Pins labeled “NC” stand for “No Connect” and should be left uncommitted.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

7

10/03/2014

IS25LP032/064/128

3. BLOCK DIAGRAM

Control Logic

High Voltage Generator

Status

Register

I/O Buffers and

Data Latches

256 Bytes

Page Buffer

CE#

SCK

WP#

(IO2)

Y-Decoder

SI

(IO0)

SO

(IO1)

HOLD# or RESET#⁽¹⁾

(IO3)

Memory Array

Address Latch &

Counter

Note1: For RESET# pin option instead of HOLD# pin, call Factory.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

8

10/03/2014

IS25LP032/064/128

4. SPI MODES DESCRIPTION

Multiple IS25LP032/064/128 devices can be connected on the SPI serial bus and controlled by a SPI Master,

i.e. microcontroller, as shown in Figure 4.1. The devices support either of two SPI modes:

Mode 0 (0, 0)

Mode 3 (1, 1)

The difference between these two modes is the clock polarity. When the SPI master is in stand-by mode, the

serial clock remains at “0” (SCK = 0) for Mode 0 and the clock remains at “1” (SCK = 1) for Mode 3. Please refer

to Figure 4.2 and Figure 4.3 for SPI and QPI mode. In both modes, the input data is latched on the rising edge

of Serial Clock (SCK), and the output data is available from the falling edge of SCK.

Figure 4.1 Connection Diagram among SPI Master and SPI Slaves (Memory Devices)

SDO

SDI

SPI interface with

(0,0) or (1,1)

SCK

SCK SO SI

SPI Master

(i.e. Microcontroller)

SPI

Memory

Device

Memory

Device

Memory

Device

CS3

CS2

CS1

CE#

HOLD# or⁽¹⁾

HOLD# or ⁽¹⁾

HOLD# or⁽¹⁾

WP#

RESET

RESET#

Notes:

1. For RESET# pin option instead of HOLD# pin, call Factory.

2. SI and SO pins become bidirectional IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3 respectively

during QPI mode.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

9

10/03/2014

IS25LP032/064/128

Figure 4.2 SPI Mode Support

SCK

Mode 0 (0,0)

SCK

Mode 3 (1,1)

MSB

SI

SO

MSB

Figure 4.3 QPI Mode Support

CE#

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Mode 3

Mode 0

SCK

3-byte Address

Mode Bits

Data 1

Data 2

Data 3

...

IO0

IO1

4

5

6

7

4

5

6

7

C4

C5

C6

C7

C0

C1

C2

C3

0

1

2

3

4

5

6

7

0

1

2

3

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

20

21

22

23

16

17

18

19

12

13

14

15

8

9

IO2

IO3

10

11

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

10

10/03/2014

IS25LP032/064/128

5. SYSTEM CONFIGURATION

The memory array of IS25LP032/064/128 is divided into uniform 4 Kbyte sectors or uniform 32K/64 Kbyte

blocks (a block consists of eight/sixteen adjacent sectors respectively).

Table 5.1 illustrates the memory map of the device. The Status Register controls how the memory is mapped.

5.1 BLOCK/SECTOR ADDRESSES

Table 5.1 Block/Sector Addresses of IS25LP032/064/128

Sector

Block No.

(64Kbyte)

Block No.

(32Kbyte)

Memory Density

Sector No.

Size

(KBytes)

Address Range

Sector 0

4

:

000000h – 000FFFh

Block 0

Block 1

Block 2

Block 3

Block 4

Block 5

:

Block 0

Block 1

Block 2

:

Sector 15

4

:

00F000h - 00FFFFh

Sector 16

010000h – 010FFFh

:

Sector 31

4

:

01F000h - 01FFFFh

32Mb

Sector 32

020000h - 0200FFh

:

Sector 47

4

:

02F000h – 02FFFFh

64Mb

:

Block 126

:

Block 63

Block 127

Sector 1023

4

3FF000h – 3FFFFFh

:

128Mb

:

Block 127

:

Block 255

Sector 2047

4

:

7FF000h – 7FFFFFh

:

Sector 4064

4

:

FE0000h – FE0FFFh

Block 508

Block 509

Block 510

Block 511

:

Block 254

Block 255

:

Sector 4079

4

:

FEF000h – FEFFFFh

Sector 4080

FF0000h – FF0FFFh

:

Sector 4095

4

FFF000h – FFFFFFh

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

11

10/03/2014

IS25LP032/064/128

6. REGISTERS

The IS25LP032/064/128 has three sets of Registers: Status, Function and Read.

6.1 STATUS REGISTER

Status Register Format and Status Register Bit Definitions are described in Tables 6.1 & 6.2.

Table 6.1 Status Register Format

Bit 7

SRWD

0

Bit 6

QE

0

Bit 5

BP3

0

Bit 4

BP2

0

Bit 3

BP1

0

Bit 2

BP0

0

Bit 1

WEL

0

Bit 0

WIP

0

Default (Flash bit)

Table 6.2 Status Register Bit Definition

Read-

/Write

Non-Volatile

bit

Bit

Name

Definition

Write In Progress Bit:

"0" indicates the device is ready(default)

"1" indicates a write cycle is in progress and the device is busy

Write Enable Latch:

"0" indicates the device is not write enabled (default)

"1" indicates the device is write enabled

Bit 0

WIP

R

No

Bit 1

WEL

R/W

Bit 2

Bit 3

Bit 4

Bit 5

BP0

BP1

BP2

BP3

Block Protection Bit: (See Tables 6.3 for details)

"0" indicates the specific blocks are not write-protected (default)

"1" indicates the specific blocks are write-protected

Yes

Quad Enable bit:

Bit 6

Bit 7

QE

“0” indicates the Quad output function disable (default)

“1” indicates the Quad output function enable

Status Register Write Disable: (See Table 7.1 for details)

"0" indicates the Status Register is not write-protected (default)

"1" indicates the Status Register is write-protected

R/W

Yes

SRWD

The BP0, BP1, BP2, BP3, SRWD, and QE are non-volatile memory cells that can be written by a Write Status

Register (WRSR) instruction. The default value of the BP2, BP1, BP0, and SRWD bits were set to “0” at factory.

The Status Register can be read by the Read Status Register (RDSR).

The function of Status Register bits are described as follows:

WIP bit: The Write In Progress (WIP) bit is read-only, and can be used to detect the progress or completion of a

program or erase operation. When the WIP bit is “0”, the device is ready for write status register, program or

erase operation. When the WIP bit is “1”, the device is busy.

WEL bit: The Write Enable Latch (WEL) bit indicates the status of the internal write enable latch. When the

WEL is “0”, the write enable latch is disabled and all write operations, including write status register, write

configuration register, page program, sector erase, block and chip erase operations are inhibited. When the

WEL bit is “1”, write operations are allowed. The WEL bit is set by a Write Enable (WREN) instruction. Each

write register, program and erase instruction must be preceded by a WREN instruction. The WEL bit can be

reset by a Write Disable (WRDI) instruction. It will automatically reset after the completion of any write operation.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

12

10/03/2014

IS25LP032/064/128

BP3, BP2, BP1, BP0 bits: The Block Protection (BP3, BP2, BP1 and BP0) bits are used to define the portion of

the memory area to be protected. Refer to Tables 6.3 for the Block Write Protection (BP) bit settings. When a

defined combination of BP3, BP2, BP1 and BP0 bits are set, the corresponding memory area is protected. Any

program or erase operation to that area will be inhibited.

Note: A Chip Erase (CER) instruction will be ignored unless all the Block Protection Bits are “0”s.

SRWD bit: The Status Register Write Disable (SRWD) bit operates in conjunction with the Write Protection

(WP#) signal to provide a Hardware Protection Mode. When the SRWD is set to “0”, the Status Register is not

write-protected. When the SRWD is set to “1” and the WP# is pulled low (VIL), the bits of Status Register

(SRWD, BP3, BP2, BP1, BP0) become read-only, and a WRSR instruction will be ignored. If the SRWD is set to

“1” and WP# is pulled high (VIH), the Status Register can be changed by a WRSR instruction.

QE bit: The Quad Enable (QE) is a non-volatile bit in the status register that allows quad operation. When the

QE bit is set to “0”, the pin WP# and HOLD# are enabled. When the QE bit is set to “1”, the IO2 and IO3 pins

are enabled.

WARNING: The QE bit must be set to 0 if WP# or HOLD# pin is tied directly to the power supply or ground.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

13

10/03/2014

IS25LP032/064/128

Table 6.3 Block (64Kbyte) assignment by Block Write Protect (BP) Bits

Status Register Bits

Protected Memory Area (IS25LP128, 256Blocks)

BP3

0

BP2

0

BP1

0

BP0 TBS(T/B selection) = 0, TOP area

TBS(T/B selection) = 1, Bottom area

0( None)

0

1

0

1

0

1

0

1

0

1

x

0( None)

0

1(1 block : 255th)

1(1 block : 0th)

0

1

2(2 blocks : 254th and 255th)

3(4 blocks : 252nd to 255th)

4(8 blocks : 248th to 255th)

5(16 blocks :240th to 255th)

6(32 blocks : 224th to 255th)

7(64 blocks : 192nd to 255th)

8(128 blocks : 128th to 255th)

9(256 blocks : 0th to 255th) All blocks

10-11(256 blocks : 0th to 255th) All blocks

12-15(256 blocks : 0th to 255th) All blocks

2(2 blocks : 0th and 1st)

0

1

3(4 blocks : 0th to 3rd)

0

1

0

4(8 blocks : 0th to 7th)

0

1

0

5(16 blocks : 0th to 15th)

6(32 blocks : 0th to 31st)

0

1

0

1

7(64 blocks : 0th to 63rd)

8(128 blocks : 0th to 127th)

9(256 blocks : 0th to 255th) All blocks

10-11(256 blocks : 0th to 255th) All blocks

12-15(256 blocks : 0th to 255th) All blocks

1

0

1

0

1

0

1

x

Status Register Bits

Protected Memory Area(IS25LP064, 128Blocks)

BP3

0

BP2

0

BP1

0

BP0 TBS(T/B selection) = 0, TOP area

TBS(T/B selection) = 1, Bottom area

0( None)

0

1

0

1

0

1

0

1

x

0( None)

0

1(1 block : 127th)

1(1 block : 0th)

0

1

2(2 blocks : 126th and 127th)

3(4 blocks : 124th to 127th)

4(8 blocks : 120th to 127th)

5(16 blocks :112nd to 127th)

6(32 blocks : 96th to 127th)

7(64 blocks : 64th to 127th)

8~15(128 blocks : 0th to 127th) All blocks

2(2 blocks : 0th and 1st)

3(4 blocks : 0th to 3rd)

4(8 blocks : 0th to 7th)

0

1

0

1

0

1

0

5(16 blocks : 0th to 15th)

6(32 blocks : 0th to 31st)

7(64 blocks : 0th to 63rd)

8~15(128 blocks : 0th to 127th) All blocks

0

1

0

1

x

Status Register Bits

Protected Memory Area(IS25LP032, 64Blocks)

BP3

0

BP2

0

BP1

0

BP0 TBS(T/B selection) = 0, TOP area

TBS(T/B selection) = 1, Bottom area

0( None)

0

1

0

1

0

1

0

1

x

0( None)

0

1(1 block : 63rd)

1(1 block : 0th)

0

1

2(2 blocks : 62nd and 63rd)

3(4 blocks : 60th to 63rd)

4(8 blocks : 56th to 63rd)

5(16 blocks :48th to 63rd)

6(32 blocks : 32nd to 63rd)

7(64 blocks : 0th to 63rd) All blocks

8~15(64 blocks : 0th to 63rd) All blocks

2(2 blocks : 0th and 1st)

3(4 blocks : 0th to 3rd)

0

1

0

1

0

4(8 blocks : 0th to 7th)

0

1

0

5(16 blocks : 0th to 15th)

6(32 blocks : 0th to 31st)

7(64 blocks : 0th to 63rd) All blocks

8~15(64 blocks : 0th to 63rd) All blocks

0

1

0

1

x

Note: x is don’t care

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

14

10/03/2014

IS25LP032/064/128

6.2 FUNCTION REGISTER

Function Register Format and Bit definition are described in Table 6.4 and 6.5

Table 6.4 Function Register Format

Bit 7

IRL3

0

Bit 6

IRL2

0

Bit 5

IRL1

0

Bit 4

IRL0

0

Bit 3

ESUS

0

Bit 2

PSUS

0

Bit 1

TBS

0

Bit 0

Reserved

0

Default

Table 6.5 Function Register Bit Definition

Read-

/Write

Non-Volatile

bit

Bit

Name

Definition

Bit 0

Reserved

Top/Bottom Selection. (See Tables 6.3 for details)

“0” indicates Top area.

“1” indicates Bottom area.

Top/Bottom

Selection

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

R/W

Yes

No

Program suspend bit:

PSUS

“0” indicates program is not suspend

“1” indicates program is suspend

Erase suspend bit:

"0" indicates Erase is not suspend

"1" indicates Erase is suspend

Lock the information row 0:

“0” indicates the information row can be programmed

“1” indicates the information row cannot be programmed

Lock the information row 1:

“0” indicates the information row can be programmed

“1” indicates the information row cannot be programmed

Lock the information row 2:

“0” indicates the information row can be programmed

“1” indicates the information row cannot be programmed

Lock the information row 3:

“0” indicates the information row can be programmed

“1” indicates the information row cannot be programmed

R

ESUS

R

No

IR Lock 0

IR Lock 1

IR Lock 2

IR Lock 3

R/W

Yes

Note: Table 6.5 Function Register bits are only one time programmable and cannot be modified

Top/Bottom Selection: BP0~3 area assignment changed from Top or Bottom. See Tables 6.5 for details

The Program Suspend Status bit indicates when a Program operation has been suspended. The

PSUS changes to ‘1’ after a suspend command is issued during the program operation. Once the suspended

Program resumes, the PSUS bit is reset to ‘0.’

ESUS bit: The Erase Suspend Status indicates when an Erase operation has been suspended. The ESUS bit is

‘1’ after a suspend command is issued during an Erase operation. Once the suspended Erase resumes, the

ESUS bit is reset to ‘0.’

IR lock bit 0 ~ 3: The information row lock bits are programmable. If the bit set to “1”, it can’t be programmed.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

15

10/03/2014

IS25LP032/064/128

6.3 READ REGISTERS

Read Register format and Bit definitions pertaining to QPI mode are described below.

READ PARAMETER BITS

Table 6.6 defines all bits that control features in SPI/QPI modes. The ODS2, ODS1, ODS0 (P7, P6, P5) bits

provide a method to set and control driver strength. The Dummy Cycle bits (P4, P3) define how many dummy

cycles are used during various READ modes. The wrap selection bits (P2, P1, P0) define burst length with wrap

around.

The SET READ PARAMETERS Operation (SRP, C0h) is used to set all the Read Register bits, and can thereby

define the output driver strength, number of dummy cycles used during READ modes, burst length with wrap

around.

Table 6.6 Read Parameter Table

P7

ODS2

1

P6

ODS1

1

P5

ODS0

1

P4

P3

P2

P1

P0

Dummy

Cycles

Dummy

Cycles

Wrap

Enable

Burst

Length

Burst

Length

Default (Flash bit)

0

Table 6.7 Burst Length Data

P1

P0

8 bytes

16 bytes

32 bytes

64 bytes

0

1

0

1

0

1

Table 6.8 Wrap Function

Wrap around boundary

P2

0

Whole cell regardless of P1 and P0 value

Burst Length set by P1 and P0

1

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

16

10/03/2014

IS25LP032/064/128

Table 6.9 Read Dummy Cycles.

P4,P3 = 00

Read Modes

P4,P3 = 01

P4,P3 = 10

P4,P3 = 11

Max Freq

50MHz

Mode

(Default)

Normal Read

0

8

4

8

4

0

8

0

8

SPI

03h

Fast read

8

133MHz

0Bh

4cc : 84MHz

6cc : 104MHz

8cc/10cc : 133MHz

Fast read

6

10

4

QPI

0Bh

Dual IO Read ⁽¹⁾

4cc : 104MHz

8cc : 133MHz

4

SPI

BBh

Fast Read Dual Output

8

133MHz

SPI

3Bh

4cc : 84MHz

6cc : 104MHz

8cc/10cc : 133MHz

Quad IO Read ⁽²⁾

6

10

SPI , QPI

EBh

Notes:

1. When 4 dummy cycles are used the max clock frequency is 104MHz; when 8 dummy cycles are used the max

clock frequency is 133MHz.

2. When 4 dummy cycles are used the max clock frequency is 84MHz; when 6 dummy cycles are used the max clock

frequency is 104MHz; when 8 or 10 dummy cycles are used the max clock frequency is 133MHz.

3. In SPI DTR mode the dummy cycles are reduced by half.

4. Dummy cycles in the table are including Mode bit cycles.

Table 6.10 Driver Strength Table

ODS2

ODS1

ODS0

Description

Reserved

12.50%

25%

Remark

0

1

0

1

0

1

0

1

0

1

0

1

0

1

37.50%

Reserved

75%

100%

50%

Default

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

17

10/03/2014

IS25LP032/064/128

7. PROTECTION MODE

The IS25LP032/064/128 supports hardware and software write-protection mechanisms.

7.1 HARDWARE WRITE PROTECTION

The Write Protection (WP#) pin provides a hardware write protection method for BP3, BP2, BP1, BP0, SRWD,

and QE in the Status Register. Refer to the section 6.1 STATUS REGISTER.

Write inhibit voltage is 2.1V. All write sequence will be ignored when Vcc drops to 2.1V or lower.

7.2 SOFTWARE WRITE PROTECTION

The IS25LP032/064/128 also provides a software write protection feature. The Block Protection (BP3, BP2,

BP1, BP0) bits allow part or the whole memory area to be write-protected.

Table 7.1 Hardware Write Protection on Status Register

SRWD

WP#

Low

High

Status Register

Writable

0

1

0

1

Protected

Writable

Note: Before the execution of any program, erase or write status register instruction, the Write Enable Latch (WEL)

bit must be enabled by executing a Write Enable (WREN) instruction. If the WEL bit is not enabled, the

program, erase or write register instruction will be ignored.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

18

10/03/2014

IS25LP032/064/128

8. DEVICE OPERATION

The IS25LP032/064/128 utilizes an 8-bit instruction register. Refer to Table 8.1. Instruction Set for details on

instructions and instruction codes. All instructions, addresses, and data are shifted in with the most significant bit

(MSB) first on Serial Data Input (SI) or Serial Data IOs (IO0, IO1, IO2, IO3). The input data on SI or IOs is

latched on the rising edge of Serial Clock (SCK) for normal mode and both of rising and falling edges for DTR

mode after Chip Enable (CE#) is driven low (V_IL). Every instruction sequence starts with a one-byte instruction

code and is followed by address bytes, data bytes, or both address bytes and data bytes, depending on the type

of instruction. CE# must be driven high (V_IH) after the last bit of the instruction sequence has been shifted in to

end the operation.

Table 8.1 Instruction Set

Instruction

Name

Total

Bytes

Operation

Mode

Byte0

Byte1

Byte2

Byte3

Byte4

Byte5

Byte6

Normal Read

Mode

A

<7:0>

NORD

FRD

4

5

SPI

03h

0Bh

Data out

<23:16>

<15:8>

Fast Read

Mode

SPI

QPI

A

<7:0>

Dummy⁽¹⁾

Byte

Data out

<23:16>

<15:8>

A

<7:0>

Dual

Fast Read

Dual I/O

AXh^(1),(2)

Dual

Data out

FRDIO

FRDO

3

5

2

5

3

5

SPI

BBh

3Bh

EBh

0Dh

BDh

<23:16>

Dual

<15:8>

Dual

Fast Read

Dual Output

A

<7:0>

Dummy⁽¹⁾

Byte

Dual

Data out

<23:16>

<15:8>

A

<7:0>

Quad

Fast Read

Quad I/O

SPI

QPI

AXh^{(1), (2)}

Quad

Data out

FRQIO

FRDTR

FRDDTR

<23:16>

Quad

<15:8>

Quad

Fast Read

DTR Mode

SPI

QPI

A

<7:0>

Dummy⁽¹⁾

Byte

Dual

Data out

<23:16>

<15:8>

A

<7:0>

Dual

Fast Read

Dual I/O DTR

AXh^{(1), (2)}

Dual

Data out

SPI

<23:16>

Dual

<15:8>

Dual

Fast Read

Quad I/O DTR

SPI

QPI

A

<7:0>

AXh^{(1), (2)}

Quad

Data out

FRQDTR

PP

EDh

02h

<23:16>

<15:8>

Input Page

Program

4

SPI

QPI

A

<7:0>

PD

(256byte)

+ 256

<23:16>

<15:8>

Quad Input

Page Program

4

32h

38h

A

<7:0>

Quad PD

(256byte)

PPQ

SPI

+ 256

<23:16>

<15:8>

SPI

QPI

D7h

20h

A

<7:0>

SER

Sector Erase

4

1

2

<23:16>

<15:8>

BER32

(32Kb)

Block Erase

32K

SPI

QPI

A

<7:0>

52h

D8h

<23:16>

<15:8>

BER64

(64Kb)

Block Erase

64K

SPI

QPI

A

<7:0>

<23:16>

<15:8>

SPI

QPI

C7h

60h

CER

WREN

WRDI

Chip Erase

Write Enable

Write Disable

SPI

QPI

06h

04h

05h

01h

48h

SPI

QPI

Read Status

Register

SPI

QPI

RDSR⁽⁵⁾

WRSR

RDFR⁽⁵⁾

SR

Write Status

Register

SPI

QPI

WSR

Data

Read Function

Register

SPI

QPI

Data

out

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

19

10/03/2014

IS25LP032/064/128

Instruction

Name

Total

Bytes

Operation

Mode

Byte0

Byte1

Byte2

Byte3

Byte4

Byte5

Byte6

Write Function

Register

SPI

QPI

WFR

Data

WRFR

QIOEN

QIODI

2

1

42h

35h

F5h

Enter

QPI mode

SPI

QPI

Exit

QPI mode

Suspend during

program/erase

SPI

QPI

75h

B0h

PERSUS

PERRSM

DP

Resume

program/erase

SPI

QPI

7Ah

30h

Deep Power

Down

SPI

QPI

B9h

ABh

Read ID /

Release

Power Down

RDID⁽⁵⁾

RDPD

,

SPI

QPI

4

XXh⁽³⁾

ID7-ID0

Set Read

Parameters

SPI

QPI

SRP

4

1

C0h

9Fh

Data in

Read JEDEC

ID Command

RDJDID⁽⁵⁾

RDMDID⁽⁵⁾

SPI

MF7-MF0

ID15-ID8

XXh⁽³⁾

ID7-ID0

00h

01h

MF7-MF0

ID7-ID0

Read

Manufacturer

& Device ID

SPI

QPI

4

90h

XXh⁽³⁾

MF7-MF0

Read JEDEC ID

QPI mode

RDJDIDQ⁽⁵⁾

RDUID

4

5

QPI

AFh

4Bh

5Ah

MF7-MF0

ID15-ID8

ID7-ID0

Read

Unique ID

SPI

QPI

A⁽⁴⁾

<23:16>

A⁽⁴⁾

<15:8>

A⁽⁴⁾

<7:0>

Dummy

Byte

Data out

SPI

QPI

A

<7:0>

Dummy

Byte

RDSFDP

SFDP Read

<23:16>

<15:8>

Software

Reset

Enable

SPI

QPI

RSTEN

RST

1

4

66h

99h

64h

SPI

QPI

Software Reset

Erase

Information

Row

SPI

QPI

A

IRER

<23:16>

<15:8>

<7:0>

Program

Information

Row

Read

Information

Row

4

SPI

QPI

A

<7:0>

PD

(256byte)

IRP

62h

68h

+ 256

<23:16>

<15:8>

SPI

QPI

A

<7:0>

Dummy

Byte

IRRD

4

Data out

<23:16>

<15:8>

SECUN-

LOCK

SPI

QPI

A

<7:0>

Sector Unlock

Sector Lock

4

1

26h

24h

<23:16>

<15:8>

SPI

QPI

SECLOCK

Notes:

1. The number of dummy cycles depends on the value setting in the Table 6.9 Read Dummy Cycles.

2. AXh has to be counted as a part of dummy cycles. X means “don’t care”.

3. XX means “don’t care”.

4. A<23:9> are “don’t care” and A<8:4> are always “0”.

5. The maximum clock frequency is 104MHz for Vcc=2.3V~2.7V and 133MHz for Vcc=2.7V~3.6V.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

20

10/03/2014

IS25LP032/064/128

8.1 NORMAL READ OPERATION (NORD, 03h)

The NORMAL READ (NORD) instruction is used to read memory contents of the IS25LP032/064/128 at a

maximum frequency of 50MHz.

The NORD instruction code is transmitted via the Sl line, followed by three address bytes (A23 - A0) of the first

memory location to be read. A total of 24 address bits are shifted in. The first byte addressed can be at any

memory location. Upon completion, any data on the Sl will be ignored. Refer to Table 8.2 for the related

Address Key.

The first byte data (D7 - D0) is shifted out on the SO line, MSB first. A single byte of data, or up to the whole

memory array, can be read out in one NORMAL READ instruction. The address is automatically incremented by

one after each byte of data is shifted out. The read operation can be terminated at any time by driving CE# high

(VIH) after the data comes out. When the highest address of the device is reached, the address counter will roll

over to the 000000h address, allowing the entire memory to be read in one continuous READ instruction.

If the NORMAL READ instruction is issued while an Erase, Program or Write operation is in process (WIP=1)

the instruction is ignored and will not have any effects on the current operation.

Table 8.2 Address Key

Address

IS25LP032

IS25LP064

IS25LP128

A_{N (}A_MSB– A₀₎

A23 - A0 (A23,A22=X)

A23 - A0 (A23=X)

A23 - A0

X=Don’t Care

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

21

10/03/2014

IS25LP032/064/128

Figure 8.1 Normal Read Sequence

CE#

0

1

2

3

4

5

6

7

8

9

10

21

...

28

29

30

31

Mode 3

Mode 0

SCK

SI

3-byte Address

...

3

Instruction = 03h

2

1

0

23

22

High Impedance

SO

CE#

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

SCK

SI

Data Out 1

Data Out 2

SO

1

0

3

1

0

3

6

5

4

2

7

6

5

4

2

7

t_V

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

22

10/03/2014

IS25LP032/064/128

8.2 FAST READ OPERATION (FRD, 0Bh)

The FAST READ (FRD) instruction is used to read memory data at up to a 133MHz clock.

The FAST READ instruction code is followed by three address bytes (A23 - A0) and a dummy byte (8 clocks),

transmitted via the SI line, with each bit latched-in during the rising edge of SCK. Then the first data byte from

the address is shifted out on the SO line, with each bit shifted out at a maximum frequency fCT, during the falling

edge of SCK.

The first byte addressed can be at any memory location. The address is automatically incremented by one after

each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the

000000h address, allowing the entire memory to be read with a single FAST READ instruction. The FAST

READ instruction is terminated by driving CE# high (VIH). If the FAST READ instruction is issued while an

Erase, Program or Write cycle is in process (WIP=1) the instruction is ignored without affecting the current cycle.

Figure 8.2 Fast Read Sequence

CE#

0

1

2

3

4

5

6

7

8

9

10

21

...

28

29

30

31

Mode 3

Mode 0

SCK

SI

3-byte Address

...

3

Instruction = 0Bh

2

1

0

23

22

High Impedance

SO

CE#

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

SCK

SI

Dummy Byte

Data Out

t_V

SO

...

1

0

3

7

6

5

4

2

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

23

10/03/2014

IS25LP032/064/128

FAST READ QPI OPERATION (FRD QPI, 0Bh)

The FAST READ QPI (FRD QPI) instruction is used to read memory data at up to a 133MHz clock.

The FAST READ QPI instruction code (2 clocks) is followed by three address bytes (A23-A0—6clocks) and

dummy cycles, transmitted via the QPI line, with each bit latched-in during the rising edge of SCK. Then the first

data byte addressed is shifted out on the SO line, with each bit shifted out at a maximum frequency fCT, during

the falling edge of SCK.

The first byte addressed can be at any memory location. The address is automatically incremented by one after

each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the

000000h address, allowing the entire memory to be read with a single FAST READ QPI instruction. The FAST

READ QPI instruction is terminated by driving CE# high (VIH). If the FAST READ QPI instruction is issued while

an Erase, Program or Write cycle is in process (WIP=1) the instruction is ignored without affecting the current

cycle.

Figure 8.3 Fast Read Sequence, QPI Mode

CE#

0

1

2

3

4

5

6

7

8

9

13

14

15

16

17

18

Mode 3

Mode 0

SCK

t_V

...

0Bh

Instruction

23:20 19:16 15:12 11:8 7:4 3:0

Address

7:4 3:0 7:4 3:0

Data 1 Data 2

IO[3:0]

6 Dummy Cycles

Note: Number of dummy cycles depends on Read Parameter setting. Detailed information in Table 6.9 Read Dummy

Cycles.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

24

10/03/2014

IS25LP032/064/128

8.3 HOLD OPERATION

HOLD# is used in conjunction with CE# to select the IS25LP032/064/128. When the device is selected and a

serial sequence is underway, HOLD# can be used to pause the serial communication with the master device

without resetting the serial sequence. To pause, HOLD# is brought low while the SCK signal is low. To resume

serial communication, HOLD# is brought high while the SCK signal is low (SCK may still toggle during HOLD).

Inputs to SlO will be ignored while SO is in the high impedance state.

Note: HOLD is not supported in DTR mode or with QE=1.

Timing graph can be referenced in AC Parameters Figure 9.3

8.4 FAST READ DUAL I/O OPERATION (FRDIO, BBh)

The FRDIO allows the address bits to be input two bits at a time. This may allow for code to be executed directly

from the SPI in some applications.

The FRDIO instruction code is followed by three address bytes (A23 – A0) and dummy cycles, transmitted via

the IO0 and IO1 lines, with each pair of bits latched-in during the rising edge of SCK. The address MSB is input

on IO1, the next bit on IO0, and this shift pattern continues to alternate between the two lines. Depending on the

usage of AX read operation mode, a mode byte may be located after address input.

The first data byte addressed is shifted out on the IO1 and IO0 lines, with each pair of bits shifted out at a

maximum frequency fCT, during the falling edge of SCK. The MSB is output on IO1, while simultaneously the

second bit is output on IO0. Figure 8.4 illustrates the timing sequence.

The first byte addressed can be at any memory location. The address is automatically incremented by one after

each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the

000000h address, allowing the entire memory to be read with a single FRDIO instruction. FRDIO instruction is

terminated by driving CE# high (VIH).

The device supports the AX read operation by applying mode bits during dummy period. Mode bits consist of 8

bits, such as M7 to M0. Four cycles after address input are reserved for Mode bits in FRDIO execution. M7 to

M4 are important for enabling this mode. M3 to M0 become don’t care for future use. When M[7:4]=1010(Ah), it

enables the AX read operation and subsequent FRDIO execution skips command code. It saves cycles as

described in Figure 8.5. When the code is different from AXh (X: don’t care), the device exits the AX read

operation. After finishing the read operation, device becomes ready to receive a new command. SPI or QPI

mode configuration retains the prior setting. Mode bit must be applied during dummy cycles. Number of dummy

cycle in Table 6.9 includes number of mode bit cycles. If dummy cycles is configured as 4 cycles, data output

will starts right after mode bit applied.

If the FRDIO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is

ignored and will not affect the current cycle.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

25

10/03/2014

IS25LP032/064/128

Figure 8.4 Fast Read Dual I/O Sequence (with command decode cycles)

CE#

0

1

2

3

4

5

6

7

8

9

10

...

18

19

20

21

Mode 3

Mode 0

SCK

3-byte Address

Mode Bits

4

...

IO0

IO1

2

3

Instruction = 03h

0

1

6

7

22

23

20

21

18

High Impedance

...

5

19

CE#

SCK

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

t_V

...

IO0

IO1

2

3

0

1

2

0

1

2

0

1

6

7

6

7

6

7

4

2

0

1

4

Data Out 1

Data Out 2

Data Out 3

3

5

3

5

3

Notes:

1. If the mode bits=AXh (X: don’t care), it can execute the AX read mode (without command). When the mode bits are

different from AXh (X is don’t care), the device exits the AX read operation.

2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.9. Read Dummy Cycles.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

26

10/03/2014

IS25LP032/064/128

Figure 8.5 Fast Read Dual I/O Sequence (without command decode cycles)

CE#

...

0

1

2

3

11

12

13

14

15

16

17

18

19

20

21

Mode 3

Mode 0

SCK

t_V

3-byte Address

Mode Bits

Data Out

...

IO0

IO1

2

3

6

7

2

6

7

2

0

1

4

0

1

4

0

1

22

23

20

21

18

...

3

5

19

Notes:

1. If the mode bits=AXh (X: don’t care), it can execute the AX read mode (without command). When the mode bits are

different from AXh (X is don’t care), the device exits the AX read operation.

2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.9 Read Dummy Cycles.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

27

10/03/2014

IS25LP032/064/128

8.5 FAST READ DUAL OUTPUT OPERATION (FRDO, 3Bh)

The FRDO instruction is used to read memory data on two output pins each at up to a 133MHz clock.

The FRDO instruction code is followed by three address bytes (A23 – A0) and a dummy byte (8 clocks),

transmitted via the SI line, with each bit

latched-in during the rising edge of SCK. Then the first data byte addressed is shifted out on the SO and SIO lines,

with each pair of bits shifted out at a maximum frequency fCT, during the falling edge of SCK. The first bit (MSB) is

output on SO, while simultaneously the second bit is output on SIO.

The first byte addressed can be at any memory location. The address is automatically incremented by one after

each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the

000000h address, allowing the entire memory to be read with a single FRDO instruction. The FRDO instruction is

terminated by driving CE# high (VIH). If the FRDO instruction is issued while an Erase, Program or Write cycle is in

process (BUSY=1) the instruction is ignored and will not have any effects on the current cycle.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

28

10/03/2014

IS25LP032/064/128

Figure 8.6 Fast Read Dual-Output Sequence

CE#

0

1

2

3

4

5

6

7

8

9

10

21

11

28

29

30

31

Mode 3

Mode 0

SCK

3-byte Address

...

3

IO0

IO1

Instruction = 3Bh

2

1

0

23

22

High Impedance

CE#

SCK

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

t_V

IO0

IO1

0

1

...

2

6

7

4

6

7

4

2

0

1

8 Dummy Cycles

Data Out 1

Data Out 2

3

5

3

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

29

10/03/2014

IS25LP032/064/128

8.6 FAST READ QUAD I/O OPERATION (FRQIO, EBh)

The FRQIO instruction allows the address bits to be input four bits at a time. This may allow for code to be

executed directly from the SPI in some applications.

The FRQIO instruction code is followed by three address bytes (A23 – A0) and dummy cycles, transmitted via

the IO3, IO2, IO0 and IO1 lines, with each group of four bits latched-in during the rising edge of SCK. The

address of MSB inputs on IO3, the next bit on IO2, the next bit on IO1, the next bit on IO0, and continue to shift

in alternating on the four. Depending on the usage of AX read operation mode, a mode byte may be located

after address input.

The first data byte addressed is shifted out on the IO3, IO2, IO1 and IO0 lines, with each group of four bits

shifted out at a maximum frequency fCT, during the falling edge of SCK. The first bit (MSB) is output on IO3,

while simultaneously the second bit is output on IO2, the third bit is output on IO1, etc. Figure 8.7 illustrates the

timing sequence.

The first byte addressed can be at any memory location. The address is automatically incremented after each

byte of data is shifted out. When the highest address is reached, the address counter will roll over to the

000000h address, allowing the entire memory to be read with a single FRQIO instruction. FRQIO instruction is

terminated by driving CE# high (VIH).

The device supports the AX read operation by applying mode bits during dummy period. Mode bits consists of 8

bits, such as M7 to M0. Two cycles after address input are reserved for Mode bits in FRQIO execution. M7 to

M4 are important for enabling this mode. M3 to M0 become don’t care for future use. When M[7:4]=1010(Ah), it

enables the AX read operation and subsequent FRQIO execution skips command code. It saves cycles as

described in Figure 8.8. When the code is different from AXh (X: don’t care), the device exits the AX read

operation. After finishing the read operation, device becomes ready to receive a new command. SPI or QPI

mode configuration retains the prior setting. Mode bit must be applied during dummy cycles. Number of dummy

cycle in Table 6.9 includes number of mode bit cycles. If dummy cycles is configured as 6 cycles, data output

will starts right after mode bits and 4 additional dummy cycles are applied

If the FRQIO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is

ignored and will not have any effects on the current cycle.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

30

10/03/2014

IS25LP032/064/128

Figure 8.7 Fast Read Quad I/O Sequence (with command decode cycles)

CE#

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Mode 3

Mode 0

SCK

3-byte Address

IO0

IO1

4

5

6

7

Instruction = EBh

High Impedance

0

1

2

3

4

5

6

7

0

1

2

3

20

21

22

23

16

17

18

19

12

13

14

15

8

9

IO2

10

11

IO3

Mode Bits

CE#

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

SCK

6 Dummy Cycles

Data Out 1 Data Out 2 Data Out 3 Data Out 4

Data Out 5 Data Out 6

t_V

IO0

IO1

0

1

2

3

0

1

2

3

...

4

5

6

7

4

5

6

7

4

5

6

7

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

0

1

2

3

4

5

6

7

0

1

2

3

IO2

IO3

Notes:

1. If the mode bits=AXh (X: don’t care), it can execute the AX read mode (without command). When the mode bits

are different from AXh (X is don’t care), the device exits the AX read operation.

2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.9 Read Dummy Cycles.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

31

10/03/2014

IS25LP032/064/128

Figure 8.8 Fast Read Quad I/O Sequence (without command decode cycles)

CE#

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

Mode 3

Mode 0

SCK

3-byte Address

Mode Bits

Dummy Byte

Data Out 1 Data Out 2

t_V

...

IO0

IO1

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

0

1

2

3

4

5

6

7

4

5

6

7

20

21

22

23

16

17

18

19

12

13

14

15

8

9

0

1

2

3

IO2

IO3

10

11

Notes:

1. If the mode bits=AXh (X: don’t care), it can execute the AX read mode (without command). When the mode bits

are different from AXh (X is don’t care), the device exits the AX read operation.

2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.10 Read Dummy Cycles.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

32

10/03/2014

IS25LP032/064/128

8.7 PAGE PROGRAM OPERATION (PP, 02h)

The Page Program (PP) instruction allows up to 256 bytes data to be programmed into memory in a single

operation. The destination of the memory to be programmed must be outside the protected memory area set by

the Block Protection (BP2, BP1, BP0) bits. A PP instruction which attempts to program into a page that is write-

protected will be ignored. Before the execution of PP instruction, the Write Enable Latch (WEL) must be enabled

through a Write Enable (WREN) instruction.

The PP instruction code, three address bytes and program data (1 to 256 bytes) are input via the Sl line.

Program operation will start immediately after the CE# is brought high, otherwise the PP instruction will not be

executed. The internal control logic automatically handles the programming voltages and timing. During a

program operation, all instructions will be ignored except the RDSR instruction. The progress or completion of

the program operation can be determined by reading the WIP bit in Status Register via a RDSR instruction. If

the WIP bit is “1”, the program operation is still in progress. If WIP bit is “0”, the program operation has

completed.

If more than 256 bytes data are sent to a device, the address counter rolls over within the same page, the

previously latched data are discarded, and the last 256 bytes are kept to be programmed into the page. The

starting byte can be anywhere within the page. When the end of the page is reached, the address will wrap

around to the beginning of the same page. If the data to be programmed are less than a full page, the data of all

other bytes on the same page will remain unchanged.

Note: A program operation can alter “1”s into “0”s, but an erase operation is required to change “0”s back to “1”s.

A byte cannot be reprogrammed without first erasing the whole sector or block.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

33

10/03/2014

IS25LP032/064/128

Figure 8.9 Page Program Sequence

CE#

0

1

...

7

8

9

...

31

32

33

...

39

...

Mode 3

Mode 0

SCK

3-byte Address

Data In 1

Data In 256

...

SI

...

6

...

0

7

0

Instruction = 02h

High Impedance

7

23

22

SO

Figure 8.10 Page Program Sequence (QPI)

CE#

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

...

Mode 3

Mode 0

SCK

02h

23:20 19:16 15:12 11:8 7:4 3:0 7:4 3:0 7:4 3:0 7:4 3:0 7:4 3:0

IO[3:0]

Data In 1

Data In 2

Data In 3

Data In 4

Address

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

34

10/03/2014

IS25LP032/064/128

8.8 QUAD INPUT PAGE PROGRAM OPERATION (PPQ, 32h/38h)

The Quad Input Page Program instruction allows up to 256 bytes data to be programmed into memory in a

single operation with four pins (IO0, IO1, IO2 and IO3). The destination of the memory to be programmed must

be outside the protected memory area set by the Block Protection (BP3, BP2, BP1, BP0) bits. A Quad Input

Page Program instruction which attempts to program into a page that is write-protected will be ignored. Before

the execution of Quad Input Page Program instruction, the QE bit in the status register must be set to “1” and

the Write Enable Latch (WEL) must be enabled through a Write Enable (WREN) instruction.

The Quad Input Page Program instruction code, three address bytes and program data (1 to 256 bytes) are

input via the four pins (IO0, IO1, IO2 and IO3). Program operation will start immediately after the CE# is brought

high, otherwise the Quad Input Page Program instruction will not be executed. The internal control logic

automatically handles the programming voltages and timing. During a program operation, all instructions will be

ignored except the RDSR instruction. The progress or completion of the program operation can be determined

by reading the WIP bit in Status Register via a RDSR instruction. If the WIP bit is “1”, the program operation is

still in progress. If WIP bit is “0”, the program operation has completed.

If more than 256 bytes data are sent to a device, the address counter rolls over within the same page, the

previously latched data are discarded, and the last 256 bytes data are kept to be programmed into the page.

The starting byte can be anywhere within the page. When the end of the page is reached, the address will wrap

around to the beginning of the same page. If the data to be programmed are less than a full page, the data of all

other bytes on the same page will remain unchanged.

Note: A program operation can alter “1”s into “0”s, but an erase operation is required to change “0”s back to “1”s.

A byte cannot be reprogrammed without first erasing the whole sector or block.

Figure 8.11 Quad Input Page Program operation

CE#

0

1

2

3

4

5

6

7

8

9

...

31

32

33

34

35

Mode 3

Mode 0

SCK

3-byte Address

Data In 1

Data In 2

...

IO0

IO1

...

4

5

6

7

Instruction = 32h/38h

High Impedance

0

1

2

3

4

5

6

7

0

1

2

3

23

22

0

IO2

IO3

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

35

10/03/2014

IS25LP032/064/128

8.9 ERASE OPERATION

The memory array of the IS25LP032/064/128 is organized into uniform 4 Kbyte sectors or 32K/64 Kbyte uniform

blocks (a block consists of sixteen adjacent sectors).

Before a byte is reprogrammed, the sector or block that contains the byte must be erased (erasing sets bits to

“1”). In order to erase the device, there are three erase instructions available: Sector Erase (SER), Block Erase

(BER) and Chip Erase (CER). A sector erase operation allows any individual sector to be erased without

affecting the data in other sectors. A block erase operation erases any individual block. A chip erase operation

erases the whole memory array of a device. A sector erase, block erase, or chip erase operation can be

executed prior to any programming operation.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

36

10/03/2014

IS25LP032/064/128

8.10 SECTOR ERASE OPERATION (SER, D7h/20h)

A Sector Erase (SER) instruction erases a 4 Kbyte sector before the execution of a SER instruction, the Write

Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL bit is automatically reset after

the completion of sector an erase operation.

A SER instruction is entered, after CE# is pulled low to select the device and stays low during the entire

instruction sequence The SER instruction code, and three address bytes are input via SI. Erase operation will

start immediately after CE# is pulled high. The internal control logic automatically handles the erase voltage and

timing. Refer to Figure 8.12-8.13 for the Sector Erase Sequence.

During an erase operation, all instruction will be ignored except the Read Status Register (RDSR) instruction.

The progress or completion of the erase operation can be determined by reading the WIP bit in the Status

Register using a RDSR instruction. If the WIP bit is “1”, the erase operation is still in progress. If the WIP bit is

“0”, the erase operation has been completed.

Figure 8.12 Sector Erase Sequence

CE#

0

1

2

3

4

5

6

7

8

9

10

21

...

28

29

30

31

Mode 3

Mode 0

SCK

3-byte Address

...

SI

3

Instruction = D7h/20h

High Impedance

2

1

0

23

22

SO

Figure 8.13 Sector Erase Sequence (QPI)

CE#

0

1

2

3

4

5

6

7

Mode 3

SCK

Mode 0

Address

23:20 19:16 15:12 11:8 7:4 3:0

D7h/20h

IO[3:0]

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

37

10/03/2014

IS25LP032/064/128

8.11 BLOCK ERASE OPERATION (BER32K:52h, BER64K:D8h)

A Block Erase (BER) instruction erases a 32/64 Kbyte block of the IS25LP032/064/128. Before the execution of

a BER instruction, the Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL

is reset automatically after the completion of a block erase operation.

The BER instruction code and three address bytes are input via SI. Erase operation will start immediately after

the CE# is pulled high, otherwise the BER instruction will not be executed. The internal control logic

automatically handles the erase voltage and timing. Refer to Figure 8.14-8.17 for the Block Erase Sequence.

Figure 8.14 Block Erase (64k) Sequence

CE#

0

1

2

3

4

5

6

7

8

9

10

21

...

28

29

30

31

Mode 3

Mode 0

SCK

3-byte Address

...

SI

3

Instruction = D8h

2

1

0

23

22

High Impedance

SO

Figure 8.15 Block Erase (64k) Sequence (QPI)

CE#

0

1

2

3

4

5

6

7

Mode 3

Mode 0

SCK

Address

23:20 19:16 15:12 11:8 7:4 3:0

D8h

IO[3:0]

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

38

10/03/2014

IS25LP032/064/128

Figure 8.16 Block Erase Sequence (32K)

CE#

0

1

2

3

4

5

6

7

8

9

10

21

...

28

29

30

31

Mode 3

Mode 0

SCK

3-byte Address

...

SI

3

Instruction = 52h

2

1

0

23

22

High Impedance

SO

Figure 8.17 Block Erase (32K) Sequence (QPI)

CE#

0

1

2

3

4

5

6

7

Mode 3

Mode 0

SCK

Address

23:20 19:16 15:12 11:8 7:4 3:0

52h

IO[3:0]

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

39

10/03/2014

IS25LP032/064/128

8.12 CHIP ERASE OPERATION (CER, C7h/60h)

A Chip Erase (CER) instruction erases the entire memory array of a IS25LP032/064/128. Before the execution

of CER instruction, the Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL

is automatically reset after completion of a chip erase operation.

The CER instruction code is input via the SI. Erase operation will start immediately after CE# is pulled high,

otherwise the CER instruction will not be executed. The internal control logic automatically handles the erase

voltage and timing. Refer to Figure 8.18-8.19 for the Chip Erase Sequence.

Figure 8.18 Chip Erase Sequence

CE#

0

1

2

3

4

5

6

7

Mode 3

Mode 0

SCK

Instruction = C7h/60h

High Impedance

SIO

SO

Figure 8.19 Chip Erase Sequence (QPI)

CE#

0

1

Mode 3

Mode 0

SCK

C7h/60h

IO[3:0]

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

40

10/03/2014

IS25LP032/064/128

8.13 WRITE ENABLE OPERATION (WREN, 06h)

The Write Enable (WREN) instruction is used to set the Write Enable Latch (WEL) bit. The WEL bit of the

IS25LP032/064/128 is reset to the write –protected state after power-up. The WEL bit must be write enabled

before any write operation, including sector, block erase, chip erase, page program, write status register, and

write configuration register operations. The WEL bit will be reset to the write-protect state automatically upon

completion of a write operation. The WREN instruction is required before any above operation is executed.

Figure 8.20 Write Enable Sequence

CE#

0

1

2

3

4

5

6

7

Mode 3

Mode 0

SCK

Address

Instruction = 06h

SIO

SO

High Impedance

Figure 8.21 WRITE ENABLE OPERATION (QPI)

CE#

0

1

Mode 3

Mode 0

SCK

06h

IO[3:0]

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

41

10/03/2014

IS25LP032/064/128

8.14 WRITE DISABLE OPERATION (WRDI, 04h)

The Write Disable (WRDI) instruction resets the WEL bit and disables all write instructions. The WRDI

instruction is not required after the execution of a write instruction, since the WEL bit is automatically reset.

Figure 8.22 Write Disable Sequence

CE#

0

1

2

3

4

5

6

7

Mode 3

Mode 0

SCK

Instruction = 04h

SIO

SO

High Impedance

Figure 8.23 WRITE DISABLE OPERATION (QPI)

CE#

0

1

Mode 3

Mode 0

SCK

04h

IO[3:0]

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

42

10/03/2014

IS25LP032/064/128

8.15 READ STATUS REGISTER OPERATION (RDSR, 05h)

The Read Status Register (RDSR) instruction provides access to the Status Register. During the execution of a

program, erase or write status register operation, all other instructions will be ignored except the RDSR

instruction, which can be used to check the progress or completion of an operation by reading the WIP bit of

Status Register.

Figure 8.24 Read Status Register Sequence

CE#

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Mode 3

Mode 0

SCK

SI

Instruction = 05h

t_V

Data Out

SO

3

2

1

0

7

6

5

4

Figure 8.25 RDSR COMMAND (READ STATUS REGISTER) OPERATION (QPI)

CE#

0

1

2

3

Mode 3

Mode 0

SCK

t_V

IO[3:0]

05h

7:4 3:0

Data Out

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

43

10/03/2014

IS25LP032/064/128

8.16 WRITE STATUS REGISTER OPERATION (WRSR, 01h)

The Write Status Register (WRSR) instruction allows the user to enable or disable the block protection and

status register write protection features by writing “0”s or “1”s into the non-volatile BP3, BP2, BP1, BP0, QE and

SRWD bits.

Figure 8.26 Write Status Register Sequence

CE#

0

1

2

3

4

5

6

7

8

7

9

10

11

12

13

14

15

Mode 3

Mode 0

SCK

Data In

SI

Instruction = 01h

2

1

0

3

6

5

4

High Impedence

SO

Figure 8.27 WRSR COMMAND (WRITE STATUS REGISTER) OPERATION (QPI)

CE#

0

1

2

3

Mode 3

Mode 0

SCK

IO[3:0]

01h

7:4 3:0

Data In

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

44

10/03/2014

IS25LP032/064/128

8.17 READ FUNCTION REGISTER OPERATION (RDFR, 48h)

The Read Function Register (RDFR) instruction provides access to the Erase/Program suspend register. During

the execution of a program, erase or write status register suspend, which can be used to check the suspend

status.

Figure 8.28 Read Function Register Sequence

CE#

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Mode 3

Mode 0

SCK

SI

Instruction = 48h

t_V

Data Out

SO

3

2

1

0

7

6

5

4

Figure 8.29 READ FUNCTION REGISTER OPERATION (QPI) RDFR

CE#

0

1

2

3

Mode 3

Mode 0

SCK

t_V

IO[3:0]

48h

7:4 3:0

Data Out

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

45

10/03/2014

IS25LP032/064/128

8.18 WRITE FUNCTION REGISTER OPERATION (WRFR, 42h)

The Write Function Register (WRFR) instruction allows the user to select top or bottom block area by writing into

TBS bit and lock or unlock the information row by writing “0”s (IR lock) or “1”s (IR unlock) into IRL3, IRL2, IRL1,

IRL0.

Figure 8.30 Write Function Register Sequence

CE#

0

1

2

3

4

5

6

7

8

7

9

10

11

12

13

14

15

Mode 3

Mode 0

SCK

Data In

SI

Instruction = 42h

2

1

0

3

6

5

4

High Impedence

SO

Figure 8.31 WRFR COMMAND (WRITE Function REGISTER) OPERATION (QPI)

CE#

0

1

2

3

Mode 3

Mode 0

SCK

IO[3:0]

42h

7:4 3:0

Data In

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

46

10/03/2014

IS25LP032/064/128

8.19 ENTER QUAD PERIPHERAL INTERFACE (QPI) MODE OPERATION (QIOEN,35h; QIODI,F5h)

The Enter Quad I/O (QIOEN) instruction, 35h, enables the Flash device for QPI bus operation. Upon completion

of the instruction, all instructions thereafter will be 4-bit multiplexed input/output until a power cycle or an Exit

Quad I/O instruction is sent to device.

Figure 8.32 Enter Quad Peripheral Interface OPERATION (QPI)

CE#

0

1

2

3

4

5

6

7

Mode 3

Mode 0

SCK

SI

Instruction = 35h

High Impedence

SO

Figure 8.33 Exit Quad Peripheral Interface (QPI) mode OPERATION

The Exit Quad I/O instruction, F5h, resets the device to 1-bit SPI protocol operation. To execute an Exit Quad

I/O operation, the host drives CE# low, sends the Exit Quad I/O command cycle, then drives CE# high. The

device just accepts SQI (2 clocks) command cycles.

CE#

0

1

Mode 3

Mode 0

SCK

F5h

IO[3:0]

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

47

10/03/2014

IS25LP032/064/128

8.20 PROGRAM/ERASE SUSPEND & RESUME

The device allows the interruption of Sector-Erase, Block-Erase or Page-Program operations to conduct other

operations. B0h command for suspend and 30h for resume will be used. (SPI/QPI all acceptable) Function

register bit2 (PSUS) and bit3 (ESUS) are used to check whether or not the device is in suspend mode.

Suspend to read ready timing: 100µs.

Resume to another suspend timing: 400µs (recommendation).

PROGRAM/ERASE SUSPEND DURING SECTOR-ERASE OR BLOCK-Erase (PERSUS 75h/B0h)

After erase suspend, WEL bit will be disabled, therefore only read related, resume and reset commands will be

accepted (03h, 0Bh, BBh, 3Bh, EBh, 0Dh, BDh, EDh, 05h, 48h, 7Ah/30h, ABh, 9Fh, 90h, AFh, 4Bh, 5Ah, 00h,

66h and 99h, 68h).

To execute a Program/Erase Suspend operation, the host drives CE# low, sends the Program/Erase Suspend

command cycle (B0H), then drives CE# high. The Function register indicates that the erase has been

suspended by changing the ESUS bit from ‘0’ to ‘1,’ but the device will not accept another command until it is

ready. To determine when the device will accept a new command, poll the WIP bit in the Status register or wait

the specified time t_SUS. When ESUS bit is issued, the Write Enable Latch (WEL) bit will be reset.

PROGRAM/ERASE SUSPEND DURING PAGE PROGRAMMING (PERSUS 75h/B0h)

Program suspend allows the interruption of all program operations.

After a program suspend command, WEL bit will be disabled, only read related, resume and reset command

can be accepted (03h, 0Bh, BBh, 3Bh, EBh, 0Dh, BDh, EDh, 05h, 48h, 7Ah/30h, ABh, 9Fh, 90h, AFh, 4Bh, 5Ah,

00h, 66h and 99h, 68h).

To execute a Program/Erase Suspend operation, the host drives CE# low, sends the Program/Erase Suspend

command cycle (B0H), then drives CE# high. The Function register indicates that the programming has been

suspended by changing the PSUS bit from ‘0’ to ‘1,’ but the device will not accept another command until it is

ready. To determine when the device will accept a new command, poll the WIP bit in the Status register or wait

the specified time t_SUS

.

PROGRAM/ERASE RESUME (PERRSM 7A/30h)

Program/Erase Resume restarts a Program/Erase command that was suspended, and changes the suspend

status bit in the (ESUS or PSUS bits) back to ‘0’. To execute a Program/Erase Resume operation, the host

drives CE# low, sends the Program/Erase Resume command cycle (30H), then drives CE# high. A cycle is two

nibbles long, most significant nibble first. To determine if the internal, self-timed Write operation completed, poll

the WIP bit in the Status register, or wait the specified time t_SE, t_BEor t_PPfor Sector- Erase, Block-Erase, or

Page-Programming, respectively. The total write time before suspend and after resume will not exceed the

uninterrupted write times t_SE, t_BEor t_PP.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

48

10/03/2014

IS25LP032/064/128

8.21 DEEP POWER DOWN (DP, B9h)

8.22 The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption

(enter into Power-down mode). During this mode, standby current is reduced from I_sb1to I_sb2. While in the

Power-down mode, the device is not active and all Write/Program/Erase instructions are ignored. The instruction

is initiated by driving the CE# pin low and shifting the instruction code “B9h” as shown in the figure 8.34. The

CE# pin must be driven high after the instruction has been latched, or Power-down mode will not engage. Once

CE# pin driven high, the Power-down mode will be entered within the time duration of t_DP. While in the Power-

down mode only the Release from Power-down / RDID instruction, which restores the device to normal

operation, will be recognized. All other instructions are ignored, including the Read Status Register instruction

which is always available during normal operation. Ignoring all but one instruction makes the Power Down state

a useful condition for securing maximum write protection. It is available in both SPI and QPI mode.

Figure 8.34 Enter Deep Power Down Mode Operation. (SPI)

CE#

t_DP

0

1

2

3

4

5

6

7

Mode 3

Mode 0

SCK

SI

...

Instruction = B9h

Figure 8.35 Deep Power Down Sequence (QPI)

CE#

t_DP

0

1

Mode 3

Mode 0

SCK

B9h

IO[3:0]

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

49

10/03/2014

IS25LP032/064/128

8.22 RELEASE DEEP POWER DOWN (RDPD, ABh)

The Release Deep Power-down/Read Device ID instruction is a multi-purpose command. To release the device

from the Power-down mode, the instruction is issued by driving the CE# pin low, shifting the instruction code

“ABh” and driving CE# high as shown in Figure 8.36, 8.37.

Releasing the device from Power-down mode will take the time duration of tRES1 before normal operation is

restored and other instructions are accepted. The CE# pin must remain high during the tRES1 time duration. If

the Release Deep Power-down / RDID instruction is issued while an Erase, Program or Write cycle is in

progress (WIP=1) the instruction is ignored and will not have any effects on the current cycle.

Figure 8.36 Release Power Down Sequence (SPI)

CE#

t_RES1

0

1

2

3

4

5

6

7

Mode 3

Mode 0

SCK

SI

...

Instruction = ABh

Figure 8.37 Release Power Down Sequence (QPI)

CE#

t_RES1

0

1

Mode 3

SCK

Mode 0

ABh

IO[3:0]

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

50

10/03/2014

IS25LP032/064/128

8.23 SET READ PARAMETERS OPERATION (SRP, C0h)

Set Read Operational Driver Strength

This device supports configurable Operational Driver Strengths in both SPI and QPI modes by setting three bits

within the READ Register (ODS0, ODS1, ODS3). To set the ODS bits the SRP operation (C0h) instruction is

required. The device’s driver strength can be reduced as low as 12.50% of full drive strength. Details regarding

the driver strength can be found in table 6.10.

Note: The default driver strength is set to 50%

Figure 8.38 Set Read Parameters Operation.

CE#

0

1

2

3

4

5

6

7

8

7

9

10

11

12

13

14

15

Mode 3

Mode 0

SCK

SI

Instruction = C0h

High Impedance

3

Data In

2

1

0

6

5

4

SO

Figure 8.39 Set Read Parameters Operation. (QPI)

CE#

0

1

2

3

Mode 3

SCK

Mode 0

IO[3:0]

C0h

7:4 3:0

Data In

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

51

10/03/2014

IS25LP032/064/128

Read with “8/16/32/64-Byte Wrap Around”

The device is capable of burst read with wrap around in both SPI and QPI mode. The size of burst length is

configurable by using P0, P1, and P2 bits in READ register. P2 bit (Wrap enable) enables the burst mode

feature. P0 and P1 define the size of burst. Burst lengths of 8, 16, 32, and 64 bytes are supported. By default,

address increases by one up through the entire array. By setting the burst length, the data being accessed can

be limited to the length of burst boundary within a 256 byte page. The first output will be the data at the initial

address which is specified in the instruction. Following data will come out from the next address within the burst

boundary. Once the address reaches the end of boundary, it will automatically move to the first address of the

boundary. CS# high will terminate the command.

For example, if burst length of 8 and initial address being applied is 0h, following byte output will be from

address 00h and continue to 01h,..,07h, 00h, 01h… until CS# terminates the operation. If burst length of 8 and

initial address being applied is FEh(254d), following byte output will be from address FEh and continue to FFh,

F8h, F9h, FAh, FBh, FCh, FDh, and repeat from FEh until CS# terminates the operation.

The command, “SET READ PARAMETERS OPERATION (C0h)”, is used to configure the burst length. If the

following data input is one of “00h”,”01h”,”02h”, and ”03h”, the device will be in default operation mode. It will be

continuous burst read of the whole array. If the following data input is one of “04h”,”05h”,”06h”, and ”07h”, the

device will set the burst length as 8,16,32 and 64 respectively.

To exit the burst mode, another “C0h” command is necessary to set P2 to 0. Otherwise, the burst mode will be

retained until either power down or reset operation. To change burst length, another “C0h” command should be

executed to set P0 and P1 (Detailed information in Table 6.7 Burst Length Data). All read commands operate in

burst mode once the READ register is set to enable burst mode.

Refer to Figures 8.38 and 8.39 for instruction sequence.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

52

10/03/2014

IS25LP032/064/128

8.24 READ PRODUCT IDENTIFICATION (RDID, ABh)

The Release from Power-down/Read Device ID instruction is a multi-purpose instruction. It can support both SPI

and QPI modes. The Read Product Identification (RDID) instruction is for reading out the old style of 8-bit

Electronic Signature, whose values are shown as table of ID Definitions.

The RDID instruction code is followed by three dummy bytes, each bit being latched-in on SI during the rising

SCK edge. Then the Device ID is shifted out on SO with the MSB first, each bit been shifted out during the

falling edge of SCK. The RDID instruction is ended by driving CE# high. The Device ID (ID7-ID0) outputs

repeatedly if additional clock cycles are continuously sent to SCK while CE# is at low.

Table 8.3 Product Identification

Manufacturer ID

ISSI Serial Flash

Instruction

Device Density

32Mb

(MF7-MF0)

9Dh

ABh

90h

9Fh

Memory Type + Capacity

(ID15-ID0)

Device ID (ID7-ID0)

15h

16h

17h

6016h

6017h

6018h

64Mb

128Mb

Figure 8.40 Read Product Identification Sequence

CE#

0

1

...

7

8

9

...

31

32

33

...

39

40

41

...

47

Mode 3

Mode 0

SCK

SI

Instruction = ABh

3 Dummy Cyles

Data Out

t_V

Device ID

(ID7-ID0)

Device ID

(ID7-ID0)

SO

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

53

10/03/2014

IS25LP032/064/128

Figure 8.41 Read Product Identification Sequence (QPI)

CE#

0

1

2

3

4

5

...

9

10

11

12

13

Mode 3

Mode 0

SCK

t_V

Device ID Device ID

(ID7-ID0) (ID7-ID0)

ABh

6 Dummy Cyles

IO[3:0]

7:4 3:0

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

54

10/03/2014

IS25LP032/064/128

8.25 READ PRODUCT IDENTIFICATION BY JEDEC ID OPERATION (RDJDID, 9Fh; RDJDIDQ, AFh)

The JEDEC ID READ instruction allows the user to read the manufacturer and product ID of devices. Refer to

Table 8.3 Product Identification for Manufacturer ID and Device ID. After the JEDEC ID READ command (9Fh in

SPI mode, AFh in QPI mode) is input, the Manufacturer ID is shifted out MSB first followed by the 2-byte

electronic ID (ID15-ID0) that indicates memory type and density, one bit at a time. Each bit is shifted out during

the falling edge of SCK. If CE# stays low after the last bit of the 2-byte electronic ID, the Manufacturer ID and 2-

byte electronic ID will loop until CE# is pulled high.

Figure 8.42 Read Product Identification by JEDEC ID READ Sequence in SPI mode

CE#

0

1

...

7

8

9

...

15

16

17

...

23

24

25

...

31

Mode 3

Mode 0

SCK

SI

Instruction = 9Fh

Data Out

t_V

Manufacturer ID

(MF7-MF0)

Capacity

(ID7-ID0)

Memory Type

(ID15-ID8)

SO

Figure 8.43 RDJDIDQ COMMAND (Read JEDEC ID in QPI Mode) OPERATION

CE#

0

1

2

3

4

5

6

7

Mode 3

Mode 0

SCK

t_V

AFh

IO[3:0]

7:4 3:0

ID7-ID0

MF7-MF0 ID15-ID8

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

55

10/03/2014

IS25LP032/064/128

8.26 READ DEVICE MANUFACTURER AND DEVICE ID OPERATION (RDMDID, 90h)

The Read Product Identification (RDID) instruction allows the user to read the manufacturer and product ID of

devices. Refer to Table 8.3 Product Identification for manufacturer ID and device ID. The RDID instruction code

is followed by two dummy bytes and one byte address (A7~A0), each bit being latched-in on SI during the rising

edge of SCK. If one byte address is initially set as A0 = 0, then the manufacturer ID (9Dh) is shifted out on SO

with the MSB first followed by the device ID7- ID0. Each bit shifted out during the falling edge of SCK. If one

byte address is initially set as A0 = 1, then Device ID7-ID0 will be read first followed by the Manufacture ID

(9Dh). The manufacture and device ID can be read continuously alternating between the two until CE# is driven

high.

Figure 8.44 Read Product Identification by RDMDID READ Sequence

CE#

0

1

...

7

8

9

...

31

32

33

...

39

40

41

...

47

Mode 3

Mode 0

SCK

SI

Instruction = 90h

3 Byte Address

Data Out

t_V

Device ID

(ID7-ID0)

Manufacturer ID

(MF7-MF0)

SO

Notes:

1. ADDRESS A0 = 0, will output the 1-byte Manufacture ID (MF7-MF0)  1-byte device ID (ID7-ID0)

ADDRESS A0 = 1, will output the 1-byte device ID (ID7-ID0)  1-byte Manufacture ID (MF7-MF0)

2. The Manufacture and Device ID can be read continuously and will alternate from one to the other until CE# pin is pulled high.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

56

10/03/2014

IS25LP032/064/128

8.27 READ UNIQUE ID NUMBER (RDUID, 4Bh)

The Read Unique ID Number (RDUID) instruction accesses a factory-set read-only 16-byte number that is

unique to the device. The Id number can be used in conjunction with user software methods to help prevent

copying or cloning of a system. The RDUID instruction is instated by driving the CE# pin low and shifting the

instruction code (4Bh) followed by 3 address bytes and a dummy byte. After which, the 16-byte ID is shifted out

on the falling edge of SCK as shown below.

Note: 16 bytes of data will repeat as long as CE# is low and SCK is toggling.

Figure 8.45 RDUID COMMAND OPERATION

CE#

0

1

...

7

8

9

...

31

32

33

...

39

40

41

...

47

Mode 3

Mode 0

SCK

SI

Instruction = 4Bh

3 Byte Address

Dummy Byte

t_V

SO

Data Out

Table 8.4 Unique ID Addressing

A[23:16]

XXh

A[15:9]

XXh

A[8:4]

00h

A[3:0]

0h Byte address

1h Byte address

2h Byte address

XXh

00h

XXh

00h

XXh

00h

XXh

00h

Fh Byte address

Note: XX means “don’t care”.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

57

10/03/2014

IS25LP032/064/128

8.28 READ SFDP OPERATION (RDSFDP, 5Ah)

The Serial Flash Discoverable Parameters (SFDP) standard provides a consistent method of describing the

functions and features of serial Flash devices in a standard set of internal parameter tables. These parameters

can be interrogated by host system software to enable adjustments needed to accommodate divergent features

from multiple vendors. For more details please refer to the JEDEC Standard JESD216A (Serial Flash

Discoverable Parameters).

The sequence of issuing RDSFDP instruction is same as FAST_READ: CE# goes low  Send RDSFDP

instruction (5Ah)  Send 3 address bytes on SI pin  Send 1 dummy byte on SI pin  Read SFDP code on

SO  End RDSFDP operation by driving CE# high at any time during data out. Refer to ISSI’s Application note

for SFDP table. The data at the addresses that are not specified in SFDP table are undefined.

Figure 8.46 RDSFDP COMMAND (Read SFDP) OPERATION

CE#

0

1

...

7

8

9

...

31

32

33

...

39

40

41

...

47

Mode 3

Mode 0

SCK

SI

Instruction = 5Ah

3 Byte Address

Dummy Byte

t_V

SO

Data Out

8.29 NO OPERATION (NOP, 00h)

The No Operation command solely cancels a Reset Enable command and has no impact on any other

commands. It is available in both SPI and QPI modes. To execute a NOP, the host drives CE# low, sends the

NOP command cycle (00H), then drives CE# high.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

58

10/03/2014

IS25LP032/064/128

8.30 SOFTWARE RESET (RESET-ENABLE (RSTEN, 66h) AND RESET (RST, 99h)) AND HARDWARE RESET

The Software Reset operation is used as a system reset that puts the device in normal operating mode. During

the Reset operation, the value of volatile registers will default back to the value in the corresponding non-volatile

register. This operation consists of two commands: Reset-Enable (RSTEN) and Reset (RST). The operation

requires the Reset-Enable command followed by the Reset command. Any command other than the Reset

command after the Reset-Enable command will disable the Reset-Enable.

Execute the CE# pin low  sends the Reset-Enable command (66h), and drives CE# high. Next, the host drives

CE# low again, sends the Reset command (99h), and pulls CE# high.

Only for the dedicated parts that have the RESET# pin, Hardware Reset function is available. The RESET# pin

will be solely applicable in SPI mode and when the QE bit is disabled. The RESET# pin has the highest priority

among all the input signals and will reset the device to its initial power-on state regardless of the state of all

other pins (CS, IOs, SCK and WP#).

In order to activate Hardware Reset, the RESET# pin must be driven low for a minimum period of t_RESET(1µs).

Drive RESET# low for a minimum period of t_RESETwill interrupt any on-going internal and external operations,

release the device from deep power down mode¹, disable all input signals, force the output pin enter a state of

high impedance, and reset all the read parameters. If the RESET# pulse is driven for a period shorter than 1µs,

it may still reset the device, however the 1µs minimum period is recommended to ensure the reliable operation.

The required wait time after activating a HW Reset before the device will accept another instruction (t_HWRST) is

the same as the maximum value of t_SUS(100µs).

The Software/Hardware Reset during an active Program or Erase operation aborts the operation, which can

result in corrupting or losing the data of the targeted address range. Depending on the prior operation, the reset

timing may vary. Recovery from a Write operation will require more latency than recovery from other operations.

Note 1: The Status and Function Registers remain unaffected.

Figure 8.47 SOFTWARE RESET ENABLE, SOFTWARE RESET OPERATIONS (RSTEN, 66h + RST, 99h)

CE#

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Mode 3

Mode 0

SCK

Instruction = 66h

High Impedance

Instruction = 99h

SIO

SO

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

59

10/03/2014

IS25LP032/064/128

8.31 SECURITY INFORMATION ROW

The security information row is comprised of an additional 4 x 256 bytes of programmable information. The

security bits can be reprogrammed by the user. Any program security instruction issued while an erase, program

or write cycle is in progress is rejected without having any effect on the cycle that is in progress.

Table 8.5 Information Row Address

Address Assignment

A[23:16]

00h

A[15:8]

00h

A[7:0]

IRL0(Information row lock0)

Byte address

IRL1

IRL2

IRL3

00h

10h

00h

20h

00h

30h

Bit 7~4 of the Function Register is used to permanently lock the programmable memory array.

When Function Register bit IRLx = ’0’, the 256 bytes of the programmable memory array can be programmed.

When Function Register bit IRLx = ‘1’, the 256 bytes of the programmable memory array function as read only.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

60

10/03/2014

IS25LP032/064/128

8.32 INFORMATION ROW ERASE OPERATION (IRER, 64h)

Information Row Erase (IRER) instruction erases the data in the Information Row x (x: 0~3) array. Prior to the

operation, the Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL bit is

automatically reset after the completion of the operation.

The sequence of IRER operation: Pull CE# low to select the device  Send IRER instruction code  Send

three address bytes  Pull CE# high. CE# should remain low during the entire instruction sequence. Once CE#

is pulled high, Erase operation will begin immediately. The internal control logic automatically handles the erase

voltage and timing. Refer to Figure 8.48 for IRER Sequence.

Figure 8.48 IRER COMMAND (Information Row Erase) OPERATION

CE#

0

1

2

3

4

5

6

7

8

9

10

21

...

28

29

30

31

Mode 3

Mode 0

SCK

3-byte Address

...

SI

3

Instruction = 64h

2

1

0

23

22

High Impedance

SO

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

61

10/03/2014

IS25LP032/064/128

8.33 INFORMATION ROW PROGRAM OPERATION (IRP, 62h)

The Information Row Program (IRP) instruction allows up to 256 bytes data to be programmed into the memory

in a single operation. Before the execution of IRP instruction, the Write Enable Latch (WEL) must be enabled

through a Write Enable (WREN) instruction.

The IRP instruction code, three address bytes and program data (1 to 256 bytes) should be sequentially input.

Three address bytes has to be input as specified in the section 8.31 SECURITY INFORMAION ROW. Program

operation will start once the CE# goes high, otherwise the IRP instruction will not be executed. The internal

control logic automatically handles the programming voltages and timing. During a program operation, all

instructions will be ignored except the RDSR instruction. The progress or completion of the program operation

can be determined by reading the WIP bit in Status Register via a RDSR instruction. If the WIP bit is “1”, the

program operation is still in progress. If WIP bit is “0”, the program operation has completed.

If more than 256 bytes data are sent to a device, the address counter rolls over within the same page. The

previously latched data are discarded and the last 256 bytes data are kept to be programmed into the page. The

starting byte can be anywhere within the page. When the end of the page is reached, the address will wrap

around to the beginning of the same page. If the data to be programmed are less than a full page, the data of all

other bytes on the same page will remain unchanged.

Note: A program operation can alter “1”s into “0”s, but an erase operation is required to change “0”s back to “1”s.

A byte cannot be reprogrammed without first erasing the corresponding Information Row array which is one

of IR0~3.

Figure 8.49 IRP COMMAND (Information Row Program) OPERATION

CE#

0

1

...

7

8

9

...

31

32

33

...

39

...

Mode 3

Mode 0

SCK

Data In 1

Data In 256

...

3-byte Address

SI

...

6

...

0

7

0

Instruction = 62h

High Impedance

7

23

22

SO

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

62

10/03/2014

IS25LP032/064/128

8.34 INFORMATION ROW READ OPERATION (IRRD, 68h)

The IRRD instruction is used to read memory data at up to a 133MHz clock in the voltage range, 2.7V to 3.6V.

The IRRD instruction code is followed by three address bytes (A23 - A0) and a dummy byte, transmitted via the

SI line, with each bit latched-in during the rising edge of SCK. Then the first data byte addressed is shifted out

on the SO line, with each bit shifted out at a maximum frequency fCT, during the falling edge of SCK.

The address is automatically incremented after each byte of data is shifted out. When the highest address is

reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read with a

single IRRD instruction. The IRRD instruction is terminated by driving CE# high (VIH). If a IRRD instruction is

issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is ignored and will not have

any effects on the current cycle

Figure 8.50 IRRD COMMAND (Information Row Read) OPERATION

CE#

0

1

...

7

8

9

...

31

32

33

...

39

40

41

...

47

Mode 3

Mode 0

SCK

SI

Instruction = 68h

3 Byte Address

Dummy Byte

t_V

SO

Data Out

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

63

10/03/2014

IS25LP032/064/128

8.35 FAST READ DTR MODE OPERATION (FRDTR, 0Dh)

The FRDTR instruction is for doubling the data in and out. Signals are triggered on both rising and falling edge

of clock. The address is latched on both rising and falling edge of SCK, and data of each bit shifts out on both

rising and falling edge of SCK at a maximum frequency f_C2. The 2-bit address can be latched-in at one clock,

and 2-bit data can be read out at one clock, which means one bit at the rising edge of clock, the other bit at the

falling edge of clock.

The first address byte can be at any location. The address is automatically increased to the next higher address

after each byte of data is shifted out, so the whole memory can be read out in a single FRDTR instruction. The

address counter rolls over to 0 when the highest address is reached.

The sequence of issuing FRDTR instruction is: CE# goes low  Sending FRDTR instruction code (1bit per

clock)  3-byte address on SI (2-bit per clock)  4 dummy clocks on SI  Data out on SO (2-bit per clock) 

End FRDTR operation via driving CE# high at any time during data out. (Please refer to Figure 8.51)

While a Program/Erase/Write Status Register cycle is in progress, FRDTR instruction will be rejected without

any effect on the current cycle.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

64

10/03/2014

IS25LP032/064/128

Figure 8.51 FRDTR COMMAND (Fast Read DTR Mode) OPERATION

CE#

0

1

2

3

4

5

6

7

8

9

10

...

19

20

21

Mode 3

Mode 0

SCK

SI

3-byte Address

...

Instruction = 0Dh

23 22 21 20 19 18 17

0

High Impedance

SO

CE#

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

SCK

t_V

4 Dummy

Cycles

SI

Data Out 1

Data Out 2

Data Out 3

SO

...

7

6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

65

10/03/2014

IS25LP032/064/128

8.36 FAST READ DUAL IO DTR MODE OPERATION (FRDDTR, BDh)

The FRDDTR instruction enables Double Transfer Rate throughput on dual I/O of the device in read mode. The

address (interleave on dual I/O pins) is latched on both rising and falling edge of SCK, and the data (interleave

on dual I/O pins) shift out on both rising and falling edge of SCK at a maximum frequency f_T2. The 4-bit address

can be latched-in at one clock, and 4-bit data can be read out at one clock, which means two bits at the rising

edge of clock, the other two bits at the falling edge of clock.

The first address byte can be at any location. The address is automatically increased to the next higher address

after each byte of data is shifted out, so the whole memory can be read out with a single FRDDTR instruction.

The address counter rolls over to 0 when the highest address is reached. Once writing FRDDTR instruction, the

following address/dummy/data out will perform as 4-bit instead of previous 1-bit.

The sequence of issuing FRDDTR instruction is: CE# goes low  Sending FRDDTR instruction (1-bit per clock)

 24-bit address interleave on SIO1 & SIO0 (4-bit per clock)  2 dummy clocks (configurable) on SIO1 & SIO0

 Data out interleave on SIO1 & SIO0 (4-bit per clock)  End FRDDTR operation via pulling CE# high at any

time during data out (Please refer to Figure 8.52 for 2 x I/O Double Transfer Rate Read Mode Timing

Waveform).

If AXh (X is don’t care) is input for the mode bits during dummy cycles, the device will enter AX read operation

mode which enables subsequent FRDIO execution skips command code. It saves cycles as described in Figure

8.53. When the code is different from AXh (X is don’t care), the device exits the AX read operation. After

finishing the read operation, device becomes ready to receive a new command. Since the number of dummy

cycles and AX bits cycles are same in this case, X should be Hi-Z to avoid I/O contention

If the FRDDTR instruction is issued while a Program/Erase/Write Status Register cycle is in progress (WIP=1),

the instruction will be rejected without any effect on the current cycle.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

66

10/03/2014

IS25LP032/064/128

Figure 8.52 FRDDTR (Fast Read Dual IO DTR Mode) OPERATION (with command decode cycles)

CE#

0

1

2

3

4

5

6

7

8

9

10

...

13

14

Mode 3

Mode 0

SCK

SI

3-byte Address

2 Dummy Cycles

...

Instruction = BDh

22 20 18 16 14 12 10

0

6 4

Mode Bits

High Impedance

SO

...

23 21 19 17 15 13 11

1

7

5

CE#

...

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

SCK

t_V

Data Out Data Out

Data Out

SI

...

2

0

6

4

2

0

6

4

2

0

6

7

4

2

0

6

4

2

0

6

4

2

0

6

4

2

0

Mode Bits

SO

3

1

7

5

3

1

7

5

3

1

5

3

1

7

5

3

1

7

5

3

1

7

5

3

1

Notes:

1. If the mode bits=AXh (X: don’t care), it can execute the AX read mode (without command). When the mode bits

are different from AXh (X is don’t care), the device exits the AX read operation.

2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.9 Read Dummy Cycles.

3. Since the number of dummy cycles and AX bits cycles are same in the above Figure, X should be Hi-Z to avoid

I/O contention.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

67

10/03/2014

IS25LP032/064/128

Figure 8.53 FRDDTR (Fast Read Dual IO DTR Mode) OPERATION (without command decode cycles)

CE#

...

0

1

2

6

7

8

9

10

11

12

13

14

15

16

...

Mode 3

Mode 0

SCK

2 Dummy Cycles

t_V

Data Out Data Out

Data Out

3-byte Address

SI

...

22 20 18 16 14 12 10

0

6

4

2

0

6

4

2

0

6

4

2

0

6

4

2

0

Mode Bits

SO

7

5

3

1

7

5

3

1

7

5

3

1

23 21 19 17 15 13 11

1

7

5 3 1

Notes:

1. If the mode bits=AXh (X: don’t care), it can execute the AX read mode (without command). When the mode bits

are different from AXh (X is don’t care), the device exits the AX read operation.

2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.9 Read Dummy Cycles.

3. Since the number of dummy cycles and AX bits cycles are same in the above Figure, X should be Hi-Z to avoid

I/O contention

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

68

10/03/2014

IS25LP032/064/128

8.37 FAST READ QUAD IO DTR MODE OPERATION (FRQDTR, EDh)

The FRQDTR instruction enables Double Transfer Rate throughput on quad I/O of the device in read mode. A

Quad Enable (QE) bit of status Register must be set to "1" before sending the FRQDTR instruction. The address

(interleave on 4 I/O pins) is latched on both rising and falling edge of SCK, and data (interleave on 4 I/O pins)

shift out on both rising and falling edge of SCK at a maximum frequency f_Q2. The 8-bit address can be latched-in

at one clock, and 8-bit data can be read out at one clock, which means four bits at the rising edge of clock, the

other four bits at the falling edge of clock.

The first address byte can be at any location. The address is automatically increased to the next higher address

after each byte data is shifted out, so the whole memory can be read out with a single FRQDTR instruction. The

address counter rolls over to 0 when the highest address is reached. Once writing FRQDTR instruction, the

following address/dummy/data out will perform as 8-bit instead of previous 1-bit.

The sequence of issuing FRQDTR instruction is: CE# goes low  Sending FRQDTR instruction (1-bit per clock)

 24-bit address interleave on SIO3, SIO2, SIO1 & SIO0 (8-bit per clock)  3 dummy clocks (configurable) 

Data out interleave on SIO3, SIO2, SIO1 & SIO0 (8-bit per clock)  End FRQDTR operation by driving CE#

high at any time during data out.

If AXh (X is don’t care) is input for the mode bits during dummy cycles, the device will enter AX read operation

mode which enables subsequent FRDIO execution skips command code. It saves cycles as described in Figure

8.55. When the code is different from AXh (X is don’t care), the device exits the AX read operation. After

finishing the read operation, device becomes ready to receive a new command.

If the FRQDTR instruction is issued while a Program/Erase/Write Status Register cycle is in progress (WIP=1),

the instruction will be rejected without any effect on the current cycle.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

69

10/03/2014

IS25LP032/064/128

Figure 8.54 FRQDTR (Fast Read Quad IO DTR Mode) OPERATION (with command decode cycles)

CE#

0

1

2

3

4

5

6

7

8

9

10

11

12

Mode 3

Mode 0

SCK

IO0

3 Dummy Cycles

3-byte Address

20 16 12 8 4

Instruction = EDh

High Impedance

0

IO1

IO2

21 17 13 9 5

22 18 14 10 6

23 19 15 11 7

1

2

3

IO3

CE#

SCK

IO0

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

Data Data Data Data Data Data Data Data Data Data Data Data

Out Out Out Out Out Out Out Out Out Out Out Out

t_V

...

4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0

5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1

6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2

7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3

IO1

IO2

IO3

Notes:

1. If the mode bits=AXh (X: don’t care), it can execute the AX read mode (without command). When the mode bits

are different from AXh (X is don’t care), the device exits the AX read operation.

2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.9 Read Dummy Cycles.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

70

10/03/2014

IS25LP032/064/128

Figure 8.55 FRQDTR (Fast Read Quad IO DTR Mode) OPERATION (without command decode cycles)

CE#

0

1

2

3

4

5

6

7

8

9

10

11

12

13

Mode 3

Mode 0

SCK

IO0

Data Data Data Data Data Data Data

Out Out Out Out Out Out Out

3 Dummy Cycles

3-byte Address

t_V

...

20 16 12 8

4

0

4

0

1

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

IO1

IO2

21 17 13 9

5

1

2

3

5

6

7

22 18 14 10 6

23 19 15 11 7

2

3

IO3

Mode Bits

Notes:

1. If the mode bits=AXh (X: don’t care), it can execute the AX read mode (without command). When the mode bits

are different from AXh (X is don’t care), the device exits the AX read operation.

2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.9 Read Dummy Cycles.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

71

10/03/2014

IS25LP032/064/128

8.38 SECTOR LOCK/UNLOCK FUNCTIONS

SECTOR UNLOCK OPERATION (SECUNLOCK, 26h)

The Sector Unlock command allows the user to select a specific sector to allow program and erase operations.

This instruction is effective when the blocks are designated as write-protected through the BP0, BP1, BP2, and

BP3 bits in the Status register. Only one sector can be enabled at any time. To enable a different sector, a

previously enabled sector must be disabled by executing a Sector Lock command. The instruction code is

followed by a 24-bit address specifying the target sector, but A0 through A11 are not decoded. The remaining

sectors within the same block remain as read-only.

In the Sector Unlock procedure, [A11:A0] must be “0” for the unlock procedure to execute properly. The chip will

regard anything else as an illegal command.

Figure 8.56 Sector Unlock Sequence

CE#

0

1

2

3

4

5

6

7

8

9

10

11

Mode 3

Mode 0

SCK

IO0

3-byte Address

Instruction = 26h

High Impedance

20 16 12 8

4

0

IO1

IO2

21 17 13 9

5

1

2

3

22 18 14 10 6

23 19 15 11 7

IO3

Notes:

1. If the number of clock cycles do not match 8 cycles (command) + 24 clocks (address), the command will be

ignored.

2. WREN (06h) must be executed before sector unlock instructions.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

72

10/03/2014

IS25LP032/064/128

SECTOR LOCK OPERATION (SECLOCK, 24h)

The Sector Lock command relocks a sector that was previously unlocked by the Sector Unlock command. The

instruction code does not require an address to be specified, as only one sector can be enabled at a time. The

remaining sectors within the same block remain in read-only mode.

Figure 8.57 Sector Lock Sequence

CE#

0

1

2

3

4

5

6

7

Mode 3

Mode 0

SCK

SI

Instruction = 24h

High Impedance

SO

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

73

10/03/2014

IS25LP032/064/128

9. ELECTRICAL CHARACTERISTICS

9.1 ABSOLUTE MAXIMUM RATINGS ⁽¹⁾

Storage Temperature

-65^oC to +150^oC

240^oC 3 Seconds

260^oC 3 Seconds

-0.5V to V_CC+ 0.5V

-0.5V to +6.0V

Standard Package

Lead-free Package

Surface Mount Lead Soldering Temperature

Input Voltage with Respect to Ground on All Pins

All Output Voltage with Respect to Ground

V_CC

Note:

1. Applied conditions greater than those listed in “Absolute Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional operation of the device at these or any other conditions

above those indicated in the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

9.2 OPERATING RANGE

Part Number

IS25LP032/064/128

-40°C to 105°C

Operating Temperature (Extended Grade)

Operating Temperature (V Grade: Hybrid Flow)

Operating Temperature (Automotive Grade A1)

Operating Temperature (Automotive Grade A2)

Operating Temperature (Automotive Grade A3)

V_CCPower Supply

-40°C to 125°C

-40°C to 85°C

-40°C to 105°C

-40°C to 125°C

2.3V (VMIN) – 3.6V (VMAX) ; 3.3V (Typ)

9.3 DC CHARACTERISTICS

(Under operating range)

Typ⁽²⁾

10

Symbol

I_CC1

I_CC2

I_SB1

Parameter

Condition

Min

Max

Units

mA

µA

V

V_CCActive Read Current

V_CCProgram/Erase Current

V_CCStandby Current CMOS

Deep power down current

Input Leakage Current

Output Leakage Current

Input Low Voltage

V_CC= VMAX at 50MHz, SO = Open

V_CC= VMAX, CE# = V_CC

V_IN= 0V to V_CC

15

25

40

10

50

I_SB2

5

20

1

I_LI

I_LO

V_IN= 0V to V_CC

1

(1)

V_IL

-0.5

0.3V_CC

V_CC+ 0.3

0.2

(1)

V_IH

Input High Voltage

0.7V_CC

V

V_OL

V_OH

Output Low Voltage

I_OL= 100 µA

2.3V < V_CC< 3.6V

V

Output High Voltage

I_OH= -100 µA

V_CC- 0.2

V

Notes:

1. Maximum DC voltage on input or I/O pins is VCC + 0.5V. During voltage transitions, input or I/O pins may

overshoot VCC by + 2.0 V for a period of time not to exceed 20ns. Minimum DC voltage on input or I/O pins is -

0.5V. During voltage transitions, input or I/O pins may undershoot GND by -2.0 V for a period of time not to

exceed 20ns.

2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at

V_CC= V_CC(Typ), TA=25°C

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

74

10/03/2014

IS25LP032/064/128

9.4 AC MEASUREMENT CONDITIONS

Symbol

Parameter

Min

Max

30

15

5

Units

CL

Load Capacitance up to 104MHz

Load Capacitance up to 133MHz

Input Rise and Fall Times

pF

ns

V

TR,TF

VIN

Input Pulse Voltages

0.2V_CCto 0.8V_CC

VREFI

VREFO

Input Timing Reference Voltages

Output Timing Reference Voltages

0.3V_CCto 0.7V_CC

0.5V_CC

V

Figure9.1 Output test load & AC measurement I/O Waveform

0.8V_CC

AC

Input

V_CC/2

Measurement

Level

1.8k

0.2V_CC

OUTPUT PIN

1.2k

15/30pf

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

75

10/03/2014

IS25LP032/064/128

9.5 AC CHARACTERISTICS

(Under operating range, refer to section 9.4 for AC measurement conditions)

Symbol

Parameter

Min

Typ⁽³⁾

Max

Units

Clock Frequency for fast read mode:

SPI, Dual, Dual I/O, Quad I/O, and QPI.

Clock Frequency for fast read DTR:

SPI DTR, Dual DTR, Dual I/O DTR, Quad I/O DTR, and

QPI DTR.

f_CT

0

133

MHz

f_C2, f_T2, f_Q2

f_C

0

66

50

MHz

Clock Frequency for read mode SPI

SCK Rise Time (peak to peak)

SCK Fall Time ( peak to peak)

0

MHz

V/ns

ns

(1)

t_CLCH

0.1

(1)

t_CHCL

0.1

For read mode

45% f_C

t_CKH

SCK High Time

For others

45% f_CT/C2/T2/Q2

For read mode

45% f_C

ns

t_CKL

SCK Low Time

For others

45% f_CT/C2/T2/Q2

t_CEH

t_CS

CE# High Time

CE# Setup Time

CE# Hold Time

7

6

ns

ms

s

t_CH

6

Normal Mode

Data In Setup Time

2

t_DS

DTR Mode

1.5

2

Normal Mode

t_DH

Data in Hold Time

DTR Mode

1.5

Output Valid @ 133MHz (CL = 15pF)

Output Valid @ 104MHz (CL = 30pF)

Output Hold Time Normal Mode

Output Disable Time

7

8

t_V

t_OH

2

(1)

t_DIS

8

t_HD

Output Hold Time

2

5

t_HLCH

t_CHHH

t_HHCH

t_CHHL

HOLD Active Setup Time relative to SCK

HOLD Active Hold Time relative to SCK

HOLD Not Active Setup Time relative to SCK

HOLD Not Active Hold Time relative to SCK

HOLD to Output Low Z

(1)

t_LZ

12

(1)

t_HZ

HOLD to Output High Z

Sector Erase Time (4Kbyte)

Block Erase Time (32Kbyte)

Block Erase time (64Kbyte)

Chip Erase Time (32Mb)

45

0.15

0.3

8

300

0.75

1.5

23

s

t_EC

s

Chip Erase Time (64Mb)

16

45

s

Chip Erase Time (128Mb)

30

90

s

t_PP

Page Program Time

0.2

1.0

ms

t_VCE

Vcc(min) to CE# Low

1

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

76

10/03/2014

IS25LP032/064/128

Symbol

Parameter

Min

Typ⁽³⁾

Max

3

Units

µs

(1)

t_RES1

Release deep power down

Deep power down

(1)

t_DP

3

µs

t_W

Write Status Register time

Suspend to read ready

Software Reset recovery time

RESET# pin low pulse width

Hardware Reset recovery time

2

15

ms

µs

(1)

t_SUS

100

(1)

t_SRST

µs

(1),(4)

t_RESET

1⁽²⁾

µs

(1),(4)

t_HWRST

100

µs

Notes:

1. These parameters are characterized and not 100% tested.

2. If the RESET# pulse is driven for a period shorter than 1µs (t_RESETminimum), it may still reset the device, however

the 1µs minimum period is recommended to ensure reliable operation.

3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at

V_CC= V_CC(Typ), TA=25°C

4. Only applicable to the parts that have the RESET# pin option

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

77

10/03/2014

IS25LP032/064/128

9.6 SERIAL INPUT/OUTPUT TIMING

Figure 9.2 SERIAL INPUT/OUTPUT TIMING (Normal Mode) ⁽¹⁾

t_CEH

CE#

t_CS

t_CH

t_CKH

t_CKL

SCK

SI

t_DS

t_DH

VALID IN

t_V

t_OH

VALID OUTPUT

t_DIS

HI-Z

SO

Note1. For SPI Mode 0 (0,0)

Figure 9.3 SERIAL INPUT/OUTPUT TIMING (DTR Mode) ⁽¹⁾

t_CEH

CE#

t_CS

t_CH

t_CKH

t_CKL

SCK

SI

t_DS

t_DH

VALID IN

t_DIS

t_OH

t_V

HI-Z

SO

Output

Note1. For SPI Mode 0 (0,0)

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

78

10/03/2014

IS25LP032/064/128

Figure 9.4 HOLD TIMING

CE#

t_HLCH

t_CHHL

t_HHCH

SCK

t_CHHH

t_HZ

t_LZ

SO

SI

HOLD#

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

79

10/03/2014

IS25LP032/064/128

9.7 POWER-UP AND POWER-DOWN

At Power-up and Power-down, the device must be NOT SELECTED until Vcc reaches at the right level. (Adding

a simple pull-up resistor on CE# is recommended.)

Power up timing

V_CC

V_CC(max)

All Write Commands are Rejected

Chip Selection Not Allowed

V_CC(min)

Reset State

Device fully

accessible

t_VCE

Read Access Allowed

V(write inhibit)

t_PUW

Symbol

tVCE⁽¹⁾

tPUW⁽¹⁾

Parameter

Min.

1

Max

Unit

ms

V

Vcc(min) to CE# Low

Power-up time delay to write instruction

Write Inhibit Voltage

1

10

(1)

V_WI

1.9

Note: These parameters are characterized and not 100% tested.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

80

10/03/2014

IS25LP032/064/128

9.8 PROGRAM/ERASE PERFORMANCE

Parameter

Sector Erase Time (4Kbyte)

Block Erase Time (32Kbyte)

Block Erase Time (64Kbyte)

Chip Erase Time (32Mb/64Mb/128Mb)

Page Programming Time

Byte Program

Unit

ms

s

Typ

45

Max

300

0.75

1.5

0.15

0.3

s

8/16/30

0.2

23/45/90

1.0

ms

µs

8

40

Note: These parameters are characterized and not 100% tested.

9.9 RELIABILITY CHARACTERISTICS

Parameter

Endurance

Min

100,000

20

Unit

Test Method

Cycles

Years

Volts

mA

JEDEC Standard A117

JEDEC Standard A103

JEDEC Standard A114

JEDEC Standard A115

JEDEC Standard 78

Data Retention

ESD – Human Body Model

ESD – Machine Model

Latch-Up

2,000

200

100 + ICC1

Note: These parameters are characterized and not 100% tested.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

81

10/03/2014

IS25LP032/064/128

10. PACKAGE TYPE INFORMATION

10.1 8-PIN JEDEC 208MIL BROAD SMALL OUTLINE INTEGRATED CIRCUIT (SOIC) PACKAGE (JB)

TOP VIEW

SIDE VIEW

0.48

0.35

5.38

5.18

1.27 BSC

0.25

0.05

5.38

5.18

2.16

1.75

8.10

7.70

END VIEW

5.33

5.13

0.25

0.19

5.38

5.18

0.80

0.50

Note: All dimensions are in millimeters.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

82

10/03/2014

IS25LP032/064/128

10.2 8-CONTACT ULTRA-THIN SMALL OUTLINE NO-LEAD (WSON) PACKAGE 6X5MM (JK)

Top View

Side View

5.00

BSC

0.25

0.19

6.00

BSC

0.80

0.70

Pin 1

Bottom View

1.27

BSC

3.40

0.48

0.35

0.75

0.50

Note: All dimensions are in millimeters.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

83

10/03/2014

IS25LP032/064/128

10.3 8-CONTACT ULTRA-THIN SMALL OUTLINE NO-LEAD (WSON) PACKAGE 8X6MM (JL)

.

DIMENSION IN MM

SYMBOL

MIN.

0.70

0.00

- - -

NOM

0.75

0.02

0.20

8.00

6.00

4.70

4.60

1.27

0.40

0.50

MAX

0.80

0.05

- - -

A

A1

A2

D

7.90

5.90

4.65

4.55

- - -

8.10

6.10

4.75

4.65

- - -

E

D1

E1

e

b

0.35

0.4

0.48

0.60

L

Note: All dimensions are in millimeters.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

84

10/03/2014

IS25LP032/064/128

10.4 8-PIN 208MIL VSOP PACKAGE (JF)

θ

L

D

10°(4x)

c

e

b

Symbols

Min

Typ

Max

A

-

1

A1

A2

b

0.05

0.75

0.35

-

0.1

0.8

0.15

0.85

0.48

-

0.42

.127 REF

5.28

7.9

c

D

E

5.18

7.7

5.18

-

5.38

8.1

5.38

-

E1

e

5.28

1.27

0.65

-

L

0.5

-

0.8

0.1

8°

y

θ

0°

-

Note: All dimensions are in millimeters.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

85

10/03/2014

IS25LP032/064/128

10.5 16-LEAD PLASTIC SMALL OUTLINE PACKAGE (300 MILS BODY WIDTH) (JM)

Millimeters

10.1

10.5

16

9

0.23

0.32

Detail A

1

8

Detail A

1.27

0.1

0.3

0.33

0.51

0⁰

8⁰

0.4

1.27

Note: All dimensions are in millimeters.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

86

10/03/2014

IS25LP032/064/128

10.6 24-BALL THIN PROFILE FINE PITCH BGA 6X8MM (JG)

A1 Corner

Index Area

D

4

3

2

1

A

B

C

E

E1

e

D

E

F

nX Øb

A1 Corner

Index Area

e

D1

(TOP VIEW)

(BOTTOM VIEW)

A3

A1

A

A2

DIMENSIONS (MM)

SYMBOL

MIN

NOM

-

MAX

1.20

0.37

A

A1

A2

A3

D

-

0.27

-

0.21 REF

0.54 REF

6 BSC

8 BSC

3.00

E

D1

E1

e

-

5.00

1.00

0.40

b

Note: All dimensions are in millimeters.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

87

10/03/2014

IS25LP032/064/128

11. ORDERING INFORMATION- Valid Part Numbers

IS25LP128

-

JB

L

E

TEMPERATURE RANGE

E = Extended (-40°C to +105°C)

V = Hybrid Flow (-40°C to +125°C)

A1 = Automotive Grade (-40°C to +85°C)

A2 = Automotive Grade (-40°C to +105°C)

A3 = Automotive Grade (-40°C to +125°C)

PACKAGING CONTENT

L = RoHS compliant

PACKAGE Type

JB = 8-pin SOIC 208mm

JK = 8-pin WSON (6x5mm)

JL = 8-pin WSON (6x8mm)

JF = 8-pin VSOP 208mil

JM = 16-pin 300mil

JG = 24-ball TFBGA (6x8mm)

JW = KGD (Call Factory)

SPEED

Blank = 133MHz

B = 66MHz DTR (Call Factory)

Density

128 = 128 Megabit

064 = 64 Megabit

032 = 32 Megabit

BASE PART NUMBER

IS = Integrated Silicon Solution Inc.

25LP = FLASH, 2.3V ~ 3.6V, QPI

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

88

10/03/2014

IS25LP032/064/128

Density

Frequency (MHz)

Order Part Number⁽¹⁾

IS25LP032-JBLE

Package⁽²⁾

8-pin SOIC 208mil

IS25LP032-JBLV

IS25LP032-JKLV

IS25LP032-JLLV

IS25LP032-JFLV

IS25LP032-JMLV

IS25LP032-JGLV

IS25LP032-JKLE

IS25LP032-JLLE

IS25LP032-JFLE

IS25LP032-JMLE

IS25LP032-JGLE

8-pin WSON (6x5mm)

8-pin WSON (6x8mm)

8-pin VSOP 208mil

16-pin 300mil

24-ball TFBGA (6x8mm)

8-pin SOIC 208mil (Call Factory)

8-pin WSON (6x5mm) (Call Factory)

8-pin WSON (6x8mm) (Call Factory)

8-pin VSOP 208mil (Call Factory)

16-pin 300mil (Call Factory)

24-ball TFBGA (6x8mm) (Call Factory)

KGD (Call Factory)

32Mb

133

IS25LP032-JBLA*

IS25LP032-JKLA*

IS25LP032-JLLA*

IS25LP032-JFLA*

IS25LP032-JMLA*

IS25LP032-JGLA*

IS25LP032-JWLE

IS25LP064-JBLE

IS25LP064-JBLV

IS25LP064-JKLV

IS25LP064-JLLV

IS25LP064-JFLV

IS25LP064-JMLV

IS25LP064-JGLV

8-pin SOIC 208mil

8-pin WSON (6x5mm)

IS25LP064-JKLE

IS25LP064-JLLE

IS25LP064-JFLE

IS25LP064-JMLE

IS25LP064-JGLE

8-pin WSON (6x8mm)

8-pin VSOP 208mil

16-pin 300mil

24-ball TFBGA (6x8mm)

64Mb

133

IS25LP064-JBLA*

8-pin SOIC 208mil (Call Factory)

8-pin WSON (6x5mm) (Call Factory)

8-pin WSON (6x8mm) (Call Factory)

8-pin VSOP 208mil (Call Factory)

16-pin 300mil (Call Factory)

24-ball TFBGA (6x8mm) (Call Factory)

KGD (Call Factory)

IS25LP064-JKLA*

IS25LP064-JLLA*

IS25LP064-JFLA*

IS25LP064-JMLA*

IS25LP064-JGLA*

IS25LP064-JWLE

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

89

10/03/2014

IS25LP032/064/128

Density

Frequency (MHz)

Order Part Number⁽¹⁾

IS25LP128-JBLE

Package⁽²⁾

8-pin SOIC 208mil

IS25LP128-JBLV

IS25LP128-JKLV

IS25LP128-JLLV

IS25LP128-JFLV

IS25LP128-JMLV

IS25LP128-JGLV

IS25LP128-JKLE

IS25LP128-JLLE

IS25LP128-JFLE

IS25LP128-JMLE

IS25LP128-JGLE

8-pin WSON (6x5mm)

8-pin WSON (6x8mm)

8-pin VSOP 208mil

16-pin 300mil

24-ball TFBGA (6x8mm)

8-pin SOIC 208mil

128Mb

133

IS25LP128-JBLA*

IS25LP128-JKLA*

IS25LP128-JLLA*

IS25LP128-JFLA*

IS25LP128-JMLA*

IS25LP128-JGLA*

IS25LP128-JWLE

8-pin WSON (6x5mm) (Call Factory)

8-pin WSON (6x8mm) (Call Factory)

8-pin VSOP 208mil (Call Factory)

16-pin 300mil (Call Factory)

24-ball TFBGA (6x8mm) (Call Factory)

KGD (Call Factory)

Notes:

1. A* = A1, A2, A3: Meets AEC-Q100 requirements with PPAP, V = Hybrid Flow non-Auto qualified

Temp Grades: E = -40 to 105 C, V = -40 to 125 C, A1 = -40 to 85 C, A2 = -40 to 105 C, A3 = -40 to 125 C

2. For Reset# pin option instead of Hold# pin, call Factory

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

90

10/03/2014


型号：	IS25LP128-JLLE
厂家：	INTEGRATED SILICON SOLUTION, INC
描述：	IC FLASH 128M SPI 133MHZ 8WSON
文件：	总90页 (文件大小：2488K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IS25LP128-JLLE [ISSI]

相关型号：

IS25LP128-JMLE

IS25LP128F-JBLE-TR

IS25LP128F-JLLE-TR

IS25LP128F-RMLE

IS25LP128F-RMLE-TR

IS25LP256

IS25LP256-JGLA

IS25LP256-JGLE

IS25LP256-JGLE1

IS25LP256-JLLA

IS25LP256-JLLE

IS25LP256-JLLE1