IS31AP4066D-QFLS2-TR [ISSI]

Audio Amplifier, 1.6W, 2 Channel(s), 1 Func, QFN-16;
IS31AP4066D-QFLS2-TR
型号: IS31AP4066D-QFLS2-TR
厂家: INTEGRATED SILICON SOLUTION, INC    INTEGRATED SILICON SOLUTION, INC
描述:

Audio Amplifier, 1.6W, 2 Channel(s), 1 Func, QFN-16

放大器 商用集成电路
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IS31AP4066D  
DUAL 1.3W STEREO AUDIO AMPLIFIER  
January 2014  
GENERAL DESCRIPTION  
KEY SPECIFICATIONS  
The IS31AP4066D is a dual bridge-connected audio  
power amplifier which, when connected to a 5V supply,  
will deliver 1.3W to an 8load.  
PO at RL = 8, VCC = 5V  
THD+N = 1% ---------------------- 1.3W (Typ.)  
THD+N = 10% --------------------- 1.6W (Typ.)  
PO at RL = 8, VCC = 4V  
THD+N = 1% ----------------------- 0.81W (Typ.)  
Shutdown current ------------------- 0.3μA (Typ.)  
Supply voltage range --------------- 2.7V ~ 5.5V  
QFN-16 (3mm × 3mm) package  
The IS31AP4066D features a low-power consumption  
shutdown mode and thermal shutdown protection. It  
also utilizes circuitry to reduce “click-and-pop” during  
device turn-on.  
APPLICATIONS  
FEATURES  
Cell phones, PDA, MP4,PMP  
Portable and desktop computers  
Desktops audio system  
Suppress “click-and-pop”  
Thermal shutdown protection circuitry  
Micro power shutdown mode  
Multimedia monitors  
TYPICAL APPLICATION CIRCUIT  
Figure 1 Typical Application Circuit  
1
Integrated Silicon Solution, Inc. – www.issi.com  
Rev. B, 01/03/2014  
IS31AP4066D  
PIN CONFIGURATION  
Package  
Pin Configuration (Top View)  
QFN-16  
PIN DESCRIPTION  
No.  
Pin  
Description  
1
OUTA+  
VCC  
Left channel positive output.  
Supply voltage.  
2,11  
3
OUTA-  
INA  
Left channel negative output.  
Left channel input.  
Ground.  
4
5~7,13,14,16  
GND  
Bypass capacitor which provides the  
common mode voltage.  
8
BYPASS  
9
INB  
Right channel input.  
10  
12  
OUTB-  
OUTB+  
Right channel negative output.  
Right channel positive output.  
Shutdown control, hold low for shutdown  
mode.  
15  
SDB  
Thermal Pad  
Connect to GND.  
2
Integrated Silicon Solution, Inc. – www.issi.com  
Rev. B, 01/03/2014  
IS31AP4066D  
ORDERING INFORMATION  
Industrial Range: -40°C to +85°C  
Order Part No.  
Package  
QTY/Reel  
IS31AP4066D-QFLS2-TR  
QFN-16, Lead-free  
2500  
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any  
time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are  
advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the  
product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not  
authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
3
Integrated Silicon Solution, Inc. – www.issi.com  
Rev. B, 01/03/2014  
IS31AP4066D  
ABSOLUTE MAXIMUM RATINGS  
Supply voltage, VCC  
-0.3V ~ +6.0V  
Voltage at any input pin  
Maximum junction temperature, TJMAX  
Storage temperature range, TSTG  
-0.3V ~ VCC+0.3V  
150°C  
-65°C ~ +150°C  
40°C ~ +85°C  
1kV  
Operating temperature range, TA  
ESD (HBM)  
ESD (CDM)  
Note:  
1kV  
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and  
functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is not  
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.  
ELECTRICAL CHARACTERISTICS  
The following specifications apply for VCC= 5V, unless otherwise noted.  
Limits apply for TA = 25°C. (Note 1 or specified)  
Symbol  
Parameter  
Supply voltage  
Quiescent power supply current VIN = 0V, IO = 0A  
Condition  
Min.  
Typ. Max.  
Unit  
VCC  
ICC  
ISD  
2.7  
5.5  
V
mA  
μA  
V
3.9  
0.3  
10.0  
2.5  
Shutdown current  
GND applied to the shutdown pin  
VIH  
VIL  
tWU  
Shutdown input voltage high  
Shutdown input voltage low  
Turn on time  
1.4  
0.4  
V
CBypass = 1μF (Note 2)  
120  
ms  
ELECTRICAL CHARACTERISTICS OPERATION  
The following specifications apply for VCC= 5V, unless otherwise noted.  
Limits apply for TA = 25°C. (Note 2 or specified)  
Symbol  
Parameter  
Condition  
Min.  
Typ. Max.  
Unit  
VOS  
Output offset voltage  
VIN = 0V  
5.0  
1.3  
1.6  
25.0  
mV  
W
THD+N = 1%, f = 1kHz, RL= 8Ω  
THD+N = 10%, f = 1kHz, RL = 8Ω  
Po  
Output power  
W
Total harmonic  
distortion +noise  
THD+N  
f = 1kHz, AV = 2, RL = 8, PO = 1W  
0.1  
%
Input floating, 217Hz, VRipple = 200mVp-p  
80.0  
70.0  
60.0  
60.0  
dB  
dB  
dB  
dB  
C
Bypass = 1μF, RL = 8Ω  
Input floating 1kHz, VRipple = 200mVp-p  
CBypass = 1μF, RL = 8Ω  
Power supply rejection  
ratio  
PSRR  
Input GND 217Hz, VRipple = 200mVp-p  
C
Bypass = 1μF, RL =8Ω  
Input GND 1kHz VRipple = 200mVp-p  
Bypass = 1μF, RL = 8Ω  
C
XTalk  
VNO  
Channel separation  
Output noise voltage  
f = 1kHz, CBypass = 1μF  
-100  
7.0  
dB  
1kHz, A-weighted  
μV  
4
Integrated Silicon Solution, Inc. – www.issi.com  
Rev. B, 01/03/2014  
IS31AP4066D  
ELECTRICAL CHARACTERISTICS  
The following specifications apply for VCC= 3V, unless otherwise noted.  
Limits apply for TA = 25°C. (Note 1 or specified)  
Symbol  
Parameter  
Condition  
Min.  
Typ. Max. Unit  
ICC  
ISD  
VIH  
VIL  
tWU  
Quiescent power supply current VIN = 0V, IO = 0A  
2.6  
0.1  
6.5  
2.2  
mA  
μA  
V
Shutdown current  
GND applied to the shutdown pin  
Shutdown input voltage high  
Shutdown input voltage low  
Turn on time  
1.1  
0.4  
V
CBypass = 1μF (Note 2)  
110  
ms  
ELECTRICAL CHARACTERISTICS OPERATION  
The following specifications apply for VCC= 3V, unless otherwise noted.  
Limits apply for TA = 25°C. (Note 2 or specified)  
Symbol  
Parameter  
Condition  
Min.  
Typ. Max.  
Unit  
VOS  
Output offset voltage VIN = 0V  
2.5  
0.5  
25.0  
mV  
W
THD+N = 1%, f = 1kHz, RL= 8Ω  
Po  
Output power  
THD+N = 10%, f = 1kHz, RL = 8Ω  
0.6  
0.1  
W
%
Total harmonic  
distortion+noise  
THD+N  
f = 1kHz, AV = 2, RL = 8, PO = 0.3W  
Input floating, 217Hz, VRipple = 200mVp-p  
CBypass = 1μF, RL = 8Ω  
75.0  
70.0  
62.0  
62.0  
dB  
dB  
dB  
dB  
Input floating 1kHz, VRipple = 200mVp-p  
C
Bypass = 1μF, RL = 8Ω  
Input GND 217Hz, VRipple = 200mVp-p  
Bypass = 1μF, RL =8Ω  
Power supply  
rejection ratio  
PSRR  
C
Input GND 1kHz VRipple = 200mVp-p  
CBypass = 1μF, RL = 8Ω  
XTalk  
VNO  
Channel separation  
f = 1kHz, CBypass = 1μF  
-100  
7.0  
dB  
uV  
Output noise voltage 1kHz, A-weighted  
Note1: All parameters are production tested at 25°C, functional operation of the device and parameters specified over other temperature range,  
are guaranteed by design, characterization and process control.  
Note 2: Guaranteed by design.  
5
Integrated Silicon Solution, Inc. – www.issi.com  
Rev. B, 01/03/2014  
IS31AP4066D  
TYPICAL PERFORMANCE CHARACTERISTICS  
Vcc = 5V  
Vcc = 3V  
RL  
RL  
f = 1kHz  
f = 1kHz  
Figure 2 THD+N vs. Output Power  
Figure 3 THD+N vs. Output Power  
Vcc = 5V  
Vcc = 3V  
R
L
R
L
Po = 1W  
Po=300mW  
Figure 4 THD+N vs. Frequency  
Figure 5 THD+N vs. Frequency  
Vcc = 5V  
Vcc = 3V  
R
L
RL  
Input GND  
Input GND  
Figure 7 PSRR vs. Frequency  
Figure 6 PSRR vs. Frequency  
6
Integrated Silicon Solution, Inc. – www.issi.com  
Rev. B, 01/03/2014  
IS31AP4066D  
Vcc = 5V  
Vcc = 5V  
R
L
R
L
Input Floating  
Figure 9 Crosstalk vs. Frequency  
Figure 8 PSRR vs. Frequency  
Vcc = 3V  
Vcc = 5V  
R
L
R
L
Input Floating  
A-Weighting  
Figure 11 Noise Floor  
Figure 10 PSRR vs. Frequency  
Vcc = 3V  
Vcc = 5V  
R
L
R
L
Figure 13 Frequency Response  
Figure 12 Frequency Response  
7
Integrated Silicon Solution, Inc. – www.issi.com  
Rev. B, 01/03/2014  
IS31AP4066D  
Vcc = 3V  
Vcc = 3V  
R
L
R
L
A-Weighting  
Figure 14 Crosstalk vs. Frequency  
Figure 15 Noise Floor  
R
L
Top Side  
Bottom Side  
Vcc = 5V  
RL  
f = 1kHz  
Output Power (W)  
Figure 17 Power Dissipation vs. Output Power  
Figure 16 Dropout Voltage vs. Supply Voltage  
R
L
f = 1kHz  
THD+N = 10%  
THD+N = 1%  
Figure18 Output Power vs. Supply Voltage  
8
Integrated Silicon Solution, Inc. – www.issi.com  
Rev. B, 01/03/2014  
IS31AP4066D  
FUNCTIONAL BLOCK DIAGRAM  
VCC  
INA  
OUTA-  
OUTA+  
OUTB+  
OUTB-  
BYPASS  
SDB  
INB  
GND  
9
Integrated Silicon Solution, Inc. – www.issi.com  
Rev. B, 01/03/2014  
IS31AP4066D  
APPLICATION INFORMATION  
EXPOSED-DAP PACKAGE PCB MOUNTING  
CONSIDERATIONS  
POWER SUPPLY BYPASSING  
As with any power amplifier, proper supply bypassing  
is critical for low noise performance and high power  
supply rejection. Applications that employ a 5V  
regulator typically use a 10μF in parallel with a 0.1μF  
filter capacitor to stabilize the regulator’s output,  
reduce noise on the supply line, and improve the  
supply’s transient response. However, their presence  
does not eliminate the need for a local 1.0μF tantalum  
bypass capacitance connected between the  
IS31AP4066D’s supply pins and ground. Keep the  
length of leads and traces that connect capacitors  
between the IS31AP4066D’s power supply pin and  
ground as short as possible.  
The IS31AP4066D’s QFN (die attach paddle) package  
provides a low thermal resistance between the die and  
the PCB to which the part is mounted and soldered.  
This allows rapid heat transfer from the die to the  
surrounding PCB copper traces, ground plane and,  
finally, surrounding air.  
The QFN package must have it’s DAP soldered to a  
copper pad on the PCB. The DAP’s PCB copper pad is  
connected to a large plane of continuous unbroken  
copper. This plane forms a thermal mass and heat sink  
and radiation area. Place the heat sink area on either  
outside plane in the case of a two-sided PCB, or on an  
inner layer of a board with more than two layers.  
MICRO-POWER SHUTDOWN  
BRIDGE CONFIGURATION EXPLANATION  
The voltage applied to the SDB pin controls the  
IS31AP4066D’s shutdown function. Activate  
As shown in Figure 1, the IS31AP4066D consists of  
two pairs of operational amplifiers, forming a  
two-channel (Channel A and Channel B) stereo  
amplifier. External feedback resistors RF and input  
resistors RIN set the closed-loop gain of Amp A (OUT-)  
and Amp B OUT-) whereas two internal 20kresistors  
set Amp A’s (OUT+) and Amp B’s (OUT+) gain at 1.  
The IS31AP4066D drives a load, such speaker,  
connected between the two amplifier outputs, OUTA−  
and OUTA+.  
micro-power shutdown by applying GND to the SDB  
pin. When active, the IS31AP4066D’s micro-power  
shutdown feature turns off the amplifier’s bias circuitry,  
reducing the supply current. The low 0.3μA typical  
shutdown current is achieved by applying a voltage  
that is as near as GND as possible to the SDB pin.  
There are a few ways to control the micro-power  
shutdown. These include using a single-pole,  
single-throw switch, a microprocessor, or a  
microcontroller. When use a switch, connect an  
external 100kresistor between the SDB pin and  
GND. Select normal amplifier operation by closing the  
switch. Opening the switch sets the SDB pin to ground  
through the 100kresistor, which activates the  
micropower shutdown. The switch and resistor  
guarantee that the SDB pin will not float. This prevents  
unwanted state changes. In a system with a  
microprocessor or a microcontroller, use a digital  
output to apply the control voltage to the SDB pin.  
Driving the SDB pin with active circuitry eliminates the  
pull up resistor.  
Figure 1 shows that Amp A’s (OUT-) output serves as  
Amp A’s (OUT+) input. This results in both amplifiers  
producing signals identical in magnitude, but 180° out  
of phase. Taking advantage of this phase difference, a  
load is placed between OUTAand OUTA+ and driven  
differentially (commonly referred to as “bridge mode”).  
This results in a differential gain of  
AV = 2×(RF/RIN)  
(1)  
Bridge mode amplifiers are different from single-ended  
amplifiers that drive loads connected between a single  
amplifier’s output and ground. For a given supply  
voltage, bridge mode has a distinct advantage over the  
single-ended configuration: its differential output  
doubles the voltage swing across the load. This  
produces four times the output power when compared  
to a single-ended amplifier under the same conditions.  
This increase in attainable output power assumes that  
the amplifier is not current limited  
SELECTING PROPER EXTERNAL COMPONENTS  
Optimizing the IS31AP4066D’s performance requires  
properly selecting external components. Though the  
IS31AP4066D operates well when using external  
components with wide tolerances, best performance is  
achieved by optimizing component values.  
The IS31AP4066D is unity-gain stable, giving a  
designer maximum design flexibility. The gain should  
be set to no more than a given application requires.  
This allows the amplifier to achieve minimum THD+N  
and maximum signal-to-noise ratio. These parameters  
are compromised as the closed-loop gain increases.  
However, low gain demands input signals with greater  
voltage swings to achieve maximum output power.  
Fortunately, many signal sources such as audio  
CODECs have outputs of 1VRMS (2.83VP-P). Please  
Another advantage of the differential bridge output is  
no net DC voltage across the load. This is  
accomplished by biasing Channel A’s and Channel B’s  
outputs at half-supply. This eliminates the coupling  
capacitor that single supply, single ended amplifiers  
require. Eliminating an output coupling capacitor in a  
single-ended configuration forces a single-supply  
amplifier’s half-supply bias voltage across the load.  
This increases internal IC power dissipation and may  
permanently damage loads such as speakers.  
10  
Integrated Silicon Solution, Inc. – www.issi.com  
Rev. B, 01/03/2014  
IS31AP4066D  
refer to the Audio Power Amplifier Design section for  
more information on selecting the proper gain.  
Choosing CBYPASS equal to 1.0μF along with a small  
value of CIN (in the range of 0.1μF to 0.39μF),  
produces a click-less and pop-less shutdown function.  
As discussed above, choosing CIN no larger than  
necessary for the desired band with helps minimize  
INPUT CAPACITOR VALUE SELECTION  
Amplifying the lowest audio frequencies requires high  
value input coupling capacitors CIN in Figure 1. A high  
value capacitor can be expensive and may  
compromise space efficiency in portable designs. In  
many cases, however, the speakers used in portable  
systems, whether internal or external, have little ability  
to reproduce signals below 150Hz. Applications using  
speakers with this limited frequency response reap  
little improvement by using large input capacitor.  
click-and-pop. Connecting a 1μF capacitor, CBYPASS  
,
between the BYPASS pin and ground improves the  
internal bias voltage’s stability and improves the  
amplifier’s PSRR.  
OPTIMIZING CLICK-AND-POP REDUCTION  
PERFORMANCE  
The IS31AP4066D contains circuitry that minimizes  
turn-on and shutdown transients or “click-and-pop”.  
For this discussion, turn-on refers to either applying  
the power supply voltage or when the shutdown mode  
is deactivated. When the part is turned on, an internal  
current source changes the voltage of the BYPASS pin  
in a controlled, linear manner. Ideally, the input and  
outputs track the voltage applied to the BYPASS pin.  
The gain of the internal amplifiers remains unity until  
the voltage on the bypass pin reaches 1/2VCC. As soon  
as the voltage on the bypass pin is stable, the device  
becomes fully operational. Although the BYPASS pin  
current cannot be modified, changing the size of  
Besides effecting system cost and size, CIN have an  
effect on the IS31AP4066D’s click and pop  
performance. When the supply voltage is first applied,  
a transient (pop) is created as the charge on the input  
capacitor changes from zero to a quiescent state. The  
magnitude of the pop is directly proportional to the  
input capacitor’s size. Higher value capacitors need  
more time to reach a quiescent DC voltage (usually  
VCC/2) when charged with a fixed current. The  
amplifier’s output charges the input capacitor through  
the feedback resistors, RF. Thus, pops can be  
minimized by selecting an input capacitor value that is  
no higher than necessary to meet the desired 3dB  
frequency.  
C
BYPASS alters the device’s turn-on time and the  
magnitude of “click-and-pop”. Increasing the value of  
BYPASS reduces the magnitude of turn-on pops.  
However, this presents a tradeoff: as the size of  
BYPASS increases, the turn-on time increases. There is  
C
A shown in Figure 1, the input resistors RIN and the  
input capacitors CIN produce a 3dB high pass filter  
cutoff frequency that is found using Equation (2).  
C
a linear relationship between the size of CBYPASS and  
the turn-on time. Here are some typical turn-on times  
for various values of CBYPASS (all tested at VCC = 5V):  
f-3dB = 1/2πRINCIN  
(2)  
As an example when using a speaker with a low  
frequency limit of 150Hz, CINA, using Equation (2) is  
0.053μF. The 0.33μF CINA allows the IS31AP4066D to  
drive high efficiency, full range speaker whose  
response extends below 30Hz.  
CBYPASS  
tON  
0.01μF  
0.1μF  
13ms  
26ms  
BYPASS CAPACITOR VALUE SELECTION  
0.22μF  
0.47μF  
1.0μF  
44ms  
Besides minimizing the input capacitor size, careful  
consideration should be paid to value of CBYPASS, the  
capacitor connected to the BYPASS pin. Since CBYPASS  
determines how fast the IS31AP4066D settles to  
quiescent operation, its value is critical when  
minimizing turn-on pops. The slower the  
IS31AP4066D’s outputs ramp to their quiescent DC  
voltage (nominally 1/2VCC), the smaller the turn-on pop.  
68ms  
120 ms  
In order eliminate “click-and-pop”; all capacitors must  
be discharged before turn-on. Rapidly switching VCC  
on and off may not allow the capacitors to fully  
discharge, which may cause “click-and-pop”.  
11  
Integrated Silicon Solution, Inc. – www.issi.com  
Rev. B, 01/03/2014  
IS31AP4066D  
CLASSIFICATION REFLOW PROFILES  
Profile Feature  
Pb-Free Assembly  
Preheat & Soak  
150°C  
Temperature min (Tsmin)  
Temperature max (Tsmax)  
Time (Tsmin to Tsmax) (ts)  
200°C  
60-120 seconds  
Average ramp-up rate (Tsmax to Tp)  
3°C/second max.  
Liquidous temperature (TL)  
Time at liquidous (tL)  
217°C  
60-150 seconds  
Peak package body temperature (Tp)*  
Max 260°C  
Time (tp)** within 5°C of the specified  
classification temperature (Tc)  
Max 30 seconds  
Average ramp-down rate (Tp to Tsmax)  
Time 25°C to peak temperature  
6°C/second max.  
8 minutes max.  
Figure 19 Classification Profile  
12  
Integrated Silicon Solution, Inc. – www.issi.com  
Rev. B, 01/03/2014  
IS31AP4066D  
PACKAGE INFORMATION  
QFN-16  
Note: All dimensions in millimeters unless otherwise stated.  
13  
Integrated Silicon Solution, Inc. – www.issi.com  
Rev. B, 01/03/2014  

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