IS41C16100-60KE [ISSI]
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| 型号： | IS41C16100-60KE |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
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®
IS41C16100
IS41LV16100
1M x 16 (16-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
ISSI
April 2003
FEATURES
DESCRIPTION
• TTL compatible inputs and outputs; tristate I/O
The ISSI IS41C16100 and IS41LV16100 are 1,048,576 x 16-bit
high-performance CMOS Dynamic Random Access Memories.
ThesedevicesofferanacceleratedcycleaccesscalledEDOPage
Mode. EDO Page Mode allows 1,024 random accesses within a
singlerowwithaccesscycletimeasshortas20nsper16-bitword.
The Byte Write control, of upper and lower byte, makes the
IS41C16100idealforusein16-bitand32-bitwidedatabussystems.
• Refresh Interval:
— Auto refresh Mode: 1,024 cycles /16 ms
—
RAS-Only, CAS-before-RAS (CBR), and Hidden
— Self refresh Mode - 1,024 cycles / 128ms
• JEDEC standard pinout
ThesefeaturesmaketheIS41C16100andIS41LV16100ideallysuited
for high-bandwidth graphics, digital signal processing, high-
performancecomputingsystems,andperipheralapplications.
• Single power supply:
— 5V ± 10% (IS41C16100)
— 3.3V ± 10% (IS41LV16100)
TheIS41C16100andIS41LV16100arepackagedina42-pin400-
milSOJand400-mil50-(44-)pinTSOP(TypeII).Thelead-free400-
mil50-(44-)optionisavailabletoo.
• Byte Write and Byte Read operation via two CAS
• Industrail Temperature Range -40oC to 85oC
KEY TIMING PARAMETERS
Parameter
-50
50
13
25
20
84
-60
60
Unit
ns
PIN CONFIGURATIONS
Max. RAS Access Time (tRAC)
Max. CAS Access Time (tCAC)
Max. Column Address Access Time (tAA)
Min. EDO Page Mode Cycle Time (tPC)
Min. Read/Write Cycle Time (tRC)
50(44)-Pin TSOP (Type II)
42-PinSOJ
15
ns
30
ns
25
ns
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
1
44
43
42
41
40
39
38
37
36
35
34
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
1
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
2
2
104
ns
3
3
4
4
5
5
6
PIN DESCRIPTIONS
6
7
7
8
8
A0-A9
I/O0-15
WE
Address Inputs
Data Inputs/Outputs
Write Enable
9
9
10
11
I/O8
10
11
12
13
14
15
16
17
18
19
20
21
NC
NC
NC
WE
RAS
NC
NC
A0
12
13
14
15
16
17
18
19
20
21
22
33
32
31
30
29
28
27
26
25
24
23
NC
NC
LCAS
UCAS
OE
OE
Output Enable
LCAS
UCAS
OE
WE
RAS
NC
RAS
UCAS
LCAS
Vcc
Row Address Strobe
A9
A9
Upper Column Address Strobe
Lower Column Address Strobe
Power
NC
A8
A8
A0
A7
A7
A1
A6
A1
A6
A2
A5
A2
A5
A3
A4
A3
A4
GND
NC
Ground
VCC
GND
VCC
GND
No Connection
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
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®
IS41C16100
IS41LV16100
ISSI
FUNCTIONAL BLOCK DIAGRAM
OE
WE
WE
CONTROL
LOGICS
OE
CONTROL
LOGIC
CAS
CLOCK
GENERATOR
LCAS
UCAS
CAS
WE
DATA I/O BUS
RAS
CLOCK
RAS
GENERATOR
COLUMN DECODERS
SENSE AMPLIFIERS
REFRESH
COUNTER
I/O0-I/O15
MEMORY ARRAY
1,048,576 x 16
ADDRESS
BUFFERS
A0-A9
2
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IS41C16100
IS41LV16100
ISSI
TRUTHTABLE
Function
RAS
H
LCAS UCAS
WE
X
OE
X
Addresst
R
/tC
I/O
High-Z
Standby
H
L
L
H
L
X
Read:Word
Read:LowerByte
L
H
L
ROW/COL
ROW/COL
D
OUT
L
H
H
L
LowerByte, DOUT
UpperByte,High-Z
Read:UpperByte
L
H
L
H
L
ROW/COL
LowerByte,High-Z
UpperByte, DOUT
Write:Word(EarlyWrite)
L
L
L
L
L
L
L
X
X
ROW/COL
ROW/COL
D
IN
Write:LowerByte(EarlyWrite)
H
LowerByte,DIN
UpperByte,High-Z
Write:UpperByte(EarlyWrite)
Read-Write(1,2)
L
L
H
L
L
L
L
X
ROW/COL
ROW/COL
LowerByte,High-Z
UpperByte,DIN
H→L
L→H
D
OUT, DIN
EDOPage-ModeRead(2) 1stCycle:
2ndCycle:
L
L
L
H→L
H→L
L→H
H→L
H→L
L→H
H
H
H
L
L
L
ROW/COL
NA/COL
NA/NA
D
D
D
OUT
OUT
OUT
AnyCycle:
EDOPage-ModeWrite(1) 1stCycle:
2ndCycle:
L
L
H→L
H→L
H→L
H→L
L
L
X
X
ROW/COL
NA/COL
D
D
IN
IN
EDOPage-Mode(1,2)
Read-Write
1stCycle:
2ndCycle:
L
L
H→L
H→L
H→L
H→L
H→L
H→L
L→H
L→H
ROW/COL
NA/COL
D
D
OUT, DIN
OUT, DIN
HiddenRefresh
Read(2)
L→H→L
L→H→L
L
L
L
L
H
L
L
X
ROW/COL
ROW/COL
D
D
OUT
OUT
Write(1,3)
RAS-OnlyRefresh
CBRRefresh(4)
Notes:
L
H
L
H
L
X
X
X
X
ROW/NA
X
High-Z
High-Z
H→L
1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).
2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).
3. EARLY WRITE only.
4. At least one of the two CAS signals must be active (LCAS or UCAS).
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IS41C16100
IS41LV16100
ISSI
while holding CAS LOW. In CAS-before-RAS refresh
cycle, an internal 9-bit counter provides the row ad-
dresses and the external address inputs are ignored.
Functional Description
The IS41C16100 and IS41LV16100 is a CMOS DRAM
optimizedforhigh-speedbandwidth,lowpowerapplications.
During READ or WRITE cycles, each bit is uniquely
addressedthroughthe16addressbits. Theseareentered
ten bits (A0-A9) at time. The row address is latched by
the Row Address Strobe (RAS). The column address is
latchedbytheColumnAddressStrobe(CAS). RAS is used
tolatchthefirstninebitsandCASisusedtolatchthelatterninebits.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Self Refresh Cycle
The Self Refresh allows the user a dynamic refresh, data
retention mode at the extended refresh period of 128 ms.
i.e., 125 µs per row when using distributed CBR refreshes.
The feature also allows the user the choice of a fully
static, low power data retention mode. The optional Self
Refresh feature is initiated by performing a CBR Refresh
cycle and holding RAS LOW for the specified tRAS.
The IS41C16100 and IS41LV16100 has two CAS con-
trols, LCASand UCAS. TheLCAS andUCASinputsinternally
generatesaCASsignalfunctioninginanidenticalmannertothe
single CAS input on the other 1M x 16 DRAMs. The key differ-
ence is that each CAS controls its corresponding I/O
tristate logic (in conjunction with OE and WE and RAS). LCAS
controlsI/O0throughI/O7andUCAScontrolsI/O8through I/O15.
The Self Refresh mode is terminated by driving RAS
HIGH for a minimum time of tRP. This delay allows for the
completion of any internal refresh cycles that may be in
process at the time of the RAS LOW-to-HIGH transition.
If the DRAM controller uses a distributed refresh sequence,
a burst refresh is not required upon exiting Self Refresh.
The IS41C16100 and IS41LV16100 CAS function is
determined by the first CAS (LCAS or UCAS) transitioning
LOW and the last transitioning back HIGH. The two CAS
controls give the IS41C16100 and IS41LV16100 both
BYTE READ and BYTE WRITE cycle capabilities.
However, if the DRAM controller utilizes a RAS-only or
burst refresh sequence, all 1,024 rows must be refreshed
within the average internal refresh rate, prior to the
resumption of normal operation.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum tRAS time has expired. A new
cycle must not be initiated until the minimum precharge
time tRP, tCP has elapsed.
Extended Data Out Page Mode
EDOpagemodeoperationpermitsall1,024columnswithin
a selected row to be randomly accessed at a high data rate.
In EDO page mode read cycle, the data-out is held to the
next CAS cycle’s falling edge, instead of the rising edge.
For this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the CAS cycle time becomes shorter. There-
fore, in EDO page mode, the timing margin in read cycle
is larger than that of the fast page mode even if the CAS
cycle time becomes shorter.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The column
address must be held for a minimum time specified by tAR.
Data Out becomes valid only when tRAC, tAA, tCAC and tOEA
are all satisfied. As a result, the access time is dependent
on the timing relationships between these parameters.
In EDO page mode, due to the extended data function, the
CAS cycle time can be shorter than in the fast page mode
if the timing margin is the same.
Write Cycle
A write cycle is initiated by the falling edge of CAS and WE,
whichever occurs last. The input data must be valid at or
before the falling edge of CAS or WE, whichever occurs first.
The EDO page mode allows both read and write opera-
tions during one RAS cycle, but the performance is
equivalent to that of the fast page mode in that case.
Auto Refresh Cycle
Power-On
To retain data, 1,024 refresh cycles are required in each
16 ms period. There are two ways to refresh the memory.
After application of the VCC supply, an initial pause of
200 µs is required followed by a minimum of eight
initialization cycles (any combination of cycles contain-
ing a RAS signal).
1. Byclockingeachofthe1,024rowaddresses(A0throughA9)
with RAS at least once every 128 ms. Any read, write, read-
modify-writeorRAS-onlycyclerefreshestheaddressedrow.
During power-on, it is recommended that RAS track with
VCC or be held at a valid VIH to avoid current surges.
2. Using a CAS-before-RAS refresh cycle. CAS-before-
RAS refresh is activated by the falling edge of RAS,
4
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IS41C16100
IS41LV16100
ISSI
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Parameters
Rating
Unit
VT
Voltage on Any Pin Relative to GND
5V
3.3V
–1.0 to +7.0
–0.5 to +4.6
V
VCC
SupplyVoltage
5V
3.3V
–1.0 to +7.0
–0.5 to +4.6
V
IOUT
PD
OutputCurrent
50
1
mA
W
PowerDissipation
TA
CommercialOperationTemperature
IndustrialOperationgTemperature
0 to +70
-40 to +85
°C
°C
TSTG
StorageTemperature
–55 to +125
°C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)
Symbol
Parameter
Min.
Typ.
Max.
Unit
VCC
SupplyVoltage
5V
3.3V
4.5
3.0
5.0
3.3
5.5
3.6
V
VIH
VIL
TA
Input High Voltage
Input Low Voltage
5V
3.3V
2.4
2.0
—
—
VCC + 1.0
VCC + 0.3
V
V
5V
3.3V
–1.0
–0.3
—
—
0.8
0.8
CommercialAmbientTemperature
IndustrialAmbientTemperature
0
–40
—
—
70
85
°C
°C
CAPACITANCE(1,2)
Symbol
Parameter
Input Capacitance: A0-A9
Max.
Unit
pF
CIN1
CIN2
5
7
7
Input Capacitance: RAS, UCAS, LCAS, WE, OE
pF
CIO
Data Input/Output Capacitance: I/O0-I/O15
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz.
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IS41C16100
IS41LV16100
ISSI
ELECTRICALCHARACTERISTICS(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol
Parameter
Test Condition
Speed Min. Max.
Unit
IIL
InputLeakageCurrent
Any input 0V ≤ VIN ≤ Vcc
Other inputs not under test = 0V
–5
–5
2.4
—
5
µA
IIO
Output Leakage Current
Output High Voltage Level
Output Low Voltage Level
Standby Current: TTL
Output is disabled (Hi-Z)
0V ≤ VOUT ≤ Vcc
5
µA
V
VOH
VOL
ICC1
IOH = –5.0 mA (5V)
IOH = –2.0 mA (3.3V)
—
0.4
IOL = 4.2 mA (5V)
IOL = 2.0 mA (3.3V)
V
RAS, LCAS, UCAS ≥ VIH Commerical 5V
—
—
—
—
3
3
4
4
mA
mA
3.3V
Industrial 5V
3.3V
ICC2
ICC3
Standby Current: CMOS
RAS, LCAS, UCAS ≥ VCC – 0.2V
5V
3.3V
—
—
2
2
mA
mA
Operating Current:
RAS, LCAS, UCAS,
Address Cycling, tRC = tRC (min.)
-50
-60
—
—
160
145
Random Read/Write(2,3,4)
AveragePowerSupplyCurrent
ICC4
ICC5
Operating Current:
RAS = VIL, LCAS, UCAS,
Cycling tPC = tPC (min.)
-50
-60
—
—
90
80
mA
mA
mA
EDO Page Mode(2,3,4)
AveragePowerSupplyCurrent
Refresh Current:
RAS Cycling, LCAS, UCAS ≥ VIH
tRC = tRC (min.)
-50
-60
—
—
160
145
RAS-Only(2,3)
AveragePowerSupplyCurrent
ICC6
Refresh Current:
CBR(2,3,5)
RAS, LCAS, UCAS Cycling
tRC = tRC (min.)
-50
-60
—
—
160
145
AveragePowerSupplyCurrent
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
6
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IS41C16100
IS41LV16100
ISSI
ACCHARACTERISTICS(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-50
-60
Symbol
tRC
Parameter
Min. Max.
Min. Max.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Random READ or WRITE Cycle Time
Access Time from RAS(6, 7)
Access Time from CAS(6, 8, 15)
Access Time from Column-Address(6)
RAS Pulse Width
84
—
—
—
50
30
8
—
50
13
25
10K
—
104
—
—
—
60
40
10
9
—
60
15
30
10K
—
tRAC
tCAC
tAA
tRAS
tRP
RAS Precharge Time
CAS Pulse Width(26)
CAS Precharge Time(9, 25)
CAS Hold Time (21)
RAS to CAS Delay Time(10, 20)
Row-Address Setup Time
Row-Address Hold Time
Column-Address Setup Time(20)
Column-Address Hold Time(20)
tCAS
tCP
10K
—
10K
—
9
tCSH
tRCD
tASR
tRAH
tASC
tCAH
tAR
38
12
0
—
40
14
0
—
37
—
45
—
8
—
10
0
—
0
—
—
8
—
10
40
—
Column-Address Hold Time
30
—
—
(referenced to RAS)
tRAD
tRAL
tRPC
tRSH
tRHCP
tCLZ
tCRP
tOD
RAS to Column-Address Delay Time(11)
Column-Address to RAS Lead Time
RAS to CAS Precharge Time
RAS Hold Time(27)
10
25
5
25
—
—
—
—
—
—
15
13
—
—
—
—
—
—
12
30
5
30
—
—
—
—
—
—
15
15
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
10
37
0
RAS Hold Time from CAS Precharge
CAS to Output in Low-Z(15, 29)
CAS to RAS Precharge Time(21)
Output Disable Time(19, 28, 29)
37
0
5
5
3
3
tOE
Output Enable Time(15, 16)
—
20
5
—
20
5
tOED
tOEHC
tOEP
tOES
tRCS
tRRH
Output Enable Data Delay (Write)
OE HIGH Hold Time from CAS HIGH
OE HIGH Pulse Width
10
5
10
5
OE LOW to CAS HIGH Setup Time
Read Command Setup Time(17, 20)
0
0
Read Command Hold Time
0
0
(referenced to RAS)(12)
tRCH
Read Command Hold Time
0
—
0
—
ns
(referenced to CAS)(12, 17, 21)
tWCH
tWCR
Write Command Hold Time(17, 27)
8
—
—
10
50
—
—
ns
ns
Write Command Hold Time
40
(referenced to RAS)(17)
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IS41C16100
IS41LV16100
ISSI
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-50
-60
Symbol
tWP
Parameter
Min. Max.
Min. Max.
Units
ns
Write Command Pulse Width(17)
WE Pulse Widths to Disable Outputs
Write Command to RAS Lead Time(17)
Write Command to CAS Lead Time(17, 21)
Write Command Setup Time(14, 17, 20)
Data-in Hold Time (referenced to RAS)
8
10
13
8
—
—
—
—
—
—
—
10
10
15
10
0
—
—
—
—
—
—
—
tWPZ
ns
tRWL
tCWL
tWCS
tDHR
tACH
ns
ns
0
ns
39
15
39
15
ns
Column-Address Setup Time to CAS
ns
Precharge during WRITE Cycle
tOEH
OE Hold Time from WE during
8
—
10
—
ns
READ-MODIFY-WRITE cycle(18)
tDS
Data-In Setup Time(15, 22)
0
8
—
—
—
—
0
—
—
—
—
ns
ns
ns
ns
tDH
Data-In Hold Time(15, 22)
10
tRWC
tRWD
READ-MODIFY-WRITE Cycle Time
108
64
133
77
RAS to WE Delay Time during
READ-MODIFY-WRITE Cycle(14)
tCWD
tAWD
tPC
CAS to WE Delay Time(14, 20)
Column-Address to WE Delay Time(14)
26
39
20
—
—
—
32
47
25
—
—
—
ns
ns
ns
EDO Page Mode READ or WRITE
Cycle Time(24)
tRASP
tCPA
RAS Pulse Width in EDO Page Mode
Access Time from CAS Precharge(15)
50
—
56
100K
30
60
—
68
100K
35
ns
ns
ns
tPRWC
EDO Page Mode READ-WRITE
Cycle Time(24)
—
—
tCOH
tOFF
Data Output Hold after CAS LOW
5
—
12
5
—
15
ns
ns
Output Buffer Turn-Off Delay from
1.6
1.6
CAS or RAS(13,15,19, 29)
tWHZ
Output Disable Delay from WE
3
10
—
3
10
—
ns
ns
tCLCH
Last CAS going LOW to First CAS
10
10
returning HIGH(23)
tCSR
tCHR
tORD
CAS Setup Time (CBR REFRESH)(30, 20)
CAS Hold Time (CBR REFRESH)(30, 21)
5
8
0
—
—
—
5
10
0
—
—
—
ns
ns
ns
OE Setup Time prior to RAS during
HIDDEN REFRESH Cycle
tREF
tREF
tT
Auto Refresh Period (1,024 Cycles)
Self Refresh Period (1,024 Cycles)
Transition Time (Rise or Fall)(2, 3)
—
—
1
16
128
50
—
—
1
16
128
50
ms
ms
ns
8
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®
IS41C16100
IS41LV16100
ISSI
AC TEST CONDITIONS
Output load: Two TTL Loads and 50 pF (Vcc = 5.0V ±10%)
One TTL Load and 50 pF (Vcc = 3.3V ±10%)
Input timing reference levels: VIH = 2.4V, VIL = 0.8V (Vcc = 5.0V ±10%);
VIH = 2.0V, VIL = 0.8V (Vcc = 3.3V ±10%)
Output timing reference levels: VOH = 2.0V, VOL = 0.8V (Vcc = 5V ±10%, 3.3V ±10%)
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH and
VIL (or between VIL and VIH) and assume to be 1 ns for all inputs.
3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a
monotonicmanner.
4. If CAS and RAS = VIH, data output is High-Z.
5. If CAS = VIL, data output may contain data from the last valid READ cycle.
6. Measured with a load equivalent to one TTL gate and 50 pF.
7. AssumesthattRCD - tRCD (MAX). IftRCD isgreaterthanthemaximumrecommendedvalueshowninthistable, tRAC willincreasebythe
amount that tRCD exceeds the value shown.
8. Assumes that tRCD • tRCD (MAX).
9. IfCASisLOWatthefallingedgeof RAS, dataoutwillbemaintainedfromthepreviouscycle. Toinitiateanewcycleandclearthedata
output buffer, CAS and RAS must be pulsed for tCP.
10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD is
greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC.
11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD is
greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA.
12. Either tRCH or tRRH must be satisfied for a READ cycle.
13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL.
14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS • tWCS
(MIN),thecycleisanEARLYWRITEcycleandthedataoutputwillremainopencircuitthroughouttheentirecycle.IftRWD • tRWD (MIN),
tAWD • tAWD (MIN)andtCWD • tCWD (MIN),thecycleisaREAD-WRITEcycleandthedataoutputwillcontaindatareadfromtheselected
cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to VIH) is
indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle.
15. Output parameter (I/O) is referenced to corresponding CAS input, I/O0-I/O7 by LCAS and I/O8-I/O15 by UCAS.
16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. IfOE is tied permanently LOW, a LATE
WRITE or READ-MODIFY-WRITE is not possible.
17. Write command is defined as WE going low.
18. LATEWRITEandREAD-MODIFY-WRITEcyclesmusthavebothtOD andtOEH met(OEHIGHduringWRITEcycle)inordertoensure
thattheoutputbufferswillbeopenduringtheWRITEcycle. TheI/OswillprovidethepreviouslywrittendataifCASremainsLOWand
OE is taken back to LOW after tOEH is met.
19. The I/Os are in open during READ cycles once tOD or tOFF occur.
20. The first χCAS edge to transition LOW.
21. The last χCAS edge to transition HIGH.
22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ-
MODIFY-WRITE cycles.
23. Last falling χCAS edge to first rising χCAS edge.
24. Last rising χCAS edge to next cycle’s last rising χCAS edge.
25. Last rising χCAS edge to first falling χCAS edge.
26. Each χCAS must meet minimum pulse width.
27. Last χCAS to go LOW.
28. I/Os controlled, regardless UCAS and LCAS.
29. The 3 ns minimum is a parameter guaranteed by design.
30. Enables on-chip refresh and address counters.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
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04/16/03
®
IS41C16100
IS41LV16100
ISSI
READCYCLE
t
RC
t
RAS
t
RP
RAS
t
CSH
t
RSH
t
RRH
t
CRP
ASR
t
CAS CLCH
t
t
RCD
UCAS/LCAS
t
AR
t
RAD
tRAL
t
t
RAH
t
CAH
t
ASC
ADDRESS
WE
Row
Column
Row
t
RCS
t
RCH
t
AA
t
RAC
(1)
OFF
t
t
CAC
CLC
t
Open
Open
Valid Data
I/O
OE
t
OE
tOD
t
OES
Undefined
Don’t Care
Note:
1. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
10
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R e v .
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04/16/03
®
IS41C16100
IS41LV16100
ISSI
EARLY WRITE CYCLE (OE = DON'T CARE)
t
RC
t
RAS
tRP
RAS
t
CSH
t
RSH
t
CRP
ASR
t
CAS CLCH
t
t
RCD
UCAS/LCAS
ADDRESS
t
AR
t
RAD
t
t
t
RAL
CAH
ACH
t
t
RAH
t
ASC
Row
Column
Row
t
t
CWL
RWL
t
WCR
t
WCS
tWCH
t
WP
WE
I/O
t
DHR
t
DH
t
DS
Valid Data
Don’t Care
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
11
R e v .
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04/16/03
®
IS41C16100
IS41LV16100
ISSI
READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)
t
t
RWC
RAS
t
RP
RAS
t
CSH
t
RSH
t
CRP
ASR
t
CAS CLCH
t
t
RCD
UCAS/LCAS
t
AR
t
RAD
tRAL
t
t
RAH
tCAH
t
ASC
t
ACH
ADDRESS
WE
Row
Column
Row
t
RWD
tCWL
t
RCS
t
CWD
t
RWL
t
AWD
t
WP
t
AA
t
RAC
t
t
CAC
CLZ
t
DS
tDH
Open
Open
Valid DOUT
Valid DIN
I/O
OE
t
OD
tOEH
t
OE
Undefined
Don’t Care
12
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R e v .
I
04/16/03
®
IS41C16100
IS41LV16100
ISSI
EDO-PAGE-MODE READ CYCLE
t
RASP
t
RP
RAS
(1)
PC
t
CSH
t
t
RSH
t
CRP
t
CAS,
t
CP
t
CAS,
t
CP
t
CAS,
tCP
t
RCD
t
CLCH
t
CLCH
tCLCH
UCAS/LCAS
t
AR
t
RAD
t
RAL
CAH
t
ASR
t
ASC
t
CAH
t
ASC
t
CAH
t
ASC
t
ADDRESS
WE
Row
Column
Column
Column
Row
t
RAH
t
RRH
t
RCS
t
RCH
t
AA
t
AA
t
AA
t
RAC
CAC
CLZ
t
CPA
t
CPA
t
t
t
CAC
t
t
CAC
CLZ
t
COH
t
OFF
Open
Open
Valid Data
Valid Data
Valid Data
I/O
OE
t
OE
t
OEHC
tOE
t
OD
t
OES
t
OD
t
OES
t
OEP
Undefined
Don’t Care
Note:
1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both
measurements must meet the tPC specifications.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
13
R e v .
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®
IS41C16100
IS41LV16100
ISSI
EDO-PAGE-MODE EARLY-WRITE CYCLE
t
RASP
t
RP
t
RHCP
RAS
t
CSH
t
PC
t
RSH
t
CRP
t
CAS,
t
CP
t
CAS,
t
CP
t
CAS,
tCP
t
RCD
t
CLCH
t
CLCH
tCLCH
UCAS/LCAS
ADDRESS
t
AR
tACH
t
ACH
t
ACH
CAH
t
RAD
t
RAL
t
ASR
t
ASC
t
CAH
t
ASC
t
t
ASC
t
CAH
Row
Column
Column
Column
Row
t
RAH
t
CWL
WCS
WCH
t
CWL
tCWL
t
t
WCS
t
WCS
t
t
WCH
tWCH
t
WP
t
WP
t
WP
WE
t
WCR
DHR
tRWL
t
tDS
tDS
tDS
t
DH
t
DH
tDH
I/O
OE
Valid Data
Valid Data
Valid Data
Don’t Care
14
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
R e v .
I
04/16/03
®
IS41C16100
IS41LV16100
ISSI
EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY WRITE Cycles)
t
RASP
t
RP
RAS
(1)
tPC / tPRWC
t
CSH
t
RSH
CLCH
t
CRP
t
RCD
t
CAS,
t
CLCH
t
CP
t
CAS,
t
CLCH
t
CP
t
CAS,
t
tCP
UCAS/LCAS
t
AR
t
ASR
t
t
RAD
t
RAL
t
ASC
t
CAH
t
ASC
t
CAH
t
ASC
tCAH
RAH
ADDRESS
Row
Column
Column
Column
Row
tRWD
tRCS
t
t
t
RWL
CWL
WP
t
t
CWL
WP
t
t
CWL
WP
t
AWD
t
AWD
t
AWD
t
CWD
t
CWD
t
CWD
WE
t
AA
t
AA
CPA
t
AA
tCPA
t
t
RAC
t
DH
DS
t
DH
DS
t
DH
tDS
t
t
t
CAC
t
CAC
t
CAC
t
CLZ
t
CLZ
t
CLZ
Open
Open
I/O
OE
DOUT
D
IN
DOUT
D
IN
DOUT
D
IN
t
OD
t
OD
t
OD
t
OE
t
OE
tOE
t
OEH
Undefined
Don’t Care
Note:
1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both
measurements must meet the tPC specifications.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
15
R e v .
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04/16/03
®
IS41C16100
IS41LV16100
ISSI
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Psuedo READ-MODIFY WRITE)
t
RASP
t
RP
RAS
t
CSH
t
PC
tPC
t
RSH
t
CRP
t
RCD
t
CAS
t
CP
t
CAS
t
CP
t
CAS
tCP
UCAS/LCAS
t
AR
t
ACH
RAL
CAH
t
ASR
t
t
RAD
t
t
ASC
t
CAH
t
ASC
t
CAH
t
ASC
t
RAH
ADDRESS
WE
Row
Column (A)
Column (B)
Column (N)
Row
t
RCS
t
RCH
t
WCS
tWCH
t
WHZ
t
AA
t
AA
t
CPA
CAC
COH
t
RAC
CAC
t
t
t
t
DS
tDH
Open
Open
I/O
OE
Valid Data (A)
Valid Data (B)
DIN
t
OE
Don’t Care
16
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
R e v .
I
04/16/03
®
IS41C16100
IS41LV16100
ISSI
AC WAVEFORMS
READ CYCLE (With WE-Controlled Disable)
RAS
t
CSH
t
CRP
ASR
t
RCD
tCP
t
CAS
UCAS/LCAS
t
AR
t
RAD
t
t
RAH
t
CAH
tASC
t
ASC
ADDRESS
WE
Row
Column
Column
t
RCS
t
RCH
tRCS
t
AA
t
RAC
t
t
CAC
CLZ
t
WHZ
tCLZ
Open
Open
Valid Data
I/O
OE
t
OE
tOD
Undefined
Don’t Care
RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE)
t
RC
t
RAS
tRP
RAS
t
CRP
t
RPC
UCAS/LCAS
t
ASR
tRAH
ADDRESS
I/O
Row
Row
Open
Don’t Care
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
17
R e v .
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04/16/03
®
IS41C16100
IS41LV16100
ISSI
CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE)
t
RP
t
RAS
t
RP
t
RAS
RAS
t
CHR
t
CHR
t
RPC
CP
tRPC
t
t
CSR
tCSR
UCAS/LCAS
I/O
Open
HIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW)
t
RAS
t
RAS
t
RP
RAS
t
CRP
t
RCD
t
RSH
tCHR
UCAS/LCAS
t
AR
t
RAD
t
RAL
t
ASR
t
RAH
tCAH
t
ASC
ADDRESS
Row
Column
t
AA
t
RAC
(2)
t
OFF
t
CAC
t
CLZ
Open
Open
Valid Data
I/O
OE
t
OE
tOD
t
ORD
Undefined
Don’t Care
Notes:
1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH.
2. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
18
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
R e v .
I
04/16/03
®
IS41C16100
IS41LV16100
ISSI
ORDERING INFORMATION : 5V
Commercial Range: 0°C to 70°C
Speed (ns) Order Part No.
Package
50
IS41C16100-50K
IS41C16100-50T
400-mil SOJ
400-mil TSOP (Type II)
60
IS41C16100-60K
IS41C16100-60T
400-milSOJ
400-mil TSOP (Type II)
Industrial Range: -40°C to 85°C
Speed (ns) Order Part No.
Package
50
IS41C16100-50KI
IS41C16100-50TI
400-mil SOJ
400-mil TSOP (Type II)
60
IS41C16100-60KI
IS41C16100-60TI
400-milSOJ
400-mil TSOP (Type II)
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
19
R e v .
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04/16/03
®
IS41C16100
IS41LV16100
ISSI
ORDERING INFORMATION : 3.3V
Commercial Range: 0°C to 70°C
Speed (ns)
Order Part No.
P a c k a g e
50
IS41LV16100-50K
400-milSOJ
IS41LV16100-50T
IS41LV16100-50TL
400-milTSOP(TypeII)
400-milTSOP(TypeII),Lead-free
60
IS41LV16100-60K
IS41LV16100-60T
IS41LV16100-60TL
400-milSOJ
400-milTSOP(TypeII)
400-milTSOP(TypeII), Lead-free
Industrial Range: -40°C to 85°C
Speed (ns)
Order Part No.
P a c k a g e
50
IS41LV16100-50KI
400-milSOJ
IS41LV16100-50TI
IS41LV16100-50TLI
400-milTSOP(TypeII)
400-milTSOP(TypeII),Lead-free
60
IS41LV16100-60KI
IS41LV16100-60TI
IS41LV16100-60TLI
400-milSOJ
400-milTSOP(TypeII)
400-milTSOP(TypeII),Lead-free
20
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R e v .
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04/16/03
相关型号：
IS41C16100-60TL-TR
EDO DRAM, 1MX16, 60ns, CMOS, PDSO44, 0.400 INCH, LEADFREE, PLASTIC, TSOP2-50/44
ISSI
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