IS41C16100C-50TI-TR [ISSI]
EDO DRAM, 1MX16, 50ns, CMOS, PDSO44,;
| 型号： | IS41C16100C-50TI-TR |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | EDO DRAM, 1MX16, 50ns, CMOS, PDSO44, 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总22页 (文件大小：508K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS41C16100C
IS41LV16100C
1Mx16
FEBRUARY 2012
16Mb DRAM WITH EDO PAGE MODE
FEATURES
DESCRIPTION
•ꢀ TTLꢀcompatibleꢀinputsꢀandꢀoutputs;ꢀtristateꢀI/O
TheꢀISSIꢀIS41C16100CꢀandꢀIS41LV16100Cꢀareꢀ1,048,576ꢀ
xꢀ16-bitꢀhigh-performanceꢀCMOSꢀꢀDynamicꢀRandomꢀAc-
cessꢀMemories.ꢀꢀTheseꢀdevicesꢀofferꢀaꢀcycleꢀaccessꢀcalledꢀ
ExtendedꢀDataꢀOutꢀ(EDO)ꢀPageꢀMode.ꢀEDOꢀPageꢀModeꢀ
allowsꢀ1,024ꢀrandomꢀaccessesꢀwithinꢀaꢀsingleꢀrowꢀwithꢀ
accessꢀcycleꢀtimeꢀasꢀshortꢀasꢀ30ꢀnsꢀperꢀ16-bitꢀword.ꢀItꢀisꢀ
asynchronous,ꢀasꢀitꢀdoesꢀnotꢀrequireꢀaꢀclockꢀsignalꢀinputꢀ
toꢀsynchronizeꢀcommandsꢀandꢀI/O.
•ꢀ RefreshꢀInterval:ꢀ
ꢀ —ꢀ AutoꢀrefreshꢀMode:ꢀ1,024ꢀcyclesꢀ/16ꢀms
ꢀ —ꢀ RAS-Only,ꢀCAS-before-RASꢀ(CBR),ꢀandꢀHidden
ꢀ —ꢀ SelfꢀrefreshꢀMode:ꢀ1,024ꢀcyclesꢀ/128ꢀms
•ꢀ JEDECꢀstandardꢀpinout
•ꢀ Singleꢀpowerꢀsupply:ꢀꢀ
5Vꢀ ꢀ10%ꢀ(IS41C16100C)ꢀ
3.3Vꢀ ꢀ10%ꢀ(IS41LV16100C)
TheseꢀfeaturesꢀmakeꢀtheꢀIS41C/41LV16100Cꢀideallyꢀsuitedꢀ
forꢀhigh-bandwidthꢀgraphics,ꢀdigitalꢀsignalꢀprocessing,ꢀ
high-performanceꢀ computingꢀ systems,ꢀ andꢀ peripheralꢀ
applicationsꢀthatꢀrunꢀwithoutꢀaꢀclockꢀtoꢀsynchronizeꢀwithꢀ
theꢀDRAM.
•ꢀ ByteꢀWriteꢀandꢀByteꢀReadꢀoperationꢀviaꢀꢀtwoꢀCAS
•ꢀ IndustrialꢀTemperatureꢀRange:ꢀꢀ-40oCꢀtoꢀ+85oC
TheꢀIS41C/41LV16100Cꢀisꢀpackagedꢀinꢀaꢀ42-pinꢀ400-milꢀ
SOJꢀandꢀ400-milꢀ50/44ꢀpinꢀTSOPꢀ(TypeꢀII).
KEY TIMING PARAMETERS
Parameter
-50
50ꢀ
14ꢀ
25ꢀ
30ꢀ
85ꢀ
Unit
ns
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Max.ꢀRASꢀAccessꢀTimeꢀ(trac)ꢀ
Max.ꢀCASꢀAccessꢀTimeꢀ(tcac)ꢀ
Max.ꢀColumnꢀAddressꢀAccessꢀTimeꢀ(taa)ꢀ
Min.ꢀEDOꢀPageꢀModeꢀCycleꢀTimeꢀ(tpc)ꢀ
Min.ꢀRead/WriteꢀCycleꢀTimeꢀ(trc)ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ns
ns
ns
ns
Copyrightꢀ©ꢀ2012ꢀIntegratedꢀSiliconꢀSolution,ꢀInc.ꢀꢀAllꢀrightsꢀreserved.ꢀꢀISSIꢀreservesꢀtheꢀrightꢀtoꢀmakeꢀchangesꢀtoꢀthisꢀspecificationꢀandꢀitsꢀproductsꢀatꢀanyꢀtimeꢀwithoutꢀ
notice.ꢀꢀꢀISSIꢀassumesꢀnoꢀliabilityꢀarisingꢀoutꢀofꢀtheꢀapplicationꢀorꢀuseꢀofꢀanyꢀinformation,ꢀproductsꢀorꢀservicesꢀdescribedꢀherein.ꢀCustomersꢀareꢀadvisedꢀtoꢀobtainꢀtheꢀlat-
estꢀversionꢀofꢀthisꢀdeviceꢀspecificationꢀbeforeꢀrelyingꢀonꢀanyꢀpublishedꢀinformationꢀandꢀbeforeꢀplacingꢀordersꢀforꢀproducts.ꢀꢀ
IntegratedꢀSiliconꢀSolution,ꢀInc.ꢀdoesꢀnotꢀrecommendꢀtheꢀuseꢀofꢀanyꢀofꢀitsꢀproductsꢀinꢀlifeꢀsupportꢀapplicationsꢀwhereꢀtheꢀfailureꢀorꢀmalfunctionꢀofꢀtheꢀproductꢀcanꢀreasonablyꢀbeꢀex-
pectedꢀtoꢀcauseꢀfailureꢀofꢀtheꢀlifeꢀsupportꢀsystemꢀorꢀtoꢀsignificantlyꢀaffectꢀitsꢀsafetyꢀorꢀeffectiveness.ꢀProductsꢀareꢀnotꢀauthorizedꢀforꢀuseꢀinꢀsuchꢀapplicationsꢀunlessꢀIntegratedꢀSiliconꢀ
Solution,ꢀInc.ꢀreceivesꢀwrittenꢀassuranceꢀtoꢀitsꢀsatisfaction,ꢀthat:
a.)ꢀtheꢀriskꢀofꢀinjuryꢀorꢀdamageꢀhasꢀbeenꢀminimized;
b.)ꢀtheꢀuserꢀassumeꢀallꢀsuchꢀrisks;ꢀand
c.)ꢀpotentialꢀliabilityꢀofꢀIntegratedꢀSiliconꢀSolution,ꢀIncꢀisꢀadequatelyꢀprotectedꢀunderꢀtheꢀcircumstances
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
1
Rev. C
02/16/2012
IS41C16100C
IS41LV16100C
PIN CONFIGURATIONS
50(44)-Pin TSOP (Type II)
42-Pin SOJ
VDD
I/O0
I/O1
I/O2
I/O3
VDD
I/O4
I/O5
I/O6
I/O7
NC
1
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
VDD
I/O0
I/O1
I/O2
I/O3
VDD
I/O4
I/O5
I/O6
I/O7
NC
1
44
43
42
41
40
39
38
37
36
35
34
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
11
I/O8
NC
10
11
12
13
14
15
16
17
18
19
20
21
NC
NC
WE
RAS
NC
NC
A0
12
13
14
15
16
17
18
19
20
21
22
33
32
31
30
29
28
27
26
25
24
23
NC
NC
LCAS
UCAS
OE
LCAS
UCAS
OE
WE
RAS
NC
A9
A9
NC
A8
A8
A7
A0
A7
A1
A6
A1
A6
A2
A5
A2
A5
A3
A4
A3
A4
VDD
GND
VDD
GND
PIN DESCRIPTIONS
A0-A9ꢀ
I/O0-15ꢀ
WEꢀ
AddressꢀInputs
DataꢀInputs/Outputs
WriteꢀEnable
OEꢀ
OutputꢀEnable
RASꢀ
UCASꢀ
LCASꢀ
Vddꢀ
RowꢀAddressꢀStrobe
UpperꢀColumnꢀAddressꢀStrobe
LowerꢀColumnꢀAddressꢀStrobe
Power
GNDꢀ
NCꢀ
Ground
NoꢀConnection
2ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
02/16/2012
IS41C16100C
IS41LV16100C
FUNCTIONAL BLOCK DIAGRAM
OE
WE
WE
CONTROL
LOGICS
OE
CONTROL
LOGIC
CAS
CLOCK
GENERATOR
LCAS
UCAS
CAS
WE
DATA I/O BUS
RAS
CLOCK
RAS
GENERATOR
COLUMN DECODERS
SENSE AMPLIFIERS
REFRESH
COUNTER
I/O0-I/O15
MEMORY ARRAY
1,048,576 x 16
ADDRESS
BUFFERS
A0-A9
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
3
Rev. C
02/16/2012
IS41C16100C
IS41LV16100C
TRUTH TABLE(5)
Function
Standbyꢀ
ꢀ
ꢀ
ꢀ
RASꢀ LCASꢀ UCASꢀ WEꢀ
OE
Xꢀ
Address tR/tC
Xꢀ
I/Oꢀ
Hꢀ
Lꢀ
Xꢀ
Lꢀ
Xꢀ
Lꢀ
Xꢀ
Hꢀ
High-Z
Dout
Read:ꢀWordꢀ
Lꢀ
ROW/COLꢀ
Read:ꢀLowerꢀByteꢀ
ꢀ
ꢀ
ꢀ
Lꢀ
ꢀ
Lꢀ
ꢀ
Hꢀ
ꢀ
Hꢀ
ꢀ
Lꢀ
ꢀ
ROW/COLꢀ
ꢀ
LowerꢀByte,ꢀDout
UpperꢀByte,ꢀHigh-Z
Read:ꢀUpperꢀByteꢀ
ꢀ
ꢀ
ꢀ
Lꢀ
ꢀ
Hꢀ
ꢀ
Lꢀ
ꢀ
Hꢀ
ꢀ
Lꢀ
ꢀ
ROW/COLꢀ
ꢀ
LowerꢀByte,ꢀHigh-Zꢀꢀ
UpperꢀByte,ꢀDout
Write:ꢀWordꢀ(EarlyꢀWrite)ꢀ
ꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
ROW/COLꢀ
Din
Write:ꢀLowerꢀByteꢀ(EarlyꢀWrite)ꢀ
ꢀ
ꢀ
ꢀ
Lꢀ
ꢀ
Lꢀ
ꢀ
Hꢀ
ꢀ
Lꢀ
ꢀ
Xꢀ
ꢀ
ROW/COLꢀ
ꢀ
LowerꢀByte,ꢀDinꢀ
UpperꢀByte,ꢀHigh-Z
Write:ꢀUpperꢀByteꢀ(EarlyꢀWrite)ꢀ
ꢀ
ꢀ
ꢀ
Lꢀ
ꢀ
Hꢀ
ꢀ
Lꢀ
ꢀ
Lꢀ
ꢀ
Xꢀ
ꢀ
ROW/COLꢀ
ꢀ
LowerꢀByte,ꢀHigh-Zꢀꢀ
UpperꢀByte,ꢀDin
Read-Write(1,2)
ꢀ
ꢀ
Lꢀ
Lꢀ
Lꢀ
H→Lꢀ L→Hꢀ
ROW/COLꢀ
Dout,ꢀDin
EDOꢀPage-ModeꢀRead(2)ꢀ1stꢀCycle:ꢀ
Lꢀ
Lꢀ
Lꢀ
H→Lꢀ H→Lꢀ
H→Lꢀ H→Lꢀ
L→Hꢀ L→Hꢀ
H→Lꢀ H→Lꢀ
H→Lꢀ H→Lꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
ROW/COLꢀ
NA/COLꢀ
NA/NAꢀ
Dout
Dout
Dout
ꢀ
ꢀ
2ndꢀCycle:ꢀ
AnyꢀCycle:ꢀ
EDOꢀPage-ModeꢀWrite(1)ꢀ 1stꢀCycle:ꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
Xꢀ
ROW/COLꢀ
NA/COLꢀ
Din
Din
ꢀ
2ndꢀCycle:ꢀ
EDOꢀPage-Mode(1,2)ꢀꢀ
Read-Writeꢀ
1stꢀCycle:ꢀ
2ndꢀCycle:ꢀ
Lꢀ
Lꢀ
H→Lꢀ H→Lꢀ H→Lꢀ L→Hꢀ
H→Lꢀ H→Lꢀ H→Lꢀ L→Hꢀ
ROW/COLꢀ
NA/COLꢀ
Dout,ꢀDin
Dout,ꢀDin
HiddenꢀRefreshꢀ
ꢀ
Read(2)ꢀ ꢀ
L→H→Lꢀ Lꢀ
L→H→Lꢀ Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Xꢀ
ROW/COLꢀ
ROW/COLꢀ
Dout
Dout
Write(1,3)ꢀ ꢀ
RAS-OnlyꢀRefreshꢀ
CBRꢀRefresh(4)ꢀ
Notes:ꢀ
ꢀ
ꢀ
Lꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Xꢀ
Xꢀ
ROW/NAꢀ
Xꢀ
High-Z
High-Z
H→Lꢀ
1.ꢀ TheseꢀWRITEꢀcyclesꢀmayꢀalsoꢀbeꢀBYTEꢀWRITEꢀcyclesꢀ(eitherꢀLCASꢀorꢀUCASꢀactive).
2.ꢀ TheseꢀREADꢀcyclesꢀmayꢀalsoꢀbeꢀBYTEꢀREADꢀcyclesꢀ(eitherꢀLCASꢀorꢀUCASꢀactive).
3.ꢀ EARLYꢀWRITEꢀonly.
4.ꢀ AtꢀleastꢀoneꢀofꢀtheꢀtwoꢀCASꢀsignalsꢀmustꢀbeꢀactiveꢀ(LCASꢀorꢀUCAS).
5.ꢀꢀCommandsꢀvalidꢀonlyꢀafterꢀproperꢀinitialization.
4ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
02/16/2012
IS41C16100C
IS41LV16100C
Functional Description
anꢀinternalꢀ9-bitꢀcounterꢀprovidesꢀtheꢀrowꢀaddressesꢀ
andꢀtheꢀexternalꢀaddressꢀinputsꢀareꢀignored.
Theꢀ IS41C/41LV16100Cꢀ isꢀ aꢀ CMOSꢀ DRAMꢀ optimizedꢀ
forꢀhigh-speedꢀbandwidth,ꢀlowꢀpowerꢀapplications.ꢀDuringꢀ
READꢀorꢀWRITEꢀcycles,ꢀeachꢀbitꢀisꢀuniquelyꢀaddressedꢀ
throughꢀtheꢀ16ꢀaddressꢀbits.ꢀTheseꢀareꢀenteredꢀtenꢀbitsꢀ
(A0-A9)ꢀatꢀꢀtime.ꢀꢀTheꢀrowꢀaddressꢀisꢀlatchedꢀbyꢀtheꢀRowꢀ
AddressꢀStrobeꢀ(RAS).ꢀTheꢀcolumnꢀaddressꢀisꢀlatchedꢀbyꢀ
theꢀColumnꢀAddressꢀStrobeꢀ(CAS).ꢀRASꢀisꢀusedꢀtoꢀlatchꢀ
theꢀfirstꢀnineꢀbitsꢀandꢀCASꢀisꢀusedꢀtoꢀlatchꢀtheꢀlatterꢀnineꢀbits.
CAS-before-RASꢀ isꢀ aꢀ refresh-onlyꢀ modeꢀ andꢀ noꢀ dataꢀ
accessꢀorꢀdeviceꢀselectionꢀisꢀallowed.ꢀThus,ꢀtheꢀoutputꢀ
remainsꢀinꢀtheꢀHigh-Zꢀstateꢀduringꢀtheꢀcycle.
Self Refresh Cycle
ꢀTheꢀSelfꢀRefreshꢀallowsꢀtheꢀuserꢀaꢀdynamicꢀrefresh,ꢀdataꢀ
retentionꢀmodeꢀatꢀtheꢀextendedꢀrefreshꢀperiodꢀofꢀ128ꢀms.ꢀ
i.e.,ꢀ125ꢀµsꢀperꢀrowꢀwhenꢀusingꢀdistributedꢀCBRꢀrefreshes.ꢀ
Theꢀfeatureꢀalsoꢀallowsꢀtheꢀuserꢀtheꢀchoiceꢀofꢀaꢀfullyꢀstatic,ꢀ
lowꢀpowerꢀdataꢀretentionꢀmode.ꢀTheꢀoptionalꢀSelfꢀRefreshꢀ
featureꢀisꢀinitiatedꢀbyꢀperformingꢀaꢀCBRꢀRefreshꢀcycleꢀandꢀ
holdingꢀRASꢀꢀLOWꢀforꢀtheꢀspecifiedꢀtRAS.
TheꢀIS41C/41LV16100CꢀhasꢀtwoꢀCASꢀcontrols,ꢀLCASꢀandꢀ
UCAS.ꢀTheꢀLCASꢀandꢀUCASꢀinputsꢀinternallyꢀgeneratesꢀaꢀ
CASꢀsignalꢀfunctioningꢀinꢀanꢀidenticalꢀmannerꢀtoꢀtheꢀsingleꢀ
CASꢀinputꢀonꢀtheꢀotherꢀ1Mꢀxꢀ16ꢀDRAMs.ꢀTheꢀkeyꢀdifferenceꢀ
isꢀthatꢀeachꢀCASꢀcontrolsꢀitsꢀcorrespondingꢀI/Oꢀtristateꢀlogicꢀ
(inꢀconjunctionꢀwithꢀOEꢀandꢀWEꢀandꢀRAS).ꢀLCASꢀcontrolsꢀI/
O0ꢀthroughꢀI/O7ꢀandꢀUCASꢀcontrolsꢀI/O8ꢀthroughꢀꢀI/O15.ꢀ
Theꢀ Selfꢀ Refreshꢀ modeꢀ isꢀ terminatedꢀ byꢀ drivingꢀ RASꢀ
HIGHꢀforꢀaꢀminimumꢀtimeꢀofꢀtRP.ꢀThisꢀdelayꢀallowsꢀforꢀtheꢀ
completionꢀofꢀanyꢀinternalꢀrefreshꢀcyclesꢀthatꢀmayꢀbeꢀinꢀ
processꢀatꢀtheꢀtimeꢀofꢀtheꢀRASꢀLOW-to-HIGHꢀtransition.ꢀIfꢀ
theꢀDRAMꢀcontrollerꢀusesꢀaꢀdistributedꢀrefreshꢀsequence,ꢀ
aꢀburstꢀrefreshꢀisꢀnotꢀrequiredꢀuponꢀexitingꢀSelfꢀRefresh.
TheꢀIS41C/41LV16100CꢀꢀCASꢀfunctionꢀisꢀdeterminedꢀbyꢀ
theꢀfirstꢀCASꢀ(LCASꢀorꢀUCAS)ꢀtransitioningꢀLOWꢀandꢀtheꢀ
lastꢀtransitioningꢀbackꢀHIGH.ꢀTheꢀtwoꢀCASꢀcontrolsꢀgiveꢀ
theꢀIS41C16100CꢀandꢀIS41LV16100CꢀbothꢀBYTEꢀREADꢀ
andꢀBYTEꢀWRITEꢀꢀcycleꢀcapabilities.
However,ꢀifꢀtheꢀDRAMꢀcontrollerꢀutilizesꢀaꢀRAS-onlyꢀorꢀburstꢀ
refreshꢀsequence,ꢀallꢀ1,024ꢀrowsꢀmustꢀbeꢀrefreshedꢀwithinꢀ
theꢀaverageꢀinternalꢀrefreshꢀrate,ꢀpriorꢀtoꢀtheꢀresumptionꢀ
Memory Cycle
AꢀmemoryꢀcycleꢀisꢀinitiatedꢀbyꢀbringꢀRASꢀLOWꢀandꢀitꢀisꢀ
terminatedꢀ byꢀ returningꢀ bothꢀ RASꢀ andꢀ CASꢀ HIGH.ꢀToꢀ
ensuresꢀproperꢀdeviceꢀoperationꢀandꢀdataꢀintegrityꢀanyꢀ
memoryꢀcycle,ꢀonceꢀinitiated,ꢀmustꢀnotꢀbeꢀendedꢀorꢀabortedꢀ
beforeꢀtheꢀminimumꢀtrasꢀtimeꢀhasꢀexpired.ꢀAꢀnewꢀcycleꢀ
mustꢀnotꢀbeꢀinitiatedꢀuntilꢀtheꢀminimumꢀprechargeꢀtimeꢀ
trp,ꢀtcpꢀhasꢀelapsed.
ofꢀnormalꢀoperation.ꢀꢀ
Extended Data Out Page Mode
EDOꢀ pageꢀ modeꢀ operationꢀ permitsꢀ allꢀ 1,024ꢀ columnsꢀ
withinꢀaꢀselectedꢀrowꢀtoꢀbeꢀrandomlyꢀaccessedꢀatꢀaꢀhighꢀ
dataꢀrate.ꢀ
Read Cycle
InꢀEDOꢀpageꢀmodeꢀreadꢀcycle,ꢀtheꢀdata-outꢀisꢀheldꢀtoꢀtheꢀ
nextꢀCASꢀcycle’sꢀfallingꢀedge,ꢀinsteadꢀofꢀtheꢀrisingꢀedge.ꢀ
Forꢀthisꢀreason,ꢀtheꢀvalidꢀdataꢀoutputꢀtimeꢀinꢀEDOꢀpageꢀ
modeꢀisꢀextendedꢀcomparedꢀwithꢀtheꢀfastꢀpageꢀmode.ꢀInꢀ
theꢀfastꢀpageꢀmode,ꢀtheꢀvalidꢀdataꢀoutputꢀtimeꢀbecomesꢀ
shorterꢀasꢀtheꢀCASꢀcycleꢀtimeꢀbecomesꢀshorter.ꢀThere-
fore,ꢀinꢀEDOꢀpageꢀmode,ꢀtheꢀtimingꢀmarginꢀinꢀreadꢀcycleꢀ
isꢀlargerꢀthanꢀthatꢀofꢀtheꢀfastꢀpageꢀmodeꢀevenꢀifꢀtheꢀCASꢀ
cycleꢀtimeꢀbecomesꢀshorter.
AꢀreadꢀcycleꢀisꢀinitiatedꢀbyꢀtheꢀfallingꢀedgeꢀofꢀCASꢀorꢀOE,ꢀ
whicheverꢀoccursꢀlast,ꢀwhileꢀholdingꢀWEꢀHIGH.Theꢀcolumnꢀ
addressꢀmustꢀbeꢀheldꢀforꢀaꢀminimumꢀtimeꢀspecifiedꢀbyꢀtar.ꢀ
DataꢀOutꢀbecomesꢀvalidꢀonlyꢀwhenꢀtrac,ꢀtaa,ꢀtcacꢀandꢀtoeaꢀ
areꢀallꢀsatisfied.ꢀAsꢀaꢀresult,ꢀtheꢀaccessꢀtimeꢀisꢀdependentꢀ
onꢀtheꢀtimingꢀrelationshipsꢀbetweenꢀtheseꢀparameters.
Write Cycle
InꢀEDOꢀpageꢀmode,ꢀdueꢀtoꢀtheꢀextendedꢀdataꢀfunction,ꢀ
theꢀCASꢀcycleꢀtimeꢀcanꢀbeꢀshorterꢀthanꢀinꢀtheꢀfastꢀpageꢀ
modeꢀifꢀtheꢀtimingꢀmarginꢀisꢀtheꢀsame.ꢀ
AꢀwriteꢀcycleꢀisꢀinitiatedꢀbyꢀtheꢀfallingꢀedgeꢀofꢀCASꢀandꢀWE,ꢀ
whicheverꢀoccursꢀlast.ꢀTheꢀinputꢀdataꢀmustꢀbeꢀvalidꢀatꢀorꢀ
beforeꢀtheꢀfallingꢀedgeꢀofꢀCASꢀorꢀWE,ꢀwhicheverꢀoccursꢀfirst.
TheꢀEDOꢀpageꢀmodeꢀallowsꢀbothꢀreadꢀandꢀwriteꢀoperationsꢀ
duringꢀoneꢀRASꢀcycle,ꢀbutꢀtheꢀperformanceꢀisꢀequivalentꢀ
toꢀthatꢀofꢀtheꢀfastꢀpageꢀmodeꢀinꢀthatꢀcase.
Auto Refresh Cycle
Toꢀretainꢀdata,ꢀ1,024ꢀrefreshꢀcyclesꢀareꢀrequiredꢀinꢀeachꢀ
16ꢀmsꢀperiod.ꢀThereꢀareꢀtwoꢀwaysꢀtoꢀrefreshꢀtheꢀmemory.
Power-On
1.ꢀ Byꢀclockingꢀeachꢀofꢀtheꢀ1,024ꢀrowꢀaddressesꢀ(A0ꢀthroughꢀ
A9)ꢀwithꢀRASꢀatꢀleastꢀonceꢀeveryꢀtrefꢀmax.ꢀAnyꢀread,ꢀwrite,ꢀ
read-modify-writeꢀorꢀRAS-onlyꢀcycleꢀrefreshesꢀtheꢀaddressedꢀ
row.
Duringꢀ Power-On,ꢀ RAS,ꢀ UCAS,ꢀ LCAS,ꢀ andꢀ WEꢀ mustꢀ
allꢀ trackꢀ withꢀ Vddꢀ (HIGH)ꢀ toꢀ avoidꢀ currentꢀ surges,ꢀ
andꢀ allowꢀ initializationꢀ toꢀ continue.ꢀ Anꢀ initialꢀ pauseꢀ ofꢀ
200ꢀµsꢀisꢀrequiredꢀfollowedꢀbyꢀaꢀminimumꢀofꢀeightꢀinitial-
izationꢀ cyclesꢀ (anyꢀ combinationꢀ ofꢀ cyclesꢀ containingꢀ aꢀ
RASꢀsignal).
2.ꢀUsingꢀaꢀCAS-before-RASꢀrefreshꢀcycle.ꢀCAS-before-
RASꢀrefreshꢀisꢀactivatedꢀbyꢀtheꢀfallingꢀedgeꢀofꢀRAS,ꢀwhileꢀ
holdingꢀCASꢀLOW.ꢀInꢀCAS-before-RASꢀrefreshꢀcycle,ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
5
Rev. C
02/16/2012
IS41C16100C
IS41LV16100C
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Parameters
Rating
Unit
ꢀ
ꢀ
ꢀ
ꢀ
Vtꢀ
ꢀ
VoltageꢀonꢀAnyꢀPinꢀRelativeꢀtoꢀGNDꢀ
ꢀ
SupplyꢀVoltageꢀ
ꢀ
5Vꢀ
3.3Vꢀ
5Vꢀ
3.3Vꢀ
–1.0ꢀtoꢀ+7.0ꢀ
–0.5ꢀtoꢀ+4.6
–1.0ꢀtoꢀ+7.0ꢀ
–0.5ꢀtoꢀ+4.6ꢀ
Vꢀ
ꢀ
ꢀ
Vddꢀ
ꢀ
Vꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Ioutꢀ
Pdꢀ
OutputꢀCurrentꢀ
PowerꢀDissipationꢀ
IndustrialꢀOperationꢀTemperatureꢀ
StorageꢀTemperatureꢀ
ꢀ
ꢀ
ꢀ
ꢀ
50ꢀ
1ꢀ
-40ꢀtoꢀ+85ꢀ
mA
W
°C
Taꢀ
Tstgꢀ
–55ꢀtoꢀ+125ꢀ °C
Note:
1.ꢀ StressꢀgreaterꢀthanꢀthoseꢀlistedꢀunderꢀABSOLUTEꢀMAXIMUMꢀRATINGSꢀmayꢀcauseꢀpermanentꢀdam-
ageꢀtoꢀtheꢀdevice.ꢀThisꢀisꢀaꢀstressꢀratingꢀonlyꢀandꢀfunctionalꢀoperationꢀofꢀtheꢀdeviceꢀatꢀtheseꢀorꢀanyꢀotherꢀ
conditionsꢀaboveꢀthoseꢀindicatedꢀinꢀtheꢀoperationalꢀsectionsꢀofꢀthisꢀspecificationꢀisꢀnotꢀimplied.ꢀExposureꢀ
toꢀabsoluteꢀmaximumꢀratingꢀconditionsꢀforꢀextendedꢀperiodsꢀmayꢀaffectꢀreliability.
RECOMMENDED OPERATING CONDITIONS
(AtꢀTaꢀ=ꢀ-40°Cꢀtoꢀ+85°CꢀforꢀIndustrialꢀgrade.ꢀVoltagesꢀareꢀreferencedꢀtoꢀGND.)
Symbol Parameter
Test Condition
Min. Typ.
Max.
Unit
Vꢀ ꢀ
ꢀ Vddꢀ
SupplyꢀVoltageꢀ
ꢀ
ꢀ
5Vꢀ
3.3Vꢀ
4.5ꢀ
3.0ꢀ
5.0ꢀ
3.3ꢀ
5.5ꢀ
3.6ꢀ
ꢀ ꢀ
ꢀ
ꢀ Vihꢀ
ꢀ ꢀ
InputꢀHighꢀVoltageꢀ
ꢀ
ꢀ
ꢀ
5V
3.3V
2.4ꢀ
2.0ꢀ
—ꢀ Vddꢀ+ꢀ1.0ꢀ Vꢀ ꢀ
—ꢀ Vddꢀ+ꢀ0.3ꢀ
ꢀ Vilꢀ
ꢀ ꢀ
InputꢀLowꢀVoltageꢀ
ꢀ
ꢀ
ꢀ
5V
3.3V
–1.0ꢀ —ꢀ
–0.3ꢀ —ꢀ
0.8ꢀ
0.8ꢀ
Vꢀ ꢀ
ꢀ iilꢀ
ꢀ ꢀ
InputꢀLeakageꢀCurrentꢀ
ꢀ
Anyꢀinputꢀ0Vꢀ≤ꢀVinꢀ≤ꢀVddꢀ
Otherꢀinputsꢀnotꢀunderꢀtestꢀ=ꢀ0Vꢀ
ꢀ
ꢀ
–5ꢀ
ꢀ
ꢀ
ꢀ
5ꢀ
µA
ꢀ iioꢀ
ꢀ ꢀ
OutputꢀLeakageꢀCurrentꢀ
ꢀ
Outputꢀisꢀdisabledꢀ(Hi-Z)ꢀ
0Vꢀ≤ꢀVoutꢀ≤ꢀVddꢀ
ꢀ
ꢀ
–5ꢀ
ꢀ
ꢀ
ꢀ
5ꢀ
ꢀ
µA
ꢀ Vohꢀ
ꢀ ꢀ
OutputꢀHighꢀVoltageꢀLevelꢀ iohꢀ=ꢀ–5.0ꢀmAꢀ
5Vꢀ
3.3Vꢀ
2.4ꢀ
2.4ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
Vꢀ ꢀ
ꢀ
iohꢀ=ꢀ–2.0ꢀmAꢀ
ꢀ Volꢀ
ꢀ ꢀ
OutputꢀLowꢀVoltageꢀLevelꢀ
ꢀ
iolꢀ=ꢀ4.2ꢀmAꢀ
iolꢀ=ꢀ2.0ꢀmAꢀ
5Vꢀ
3.3Vꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
0.4ꢀ
0.4ꢀ
Vꢀ ꢀ
ꢀ
CAPACITANCE(1,2)
Symbol
Cin1ꢀ
Parameter
InputꢀCapacitance:ꢀA0-A9ꢀ
InputꢀCapacitance:ꢀRAS,ꢀUCAS,ꢀLCAS,ꢀWE,ꢀOEꢀꢀ
Max.
Unit
ꢀ
ꢀ
ꢀ
5ꢀ
7ꢀ
7ꢀ
pF
pF
pF
Cin2ꢀ
Cioꢀ
DataꢀInput/OutputꢀCapacitance:ꢀI/O0-I/O15ꢀ
Notes:
1.ꢀ Testedꢀinitiallyꢀandꢀafterꢀanyꢀdesignꢀorꢀprocessꢀchangesꢀthatꢀmayꢀaffectꢀtheseꢀparameters.
2.ꢀ Testꢀconditions:ꢀꢀTaꢀ=ꢀ25°C,ꢀfꢀ=ꢀ1ꢀMHz.
6ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
02/16/2012
CBR(2,3,5)
ꢀ
ꢀ idd6ꢀꢀ
ꢀ ꢀ
ꢀ ꢀ
RefreshꢀCurrent:ꢀꢀ
RAS,ꢀLCAS,ꢀUCASꢀCyclingꢀ
trcꢀ=ꢀtrcꢀ(min.)ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
5Vꢀ
3.3Vꢀ
—ꢀ
—ꢀ
60ꢀ
60ꢀ
IS41C16100C
IS41LV16100C
ELECTRICAL CHARACTERISTICS(1)
(RecommendedꢀOperatingꢀConditionsꢀunlessꢀotherwiseꢀnoted.)
Symbolꢀ Parameterꢀ
StandbyꢀCurrent:ꢀTTLꢀ
Test Conditionꢀ
ꢀ
VDD
Min.ꢀ Max. Unit
ꢀ idd1ꢀꢀ
RAS,ꢀLCAS,ꢀUCASꢀ≥ꢀVihꢀ
ꢀ
ꢀ
ꢀ
5Vꢀ
3.3Vꢀ
—ꢀ
—ꢀ
2ꢀ
2ꢀ
mAꢀ
mA
ꢀ ꢀ
ꢀ
ꢀ idd2ꢀꢀ
ꢀ ꢀ
StandbyꢀCurrent:ꢀCMOSꢀ
ꢀ
RAS,ꢀLCAS,ꢀUCASꢀ≥ꢀVddꢀ–ꢀ0.2Vꢀꢀ
ꢀ
ꢀ
ꢀ
5Vꢀ
3.3Vꢀ
—ꢀ
—ꢀ
1ꢀ
1ꢀ
mAꢀ
mA
ꢀ idd3ꢀꢀ
ꢀ ꢀ
ꢀ ꢀ
OperatingꢀCurrent:ꢀꢀ
RAS,ꢀLCAS,ꢀUCAS,ꢀ
AddressꢀCycling,ꢀꢀtrcꢀ=ꢀtrcꢀ(min.)ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
5Vꢀ
3.3Vꢀ
—ꢀ
—ꢀ
90ꢀ
90ꢀ
mA
mA
mA
mA
RandomꢀRead/Write(2,3,4)ꢀ
AverageꢀPowerꢀSupplyꢀCurrent
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ idd4ꢀꢀ
ꢀ ꢀ
ꢀ ꢀ
OperatingꢀCurrent:ꢀꢀ
RASꢀ=ꢀVil,ꢀLCAS,ꢀUCAS,ꢀ
Cyclingꢀꢀtpcꢀ=ꢀtpcꢀ(min.)ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
5Vꢀ
3.3Vꢀ
—ꢀ
—ꢀ
30ꢀ
30ꢀ
EDOꢀPageꢀMode(2,3,4)
ꢀ
AverageꢀPowerꢀSupplyꢀCurrent
ꢀ idd5ꢀꢀ
ꢀ ꢀ
ꢀ ꢀ
RefreshꢀCurrent:ꢀ
RASꢀCycling,ꢀLCAS,ꢀUCASꢀ≥ꢀVihꢀ
trcꢀ=ꢀtrcꢀ(min.)ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
5Vꢀ
3.3Vꢀ
—ꢀ
—ꢀ
60ꢀ
60ꢀ
RAS-Only(2,3)
ꢀ
AverageꢀPowerꢀSupplyꢀCurrent
AverageꢀPowerꢀSupplyꢀCurrent
Notes:
1.ꢀ Anꢀinitialꢀpauseꢀofꢀ200ꢀµsꢀisꢀrequiredꢀafterꢀpower-upꢀfollowedꢀbyꢀeightꢀRASꢀrefreshꢀcyclesꢀ(RAS-OnlyꢀorꢀCBR)ꢀbeforeꢀproperꢀdeviceꢀ
operationꢀisꢀassured.ꢀTheꢀeightꢀRASꢀcyclesꢀwake-upꢀshouldꢀbeꢀrepeatedꢀanyꢀtimeꢀtheꢀtrefꢀrefreshꢀrequirementꢀisꢀexceeded.
2.ꢀ Dependentꢀonꢀcycleꢀrates.
3.ꢀ Specifiedꢀvaluesꢀareꢀobtainedꢀwithꢀminimumꢀcycleꢀtimeꢀandꢀtheꢀoutputꢀopen.
4.ꢀ Column-addressꢀisꢀchangedꢀonceꢀeachꢀEDOꢀpageꢀcycle.
5.ꢀ Enablesꢀon-chipꢀrefreshꢀandꢀaddressꢀcounters.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
7
Rev. C
02/16/2012
IS41C16100C
IS41LV16100C
AC CHARACTERISTICS(1,2,3,4,5,6)
(RecommendedꢀOperatingꢀConditionsꢀunlessꢀotherwiseꢀnoted.)
-50
-60
Symbol
trcꢀ
Parameter
Min. Max.
Min. Max.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
RandomꢀREADꢀorꢀWRITEꢀCycleꢀTimeꢀ
85ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
50ꢀ
14ꢀ
25ꢀ
110ꢀ ꢀ —ꢀ
tracꢀ
tcacꢀ
AccessꢀTimeꢀfromꢀRAS(6,ꢀ7)
AccessꢀTimeꢀfromꢀCAS(6,ꢀ8,ꢀ15)
AccessꢀTimeꢀfromꢀColumn-Address(6)ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
ꢀ
60ꢀ
15ꢀ
30ꢀ
ꢀ
taaꢀ
trasꢀ
trpꢀ
RASꢀPulseꢀWidthꢀ
50ꢀ ꢀ 10Kꢀ
30ꢀ —ꢀ
8ꢀ ꢀ 10Kꢀ
60ꢀ ꢀ 10Kꢀ
40ꢀ —ꢀ
10ꢀ ꢀ 10Kꢀ
RASꢀPrechargeꢀTimeꢀ
ꢀ
ꢀ
tcasꢀ
tcpꢀ
CASꢀPulseꢀWidth(26)
CASꢀPrechargeꢀTime(9,ꢀ25)
CASꢀHoldꢀTimeꢀ(21)
RASꢀtoꢀCASꢀDelayꢀTime(10,ꢀ20)
Row-AddressꢀSetupꢀTimeꢀ
Row-AddressꢀHoldꢀTimeꢀ
ꢀ
ꢀ
9ꢀ
50ꢀ
12ꢀ
0ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
37ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
10ꢀ
60ꢀ
20ꢀ
0ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
45ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
tcshꢀ
trcdꢀ
tasrꢀ
trahꢀ
tascꢀ
tcahꢀ
ꢀ
ꢀ
8ꢀ
10ꢀ
0ꢀ
Column-AddressꢀSetupꢀTime(20)
Column-AddressꢀHoldꢀTime(20)
ꢀ
0ꢀ
ꢀ
8ꢀ
10ꢀ
ꢀ
ꢀ
tarꢀ
ꢀ
Column-AddressꢀHoldꢀTimeꢀ
(referencedꢀtoꢀRAS)ꢀ
30ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
ꢀ
40ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
tradꢀ
tralꢀ
trpcꢀ
trshꢀ
trhcpꢀ
tclzꢀ
tcrpꢀ
todꢀ
RASꢀtoꢀColumn-AddressꢀDelayꢀTime(11)
Column-AddressꢀtoꢀRASꢀLeadꢀTimeꢀ
RASꢀtoꢀCASꢀPrechargeꢀTimeꢀ
ꢀ
14ꢀ
25ꢀ
5ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
25ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
12ꢀ
14ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
15ꢀ
30ꢀ
5ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
30ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
12ꢀ
15ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RASꢀHoldꢀTime(27)
RASꢀHoldꢀTimeꢀfromꢀCASꢀPrechargeꢀ
CASꢀtoꢀOutputꢀinꢀLow-Z(15,ꢀ29)
CASꢀtoꢀRASꢀPrechargeꢀTime(21)
OutputꢀDisableꢀTime(19,ꢀ28,ꢀ29)
ꢀ
14ꢀ
37ꢀ
0ꢀ
15ꢀ
37ꢀ
0ꢀ
ꢀ
ꢀ
5ꢀ
5ꢀ
ꢀ
3ꢀ
3ꢀ
toe/toeaꢀ OutputꢀEnableꢀTime(15,ꢀ16)
ꢀ
—ꢀ
15ꢀ
10ꢀ
5ꢀ
—ꢀ
15ꢀ
10ꢀ
5ꢀ
toehcꢀ
toepꢀ
toesꢀ
trcsꢀ
OEꢀHIGHꢀHoldꢀTimeꢀfromꢀCASꢀHIGHꢀ
OEꢀHIGHꢀPulseꢀWidthꢀ
OEꢀLOWꢀtoꢀCASꢀHIGHꢀSetupꢀTimeꢀ
ReadꢀCommandꢀSetupꢀTime(17,ꢀ20)
ꢀ
0ꢀ
0ꢀ
ꢀ
ꢀ
trrhꢀ
ꢀ
ReadꢀCommandꢀHoldꢀTimeꢀ
0ꢀ
ꢀ
0ꢀ
(referencedꢀtoꢀRAS)(12)
ꢀ
ꢀ
ꢀ
trchꢀ
ꢀ
ReadꢀCommandꢀHoldꢀTimeꢀ
(referencedꢀtoꢀCAS)(12,ꢀ17,ꢀ21)
WriteꢀCommandꢀHoldꢀTime(17,ꢀ27)
0ꢀ
ꢀ
ꢀ
—ꢀ
0ꢀ
ꢀ
—ꢀ
ns
ꢀ
ꢀ
twchꢀ
ꢀ
8ꢀ
—ꢀ
—ꢀ
10ꢀ
50ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
ns
ns
ꢀ
ꢀ
twcrꢀ
ꢀ
WriteꢀCommandꢀHoldꢀTimeꢀ
40ꢀ
ꢀ
ꢀ
ꢀ
(referencedꢀtoꢀRAS)(17)
ꢀ
8ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
02/16/2012
IS41C16100C
IS41LV16100C
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)
(RecommendedꢀOperatingꢀConditionsꢀunlessꢀotherwiseꢀnoted.)
-50
-60
Symbol Parameter
Min. Max.
Min. Max.
Units
ns
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
twpꢀ
WriteꢀCommandꢀPulseꢀWidth(17)
ꢀ
8ꢀ
10ꢀ
13ꢀ
8ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
10ꢀ
10ꢀ
15ꢀ
15ꢀ
0ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
twpzꢀ
trwlꢀ
tcwlꢀ
twcsꢀ
tdhrꢀ
WEꢀPulseꢀWidthsꢀtoꢀDisableꢀOutputsꢀ
WriteꢀCommandꢀtoꢀRASꢀLeadꢀTime(17)
WriteꢀCommandꢀtoꢀCASꢀLeadꢀTime(17,ꢀ21)
WriteꢀCommandꢀSetupꢀTime(14,ꢀ17,ꢀ20)
Data-inꢀHoldꢀTimeꢀ(referencedꢀtoꢀRAS)ꢀ
ns
ꢀ
ns
ꢀ
ns
ꢀ
0ꢀ
ns
39ꢀ
15ꢀ
40ꢀ
15ꢀ
ns
ꢀ
ꢀ
tachꢀ
Column-AddressꢀSetupꢀTimeꢀtoꢀCASꢀprechargeꢀ
nsꢀ ꢀ
ꢀ
duringꢀWRITEꢀcycle
ꢀ
ꢀ
toehꢀ
ꢀ
OEꢀHoldꢀTimeꢀfromꢀWEꢀduringꢀ
14ꢀ
ꢀ
—ꢀ
15ꢀ
ꢀ
—ꢀ
ns
READ-MODIFY-WRITEꢀcycle(18)
ꢀ
ꢀ
ꢀ
tdsꢀ
Data-InꢀSetupꢀTime(15,ꢀ22)
Data-InꢀHoldꢀTime(15,ꢀ22)
ꢀ
0ꢀ
8ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
0ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
ns
ns
ns
ns
tdhꢀ
ꢀ
15ꢀ
trwcꢀ
READ-MODIFY-WRITEꢀCycleꢀTimeꢀ
110ꢀ ꢀ —ꢀ
155ꢀ ꢀ —ꢀ
ꢀ
ꢀ
trwdꢀ
ꢀ
RASꢀtoꢀWEꢀDelayꢀTimeꢀduringꢀ
65ꢀ
ꢀ
—ꢀ
85ꢀ
ꢀ
—ꢀ
READ-MODIFY-WRITEꢀCycle(14)
ꢀ
tcwdꢀ
tawdꢀ
CASꢀtoꢀWEꢀDelayꢀTime(14,ꢀ20)
Column-AddressꢀtoꢀWEꢀDelayꢀTime(14)
ꢀ
ꢀ
26ꢀ
40ꢀ
30ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
40ꢀ
55ꢀ
40ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
ns
ns
ns
ꢀ
ꢀ
ꢀ
tpcꢀ
ꢀ
EDOꢀPageꢀModeꢀREADꢀorꢀWRITEꢀ
CycleꢀTime(24)
ꢀ
ꢀ
traspꢀ
tcpaꢀ
RASꢀPulseꢀWidthꢀinꢀEDOꢀPageꢀModeꢀ
50ꢀ ꢀ 100Kꢀ
60ꢀ ꢀ 100Kꢀ
ns
ns
ns
AccessꢀTimeꢀfromꢀCASꢀPrecharge(15)
ꢀ
—ꢀ
56ꢀ
ꢀ
ꢀ
30ꢀ
—ꢀ
—ꢀ
56ꢀ
ꢀ
ꢀ
35ꢀ
—ꢀ
ꢀ
ꢀ
tprwcꢀ
ꢀ
EDOꢀPageꢀModeꢀREAD-WRITEꢀ
CycleꢀTime(24)
ꢀ
ꢀ
tcohꢀ
DataꢀOutputꢀHoldꢀafterꢀCASꢀLOWꢀ
5ꢀ
3ꢀ
ꢀ
ꢀ
—ꢀ
12ꢀ
5ꢀ
3ꢀ
ꢀ
ꢀ
—ꢀ
15ꢀ
ns
ns
ꢀ
ꢀ
toffꢀ
ꢀ
OutputꢀBufferꢀTurn-OffꢀDelayꢀfromꢀ
CASꢀorꢀRAS(13,15,19,ꢀ29)
ꢀ
twhzꢀ
OutputꢀDisableꢀDelayꢀfromꢀWEꢀ
3ꢀ
ꢀ
ꢀ
10ꢀ
—ꢀ
3ꢀ
ꢀ
ꢀ
15ꢀ
—ꢀ
ns
ns
ꢀ
ꢀ
tclchꢀ
ꢀ
LastꢀCASꢀgoingꢀLOWꢀtoꢀFirstꢀCASꢀ
10ꢀ
10ꢀ
returningꢀHIGH(23)
ꢀ
ꢀ
ꢀ
tcsrꢀ
tchrꢀ
CASꢀSetupꢀTimeꢀ(CBRꢀREFRESH)(30,ꢀ20)
ꢀ
5ꢀ
8ꢀ
0ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
5ꢀ
10ꢀ
0ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
ns
ns
ns
CASꢀHoldꢀTimeꢀ(CBRꢀREFRESH)(30,ꢀ21)
ꢀ
ꢀ
ꢀ
tordꢀ
ꢀ
OEꢀSetupꢀTimeꢀpriorꢀtoꢀRASꢀduringꢀ
HIDDENꢀREFRESHꢀCycle
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
twrpꢀ
twrhꢀ
trefꢀ
trefꢀ
ttꢀ
WEꢀSetupꢀTimeꢀ(CBRꢀRefresh)ꢀ
WEꢀHoldꢀTimeꢀ(CBRꢀRefresh)ꢀ
AutoꢀRefreshꢀPeriodꢀ(1,024ꢀCycles)ꢀ
SelfꢀRefreshꢀPeriodꢀ(1,024ꢀCycles)ꢀ
5ꢀ
8ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
16ꢀ
5ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
16ꢀ
ns
ns
10ꢀ
—ꢀ
—ꢀ
ms
ms
ns
—ꢀ ꢀ 128ꢀ
1ꢀ 50ꢀ
—ꢀ ꢀ 128ꢀ
1ꢀ 50ꢀ
TransitionꢀTimeꢀ(RiseꢀorꢀFall)(2,ꢀ3)
ꢀ
ꢀ
ꢀ
Note:
Theꢀ-60ꢀtimingꢀparametersꢀareꢀshownꢀforꢀreferenceꢀonly.ꢀTheꢀ-50ꢀspeedꢀoptionꢀsupportsꢀ50nsꢀandꢀ60nsꢀtimingꢀspecifications.
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9
Rev. C
02/16/2012
17.ꢀWriteꢀcommandꢀisꢀdefinedꢀasꢀWEꢀgoingꢀlow.
18.ꢀLATEꢀWRITEꢀandꢀREAD-MODIFY-WRITEꢀcyclesꢀmustꢀhaveꢀbothꢀtodꢀandꢀtoehꢀmetꢀ(OEꢀHIGHꢀduringꢀWRITEꢀcycle)ꢀinꢀorderꢀtoꢀ
ensureꢀthatꢀtheꢀoutputꢀbuffersꢀwillꢀbeꢀopenꢀduringꢀtheꢀWRITEꢀcycle.ꢀTheꢀI/OsꢀwillꢀprovideꢀtheꢀpreviouslyꢀwrittenꢀdataꢀifꢀCASꢀremainsꢀ
LOWꢀandꢀOEꢀisꢀtakenꢀbackꢀtoꢀLOWꢀafterꢀtoehꢀisꢀmet.
19.ꢀTheꢀI/OsꢀareꢀinꢀopenꢀduringꢀREADꢀcyclesꢀonceꢀtodꢀorꢀtoffꢀoccur.
20.ꢀTheꢀfirstꢀχCASꢀedgeꢀtoꢀtransitionꢀLOW.
21.ꢀTheꢀlastꢀχCASꢀedgeꢀtoꢀtransitionꢀHIGH.
22.ꢀTheseꢀparametersꢀareꢀreferencedꢀtoꢀCASꢀleadingꢀedgeꢀinꢀEARLYꢀWRITEꢀcyclesꢀandꢀWEꢀleadingꢀedgeꢀinꢀLATEꢀWRITEꢀorꢀREAD-
MODIFY-WRITEꢀcycles.
23.ꢀLastꢀfallingꢀχCASꢀedgeꢀtoꢀfirstꢀrisingꢀχCASꢀedge.
24.ꢀLastꢀrisingꢀχCASꢀedgeꢀtoꢀnextꢀcycle’sꢀlastꢀrisingꢀχCASꢀedge.
25.ꢀLastꢀrisingꢀχCASꢀedgeꢀtoꢀfirstꢀfallingꢀχCASꢀedge.
26.ꢀEachꢀχCASꢀmustꢀmeetꢀminimumꢀpulseꢀwidth.
27.ꢀLastꢀχCASꢀtoꢀgoꢀLOW.
28.ꢀI/Osꢀcontrolled,ꢀregardlessꢀUCASꢀandꢀLCAS.
29.ꢀTheꢀ3ꢀnsꢀminimumꢀisꢀaꢀparameterꢀguaranteedꢀbyꢀdesign.ꢀ
30.ꢀEnablesꢀon-chipꢀrefreshꢀandꢀaddressꢀcounters.
IS41C16100C
IS41LV16100C
AC TEST CONDITIONS
Output load: Two TTL Loads and 100 pF (Vdd = 5.0V ±10%)
One TTL Load and 50 pF (Vdd = 3.3V ±10%)
Input timing reference levels: Vih = 2.4V, Vil = 0.8V (Vdd = 5.0V ±10%);
Vih = 2.0V, Vil = 0.8V (Vdd = 3.3V ±10%)
Output timing reference levels: Voh = 2.4V, Vol = 0.4V (Vdd = 5V ±10%, 3.3V ±10%)
Notes:
ꢀ 1.ꢀAnꢀinitialꢀpauseꢀofꢀ200ꢀµsꢀisꢀrequiredꢀafterꢀpower-upꢀfollowedꢀbyꢀeightꢀRASꢀrefreshꢀcycleꢀ(RAS-OnlyꢀorꢀCBR)ꢀbeforeꢀproperꢀdeviceꢀ
operationꢀisꢀassured.ꢀTheꢀeightꢀRASꢀcyclesꢀwake-upꢀshouldꢀbeꢀrepeatedꢀanyꢀtimeꢀtheꢀtrefꢀrefreshꢀrequirementꢀisꢀexceeded.
ꢀ 2.ꢀVihꢀ(MIN)ꢀandꢀVilꢀ(MAX)ꢀareꢀreferenceꢀlevelsꢀforꢀmeasuringꢀtimingꢀofꢀinputꢀsignals.ꢀTransitionꢀtimes,ꢀareꢀmeasuredꢀbetweenꢀVihꢀ
andꢀVilꢀ(orꢀbetweenꢀVilꢀandꢀVih)ꢀandꢀassumeꢀtoꢀbeꢀ1ꢀnsꢀforꢀallꢀinputs.
ꢀ 3.ꢀInꢀadditionꢀtoꢀmeetingꢀtheꢀtransitionꢀrateꢀspecification,ꢀallꢀinputꢀsignalsꢀmustꢀtransitꢀbetweenꢀVihꢀandꢀVilꢀ(orꢀbetweenꢀVilꢀandꢀVih)ꢀ
inꢀaꢀmonotonicꢀmanner.
ꢀ 4.ꢀIfꢀCASꢀandꢀRASꢀ=ꢀVih,ꢀdataꢀoutputꢀisꢀHigh-Z.
ꢀ 5.ꢀIfꢀCASꢀ=ꢀVil,ꢀdataꢀoutputꢀmayꢀcontainꢀdataꢀfromꢀtheꢀlastꢀvalidꢀREADꢀcycle.
ꢀ 6.ꢀMeasuredꢀwithꢀaꢀloadꢀequivalentꢀtoꢀoneꢀTTLꢀgateꢀandꢀ50ꢀpF.
ꢀ 7.ꢀAssumesꢀthatꢀtrcdꢀ≤ ꢀtrcdꢀ(MAX).ꢀIfꢀtrcdꢀisꢀgreaterꢀthanꢀtheꢀmaximumꢀrecommendedꢀvalueꢀshownꢀinꢀthisꢀtable,ꢀtracꢀwillꢀincreaseꢀ
byꢀtheꢀamountꢀthatꢀtrcdꢀexceedsꢀtheꢀvalueꢀshown.
ꢀ 8.ꢀAssumesꢀthatꢀtrcdꢀ≤ꢀꢀtrcdꢀ(MAX).
ꢀ 9.ꢀIfꢀCASꢀisꢀLOWꢀatꢀtheꢀfallingꢀedgeꢀofꢀRAS,ꢀdataꢀoutꢀwillꢀbeꢀmaintainedꢀfromꢀtheꢀpreviousꢀcycle.ꢀToꢀinitiateꢀaꢀnewꢀcycleꢀandꢀclearꢀtheꢀ
dataꢀoutputꢀbuffer,ꢀCASꢀandꢀRASꢀmustꢀbeꢀpulsedꢀforꢀtcp.
10.ꢀOperationꢀwithꢀtheꢀtrcdꢀ(MAX)ꢀlimitꢀensuresꢀthatꢀtracꢀ(MAX)ꢀcanꢀbeꢀmet.ꢀtrcdꢀ(MAX)ꢀisꢀspecifiedꢀasꢀaꢀreferenceꢀpointꢀonly;ꢀifꢀtrcdꢀ
isꢀgreaterꢀthanꢀtheꢀspecifiedꢀtrcdꢀ(MAX)ꢀlimit,ꢀaccessꢀtimeꢀisꢀcontrolledꢀexclusivelyꢀbyꢀtcac.
11.ꢀOperationꢀwithinꢀtheꢀtradꢀ(MAX)ꢀlimitꢀensuresꢀthatꢀtrcdꢀ(MAX)ꢀcanꢀbeꢀmet.ꢀtradꢀ(MAX)ꢀisꢀspecifiedꢀasꢀaꢀreferenceꢀpointꢀonly;ꢀifꢀtradꢀ
isꢀgreaterꢀthanꢀtheꢀspecifiedꢀtradꢀ(MAX)ꢀlimit,ꢀaccessꢀtimeꢀisꢀcontrolledꢀexclusivelyꢀbyꢀtaa.
12.ꢀEitherꢀtrchꢀorꢀtrrhꢀmustꢀbeꢀsatisfiedꢀforꢀaꢀREADꢀcycle.
13.ꢀtoffꢀ(MAX)ꢀdefinesꢀtheꢀtimeꢀatꢀwhichꢀtheꢀoutputꢀachievesꢀtheꢀopenꢀcircuitꢀcondition;ꢀitꢀisꢀꢀnotꢀaꢀreferenceꢀtoꢀVohꢀorꢀVol.
14.ꢀtwcs,ꢀtrwd,ꢀtawdꢀandꢀtcwdꢀareꢀrestrictiveꢀoperatingꢀparametersꢀinꢀLATEꢀWRITEꢀandꢀREAD-MODIFY-WRITEꢀcycleꢀonly.ꢀIfꢀtwcsꢀ≤ꢀ
twcsꢀ(MIN),ꢀtheꢀcycleꢀisꢀanꢀEARLYꢀWRITEꢀcycleꢀandꢀtheꢀdataꢀoutputꢀwillꢀremainꢀopenꢀcircuitꢀthroughoutꢀtheꢀentireꢀcycle.ꢀIfꢀtrwdꢀ≤ꢀ
trwdꢀ(MIN),ꢀtawdꢀ≤ ꢀtawdꢀ(MIN)ꢀandꢀtcwdꢀ≤ ꢀtcwdꢀ(MIN),ꢀtheꢀcycleꢀisꢀaꢀREAD-WRITEꢀcycleꢀandꢀtheꢀdataꢀoutputꢀwillꢀcontainꢀdataꢀreadꢀ
fromꢀtheꢀselectedꢀcell.ꢀIfꢀneitherꢀofꢀtheꢀaboveꢀconditionsꢀisꢀmet,ꢀtheꢀstateꢀofꢀI/Oꢀ(atꢀaccessꢀtimeꢀandꢀuntilꢀCASꢀandꢀRASꢀorꢀOEꢀgoꢀ
backꢀtoꢀVih)ꢀisꢀindeterminate.ꢀOEꢀheldꢀHIGHꢀandꢀWEꢀtakenꢀLOWꢀafterꢀCASꢀgoesꢀLOWꢀresultꢀinꢀaꢀLATEꢀWRITEꢀ(OE-controlled)ꢀ
cycle.
15.ꢀOutputꢀparameterꢀ(I/O)ꢀisꢀreferencedꢀtoꢀcorrespondingꢀCASꢀinput,ꢀI/O0-I/O7ꢀbyꢀLCASꢀandꢀI/O8-I/O15ꢀbyꢀUCAS.
16.ꢀDuringꢀaꢀREADꢀcycle,ꢀifꢀOEꢀisꢀLOWꢀthenꢀtakenꢀHIGHꢀbeforeꢀCASꢀgoesꢀHIGH,ꢀI/Oꢀgoesꢀopen.ꢀIfꢀOEꢀisꢀtiedꢀpermanentlyꢀLOW,ꢀaꢀ
LATEꢀWRITEꢀorꢀREAD-MODIFY-WRITEꢀisꢀnotꢀpossible.
10ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
02/16/2012
IS41C16100C
IS41LV16100C
READ CYCLE
tRC
t
RAS
t
RP
RAS
tCSH
t
RSH
t
RRH
tCRP
t
CAS CLCH
t
tRCD
UCAS/LCAS
t
AR
tRAD
tRAL
tASR
tRAH
tCAH
t
ASC
ADDRESS
Row
Column
Row
tRCS
t
RCH
WE
tAA
tRAC
(1)
OFF
tCAC
t
tCLC
Open
Open
Valid Data
I/O
tOE
tOD
OE
tOES
Undefined
Don’tꢀCare
Note:ꢀ
1.ꢀ toffꢀisꢀreferencedꢀfromꢀrisingꢀedgeꢀofꢀRASꢀorꢀCAS,ꢀwhicheverꢀoccursꢀlast.
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11
Rev. C
02/16/2012
IS41C16100C
IS41LV16100C
EARLY WRITE CYCLE (OEꢀ=ꢀDON'TꢀCARE)
t
RC
t
RAS
tRP
RAS
t
CSH
t
RSH
t
CRP
ASR
t
CAS CLCH
t
t
RCD
UCAS/LCAS
t
AR
t
RAD
t
t
t
RAL
CAH
ACH
t
t
RAH
t
ASC
ADDRESS
Row
Column
Row
t
t
CWL
RWL
t
WCR
tWCS
tWCH
t
WP
WE
t
DHR
t
DH
t
DS
I/O
Valid Data
Don’tꢀCare
12ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
02/16/2012
IS41C16100C
IS41LV16100C
READ WRITE CYCLE (LATEꢀWRITEꢀandꢀREAD-MODIFY-WRITEꢀCycles)ꢀ
t
t
RWC
RAS
t
RP
RAS
t
CSH
t
RSH
t
CRP
ASR
t
CAS CLCH
t
t
RCD
UCAS/LCAS
tAR
t
RAD
tRAL
t
t
RAH
tCAH
tASC
tACH
ADDRESS
Row
Column
Row
t
RWD
tCWL
tRCS
tCWD
tRWL
tAWD
tWP
WE
tAA
t
RAC
tCAC
tCLZ
tDS
tDH
Open
Open
Valid DOUT
Valid DIN
I/O
tOD
tOEH
t
OE
OE
Undefined
Don’tꢀCare
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13
Rev. C
02/16/2012
IS41C16100C
IS41LV16100C
EDO-PAGE-MODE READ CYCLE
t
RASP
t
RP
RAS
(1)
PC
t
CSH
t
t
RSH
t
CRP
t
CAS,
t
CP
t
CAS,
t
CP
t
CAS,
tCP
t
RCD
t
CLCH
t
CLCH
tCLCH
UCAS/LCAS
t
AR
t
RAD
tRAL
t
ASR
t
ASC
t
CAH
t
ASC
t
CAH
t
ASC
t
CAH
ADDRESS
Row
Column
Column
Column
Row
t
RAH
tRRH
t
RCS
t
RCH
WE
t
AA
t
AA
t
AA
t
RAC
CAC
CLZ
tCPA
t
CPA
t
t
t
CAC
t
t
CAC
CLZ
t
COH
t
OFF
Open
Open
Valid Data
ValidData
ValidData
I/O
t
OE
t
OEHC
tOE
tOD
t
OES
t
OD
t
OES
OE
t
OEP
Undefined
Don’tꢀCare
Note:ꢀ
1.ꢀ tpcꢀcanꢀbeꢀmeasuredꢀfromꢀfallingꢀedgeꢀofꢀCASꢀtoꢀfallingꢀedgeꢀofꢀCAS,ꢀorꢀfromꢀrisingꢀedgeꢀofꢀCASꢀtoꢀrisingꢀedgeꢀofꢀCAS.ꢀBothꢀ
measurementsꢀmustꢀmeetꢀtheꢀtpcꢀspecifications.
14ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
02/16/2012
IS41C16100C
IS41LV16100C
EDO-PAGE-MODE EARLY-WRITE CYCLE
t
RASP
tRP
tRHCP
RAS
t
CSH
t
PC
t
RSH
tCRP
t
CAS,
t
CP
t
CAS,
t
CP
t
CAS,
tCP
tRCD
t
CLCH
t
CLCH
tCLCH
UCAS/LCAS
t
AR
tACH
t
ACH
tACH
t
RAD
t
RAL
t
ASR
tASC
t
CAH
t
ASC
tCAH
tASC
t
CAH
ADDRESS
Row
Column
Column
Column
Row
tRAH
t
CWL
WCS
WCH
t
CWL
tCWL
t
t
WCS
tWCS
t
tWCH
tWCH
t
WP
t
WP
tWP
WE
tWCR
tRWL
tDHR
tDS
tDS
tDS
t
DH
t
DH
tDH
I/O
Valid Data
Valid Data
Valid Data
OE
Don’tꢀCare
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15
Rev. C
02/16/2012
IS41C16100C
IS41LV16100C
EDO-PAGE-MODE READ-WRITE CYCLEꢀ(LATEꢀWRITEꢀandꢀREAD-MODIFYꢀWRITEꢀCycles)
t
RASP
t
RP
RAS
(1)
tPC / tPRWC
t
CSH
tRSH
tCRP
t
RCD
t
CAS,
t
CLCH
t
CP
t
CAS,
t
CLCH
t
CP
t
CAS,
t
CLCH
tCP
UCAS/LCAS
t
AR
t
ASR
t
t
RAD
t
RAL
t
ASC
t
CAH
t
ASC
t
CAH
tASC
tCAH
RAH
ADDRESS
Row
Column
Column
Column
Row
t
RWD
t
t
RWL
CWL
t
RCS
t
CWL
WP
t
CWL
t
t
WP
t
WP
tAWD
tAWD
tAWD
t
CWD
t
CWD
tCWD
WE
t
AA
t
AA
CPA
t
AA
tCPA
t
t
RAC
t
DH
DS
t
DH
DS
t
DH
DS
t
t
t
t
CAC
CLZ
t
t
CAC
CLZ
t
t
CAC
CLZ
t
Open
Open
I/O
D
OUT
D
t
IN
DOUT
D
IN
DOUT
D
IN
OD
t
OD
t
OD
tOE
t
OE
tOE
tOEH
OE
Undefined
Don’tꢀCare
Note:ꢀ
1.ꢀ tpcꢀcanꢀbeꢀmeasuredꢀfromꢀfallingꢀedgeꢀofꢀCASꢀtoꢀfallingꢀedgeꢀofꢀCAS,ꢀorꢀfromꢀrisingꢀedgeꢀofꢀCASꢀtoꢀrisingꢀedgeꢀofꢀCAS.ꢀBothꢀ
measurementsꢀmustꢀmeetꢀtheꢀtpcꢀspecifications.
16ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
02/16/2012
IS41C16100C
IS41LV16100C
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (PseudoꢀREAD-MODIFYꢀWRITE)
t
RASP
t
RP
RAS
t
CSH
tPC
tPC
tRSH
tCRP
t
RCD
t
CAS
t
CP
t
CAS
tCP
t
CAS
tCP
UCAS/LCAS
t
AR
t
ACH
RAL
CAH
tASR
t
RAD
t
t
ASC
t
CAH
t
ASC
t
CAH
tASC
t
tRAH
ADDRESS
Row
Column (A)
Column (B)
Column (N)
Row
t
RCS
t
RCH
t
WCS
tWCH
WE
t
WHZ
t
AA
t
AA
t
CPA
CAC
COH
t
RAC
tCAC
t
t
tDS
tDH
Open
Open
I/O
Valid Data (A)
Valid Data (B)
DIN
tOE
OE
Don’tꢀCare
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
17
Rev. C
02/16/2012
IS41C16100C
IS41LV16100C
AC WAVEFORMS
READ CYCLE (WithꢀWE-ControlledꢀDisable)
RAS
t
CSH
t
CRP
ASR
t
RCD
tCP
tCAS
UCAS/LCAS
t
AR
t
RAD
t
t
RAH
t
CAH
tASC
tASC
ADDRESS
Row
Column
Column
t
RCS
t
RCS
tRCH
t
WPZ
WE
tAA
t
RAC
t
t
CAC
CLZ
tWHZ
tCLZ
Open
Open
Valid Data
I/O
t
OE
tOD
OE
Undefined
Don’tꢀCare
RAS-ONLY REFRESH CYCLE (OE,ꢀWEꢀ=ꢀDON'TꢀCARE)
tRC
t
RAS
tRP
RAS
tCRP
t
RPC
UCAS/LCAS
tASR
tRAH
ADDRESS
I/O
Row
Row
Open
Don’tꢀCare
18ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
02/16/2012
IS41C16100C
IS41LV16100C
CBR REFRESH CYCLE (Addresses;ꢀOEꢀ=ꢀDON'TꢀCARE)
tRP
tRAS
t
RP
tRAS
RAS
tCHR
tCHR
t
RPC
tRPC
t
CP
tCSR
tCSR
UCAS/LCAS
Open
I/O
WE
tWRH
t
WRP
t
WRH
t
WRP
HIDDEN REFRESH CYCLE(1) (WEꢀ=ꢀHIGH;ꢀOEꢀ=ꢀLOW)
t
RAS
tRAS
t
RP
RAS
t
CRP
tRCD
tRSH
tCHR
UCAS/LCAS
t
AR
tRAD
t
RAL
t
ASR
t
RAH
tCAH
tASC
ADDRESS
Row
Column
t
AA
tRAC
(2)
OFF
t
tCAC
tCLZ
Open
Open
Valid Data
I/O
tOE
tOD
tORD
OE
Undefined
Don’tꢀCare
Notes:ꢀ
1.ꢀ AꢀHiddenꢀRefreshꢀmayꢀalsoꢀbeꢀperformedꢀafterꢀaꢀWriteꢀCycle.ꢀInꢀthisꢀcase,ꢀWEꢀ=ꢀLOWꢀandꢀOEꢀ=ꢀHIGH.
2.ꢀ toffꢀisꢀreferencedꢀfromꢀrisingꢀedgeꢀofꢀRASꢀorꢀCAS,ꢀwhicheverꢀoccursꢀlast.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
19
Rev. C
02/16/2012
IS41C16100C
IS41LV16100C
ORDERING INFORMATION : 5V
Industrial Range: -40°C to +85°C
Speed (ns)
Order Part No.
Package
ꢀ
ꢀ
ꢀ
ꢀ
50ꢀ
IS41C16100C-50KIꢀ
IS41C16100C-50KLIꢀ
IS41C16100C-50TIꢀ
IS41C16100C-50TLIꢀ
400-milꢀSOJꢀꢀ
400-milꢀSOJ,ꢀLead-freeꢀ
400-milꢀTSOPꢀ(TypeꢀII)ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
400-milꢀTSOPꢀ(TypeꢀII),ꢀLead-free
ORDERING INFORMATION : 3.3V
Industrial Range: -40°C to +85°C
Speed (ns)
Order Part No.
Package
ꢀ
ꢀ
ꢀ
ꢀ
50ꢀ
IS41LV16100C-50KIꢀ
IS41LV16100C-50KLIꢀ
IS41LV16100C-50TIꢀ
IS41LV16100C-50TLIꢀ
400-milꢀSOJꢀꢀ
400-milꢀSOJ,ꢀLead-freeꢀ
400-milꢀTSOPꢀ(TypeꢀII)ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
400-milꢀTSOPꢀ(TypeꢀII),ꢀLead-free
Note:ꢀ
Theꢀ-50ꢀspeedꢀoptionꢀsupportsꢀ50nsꢀandꢀ60nsꢀtimingꢀspecifications.
20ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
02/16/2012
IS41C16100C
IS41LV16100C
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
21
Rev. C
02/16/2012
IS41C16100C
IS41LV16100C
22ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
02/16/2012
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