IS41C16105C [ISSI]
16Mb DRAM WITH FAST PAGE MODE; 与快速页模式DRAM 16MB
| 型号： | IS41C16105C |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 16Mb DRAM WITH FAST PAGE MODE |
| 文件： | 总20页 (文件大小：712K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS41C16105C
IS41LV16105C
1Mx16ꢀ
ꢀ
16MbꢀDRAMꢀWITHꢀFASTꢀPAGEꢀMODE
FEBRUARYꢀ2012
FEATURES
DESCRIPTION
•ꢀ TTLꢀcompatibleꢀinputsꢀandꢀoutputs;ꢀtristateꢀI/O
TheꢀISSIꢀꢀIS41C16105CꢀandꢀIS41LV16105Cꢀareꢀ1,048,576ꢀxꢀ
16-bitꢀhigh-performanceꢀCMOSꢀꢀDynamicꢀRandomꢀAccessꢀ
Memories.ꢀꢀFastꢀPageꢀModeꢀallowsꢀ1,024ꢀrandomꢀaccessesꢀ
withinꢀaꢀsingleꢀrowꢀwithꢀaccessꢀcycleꢀtimeꢀasꢀshortꢀasꢀ20ꢀnsꢀ
perꢀ16-bitꢀword.ꢀItꢀisꢀasynchronous,ꢀasꢀitꢀdoesꢀnotꢀrequireꢀaꢀ
clockꢀsignalꢀinputꢀtoꢀsynchronizeꢀcommandsꢀandꢀI/O.
•ꢀ RefreshꢀInterval:ꢀ
—ꢀ1,024ꢀcycles/16ꢀms
•ꢀ RefreshꢀMode:ꢀ
ꢀ—ꢀRAS-Only,ꢀCAS-before-RASꢀ(CBR),ꢀandꢀHidden
TheseꢀfeaturesꢀmakeꢀtheꢀIS41C16105CꢀandꢀIS41LV16105Cꢀ
ideallyꢀsuitedꢀforꢀhigh-bandwidthꢀgraphics,ꢀdigitalꢀsignalꢀ
processing,ꢀhigh-performanceꢀcomputingꢀsystems,ꢀandꢀ
peripheralꢀapplicationsꢀthatꢀrunꢀwithoutꢀaꢀclockꢀtoꢀsynchronizeꢀ
withꢀtheꢀDRAM.
•ꢀ JEDECꢀstandardꢀpinout
•ꢀ Singleꢀpowerꢀsupply:ꢀ
—ꢀ5Vꢀ±ꢀꢀ10%ꢀ(IS41C16105C)ꢀ
—ꢀ3.3Vꢀ±ꢀ10%ꢀ(IS41LV16105C)
TheꢀIS41C/LV16105Cꢀisꢀpackagedꢀinꢀaꢀ42-pinꢀ400-milꢀSOJꢀ
andꢀ400-milꢀ50/44-pinꢀTSOPꢀ(TypeꢀII).
•ꢀ ByteꢀWriteꢀandꢀByteꢀReadꢀoperationꢀviaꢀꢀtwoꢀCAS
•ꢀ IndustrialꢀTemperatureꢀRangeꢀꢀꢀ-40oCꢀtoꢀ85oC
KEYꢀTIMINGꢀPARAMETERS
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Parameterꢀ
-50ꢀ
50ꢀ
13ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Unit
ns
Max.ꢀRASꢀAccessꢀTimeꢀ(trac)ꢀ
Max.ꢀCASꢀAccessꢀTimeꢀ(tcac)ꢀ
ns
Max.ꢀColumnꢀAddressꢀAccessꢀTimeꢀ(taa)ꢀ 25ꢀ
ns
Min.ꢀFastꢀPageꢀModeꢀCycleꢀTimeꢀ(tpc)ꢀ
Min.ꢀRead/WriteꢀCycleꢀTimeꢀ(trc)ꢀ
20ꢀ
84ꢀ
ns
ns
Copyright © 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex-
pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon
Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — 1-800-379-4774ꢀ
1
Rev.ꢀ A
02/24/2012
IS41C16105C
IS41LV16105Cꢀ
PIN CONFIGURATIONS
44(50)-PinꢀTSOPꢀ(TypeꢀII)ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢀꢀꢀꢀꢀꢀꢀꢀ42-PinꢀSOJ
VDD
I/O0
I/O1
I/O2
I/O3
VDD
I/O4
I/O5
I/O6
I/O7
NC
1
44
43
42
41
40
39
38
37
36
35
34
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
VDD
1
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
2
I/O0
I/O1
I/O2
I/O3
VDD
I/O4
I/O5
I/O6
I/O7
NC
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
11
I/O8
NC
10
11
12
13
14
15
16
17
18
19
20
21
NC
NC
WE
RAS
NC
NC
A0
12
13
14
15
16
17
18
19
20
21
22
33
32
31
30
29
28
27
26
25
24
23
NC
NC
LCAS
UCAS
OE
LCAS
UCAS
OE
WE
RAS
NC
A9
A9
NC
A8
A8
A0
A7
A7
A1
A6
A1
A6
A2
A5
A2
A5
A3
A4
A3
A4
VDD
GND
VDD
GND
PINꢀDESCRIPTIONS
A0-A9ꢀ
I/O0-15ꢀ
WEꢀꢀ
AddressꢀInputs
DataꢀInputs/Outputs
WriteꢀEnable
OEꢀꢀ
OutputꢀEnable
RASꢀꢀ
UCASꢀꢀ
LCASꢀꢀ
Vddꢀ
RowꢀAddressꢀStrobe
UpperꢀColumnꢀAddressꢀStrobe
LowerꢀColumnꢀAddressꢀStrobe
Power
GNDꢀ
NCꢀ
Ground
NoꢀConnection
2ꢀ
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev.ꢀ A
02/24/2012
IS41C16105C
IS41LV16105Cꢀ
FUNCTIONAL BLOCK DIAGRAM
OE
WE
WE
CONTROL
LOGICS
OE
CONTROL
LOGIC
CAS
CLOCK
GENERATOR
LCAS
UCAS
CAS
WE
DATA I/O BUS
RAS
CLOCK
RAS
GENERATOR
COLUMN DECODERS
SENSE AMPLIFIERS
REFRESH
COUNTER
I/O0-I/O15
MEMORY ARRAY
1,048,576 x 16
ADDRESS
BUFFERS
A0-A9
Integrated Silicon Solution, Inc. — 1-800-379-4774ꢀ
3
Rev.ꢀ A
02/24/2012
IS41C16105C
IS41LV16105Cꢀ
TRUTHꢀTABLE(5)
Functionꢀ
Standbyꢀ
ꢀ
ꢀ
ꢀ
RASꢀ LCASꢀ UCASꢀ WEꢀ
OEꢀ
Xꢀ
AddressꢀtR/tCꢀ
Xꢀ
I/Oꢀ
Hꢀ
Lꢀ
Xꢀ
Lꢀ
Xꢀ
Lꢀ
Xꢀ
Hꢀ
High-Z
Dout
Read:ꢀWordꢀ
Lꢀ
ROW/COLꢀ
Read:ꢀLowerꢀByteꢀ
ꢀ
ꢀ
ꢀ
Lꢀ
ꢀ
Lꢀ
ꢀ
Hꢀ
ꢀ
Hꢀ
ꢀ
Lꢀ
ꢀ
ROW/COLꢀ
ꢀ
LowerꢀByte,ꢀDout
UpperꢀByte,ꢀHigh-Z
Read:ꢀUpperꢀByteꢀ
ꢀ
ꢀ
ꢀ
Lꢀ
ꢀ
Hꢀ
ꢀ
Lꢀ
ꢀ
Hꢀ
ꢀ
Lꢀ
ꢀ
ROW/COLꢀ
ꢀ
LowerꢀByte,ꢀHigh-Zꢀꢀ
UpperꢀByte,ꢀDout
Write:ꢀWordꢀ(EarlyꢀWrite)ꢀ
ꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
ROW/COLꢀ
Din
Write:ꢀLowerꢀByteꢀ(EarlyꢀWrite)ꢀ
Lꢀ
ꢀ
Lꢀ
ꢀ
Hꢀ
ꢀ
Lꢀ
ꢀ
Xꢀ
ꢀ
ROW/COLꢀ
ꢀ
LowerꢀByte,ꢀDinꢀ
UpperꢀByte,ꢀHigh-Z
ꢀ
ꢀ
Write:ꢀUpperꢀByteꢀ(EarlyꢀWrite)ꢀ
Lꢀ
ꢀ
Hꢀ
ꢀ
Lꢀ
ꢀ
Lꢀ
ꢀ
Xꢀ
ꢀ
ROW/COLꢀ
ꢀ
LowerꢀByte,ꢀHigh-Zꢀꢀ
UpperꢀByte,ꢀDin
ꢀ
ꢀ
Read-Write(1,2)
ꢀ
ꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
H→Lꢀ L→Hꢀ
ROW/COLꢀ
ROW/COLꢀ
ROW/COLꢀ
Dout,ꢀDin
Dout
HiddenꢀRefreshꢀ
Read(2)ꢀ ꢀ
Write(1,3)ꢀ ꢀ
L→H→Lꢀ Lꢀ
L→H→Lꢀ Lꢀ
Hꢀ
Lꢀ
Lꢀ
ꢀ
Xꢀ
Dout
RAS-OnlyꢀRefreshꢀ
ꢀ
ꢀ
Lꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Xꢀ
Xꢀ
ROW/NAꢀ
Xꢀ
High-Z
High-Z
CBRꢀRefresh(4)ꢀ
H→Lꢀ
Notes:ꢀ
1.ꢀ TheseꢀWRITEꢀcyclesꢀmayꢀalsoꢀbeꢀBYTEꢀWRITEꢀcyclesꢀ(eitherꢀLCASꢀorꢀUCASꢀactive).
2.ꢀ TheseꢀREADꢀcyclesꢀmayꢀalsoꢀbeꢀBYTEꢀREADꢀcyclesꢀ(eitherꢀLCASꢀorꢀUCASꢀactive).
3.ꢀ EARLYꢀWRITEꢀonly.
4.ꢀ AtꢀleastꢀoneꢀofꢀtheꢀtwoꢀCASꢀsignalsꢀmustꢀbeꢀactiveꢀ(LCASꢀorꢀUCAS).
5.ꢀCommandsꢀvalidꢀonlyꢀafterꢀinitialization.ꢀ
4ꢀ
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev.ꢀ A
02/24/2012
IS41C16105C
IS41LV16105Cꢀ
FunctionalꢀDescription
WriteꢀCycle
TheꢀIS41C/LV16105CꢀisꢀaꢀCMOSꢀDRAMꢀoptimizedꢀforꢀ
high-speedꢀ bandwidth,ꢀ lowꢀ powerꢀ applications.ꢀ Duringꢀ
READꢀorꢀWRITEꢀcycles,ꢀeachꢀbitꢀisꢀuniquelyꢀaddressedꢀ
throughꢀtheꢀ16ꢀaddressꢀbits.ꢀTheseꢀareꢀenteredꢀtenꢀbitsꢀ
(A0-A9)ꢀatꢀaꢀtime.ꢀꢀTheꢀrowꢀaddressꢀisꢀlatchedꢀbyꢀtheꢀRowꢀ
AddressꢀStrobeꢀ(RAS).ꢀTheꢀcolumnꢀaddressꢀisꢀlatchedꢀbyꢀ
theꢀColumnꢀAddressꢀStrobeꢀ(CAS).ꢀꢀRASꢀisꢀusedꢀtoꢀlatchꢀ
theꢀfirstꢀnineꢀbitsꢀandꢀCASꢀisꢀusedꢀtheꢀlatterꢀnineꢀbits.
AꢀwriteꢀcycleꢀisꢀinitiatedꢀbyꢀtheꢀfallingꢀedgeꢀofꢀCASꢀandꢀ
WE,ꢀwhicheverꢀoccursꢀlast.ꢀTheꢀinputꢀdataꢀmustꢀbeꢀvalidꢀ
atꢀorꢀbeforeꢀtheꢀfallingꢀedgeꢀofꢀCASꢀorꢀWE,ꢀwhicheverꢀ
occursꢀlast.
RefreshꢀCycle
Toꢀretainꢀdata,ꢀ1,024ꢀrefreshꢀcyclesꢀareꢀrequiredꢀinꢀeachꢀ
16ꢀmsꢀperiod.ꢀThereꢀareꢀtwoꢀwaysꢀtoꢀrefreshꢀtheꢀmem-
ory.
TheꢀIS41C/LV16105CꢀhasꢀtwoꢀCASꢀcontrols,ꢀLCASꢀandꢀ
UCAS.ꢀTheꢀLCASꢀandꢀUCASꢀinputsꢀinternallyꢀgeneratesꢀ
aꢀCASꢀsignalꢀfunctioningꢀinꢀanꢀidenticalꢀmannerꢀtoꢀtheꢀ
singleꢀCASꢀinputꢀonꢀtheꢀotherꢀ1Mꢀxꢀ16ꢀDRAMs.ꢀTheꢀkeyꢀ
differenceꢀisꢀthatꢀeachꢀCASꢀcontrolsꢀitsꢀcorrespondingꢀI/Oꢀ
tristateꢀlogicꢀ(inꢀconjunctionꢀwithꢀOEꢀandꢀWEꢀandꢀRAS).ꢀ
LCASꢀcontrolsꢀI/O0ꢀthroughꢀI/O7ꢀandꢀUCASꢀcontrolsꢀI/
O8ꢀthroughꢀꢀI/O15.ꢀ
1.ꢀByꢀclockingꢀeachꢀofꢀtheꢀ1,024ꢀrowꢀaddressesꢀ(A0ꢀthroughꢀ
A9)ꢀwithꢀRASꢀatꢀleastꢀonceꢀeveryꢀtref max.ꢀAnyꢀread,ꢀ
write,ꢀread-modify-writeꢀorꢀRAS-onlyꢀcycleꢀrefreshesꢀ
theꢀaddressedꢀrow.
2.ꢀUsingꢀaꢀCAS-before-RASꢀrefreshꢀcycle.ꢀCAS-before-
RASꢀrefreshꢀisꢀactivatedꢀbyꢀtheꢀfallingꢀedgeꢀofꢀRAS,ꢀwhileꢀ
holdingꢀCASꢀLOW.ꢀInꢀCAS-before-RASꢀrefreshꢀcycle,ꢀ
anꢀinternalꢀ9-bitꢀcounterꢀprovidesꢀtheꢀrowꢀaddressesꢀ
andꢀtheꢀexternalꢀaddressꢀinputsꢀareꢀignored.
TheꢀIS41C/LV16105CꢀCASꢀfunctionꢀisꢀdeterminedꢀbyꢀtheꢀ
firstꢀCASꢀ(LCASꢀorꢀUCAS)ꢀtransitioningꢀLOWꢀandꢀtheꢀlastꢀ
transitioningꢀbackꢀHIGH.ꢀTheꢀtwoꢀCASꢀcontrolsꢀgiveꢀtheꢀ
IS41C16105CꢀandꢀIS41LV16105CꢀbothꢀBYTEꢀREADꢀandꢀ
BYTEꢀWRITEꢀꢀcycleꢀcapabilities.
CAS-before-RASꢀ isꢀ aꢀ refresh-onlyꢀ modeꢀ andꢀ noꢀ dataꢀ
accessꢀorꢀdeviceꢀselectionꢀisꢀallowed.ꢀThus,ꢀtheꢀoutputꢀ
remainsꢀinꢀtheꢀHigh-Zꢀstateꢀduringꢀtheꢀcycle.
MemoryꢀCycle
Power-On
AꢀmemoryꢀcycleꢀisꢀinitiatedꢀbyꢀbringꢀRASꢀLOWꢀandꢀitꢀisꢀ
terminatedꢀ byꢀ returningꢀ bothꢀ RASꢀ andꢀ CASꢀ HIGH.ꢀToꢀ
ensuresꢀproperꢀdeviceꢀoperationꢀandꢀdataꢀintegrityꢀanyꢀ
memoryꢀcycle,ꢀonceꢀinitiated,ꢀmustꢀnotꢀbeꢀendedꢀorꢀabortedꢀ
beforeꢀtheꢀminimumꢀtrasꢀtimeꢀhasꢀexpired.ꢀAꢀnewꢀcycleꢀ
mustꢀnotꢀbeꢀinitiatedꢀuntilꢀtheꢀminimumꢀprechargeꢀtimeꢀ
trp,ꢀtcpꢀhasꢀelapsed.
During Power-On, RAS, UCAS, LCAS, and WE must
all track with Vdd (HIGH) to avoid current surges,
and allow initialization to continue. An initial pause of
200 µs is required followed by a minimum of eight initial-
ization cycles (any combination of cycles containing a
RAS signal).ꢀ
ReadꢀCycle
AꢀreadꢀcycleꢀisꢀinitiatedꢀbyꢀtheꢀfallingꢀedgeꢀofꢀCASꢀorꢀOE,ꢀ
whicheverꢀoccursꢀlast,ꢀwhileꢀholdingꢀWEꢀHIGH.ꢀTheꢀcolumnꢀ
addressꢀmustꢀbeꢀheldꢀforꢀaꢀminimumꢀtimeꢀspecifiedꢀbyꢀtar.ꢀ
DataꢀOutꢀbecomesꢀvalidꢀonlyꢀwhenꢀtrac,ꢀtaa,ꢀtcacꢀandꢀtoeaꢀ
areꢀallꢀsatisfied.ꢀAsꢀaꢀresult,ꢀtheꢀaccessꢀtimeꢀisꢀdependentꢀ
onꢀtheꢀtimingꢀrelationshipsꢀbetweenꢀtheseꢀparameters.
Integrated Silicon Solution, Inc. — 1-800-379-4774ꢀ
5
Rev.ꢀ A
02/24/2012
IS41C16105C
IS41LV16105Cꢀ
ABSOLUTEꢀMAXIMUMꢀRATINGS(1)
ꢀ Symbolꢀ
Parametersꢀ
ꢀ
Ratingꢀ
Unit
ꢀ
ꢀ
Vtꢀ
ꢀ
VoltageꢀonꢀAnyꢀPinꢀRelativeꢀtoꢀGNDꢀ
ꢀ
5Vꢀꢀ
3.3Vꢀ
–1.0ꢀtoꢀ+7.0ꢀ
–0.5ꢀtoꢀ+4.6
V
ꢀ
ꢀ
Vddꢀ
ꢀ
SupplyꢀVoltageꢀ
ꢀ
5Vꢀ
3.3Vꢀ
–1.0ꢀtoꢀ+7.0ꢀ
–0.5ꢀtoꢀ+4.6
V
ꢀ
ꢀ
ꢀ
ꢀ
Ioutꢀ
Pdꢀ
OutputꢀCurrentꢀ
ꢀ
ꢀ
ꢀ
ꢀ
50ꢀ
1ꢀ
mA
W
PowerꢀDissipationꢀ
IndustrialꢀTemperatureꢀ
StorageꢀTemperatureꢀ
Taꢀ
–40ꢀtoꢀ+85ꢀ
°C
Tstgꢀ
–55ꢀtoꢀ+125ꢀ °C
Note:
1.ꢀ StressꢀgreaterꢀthanꢀthoseꢀlistedꢀunderꢀABSOLUTEꢀMAXIMUMꢀRATINGSꢀmayꢀcauseꢀpermanentꢀdamageꢀtoꢀtheꢀ
device.ꢀThisꢀisꢀaꢀstressꢀratingꢀonlyꢀandꢀfunctionalꢀoperationꢀofꢀtheꢀdeviceꢀatꢀtheseꢀorꢀanyꢀotherꢀconditionsꢀaboveꢀ
thoseꢀindicatedꢀinꢀtheꢀoperationalꢀsectionsꢀofꢀthisꢀspecificationꢀisꢀnotꢀimplied.ꢀExposureꢀtoꢀabsoluteꢀmaximumꢀ
ratingꢀconditionsꢀforꢀextendedꢀperiodsꢀmayꢀaffectꢀreliability.
RECOMMENDEDꢀOPERATINGꢀCONDITIONSꢀ(VoltagesꢀareꢀreferencedꢀtoꢀGND.)
ꢀ Symbolꢀ Parameterꢀ
TestꢀConditionꢀ
ꢀ
Min.ꢀ Typ.ꢀ
Max.ꢀ
Unit
ꢀ Vddꢀ
ꢀ ꢀ
SupplyꢀVoltageꢀ
ꢀ
ꢀ
ꢀ
5Vꢀ
3.3Vꢀ
4.5ꢀ
3.0ꢀ
5.0ꢀ
3.3ꢀ
5.5ꢀ
3.6
V
ꢀ Vihꢀ
ꢀ ꢀ
InputꢀHighꢀVoltageꢀ
ꢀ
ꢀ
ꢀ
5Vꢀ
3.3Vꢀ
2.4ꢀ
2.0ꢀ
—ꢀ Vddꢀ+ꢀ1.0ꢀ
—ꢀ Vddꢀ+ꢀ0.3
V
V
ꢀ Vilꢀ
ꢀ ꢀ
InputꢀLowꢀVoltageꢀ
ꢀ
ꢀ
ꢀ
5Vꢀ
3.3Vꢀ
–1.0ꢀ
–0.3ꢀ
—ꢀ
—ꢀ
0.8ꢀ
0.8
ꢀ iilꢀ
ꢀ ꢀ
InputꢀLeakageꢀCurrentꢀ
ꢀ
Anyꢀinputꢀ0Vꢀ≤ꢀVinꢀ≤ꢀVddꢀ
Otherꢀinputsꢀnotꢀunderꢀtestꢀ=ꢀ0Vꢀ
ꢀ
ꢀ
–5ꢀ
ꢀ
ꢀ
ꢀ
5ꢀ
µA
µA
V
ꢀ iioꢀ
ꢀ ꢀ
OutputꢀLeakageꢀCurrentꢀ
ꢀ
Outputꢀisꢀdisabledꢀ(Hi-Z)ꢀ
0Vꢀ≤ꢀVoutꢀ≤ꢀVddꢀ
ꢀ
ꢀ
–5ꢀ
ꢀ
ꢀ
ꢀ
5ꢀ
ꢀ
ꢀ Vohꢀ
ꢀ ꢀ
OutputꢀHighꢀVoltageꢀLevelꢀ
ꢀ
iohꢀ=ꢀ–5.0ꢀmAꢀ
iohꢀ=ꢀ–2.0ꢀmAꢀꢀ
5Vꢀ
3.3Vꢀ
2.4ꢀ
2.4ꢀ
ꢀ
ꢀ
—ꢀ
—
ꢀ Volꢀ
ꢀ ꢀ
OutputꢀLowꢀVoltageꢀLevelꢀ
ꢀ
iolꢀ=ꢀ4.2ꢀmAꢀ
iolꢀ=ꢀ2.0ꢀmAꢀꢀ
5Vꢀ
3.3Vꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
0.4ꢀ
0.4
V
CAPACITANCE(1,2)
ꢀ Symbolꢀ
Parameterꢀ
Max.ꢀ
Unit
pF
ꢀ
ꢀ
ꢀ
Cin1ꢀ
Cin2ꢀ
Cioꢀ
InputꢀCapacitance:ꢀA0-A9ꢀ
5ꢀ
7ꢀ
7ꢀ
InputꢀCapacitance:ꢀRAS,ꢀUCAS,ꢀLCAS,ꢀWE,ꢀOEꢀꢀ
DataꢀInput/OutputꢀCapacitance:ꢀI/O0-I/O15ꢀ
pF
pF
Notes:
1.ꢀꢀTestedꢀinitiallyꢀandꢀafterꢀanyꢀdesignꢀorꢀprocessꢀchangesꢀthatꢀmayꢀaffectꢀtheseꢀparameters.
2.ꢀꢀTestꢀconditions:ꢀꢀTaꢀ=ꢀ25°C,ꢀfꢀ=ꢀ1ꢀMHz,
6ꢀ
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev.ꢀ A
02/24/2012
IS41C16105C
IS41LV16105Cꢀ
ELECTRICALꢀCHARACTERISTICS(1)
(RecommendedꢀOperatingꢀConditionsꢀunlessꢀotherwiseꢀnoted.)
ꢀ
Symbolꢀ Parameterꢀ
TestꢀConditionꢀ
ꢀ
ꢀ VDD/Speedꢀ Min.ꢀ Max.ꢀ Unit
ꢀ
ꢀ
ꢀ
idd1ꢀꢀ
ꢀ
ꢀ
StandbyꢀCurrent:ꢀTTLꢀ
ꢀ
ꢀ
RAS,ꢀLCAS,ꢀUCASꢀ≥ꢀVihꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
5Vꢀ
3.3Vꢀ
—ꢀ
—ꢀ
2ꢀ
2
mAꢀ
mAꢀ
mA
ꢀ
ꢀ
idd2ꢀꢀ
ꢀ
StandbyꢀCurrent:ꢀCMOSꢀ
ꢀ
RAS,ꢀLCAS,ꢀUCASꢀ≥ꢀVddꢀ–ꢀ0.2V
ꢀ
ꢀ
ꢀ
ꢀ
5Vꢀ
3.3Vꢀ
—ꢀ
—ꢀ
1ꢀ
1
ꢀ
ꢀ
ꢀ
ꢀ
idd3ꢀꢀ
ꢀ
ꢀ
OperatingꢀCurrent:ꢀꢀ
RAS,ꢀLCAS,ꢀUCAS,ꢀ
AddressꢀCycling,ꢀꢀtrcꢀ=ꢀtrcꢀ(min.)ꢀꢀ
ꢀ
ꢀ
ꢀ
5Vꢀ
3.3Vꢀ
—ꢀ
—ꢀ
90ꢀ
90ꢀ
RandomꢀRead/Write(2,3,4)ꢀ
AverageꢀPowerꢀSupplyꢀCurrent
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
idd4ꢀꢀ
ꢀ
ꢀ
OperatingꢀCurrent:ꢀꢀ
RASꢀ=ꢀVil,ꢀLCAS,ꢀUCAS,ꢀ
Cyclingꢀꢀtpcꢀ=ꢀtpcꢀ(min.)ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
5Vꢀ
3.3Vꢀ
—ꢀ
—ꢀ
30ꢀ
30ꢀ
mA
mA
mA
FastꢀPageꢀMode(2,3,4)
ꢀ
AverageꢀPowerꢀSupplyꢀCurrent
ꢀ
ꢀ
ꢀ
idd5ꢀꢀ
ꢀ
ꢀ
RefreshꢀCurrent:ꢀ
RASꢀCycling,ꢀLCAS,ꢀUCASꢀ≥ꢀVihꢀ ꢀ
trcꢀ=ꢀtrcꢀ(min.)ꢀ
ꢀ
5Vꢀ
3.3Vꢀ
—ꢀ
—ꢀ
60ꢀ
60ꢀ
RAS-Only(2,3)
ꢀ
ꢀ
ꢀ
ꢀ
AverageꢀPowerꢀSupplyꢀCurrent
ꢀ
ꢀ
ꢀ
idd6ꢀꢀ
ꢀ
ꢀ
RefreshꢀCurrent:ꢀꢀ
RAS,ꢀLCAS,ꢀUCASꢀCyclingꢀꢀ
trcꢀ=ꢀtrcꢀ(min.)ꢀ
ꢀ
ꢀ
ꢀ
5Vꢀ
3.3Vꢀ
—ꢀ ꢀ
—ꢀ ꢀ
60ꢀ
60ꢀ
CBR(2,3,5)
ꢀ
ꢀ
ꢀ
AverageꢀPowerꢀSupplyꢀCurrent
Notes:
1.ꢀ Anꢀinitialꢀpauseꢀofꢀ200ꢀµsꢀisꢀrequiredꢀafterꢀpower-upꢀfollowedꢀbyꢀeightꢀRASꢀrefreshꢀcyclesꢀ(RAS-OnlyꢀorꢀCBR)ꢀbeforeꢀproperꢀdeviceꢀ
operationꢀisꢀassured.ꢀꢀꢀTheꢀeightꢀRASꢀcyclesꢀwake-upꢀshouldꢀbeꢀrepeatedꢀanyꢀtimeꢀtheꢀtrefꢀrefreshꢀrequirementꢀisꢀexceeded.
2.ꢀ Dependentꢀonꢀcycleꢀrates.
3.ꢀ Specifiedꢀvaluesꢀareꢀobtainedꢀwithꢀminimumꢀcycleꢀtimeꢀandꢀtheꢀoutputꢀopen.
4.ꢀ Column-addressꢀisꢀchangedꢀonceꢀeachꢀFastꢀpageꢀcycle.
5.ꢀ Enablesꢀon-chipꢀrefreshꢀandꢀaddressꢀcounters.
Integrated Silicon Solution, Inc. — 1-800-379-4774ꢀ
7
Rev.ꢀ A
02/24/2012
IS41C16105C
IS41LV16105Cꢀ
ACꢀCHARACTERISTICS(1,2,3,4,5,6)
(RecommendedꢀOperatingꢀConditionsꢀunlessꢀotherwiseꢀnoted.)
ꢀ ꢀ
ꢀ
ꢀ -50ꢀ ꢀ
ꢀ -60
ꢀ Symbolꢀ
Parameterꢀ
Min.ꢀ ꢀ Max.ꢀ
Min.ꢀ ꢀ Max.ꢀ
104ꢀ ꢀ —ꢀ
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
trcꢀ
RandomꢀREADꢀorꢀWRITEꢀCycleꢀTimeꢀ
AccessꢀTimeꢀfromꢀRAS(6,ꢀ7)ꢀ
AccessꢀTimeꢀfromꢀCAS(6,ꢀ8,ꢀ15)ꢀ
AccessꢀTimeꢀfromꢀColumn-Address(6)ꢀ
RASꢀPulseꢀWidthꢀ
84ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
50ꢀ
13ꢀ
25ꢀ
tracꢀ
tcacꢀ
taaꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
ꢀ
60ꢀ
15ꢀ
30ꢀ
trasꢀ
trpꢀ
50ꢀ ꢀ 10Kꢀ
30ꢀ —ꢀ
8ꢀ ꢀ 10Kꢀ
60ꢀ ꢀ 10Kꢀ
40ꢀ —ꢀ
10ꢀ ꢀ 10Kꢀ
RASꢀPrechargeꢀTimeꢀ
ꢀ
ꢀ
tcasꢀ
tcpꢀ
CASꢀPulseꢀWidth(26)
CASꢀPrechargeꢀTime(9,ꢀ25)
CASꢀHoldꢀTimeꢀ(21)
RASꢀtoꢀCASꢀDelayꢀTime(10,ꢀ20)
Row-AddressꢀSetupꢀTimeꢀ
Row-AddressꢀHoldꢀTimeꢀ
ꢀ
ꢀ
9ꢀ
38ꢀ
12ꢀ
0ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
37ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
9ꢀ
40ꢀ
14ꢀ
0ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
45ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
tcshꢀ
trcdꢀ
tasrꢀ
trahꢀ
tascꢀ
tcahꢀ
ꢀ
ꢀ
8ꢀ
10ꢀ
0ꢀ
Column-AddressꢀSetupꢀTime(20)
Column-AddressꢀHoldꢀTime(20)
ꢀ
0ꢀ
ꢀ
8ꢀ
10ꢀ
ꢀ
ꢀ
tarꢀ
ꢀ
Column-AddressꢀHoldꢀTimeꢀ
(referencedꢀtoꢀRAS)ꢀ
30ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
ꢀ
40ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
tradꢀ
tralꢀ
trpcꢀ
trshꢀ
trhcpꢀ
tclzꢀ
tcrpꢀ
todꢀ
RASꢀtoꢀColumn-AddressꢀDelayꢀTime(11)
Column-AddressꢀtoꢀRASꢀLeadꢀTimeꢀ
RASꢀtoꢀCASꢀPrechargeꢀTimeꢀ
ꢀ
10ꢀ
25ꢀ
5ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
25ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
15ꢀ
13ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
12ꢀ
30ꢀ
5ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
30ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
15ꢀ
15ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RASꢀHoldꢀTime(27)
RASꢀHoldꢀTimeꢀfromꢀCASꢀPrechargeꢀ
CASꢀtoꢀOutputꢀinꢀLow-Z(15,ꢀ29)
CASꢀtoꢀRASꢀPrechargeꢀTime(21)
OutputꢀDisableꢀTime(19,ꢀ28,ꢀ29)
OutputꢀEnableꢀTime(15,ꢀ16)
ꢀ
8ꢀ
10ꢀ
37ꢀ
0ꢀ
37ꢀ
0ꢀ
ꢀ
ꢀ
5ꢀ
5ꢀ
ꢀ
3ꢀ
3ꢀ
toeꢀ
ꢀ
—ꢀ
20ꢀ
5ꢀ
—ꢀ
20ꢀ
5ꢀ
toedꢀ
toehcꢀ
toepꢀ
toesꢀ
trcsꢀ
OutputꢀEnableꢀDataꢀDelayꢀ(Write)ꢀ
OEꢀHIGHꢀHoldꢀTimeꢀfromꢀCASꢀHIGHꢀ
OEꢀHIGHꢀPulseꢀWidthꢀ
10ꢀ
5ꢀ
10ꢀ
5ꢀ
OEꢀLOWꢀtoꢀCASꢀHIGHꢀSetupꢀTimeꢀ
ReadꢀCommandꢀSetupꢀTime(17,ꢀ20)
ꢀ
0ꢀ
0ꢀ
ꢀ
ꢀ
trrhꢀ
ꢀ
ReadꢀCommandꢀHoldꢀTimeꢀ
0ꢀ
ꢀ
0ꢀ
(referencedꢀtoꢀRAS)(12)
ꢀ
ꢀ
ꢀ
trchꢀ
ꢀ
ReadꢀCommandꢀHoldꢀTimeꢀ
(referencedꢀtoꢀCAS)(12,ꢀ17,ꢀ21)
WriteꢀCommandꢀHoldꢀTime(17,ꢀ27)
0ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
0ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
ns
ns
ꢀ
ꢀ
twchꢀ
ꢀ
8ꢀ
10ꢀ
8ꢀ
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev.ꢀ A
02/24/2012
IS41C16105C
IS41LV16105Cꢀ
ACꢀCHARACTERISTICSꢀ(Continued)(1,2,3,4,5,6)ꢀ
(RecommendedꢀOperatingꢀConditionsꢀunlessꢀotherwiseꢀnoted.)
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ -50ꢀ ꢀ
Min.ꢀ ꢀ Max.ꢀ
ꢀ -60ꢀ ꢀ
Min.ꢀ ꢀ Max.ꢀ
ꢀ
Symbolꢀ
Parameterꢀ
Units
ꢀ
ꢀ
twcrꢀ
ꢀ
WriteꢀCommandꢀHoldꢀTimeꢀ
40ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
50ꢀ
ꢀ
—ꢀ
ns
(referencedꢀtoꢀRAS)(17)
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
twpꢀ
WriteꢀCommandꢀPulseꢀWidth(17)
ꢀ
8ꢀ
10ꢀ
13ꢀ
8ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
10ꢀ
10ꢀ
15ꢀ
10ꢀ
0ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
ns
ns
ns
ns
ns
ns
ns
twpzꢀ
trwlꢀ
tcwlꢀ
twcsꢀ
tdhrꢀ
WEꢀPulseꢀWidthsꢀtoꢀDisableꢀOutputsꢀ
WriteꢀCommandꢀtoꢀRASꢀLeadꢀTime(17)
WriteꢀCommandꢀtoꢀCASꢀLeadꢀTime(17,ꢀ21)
WriteꢀCommandꢀSetupꢀTime(14,ꢀ17,ꢀ20)
ꢀ
ꢀ
ꢀ
0ꢀ
Data-inꢀHoldꢀTimeꢀ(referencedꢀtoꢀRAS)ꢀ
39ꢀ
15ꢀ
39ꢀ
15ꢀ
ꢀ
ꢀ
tachꢀ
ꢀ
Column-AddressꢀSetupꢀTimeꢀtoꢀCASꢀ
PrechargeꢀduringꢀWRITEꢀCycle
ꢀ
ꢀ
toehꢀ
ꢀ
OEꢀHoldꢀTimeꢀfromꢀWEꢀduringꢀ
8ꢀ
ꢀ
—ꢀ
10ꢀ
ꢀ
—ꢀ
ns
READ-MODIFY-WRITEꢀcycle(18)
ꢀ
ꢀ
ꢀ
tdsꢀ
Data-InꢀSetupꢀTime(15,ꢀ22)
Data-InꢀHoldꢀTime(15,ꢀ22)
ꢀ
0ꢀ
8ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
0ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
ns
ns
ns
ns
tdhꢀ
ꢀ
10ꢀ
trwcꢀ
READ-MODIFY-WRITEꢀCycleꢀTimeꢀ
108ꢀ ꢀ —ꢀ
133ꢀ ꢀ —ꢀ
ꢀ
ꢀ
trwdꢀ
ꢀ
RASꢀtoꢀWEꢀDelayꢀTimeꢀduringꢀ
64ꢀ
ꢀ
—ꢀ
77ꢀ
ꢀ
—ꢀ
READ-MODIFY-WRITEꢀCycle(14)
ꢀ
tcwdꢀ
tawdꢀ
CASꢀtoꢀWEꢀDelayꢀTime(14,ꢀ20)
Column-AddressꢀtoꢀWEꢀDelayꢀTime(14)
ꢀ
ꢀ
26ꢀ
39ꢀ
20ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
32ꢀ
47ꢀ
25ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
ns
ns
ns
ꢀ
ꢀ
ꢀ
tpcꢀ
ꢀ
FastꢀPageꢀModeꢀREADꢀorꢀWRITEꢀ
CycleꢀTime(24)
ꢀ
ꢀ
ꢀ
ꢀ
traspꢀ
tcpaꢀ
RASꢀPulseꢀWidthꢀ
50ꢀ ꢀ 100Kꢀ
60ꢀ ꢀ 100Kꢀ
ns
ns
ns
ns
ns
AccessꢀTimeꢀfromꢀCASꢀPrecharge(15)
READ-WRITEꢀCycleꢀTime(24)
ꢀ
—ꢀ
56ꢀ
5ꢀ
ꢀ
ꢀ
ꢀ
30ꢀ
—ꢀ
—ꢀ
—ꢀ
68ꢀ
5ꢀ
ꢀ
ꢀ
ꢀ
35ꢀ
—ꢀ
—ꢀ
tprwcꢀ
tcohꢀ
ꢀ
DataꢀOutputꢀHoldꢀafterꢀCASꢀLOWꢀ
ꢀ
ꢀ
toffꢀ
ꢀ
OutputꢀBufferꢀTurn-OffꢀDelayꢀfromꢀ
1.6ꢀ ꢀ 12ꢀ
1.6ꢀ ꢀ 15ꢀ
CASꢀorꢀRAS(13,15,19,ꢀ29)
ꢀ
twhzꢀ
OutputꢀDisableꢀDelayꢀfromꢀWEꢀ
3ꢀ
ꢀ
ꢀ
10ꢀ
—ꢀ
3ꢀ
ꢀ
ꢀ
10ꢀ
—ꢀ
ns
ns
ꢀ
ꢀ
tclchꢀ
ꢀ
LastꢀCASꢀgoingꢀLOWꢀtoꢀFirstꢀCASꢀ
10ꢀ
10ꢀ
returningꢀHIGH(23)
ꢀ
ꢀ
ꢀ
tcsrꢀ
tchrꢀ
CASꢀSetupꢀTimeꢀ(CBRꢀREFRESH)(30,ꢀ20)
ꢀ
5ꢀ
8ꢀ
0ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
5ꢀ
10ꢀ
0ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
ns
ns
ns
CASꢀHoldꢀTimeꢀ(CBRꢀREFRESH)(30,ꢀ21)
ꢀ
ꢀ
ꢀ
tordꢀ
ꢀ
OEꢀSetupꢀTimeꢀpriorꢀtoꢀRASꢀduringꢀ
HIDDENꢀREFRESHꢀCycle
ꢀ
twrp
twrh
trefꢀ
ttꢀ
WE Setup Time (CBR Refresh)
WE Hold Time (CBR Refresh)
AutoꢀRefreshꢀPeriodꢀ(1,024ꢀCycles)ꢀ
5
—
5
—
ns
ns
ms
ns
8
—
10
—ꢀ
1ꢀ
—
ꢀ
ꢀ
—ꢀ
1ꢀ
ꢀ
ꢀ
16ꢀ
50ꢀ
ꢀ
ꢀ
16ꢀ
50ꢀ
TransitionꢀTimeꢀ(RiseꢀorꢀFall)(2,ꢀ3)
ꢀ
Note:
The -60 timing parameters are shown for reference only. The -50 speed option supports 50ns and 60ns timing specifications.
Integrated Silicon Solution, Inc. — 1-800-379-4774ꢀ
9
Rev.ꢀ A
02/24/2012
IS41C16105C
IS41LV16105Cꢀ
ACꢀTESTꢀCONDITIONS
Outputꢀload:ꢀꢀTwoꢀTTLꢀLoadsꢀandꢀ100ꢀpFꢀ(Vddꢀ=ꢀ5.0Vꢀ±10%)
ꢀ
OneꢀTTLꢀLoadꢀandꢀ50ꢀpFꢀ(Vddꢀ=ꢀ3.3Vꢀ±10%)
Inputꢀtimingꢀreferenceꢀlevels:ꢀ Vihꢀ=ꢀ2.4V,ꢀVilꢀ=ꢀ0.8Vꢀ(Vddꢀ=ꢀ5.0Vꢀ±10%);
Vihꢀ=ꢀ2.0V,ꢀVilꢀ=ꢀ0.8Vꢀ(Vddꢀ=ꢀ3.3Vꢀ±10%)
ꢀ
Outputꢀtimingꢀreferenceꢀlevels:ꢀ Vohꢀ=ꢀ2.4V,ꢀVolꢀ=ꢀ0.4Vꢀ(Vddꢀ=ꢀ5Vꢀ±10%,ꢀ3.3Vꢀ±10%)
Notes:
ꢀ 1.ꢀAnꢀinitialꢀpauseꢀofꢀ200ꢀµsꢀisꢀrequiredꢀafterꢀpower-upꢀfollowedꢀbyꢀeightꢀRASꢀrefreshꢀcycleꢀ(RAS-OnlyꢀorꢀCBR)ꢀbeforeꢀproperꢀdeviceꢀ
operationꢀisꢀassured.ꢀTheꢀeightꢀRASꢀcyclesꢀwake-upꢀshouldꢀbeꢀrepeatedꢀanyꢀtimeꢀtheꢀtrefꢀrefreshꢀrequirementꢀisꢀexceeded.
ꢀ 2.ꢀVihꢀ(MIN)ꢀandꢀVilꢀ(MAX)ꢀareꢀreferenceꢀlevelsꢀforꢀmeasuringꢀtimingꢀofꢀinputꢀsignals.ꢀTransitionꢀtimes,ꢀareꢀmeasuredꢀbetweenꢀVihꢀ
andꢀVilꢀ(orꢀbetweenꢀVilꢀandꢀVih)ꢀandꢀassumeꢀtoꢀbeꢀ1ꢀnsꢀforꢀallꢀinputs.
ꢀ 3.ꢀInꢀadditionꢀtoꢀmeetingꢀtheꢀtransitionꢀrateꢀspecification,ꢀallꢀinputꢀsignalsꢀmustꢀtransitꢀbetweenꢀVihꢀandꢀVilꢀ(orꢀbetweenꢀVilꢀandꢀVih)ꢀ
inꢀaꢀmonotonicꢀmanner.
ꢀ 4.ꢀIfꢀCASꢀandꢀRASꢀ=ꢀVih,ꢀdataꢀoutputꢀisꢀHigh-Z.
ꢀ 5.ꢀIfꢀCASꢀ=ꢀVil,ꢀdataꢀoutputꢀmayꢀcontainꢀdataꢀfromꢀtheꢀlastꢀvalidꢀREADꢀcycle.
ꢀ 6.ꢀMeasuredꢀwithꢀaꢀloadꢀequivalentꢀtoꢀoneꢀTTLꢀgateꢀandꢀ50ꢀpF.
ꢀ 7.ꢀAssumesꢀthatꢀtrcdꢀꢀtrcdꢀ(MAX).ꢀIfꢀtrcdꢀisꢀgreaterꢀthanꢀtheꢀmaximumꢀrecommendedꢀvalueꢀshownꢀinꢀthisꢀtable,ꢀtracꢀwillꢀincreaseꢀbyꢀ
theꢀamountꢀthatꢀtrcdꢀexceedsꢀtheꢀvalueꢀshown.
ꢀ 8.ꢀAssumesꢀthatꢀtrcdꢀžꢀtrcdꢀ(MAX).
ꢀ 9.ꢀIfꢀCASꢀisꢀLOWꢀatꢀtheꢀfallingꢀedgeꢀofꢀRAS,ꢀdataꢀoutꢀwillꢀbeꢀmaintainedꢀfromꢀtheꢀpreviousꢀcycle.ꢀToꢀinitiateꢀaꢀnewꢀcycleꢀandꢀclearꢀ
theꢀdataꢀoutputꢀbuffer,ꢀCASꢀandꢀRASꢀmustꢀbeꢀpulsedꢀforꢀtcp.
ꢀ10.ꢀOperationꢀwithꢀtheꢀtrcdꢀ(MAX)ꢀlimitꢀensuresꢀthatꢀtracꢀ(MAX)ꢀcanꢀbeꢀmet.ꢀtrcdꢀ(MAX)ꢀisꢀspecifiedꢀasꢀaꢀreferenceꢀpointꢀonly;ꢀifꢀtrcdꢀ
isꢀgreaterꢀthanꢀtheꢀspecifiedꢀtrcdꢀ(MAX)ꢀlimit,ꢀaccessꢀtimeꢀisꢀcontrolledꢀexclusivelyꢀbyꢀtcac.
ꢀ11.ꢀOperationꢀwithinꢀtheꢀtradꢀ(MAX)ꢀlimitꢀensuresꢀthatꢀtrcdꢀ(MAX)ꢀcanꢀbeꢀmet.ꢀtradꢀ(MAX)ꢀisꢀspecifiedꢀasꢀaꢀreferenceꢀpointꢀonly;ꢀifꢀtradꢀ
isꢀgreaterꢀthanꢀtheꢀspecifiedꢀtradꢀ(MAX)ꢀlimit,ꢀaccessꢀtimeꢀisꢀcontrolledꢀexclusivelyꢀbyꢀtaa.
ꢀ12.ꢀEitherꢀtrchꢀorꢀtrrhꢀmustꢀbeꢀsatisfiedꢀforꢀaꢀREADꢀcycle.
ꢀ13.ꢀtoffꢀ(MAX)ꢀdefinesꢀtheꢀtimeꢀatꢀwhichꢀtheꢀoutputꢀachievesꢀtheꢀopenꢀcircuitꢀcondition;ꢀitꢀisꢀꢀnotꢀaꢀreferenceꢀtoꢀVohꢀorꢀVol.
ꢀ14.ꢀtwcs,ꢀtrwd,ꢀtawdꢀandꢀtcwdꢀareꢀrestrictiveꢀoperatingꢀparametersꢀinꢀLATEꢀWRITEꢀandꢀREAD-MODIFY-WRITEꢀcycleꢀonly.ꢀIfꢀtwcsꢀžꢀ
twcsꢀ(MIN),ꢀtheꢀcycleꢀisꢀanꢀEARLYꢀWRITEꢀcycleꢀandꢀtheꢀdataꢀoutputꢀwillꢀremainꢀopenꢀcircuitꢀthroughoutꢀtheꢀentireꢀcycle.ꢀIfꢀtrwdꢀžꢀ
trwdꢀ(MIN),ꢀtawdꢀžꢀtawdꢀ(MIN)ꢀandꢀtcwdꢀžꢀtcwdꢀ(MIN),ꢀtheꢀcycleꢀisꢀaꢀREAD-WRITEꢀcycleꢀandꢀtheꢀdataꢀoutputꢀwillꢀcontainꢀdataꢀreadꢀ
fromꢀtheꢀselectedꢀcell.ꢀIfꢀneitherꢀofꢀtheꢀaboveꢀconditionsꢀisꢀmet,ꢀtheꢀstateꢀofꢀI/Oꢀ(atꢀaccessꢀtimeꢀandꢀuntilꢀCASꢀandꢀRASꢀorꢀOEꢀgoꢀ
backꢀtoꢀVih)ꢀisꢀindeterminate.ꢀOEꢀheldꢀHIGHꢀandꢀWEꢀtakenꢀLOWꢀafterꢀCASꢀgoesꢀLOWꢀresultꢀinꢀaꢀLATEꢀWRITEꢀ(OE-controlled)ꢀ
cycle.
ꢀ15.ꢀOutputꢀparameterꢀ(I/O)ꢀisꢀreferencedꢀtoꢀcorrespondingꢀCASꢀinput,ꢀI/O0-I/O7ꢀbyꢀLCASꢀandꢀI/O8-I/O15ꢀbyꢀUCAS.
ꢀ16.ꢀDuringꢀaꢀREADꢀcycle,ꢀifꢀOEꢀisꢀLOWꢀthenꢀtakenꢀHIGHꢀbeforeꢀCASꢀgoesꢀHIGH,ꢀI/Oꢀgoesꢀopen.ꢀIfꢀOEꢀisꢀtiedꢀpermanentlyꢀLOW,ꢀaꢀ
LATEꢀWRITEꢀorꢀREAD-MODIFY-WRITEꢀisꢀnotꢀpossible.
ꢀ17.ꢀWriteꢀcommandꢀisꢀdefinedꢀasꢀWEꢀgoingꢀlow.
ꢀ18.ꢀLATEꢀWRITEꢀandꢀREAD-MODIFY-WRITEꢀcyclesꢀmustꢀhaveꢀbothꢀtodꢀandꢀtoehꢀmetꢀ(OEꢀHIGHꢀduringꢀWRITEꢀcycle)ꢀinꢀorderꢀtoꢀ
ensureꢀthatꢀtheꢀoutputꢀbuffersꢀwillꢀbeꢀopenꢀduringꢀtheꢀWRITEꢀcycle.ꢀTheꢀI/OsꢀwillꢀprovideꢀtheꢀpreviouslyꢀwrittenꢀdataꢀifꢀCASꢀremainsꢀ
LOWꢀandꢀOEꢀisꢀtakenꢀbackꢀtoꢀLOWꢀafterꢀtoehꢀisꢀmet.
ꢀ19.ꢀTheꢀI/OsꢀareꢀinꢀopenꢀduringꢀREADꢀcyclesꢀonceꢀtodꢀorꢀtoffꢀoccur.
ꢀ20.ꢀTheꢀfirstꢀχCASꢀedgeꢀtoꢀtransitionꢀLOW.
ꢀ21.ꢀTheꢀlastꢀχCASꢀedgeꢀtoꢀtransitionꢀHIGH.
ꢀ22.ꢀTheseꢀparametersꢀareꢀreferencedꢀtoꢀCASꢀleadingꢀedgeꢀinꢀEARLYꢀWRITEꢀcyclesꢀandꢀWEꢀleadingꢀedgeꢀinꢀLATEꢀWRITEꢀorꢀREAD-
MODIFY-WRITEꢀcycles.
ꢀ23.ꢀLastꢀfallingꢀχCASꢀedgeꢀtoꢀfirstꢀrisingꢀχCASꢀedge.
ꢀ24.ꢀLastꢀrisingꢀχCASꢀedgeꢀtoꢀnextꢀcycle’sꢀlastꢀrisingꢀχCASꢀedge.
ꢀ25.ꢀLastꢀrisingꢀχCASꢀedgeꢀtoꢀfirstꢀfallingꢀχCASꢀedge.
ꢀ26.ꢀEachꢀχCASꢀmustꢀmeetꢀminimumꢀpulseꢀwidth.
ꢀ27.ꢀLastꢀχCASꢀtoꢀgoꢀLOW.
ꢀ28.ꢀI/Osꢀcontrolled,ꢀregardlessꢀUCASꢀandꢀLCAS.
ꢀ29.ꢀTheꢀ3ꢀnsꢀminimumꢀisꢀaꢀparameterꢀguaranteedꢀbyꢀdesign.ꢀ
ꢀ30.ꢀEnablesꢀon-chipꢀrefreshꢀandꢀaddressꢀcounters.
10ꢀ
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev.ꢀ A
02/24/2012
IS41C16105C
IS41LV16105Cꢀ
FAST-PAGE-MODEꢀREADꢀCYCLEꢀ
tRC
t
RAS
tRP
RAS
tCSH
t
RSH
t
RRH
t
CRP
ASR
t
CAS CLCH
t
t
RCD
UCAS/LCAS
tAR
t
RAD
tRAL
t
t
RAH
tCAH
tASC
ADDRESS
WE
Row
Column
Row
tRCS
t
RCH
tAA
tRAC
(1)
tOFF
t
t
CAC
CLC
Open
Open
Valid Data
I/O
OE
tOE
tOD
tOES
Don’tꢀCare
Note:ꢀ
1.ꢀ toffꢀisꢀreferencedꢀfromꢀrisingꢀedgeꢀofꢀRASꢀorꢀCAS,ꢀwhicheverꢀoccursꢀlast.
Integrated Silicon Solution, Inc. — 1-800-379-4774ꢀ
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Rev.ꢀ A
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IS41C16105C
IS41LV16105Cꢀ
FASTꢀPAGEꢀMODEꢀREAD-MODIFY-WRITEꢀCYCLE
t
RASP
t
RP
RAS
t
CSH
t
PRWC
t
t
RSH
CAS
t
CAS
t
CAS
t
CRP
t
RCD
tCRP
t
CP
tCP
UCAS/LCAS
ADDRESS
t
CPWD
t
AR
t
CPWD
tRAL
t
RAD
t
CAH
t
CAH
tCAH
t
RAH
t
ASC
tASC
t
ASC
tASR
Row
Column
Column
Column
t
CWL
t
CWL
RWL
t
CWL
t
t
RWD
tAWD
t
AWD
t
AWD
t
RCS
t
CWD
t
CWD
tCWD
t
WP
t
WP
tWP
WE
OE
t
AA
t
AA
tAA
t
CAC
t
CAC
tCAC
tOEA
t
OEA
tOEA
tOEZ
t
OEZ
tOEZ
t
RAC
t
OED
tOED
t
OED
tDH
tDH
t
DH
CLZ
t
CLZ
t
DS
t
t
DS
t
CLZ
tDS
I/O0-I/O15
OUT
OUT
IN
IN
IN
OUT
Don’tꢀCare
12ꢀ
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev.ꢀ A
02/24/2012
IS41C16105C
IS41LV16105Cꢀ
FAST-PAGE-MODEꢀEARLYꢀWRITEꢀCYCLEꢀ(OEꢀ=ꢀDON'TꢀCARE)
tRC
t
RAS
tRP
RAS
t
CSH
t
RSH
t
CRP
ASR
t
CAS CLCH
t
t
RCD
UCAS/LCAS
tAR
t
RAD
t
t
t
RAL
CAH
ACH
t
t
RAH
tASC
ADDRESS
Row
Column
Row
t
t
CWL
RWL
t
WCR
tWCS
tWCH
tWP
WE
I/O
t
t
DHR
t
DH
DS
Valid Data
Don’tꢀCare
Integrated Silicon Solution, Inc. — 1-800-379-4774ꢀ
13
Rev.ꢀ A
02/24/2012
IS41C16105C
IS41LV16105Cꢀ
FAST-PAGE-MODEꢀREADꢀWRITEꢀCYCLEꢀ(LATEꢀWRITEꢀandꢀREAD-MODIFY-WRITEꢀCycles)ꢀ
t
t
RWC
RAS
t
RP
RAS
t
CSH
t
RSH
t
CRP
ASR
t
CAS CLCH
t
t
RCD
UCAS/LCAS
t
AR
t
RAD
tRAL
t
t
RAH
tCAH
t
ASC
t
ACH
ADDRESS
WE
Row
Column
Row
tRWD
tCWL
tRCS
t
CWD
t
RWL
t
AWD
t
WP
t
AA
t
RAC
t
t
CAC
CLZ
tDS
tDH
Open
Open
Valid DOUT
Valid DIN
I/O
t
OD
tOEH
tOE
OE
Don’tꢀCare
14ꢀ
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev.ꢀ A
02/24/2012
IS41C16105C
IS41LV16105Cꢀ
FASTꢀPAGEꢀMODEꢀEARLYꢀWRITEꢀCYCLE
tRASP
tRP
RAS
t
t
RHCP
RSH
CAS
t
CSH
t
PC
t
t
CAS
tCAS
t
t
CRP
t
RCD
t
CRP
t
CP
t
CP
UCAS/LCAS
ADDRESS
t
AR
RAL
t
RAD
tCAH
tCAH
tCAH
t
RAH
t
ASC
t
ASC
t
ASC
t
ASR
Row
Column
Column
Column
t
CWL
t
CWL
t
CWL
WCH
tWCS
t
WCS
t
WCH
t
WCS
t
WCH
t
t
WP
t
WP
tWP
WE
OE
tWCR
tDHR
t
DS
tDS
tDS
t
DH
t
DH
tDH
Valid DIN
Valid DIN
Valid DIN
I/O0-I/O15
Don’tꢀCare
Integrated Silicon Solution, Inc. — 1-800-379-4774ꢀ
15
Rev.ꢀ A
02/24/2012
IS41C16105C
IS41LV16105Cꢀ
ACꢀWAVEFORMS
READꢀCYCLEꢀ(WithꢀWE-ControlledꢀDisable)
RAS
t
CSH
t
CRP
ASR
t
RCD
tCP
tCAS
UCAS/LCAS
t
AR
t
RAD
t
t
RAH
t
CAH
tASC
tASC
ADDRESS
WE
Row
Column
Column
t
RCS
t
RCH
tRCS
t
WPZ
tAA
t
RAC
t
t
CAC
CLZ
tWHZ
tCLZ
Open
Open
Valid Data
I/O
OE
t
OE
tOD
Don’tꢀCare
RAS-ONLYꢀREFRESHꢀCYCLEꢀ(OE,ꢀWEꢀ=ꢀDON'TꢀCARE)
tRC
t
RAS
tRP
RAS
t
CRP
t
RPC
UCAS/LCAS
t
ASR
tRAH
ADDRESS
I/O
Row
Row
Open
Don’tꢀCare
16ꢀ
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev.ꢀ A
02/24/2012
IS41C16105C
IS41LV16105Cꢀ
CBRꢀREFRESHꢀCYCLEꢀ(Addresses;ꢀOEꢀ=ꢀDON'TꢀCARE)
tRP
tRAS
t
RP
tRAS
RAS
tCHR
tCHR
t
RPC
tRPC
t
CP
tCSR
tCSR
UCAS/LCAS
Open
I/O
WE
tWRH
t
WRP
t
WRH
t
WRP
HIDDENꢀREFRESHꢀCYCLE(1)ꢀ(WEꢀ=ꢀHIGH;ꢀOEꢀ=ꢀLOW)
t
RAS
tRAS
t
RP
RAS
t
CRP
t
RCD
tRSH
tCHR
UCAS/LCAS
t
AR
t
RAD
t
RAL
t
ASR
t
RAH
tCAH
t
ASC
ADDRESS
Row
Column
t
AA
t
RAC
(2)
OFF
t
t
CAC
tCLZ
Open
Open
Valid Data
I/O
OE
t
OE
tOD
t
ORD
Don’tꢀCare
Notes:ꢀ
1.ꢀ AꢀHiddenꢀRefreshꢀmayꢀalsoꢀbeꢀperformedꢀafterꢀaꢀWriteꢀCycle.ꢀInꢀthisꢀcase,ꢀWEꢀ=ꢀLOWꢀandꢀOEꢀ=ꢀHIGH.
2.ꢀ toffꢀisꢀreferencedꢀfromꢀrisingꢀedgeꢀofꢀRASꢀorꢀCAS,ꢀwhicheverꢀoccursꢀlast.
Integrated Silicon Solution, Inc. — 1-800-379-4774ꢀ
17
Rev.ꢀ A
02/24/2012
IS41C16105C
IS41LV16105Cꢀ
ORDERINGꢀINFORMATIONꢀ:ꢀ5V
IndustrialꢀRange:ꢀ-40oCꢀtoꢀ85oC
ꢀSpeedꢀ(ns)ꢀ OrderꢀPartꢀNo.ꢀ
Package
ꢀ
ꢀ
ꢀ
ꢀ
50ꢀ
IS41C16105C-50KIꢀ
IS41C16105C-50KLIꢀ 400-milꢀSOJ,ꢀLead-freeꢀ
IS41C16105C-50TIꢀ 400-milꢀTSOPꢀ(TypeꢀII)ꢀ ꢀ
400-milꢀSOJꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
IS41C16105C-50TLIꢀ 400-milꢀTSOPꢀ(TypeꢀII),ꢀLead-free
ORDERINGꢀINFORMATIONꢀ:ꢀ3.3V
IndustrialꢀRange:ꢀ-40oCꢀtoꢀ85oC
ꢀSpeedꢀ(ns)ꢀ OrderꢀPartꢀNo.ꢀ
Package
400-milꢀSOJꢀ
IS41LV16105C-50KLIꢀ 400-milꢀSOJ,ꢀLead-freeꢀ
IS41LV16105C-50TIꢀ 400-milꢀTSOPꢀ(TypeꢀII)ꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ
50ꢀ
IS41LV16105C-50KIꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
IS41LV16105C-50TLIꢀ 400-milꢀTSOPꢀ(TypeꢀII),ꢀLead-free
Note:
The -50 speed option supports 50ns and 60ns timing specifications.
18ꢀ
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev.ꢀ A
02/24/2012
IS41C16105C
IS41LV16105Cꢀ
Integrated Silicon Solution, Inc. — 1-800-379-4774ꢀ
19
Rev.ꢀ A
02/24/2012
IS41C16105C
IS41LV16105Cꢀ
20ꢀ
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev.ꢀ A
02/24/2012
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