IS41LV16100D-50KLI [ISSI]
Fast Page DRAM, 1MX16, 25ns, CMOS, PDSO42, SOJ-42;
| 型号： | IS41LV16100D-50KLI |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Fast Page DRAM, 1MX16, 25ns, CMOS, PDSO42, SOJ-42 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总22页 (文件大小：511K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS41LV16100D
1Mx16
PRELIMINARY INFORMATION
MARCH 2016
16Mb DRAM WITH EDO PAGE MODE
FEATURES
DESCRIPTION
Theꢀ ISSIꢀ IS41LV16100Dꢀ isꢀ aꢀ 1,048,576ꢀ xꢀ 16-bitꢀ high-
performanceꢀCMOSꢀꢀDynamicꢀRandomꢀAccessꢀMemories.ꢀ
TheseꢀdevicesꢀofferꢀaꢀcycleꢀaccessꢀcalledꢀꢀExtendedꢀDataꢀ
Outꢀ(EDO)ꢀPageꢀMode.ꢀEDOꢀPageꢀModeꢀallowsꢀ1,024ꢀ
random accesses within a single row with access cycle
time as short as 30 ns per 16-bit word.It is asynchronous,
as it does not require a clock signal input to synchronize
commandsꢀandꢀI/O.
•ꢀ TTLꢀcompatibleꢀinputsꢀandꢀoutputs;ꢀtristateꢀI/O
•ꢀ RefreshꢀInterval:ꢀ
— Auto refresh Mode: 1,024 cycles /16 ms
—
RAS-Only,ꢀCAS-before-RASꢀ(CBR),ꢀandꢀHidden
— Self refresh Mode: 1,024 cycles /128 ms
•ꢀ JEDECꢀstandardꢀpinout
TheseꢀfeaturesꢀmakeꢀtheꢀIS41LV16100Dꢀideallyꢀsuitedꢀ
for high-bandwidth graphics, digital signal processing,
high-performance computing systems, and peripheral
applications that run without a clock to synchronize with
theꢀDRAM.
•ꢀ Singleꢀpowerꢀsupply:ꢀ
3.3V 10ꢀ
•ꢀ ByteꢀWriteꢀandꢀByteꢀReadꢀoperationꢀviaꢀꢀtwoꢀCAS
•ꢀ IndustrialꢀTemperatureꢀRange:ꢀꢀ-40oC to +85oC
TheꢀIS41LV16100Dꢀisꢀpackagedꢀinꢀaꢀ42-pinꢀ400-milꢀSOJꢀ
andꢀ400-milꢀ50/44ꢀpinꢀTSOPꢀ(TypeꢀII).
KEY TIMING PARAMETERS
Parameter
-50
50
14
25
30
85
Unit
ns
Max. RASꢀAccessꢀTimeꢀ(trac)
Max. CASꢀAccessꢀTimeꢀ(tcac)
Max.ꢀColumnꢀAddressꢀAccessꢀTimeꢀ(taa)
Min.ꢀEDOꢀPageꢀModeꢀCycleꢀTimeꢀ(tpc)
Min.ꢀRead/WriteꢀCycleꢀTimeꢀ(trc)
ns
ꢀ
ꢀ
ꢀ
ns
ns
ns
Copyright © 2016 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex-
pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon
Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
1
Rev. 0A
3/29/2016
IS41LV16100D
PIN CONFIGURATIONS
50(44)-Pin TSOP (Type II)
42-Pin SOJ
VDD
I/O0
I/O1
I/O2
I/O3
VDD
I/O4
I/O5
I/O6
I/O7
NC
1
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
VDD
I/O0
I/O1
I/O2
I/O3
VDD
I/O4
I/O5
I/O6
I/O7
NC
1
44
43
42
41
40
39
38
37
36
35
34
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
11
I/O8
NC
10
11
12
13
14
15
16
17
18
19
20
21
NC
NC
WE
RAS
NC
NC
A0
12
13
14
15
16
17
18
19
20
21
22
33
32
31
30
29
28
27
26
25
24
23
NC
NC
LCAS
UCAS
OE
LCAS
UCAS
OE
WE
RAS
NC
A9
A9
NC
A8
A8
A7
A0
A7
A1
A6
A1
A6
A2
A5
A2
A5
A3
A4
A3
A4
VDD
GND
VDD
GND
PIN DESCRIPTIONS
A0-A9
I/O0-15ꢀ
WEꢀ
Address Inputs
DataꢀInputs/Outputs
WriteꢀEnable
OEꢀ
OutputꢀEnable
RASꢀ
UCAS
LCASꢀ
Vdd
RowꢀAddressꢀStrobe
Upper Column Address Strobe
LowerꢀColumnꢀAddressꢀStrobe
Power
GNDꢀ
NC
Ground
No Connection
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 0A
3/29/2016
IS41LV16100D
FUNCTIONAL BLOCK DIAGRAM
OE
WE
WE
CONTROL
LOGICS
OE
CONTROL
LOGIC
CAS
CLOCK
GENERATOR
LCAS
UCAS
CAS
WE
DATA I/O BUS
RAS
CLOCK
RAS
GENERATOR
COLUMN DECODERS
SENSE AMPLIFIERS
REFRESH
COUNTER
I/O0-I/O15
MEMORY ARRAY
1,048,576 x 16
ADDRESS
BUFFERS
A0-A9
Integrated Silicon Solution, Inc. — www.issi.com
3
Rev. 0A
3/29/2016
IS41LV16100D
TRUTH TABLE(5)
Function
Standbyꢀ
RAS LCAS UCAS
WE
Xꢀ
OE
Xꢀ
Address tR/tC
Xꢀ
I/O
ꢀ
ꢀ
Hꢀ
Lꢀ
Xꢀ
Lꢀ
Xꢀ
Lꢀ
High-Z
Dout
Read:ꢀWordꢀ
Hꢀ
Lꢀ
ROW/COLꢀ
Read:ꢀLowerꢀByteꢀ
ꢀ
ꢀ
ꢀ
Lꢀ
ꢀ
Lꢀ
ꢀ
Hꢀ
ꢀ
Hꢀ
ꢀ
Lꢀ
ꢀ
ROW/COLꢀ
ꢀ
LowerꢀByte,ꢀDout
UpperꢀByte,ꢀHigh-Z
Read:ꢀUpperꢀByteꢀ
ꢀ
ꢀ
ꢀ
Lꢀ
ꢀ
Hꢀ
ꢀ
Lꢀ
ꢀ
Hꢀ
ꢀ
Lꢀ
ꢀ
ROW/COLꢀ
ꢀ
LowerꢀByte,ꢀHigh-Zꢀ
UpperꢀByte,ꢀDout
Write:ꢀWordꢀ(EarlyꢀWrite)ꢀ
ꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
ROW/COLꢀ
Din
Write:ꢀLowerꢀByteꢀ(EarlyꢀWrite)ꢀ
ꢀ
ꢀ
ꢀ
Lꢀ
ꢀ
Lꢀ
ꢀ
Hꢀ
ꢀ
Lꢀ
ꢀ
Xꢀ
ꢀ
ROW/COLꢀ
ꢀ
LowerꢀByte,ꢀDin
UpperꢀByte,ꢀHigh-Z
Write:ꢀUpperꢀByteꢀ(EarlyꢀWrite)ꢀ
ꢀ
ꢀ
ꢀ
Lꢀ
ꢀ
Hꢀ
ꢀ
Lꢀ
ꢀ
Lꢀ
ꢀ
Xꢀ
ꢀ
ROW/COLꢀ
ꢀ
LowerꢀByte,ꢀHigh-Zꢀ
UpperꢀByte,ꢀDin
Read-Write(1,2)
ꢀ
ꢀ
Lꢀ
Lꢀ
Lꢀ
H→Lꢀ L→Hꢀ
ROW/COLꢀ
Dout,ꢀDin
EDOꢀPage-ModeꢀRead(2)ꢀ1stꢀCycle:ꢀ
2ndꢀCycle:ꢀ
Lꢀ
Lꢀ
Lꢀ
H→Lꢀ H→Lꢀ
H→Lꢀ H→Lꢀ
L→Hꢀ L→Hꢀ
H→Lꢀ H→Lꢀ
H→Lꢀ H→Lꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
ROW/COLꢀ
NA/COLꢀ
NA/NAꢀ
Dout
Dout
Dout
AnyꢀCycle:ꢀ
EDOꢀPage-ModeꢀWrite(1) 1stꢀCycle:ꢀ
2ndꢀCycle:ꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
Xꢀ
ROW/COLꢀ
NA/COLꢀ
Din
Din
EDOꢀPage-Mode(1,2)ꢀꢀ
Read-Writeꢀ
1stꢀCycle:ꢀ
2ndꢀCycle:ꢀ
Lꢀ
Lꢀ
H→Lꢀ H→Lꢀ H→Lꢀ L→Hꢀ
H→Lꢀ H→Lꢀ H→Lꢀ L→Hꢀ
ROW/COLꢀ
NA/COLꢀ
Dout,ꢀDin
Dout,ꢀDin
HiddenꢀRefreshꢀ
Read(2)ꢀ ꢀ
L→H→Lꢀ Lꢀ
L→H→Lꢀ Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Xꢀ
ROW/COLꢀ
ROW/COLꢀ
Dout
Dout
Write(1,3)ꢀ ꢀ
RAS-OnlyꢀRefreshꢀ
CBRꢀRefresh(4)ꢀ
Notes:
ꢀ
ꢀ
Lꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Xꢀ
Xꢀ
ROW/NAꢀ
Xꢀ
High-Z
High-Z
H→Lꢀ
1.ꢀ TheseꢀWRITEꢀcyclesꢀmayꢀalsoꢀbeꢀBYTEꢀWRITEꢀcyclesꢀ(eitherꢀLCAS or UCAS active).
2.ꢀ TheseꢀREADꢀcyclesꢀmayꢀalsoꢀbeꢀBYTEꢀREADꢀcyclesꢀ(eitherꢀLCAS or UCAS active).
3.ꢀ EARLYꢀWRITEꢀonly.
4. At least one of the two CAS signals must be active (LCAS or UCAS).
5. Commands valid only after proper initialization.
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 0A
3/29/2016
16ꢀaddressꢀbits.Theseꢀareꢀenteredꢀtenꢀbitsꢀ(A0-A9)ꢀatꢀꢀtime.ꢀ
IS41LV16100D
Functional Description
an internal 9-bit counter provides the row addresses
and the external address inputs are ignored.
TheꢀIS41LV16100DꢀisꢀaꢀCMOSꢀDRAMꢀoptimizedꢀforꢀhigh-
speed bandwidth, lowꢀpowerꢀapplications.ꢀDuringꢀREADꢀorꢀ
WRITEꢀcycles,ꢀeachꢀbitꢀisꢀuniquelyꢀaddressedꢀthroughꢀtheꢀ
CAS-before-RAS is a refresh-only mode and no data
accessꢀorꢀdeviceꢀselectionꢀisꢀallowed.ꢀThus,ꢀtheꢀoutputꢀ
TheꢀrowꢀaddressꢀisꢀlatchedꢀbyꢀtheꢀRowꢀAddressꢀStrobeꢀ
(RAS).ꢀTheꢀcolumnꢀaddressꢀisꢀlatchedꢀbyꢀtheꢀColumnꢀAd-
dress Strobe (CAS). RAS is used to latch the first nine bits
and CAS is used to latch the latter nine bits.
remainsꢀinꢀtheꢀHigh-Zꢀstateꢀduringꢀtheꢀcycle.
Self Refresh Cycle
ꢀTheꢀSelfꢀRefreshꢀallowsꢀtheꢀuserꢀaꢀdynamicꢀrefresh,ꢀdataꢀ
retention mode at the extended refresh period of 128 ms.
i.e.,ꢀ125ꢀµsꢀperꢀrowꢀwhenꢀusingꢀdistributedꢀCBRꢀrefreshes.ꢀ
Theꢀfeatureꢀalsoꢀallowsꢀtheꢀuserꢀtheꢀchoiceꢀofꢀaꢀfullyꢀstatic,ꢀ
lowꢀpowerꢀdataꢀretentionꢀmode.ꢀTheꢀoptionalꢀSelfꢀRefreshꢀ
featureꢀisꢀinitiatedꢀbyꢀperformingꢀaꢀCBRꢀRefreshꢀcycleꢀandꢀ
holding RASꢀꢀLOWꢀforꢀtheꢀspecifiedꢀtRAS.
TheꢀIS41LV16100DhastwoCAScontrols,LCASandUCAS.
TheꢀLCAS and UCAS inputs internally generates a CAS signal
functioning in an identical manner to the single CAS input on
theꢀotherꢀ1Mꢀxꢀ16ꢀDRAMs.ꢀTheꢀkeyꢀdifferenceꢀisꢀthatꢀeachꢀCAS
controlsꢀitsꢀcorrespondingꢀI/Oꢀtristateꢀlogicꢀ(in conjunction with
OE and WE and RAS). LCASꢀcontrolsꢀI/O0ꢀthroughꢀI/O7ꢀandꢀ
UCASꢀcontrolsꢀI/O8ꢀthroughꢀꢀI/O15.ꢀ
Theꢀ Selfꢀ Refreshꢀ modeꢀ isꢀ terminatedꢀ byꢀ drivingꢀ RAS
HIGHꢀforꢀaꢀminimumꢀtimeꢀofꢀtRP.ꢀThisꢀdelayꢀallowsꢀforꢀtheꢀ
completion of any internal refresh cycles that may be in
process at the time of the RASꢀLOW-to-HIGHꢀtransition.ꢀIfꢀ
theꢀDRAMꢀcontrollerꢀusesꢀaꢀdistributedꢀrefreshꢀsequence,ꢀ
aꢀburstꢀrefreshꢀisꢀnotꢀrequiredꢀuponꢀexitingꢀSelfꢀRefresh.
TheꢀIS41LV16100DꢀꢀCAS function is determined by the
first CAS (LCAS or UCAS)ꢀtransitioningꢀLOWꢀandꢀtheꢀlastꢀ
transitioningꢀbackꢀHIGH.ꢀTheꢀtwoꢀCAS controls give the
IS41LV16100Dꢀ BYTEꢀ READꢀ andꢀ BYTEꢀWRITEꢀ ꢀ cycleꢀ
capabilities.
However,ꢀifꢀtheꢀDRAMꢀcontrollerꢀutilizesꢀaꢀRAS-onlyorburst
refresh sequence, all 1,024 rows must be refreshed within
the average internal refresh rate, prior to the resumption
Memory Cycle
A memory cycle is initiated by bring RASꢀLOWꢀandꢀitꢀisꢀ
terminated by returning both RAS and CASꢀ HIGH.ꢀToꢀ
ensures proper device operation and data integrity any
memorycycle,onceinitiated,mustnotbeendedoraborted
before the minimum tras time has expired. A new cycle
must not be initiated until the minimum precharge time
trp, tcp has elapsed.
of normal operation.
Extended Data Out Page Mode
EDOꢀ pageꢀ modeꢀ operationꢀ permitsꢀ allꢀ 1,024ꢀ columnsꢀ
within a selected row to be randomly accessed at a high
data rate.
Read Cycle
InꢀEDOꢀpageꢀmodeꢀreadꢀcycle,ꢀtheꢀdata-outꢀisꢀheldꢀtoꢀtheꢀ
next CAS cycle’s falling edge, instead of the rising edge.
Forꢀthisꢀreason,ꢀtheꢀvalidꢀdataꢀoutputꢀtimeꢀinꢀEDOꢀpageꢀ
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the CASꢀcycleꢀtimeꢀbecomesꢀshorter.ꢀThere-
fore,ꢀinꢀEDOꢀpageꢀmode,ꢀtheꢀtimingꢀmarginꢀinꢀreadꢀcycleꢀ
is larger than that of the fast page mode even if the CAS
cycle time becomes shorter.
A read cycle is initiated by the falling edge of CAS or OE,
whicheveroccurslast,whileholdingWEꢀHIGH.Theꢀcolumnꢀ
address must be held for a minimum time specified by tar.
DataꢀOutꢀbecomesꢀvalidꢀonlyꢀwhenꢀtrac, taa, tcac and toea
are all satisfied. As a result, the access time is dependent
on the timing relationships between these parameters.
Write Cycle
InꢀEDOꢀpageꢀmode,ꢀdueꢀtoꢀtheꢀextendedꢀdataꢀfunction,ꢀ
the CAS cycle time can be shorter than in the fast page
mode if the timing margin is the same.
A write cycle is initiated by the falling edge of CAS and WE,
whicheverꢀoccursꢀlast.ꢀTheꢀinputꢀdataꢀmustꢀbeꢀvalidꢀatꢀorꢀ
beforethefallingedgeofCASorWE,whicheveroccursfirst.
TheꢀEDOꢀpageꢀmodeꢀallowsꢀbothꢀreadꢀandꢀwriteꢀoperationsꢀ
during one RAS cycle, but the performance is equivalent
to that of the fast page mode in that case.
Auto Refresh Cycle
Toꢀretainꢀdata,ꢀ1,024ꢀrefreshꢀcyclesꢀareꢀrequiredꢀinꢀeachꢀ
16ꢀmsꢀperiod.ꢀThereꢀareꢀtwoꢀwaysꢀtoꢀrefreshꢀtheꢀmemory.
Power-On
1. By clocking each of the 1,024 row addresses (A0 through
A9) with RAS at least once every tref max. Any read, write,
read-modify-writeorRAS-onlycyclerefreshestheaddressed
row.
Duringꢀ Power-On,ꢀ RAS, UCAS, LCAS, and WE must
all track with Vddꢀ (HIGH)ꢀ toꢀ avoidꢀ currentꢀ surges,ꢀ
and allow initialization to continue. An initial pause of
200 µs is required followed by a minimum of eight initial-
ization cycles (any combination of cycles containing a
RAS signal).
2. Using a CAS-before-RAS refresh cycle. CAS-before-
RASrefreshisactivatedbythefallingedgeofRAS,while
holding CASꢀLOW.ꢀInꢀCAS-before-RAS refresh cycle,
Integrated Silicon Solution, Inc. — www.issi.com
5
Rev. 0A
3/29/2016
IS41LV16100D
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Vt
Parameters
Rating
Unit
V
Voltage on Any Pin Relative to GND
Supply Voltage
–0.5 to +4.6
–0.5 to +4.6
50
Vdd
Iout
Pd
V
Output Current
mA
W
Power Dissipation
1
Ta
Industrial Temperature
Storage Temperature
–40 to +85
–55 to +125
°C
°C
Tstg
Note:
1.ꢀ StressꢀgreaterꢀthanꢀthoseꢀlistedꢀunderꢀABSOLUTEꢀMAXIMUMꢀRATINGSꢀmayꢀcauseꢀpermanentꢀdamageꢀtoꢀtheꢀdevice.ꢀThisꢀisꢀaꢀ
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sectionsꢀofꢀthisꢀspecificationꢀisꢀnotꢀimplied.ꢀExposureꢀtoꢀabsoluteꢀmaximumꢀratingꢀconditionsꢀforꢀextendedꢀperiodsꢀmayꢀaffectꢀreli-
ability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)
Symbol Parameter
Test Condition
Min.
3.0
Typ. Max.
Unit
Vdd
Vih
Vil
iil
Supply Voltage
3.3 3.6
V
InputꢀHighꢀVoltage
InputꢀLowꢀVoltage
InputꢀLeakageꢀCurrent
2.0
—
—
Vdd + 0.3 V
–0.3
–5
0.8
5
V
Any input 0V < Vin < Vdd
Otherꢀinputsꢀnotꢀunderꢀtestꢀ=ꢀ0V
Outputꢀisꢀdisabledꢀ(Hi-Z)
0V < Vout < Vdd
µA
iio
OutputꢀLeakageꢀCurrent
–5
5
µA
Voh
Vol
OutputꢀHighꢀVoltageꢀLevel ioh = –2.0 mA
OutputꢀLowꢀVoltageꢀLevel iol = 2.0 mA
2.4
—
—
V
V
0.4
CAPACITANCE(1,2)
Symbol
Parameter
Max.
5
7ꢀ
Unit
Cin1
Cin2
Input Capacitance: A0-A9
Input Capacitance: RAS, UCAS, LCAS, WE, OEꢀꢀ
DataꢀInput/OutputꢀCapacitance:ꢀI/O0-I/O15ꢀ
pF
pF
pF
Cioꢀ
7ꢀ
Notes:
1.ꢀ Testedꢀinitiallyꢀandꢀafterꢀanyꢀdesignꢀorꢀprocessꢀchangesꢀthatꢀmayꢀaffectꢀtheseꢀparameters.
2.ꢀ Testꢀconditions:ꢀꢀTaꢀ=ꢀ25°C,ꢀfꢀ=ꢀ1ꢀMHz.
6
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 0A
3/29/2016
IS41LV16100D
ELECTRICAL CHARACTERISTICS(1) (RecommendedꢀOperationꢀConditionsꢀunlessꢀotherwiseꢀnoted.)
Symbol
idd1
Parameter
Test Condition
Max. Unit
Stand-byꢀCurrent:ꢀTTL
Stand-byꢀCurrent:ꢀCMOS
OperatingꢀCurrent:ꢀ
RAS, LCAS, UCAS ≥ Vih
RAS, LCAS, UCAS ≥ Vdd – 0.2V
RAS, LCAS, UCAS,
2
mA
mA
mA
idd2
1
idd3
90
RandomꢀRead/Write(2,3,4)
Average Power Supply Current
OperatingꢀCurrent:ꢀ
Fast Page Mode(2,3,4)
Average Power Supply Current
RefreshꢀCurrent:
Address Cycling, trc = trc (min.)
idd4
idd5
idd6
RAS = Vil, LCAS, UCAS,
Cycling tpc = tpc (min.)
30
mA
mA
mA
RAS Cycling, LCAS, UCAS ≥ Vih 60
trc = trc (min.)
RAS-Only(2,3)
Average Power Supply Current
RefreshꢀCurrent:ꢀ
CBR(2,3,5)
RAS, LCAS, UCAS Cycling
trc = trc (min.)
60
Average Power Supply Current
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-OnlyꢀorꢀCBR)ꢀbeforeꢀproperꢀdeviceꢀ
operationꢀisꢀassured.ꢀꢀꢀTheꢀeightꢀRAS cycles wake-up should be repeated any time the tref refresh requirement is exceeded.
2.ꢀꢀDependentꢀonꢀcycleꢀrates.
3. Specified values are obtained with minimum cycle time and the output open.
4.ꢀꢀColumn-addressꢀisꢀchangedꢀonceꢀeachꢀEDOꢀpageꢀcycle.
5.ꢀꢀEnablesꢀon-chipꢀrefreshꢀandꢀaddressꢀcounters.
Integrated Silicon Solution, Inc. — www.issi.comꢀ
7
Rev. 0A
3/29/2016
IS41LV16100D
AC CHARACTERISTICS(1,2,3,4,5,6)
(RecommendedꢀOperatingꢀConditionsꢀunlessꢀotherwiseꢀnoted.)
-50
-60
Symbol
trcꢀ
Parameter
Min. Max.
Min. Max.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RandomꢀREADꢀorꢀWRITEꢀCycleꢀTimeꢀ
AccessꢀTimeꢀfromꢀRAS(6,ꢀ7)
AccessꢀTimeꢀfromꢀCAS(6, 8, 15)
AccessꢀTimeꢀfromꢀColumn-Address(6)
RASꢀPulseꢀWidthꢀ
85ꢀ
—
—
—
ꢀ
—ꢀ
50
14
25
110ꢀ ꢀ —ꢀ
tracꢀ
tcacꢀ
taaꢀ
—
—
—
60
15
30
tras
trp
50ꢀ ꢀ 10Kꢀ
30ꢀ —ꢀ
8ꢀ ꢀ 10Kꢀ
60ꢀ ꢀ 10Kꢀ
40ꢀ —ꢀ
10ꢀ ꢀ 10Kꢀ
RASꢀPrechargeꢀTimeꢀ
CASꢀPulseꢀWidth(26)
ꢀ
ꢀ
ꢀ
tcas
tcp
CASꢀPrechargeꢀTime(9, 25)
CASꢀHoldꢀTimeꢀ(21)
RAS to CASꢀDelayꢀTime(10, 20)
Row-AddressꢀSetupꢀTimeꢀ
Row-AddressꢀHoldꢀTimeꢀ
9
—
—
10
60
20ꢀ
0ꢀ
—
—
tcsh
trcd
tasrꢀ
trahꢀ
tascꢀ
tcahꢀ
tarꢀ
50
12ꢀ
0ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
37ꢀ
—ꢀ
—ꢀ
—
ꢀ
ꢀ
ꢀ
45ꢀ
—ꢀ
—ꢀ
—
8ꢀ
10ꢀ
0
Column-AddressꢀSetupꢀTime(20)
Column-AddressꢀHoldꢀTime(20)
0
8
—
10
40ꢀ
—
Column-AddressꢀHoldꢀTimeꢀ
30ꢀ
ꢀ
—ꢀ
ꢀ
—ꢀ
(referenced to RAS)
trad
tral
trpc
trsh
trhcp
tclz
RASꢀtoꢀColumn-AddressꢀDelayꢀTime(11)
Column-Address to RASꢀLeadꢀTimeꢀ
RAS to CASꢀPrechargeꢀTimeꢀ
RASꢀHoldꢀTime(27)
14
25ꢀ
5ꢀ
25
—ꢀ
—ꢀ
—
15
30ꢀ
5ꢀ
30
—ꢀ
—ꢀ
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ꢀ
ꢀ
ꢀ
ꢀ
14
37ꢀ
0
15
37ꢀ
0
RASꢀHoldꢀTimeꢀfromꢀCASꢀPrechargeꢀ
CASꢀtoꢀOutputꢀinꢀLow-Z(15, 29)
CAS to RASꢀPrechargeꢀTime(21)
OutputꢀDisableꢀTime(19, 28, 29)
ꢀ
—ꢀ
—
ꢀ
—ꢀ
—
tcrp
todꢀ
5
—
5
—
3
12
14
—ꢀ
—ꢀ
—ꢀ
—
3
12
15
—ꢀ
—ꢀ
—ꢀ
—
toe/toeaꢀ OutputꢀEnableꢀTime(15, 16)
—
15ꢀ
10ꢀ
5ꢀ
—
15ꢀ
10ꢀ
5ꢀ
toehc
toep
OEꢀHIGHꢀHoldꢀTimeꢀfromꢀCASꢀHIGHꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
OEꢀHIGHꢀPulseꢀWidthꢀ
toes
OEꢀLOWꢀtoꢀCASꢀHIGHꢀSetupꢀTimeꢀ
ReadꢀCommandꢀSetupꢀTime(17,ꢀ20)
trcsꢀ
trrhꢀ
0
0
ReadꢀCommandꢀHoldꢀTimeꢀ
0ꢀ
ꢀ
ꢀ
—ꢀ
0ꢀ
ꢀ
ꢀ
—ꢀ
(referenced to RAS)(12)
trchꢀ
ReadꢀCommandꢀHoldꢀTimeꢀ
0ꢀ
—ꢀ
0ꢀ
—ꢀ
ns
(referenced to CAS)(12,ꢀ17,ꢀ21)
twchꢀ
twcrꢀ
WriteꢀCommandꢀHoldꢀTime(17,ꢀ27)
8
—
10
—
ns
WriteꢀCommandꢀHoldꢀTimeꢀ
40ꢀ
ꢀ
—ꢀ
50ꢀ
ꢀ
—ꢀ
ns
(referenced to RAS)(17)
8
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 0A
3/29/2016
IS41LV16100D
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)
(RecommendedꢀOperatingꢀConditionsꢀunlessꢀotherwiseꢀnoted.)
-50
-60
Symbol Parameter
Min. Max.
Min. Max.
Units
ns
twpꢀ
WriteꢀCommandꢀPulseꢀWidth(17)
8
—
—ꢀ
—
—
—
—
—
10
10ꢀ
15
15
0
—
—ꢀ
—
—
—
—
—
twpz
trwlꢀ
tcwlꢀ
twcsꢀ
tdhrꢀ
WEꢀPulseꢀWidthsꢀtoꢀDisableꢀOutputsꢀ
WriteꢀCommandꢀtoꢀRASꢀLeadꢀTime(17)
WriteꢀCommandꢀtoꢀCASꢀLeadꢀTime(17,ꢀ21)
WriteꢀCommandꢀSetupꢀTime(14,ꢀ17,ꢀ20)
Data-inꢀHoldꢀTimeꢀ(referencedꢀtoꢀRAS)
10ꢀ
13
8
ꢀ
ꢀ
ns
ns
ns
0
ns
39
15
40
15
ns
tachꢀ
Column-AddressꢀSetupꢀTimeꢀtoꢀCAS precharge
ns
ꢀ
ꢀ
ꢀ
duringꢀWRITEꢀcycle
toeh
ꢀ
OEꢀHoldꢀTimeꢀfromꢀWE during
14
—
15
—
ns
READ-MODIFY-WRITEꢀcycle(18)
tdsꢀ
Data-InꢀSetupꢀTime(15, 22)
Data-InꢀHoldꢀTime(15, 22)
0
8
—
—
0
—
—
ns
ns
ns
ns
tdhꢀ
15
trwcꢀ
READ-MODIFY-WRITEꢀCycleꢀTimeꢀ
110ꢀ ꢀ —ꢀ
155ꢀ ꢀ —ꢀ
trwd
ꢀ
RAS to WEꢀDelayꢀTimeꢀduringꢀ
65ꢀ
ꢀ
—ꢀ
85ꢀ
ꢀ
—ꢀ
ꢀ
ꢀ
ꢀ
READ-MODIFY-WRITEꢀCycle(14)
tcwd
tawd
CAS to WEꢀDelayꢀTime(14, 20)
Column-Address to WEꢀDelayꢀTime(14)
26
40
30ꢀ
—
—
—ꢀ
40
55
40ꢀ
—
—
—ꢀ
ns
ns
ns
tpcꢀ
ꢀ
EDOꢀPageꢀModeꢀREADꢀorꢀWRITEꢀ
CycleꢀTime(24)
ꢀ
ꢀ
trasp
tcpaꢀ
RASꢀPulseꢀWidthꢀinꢀEDOꢀPageꢀModeꢀ
AccessꢀTimeꢀfromꢀCAS Precharge(15)
50ꢀ ꢀ 100Kꢀ
60ꢀ ꢀ 100Kꢀ
ns
ns
ns
—
30
—
35
tprwcꢀ
ꢀ
EDOꢀPageꢀModeꢀREAD-WRITEꢀ
CycleꢀTime(24)
56ꢀ
ꢀ
—ꢀ
56ꢀ
ꢀ
—ꢀ
tcohꢀ
toffꢀ
DataꢀOutputꢀHoldꢀafterꢀCASꢀLOWꢀ
5ꢀ
3ꢀ
ꢀ
ꢀ
—ꢀ
12ꢀ
5ꢀ
3ꢀ
ꢀ
ꢀ
—ꢀ
15ꢀ
ns
ns
OutputꢀBufferꢀTurn-OffꢀDelayꢀfromꢀ
CAS or RAS(13,15,19, 29)
twhzꢀ
OutputꢀDisableꢀDelayꢀfromꢀWE
3
10
—
3
15
—
ns
ns
tclchꢀ
ꢀ
LastꢀCASꢀgoingꢀLOWꢀtoꢀFirstꢀCAS
10
10
ꢀ
ꢀ
returningꢀHIGH(23)
tcsr
tchr
CASꢀSetupꢀTimeꢀ(CBRꢀREFRESH)(30, 20)
CASꢀHoldꢀTimeꢀ(CBRꢀREFRESH)(30, 21)
5
8
0
—
—
—
5
10
0
—
—
—
ns
ns
ns
tord
ꢀ
OEꢀSetupꢀTimeꢀpriorꢀtoꢀRAS during
HIDDENꢀREFRESHꢀCycle
twrp
twrh
trefꢀ
trefꢀ
tt
WEꢀSetupꢀTimeꢀ(CBRꢀRefresh)ꢀ
WEꢀHoldꢀTimeꢀ(CBRꢀRefresh)ꢀ
AutoꢀRefreshꢀPeriodꢀ(1,024ꢀCycles)ꢀ
SelfꢀRefreshꢀPeriodꢀ(1,024ꢀCycles)ꢀ
TransitionꢀTimeꢀ(RiseꢀorꢀFall)(2, 3)
5ꢀ
8ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
16ꢀ
5ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
16ꢀ
ns
ns
10ꢀ
—ꢀ
—ꢀ
ms
ms
ns
—ꢀ ꢀ 128ꢀ
50
—ꢀ ꢀ 128ꢀ
50
1
1
Note:
Theꢀ-60ꢀtimingꢀparametersꢀareꢀshownꢀforꢀreferenceꢀonly.ꢀTheꢀ-50ꢀspeedꢀoptionꢀsupportsꢀ50nsꢀandꢀ60nsꢀtimingꢀspecifications.
Integrated Silicon Solution, Inc. — www.issi.com
9
Rev. 0A
3/29/2016
17.ꢀWriteꢀcommandꢀisꢀdefinedꢀasꢀWE going low.
18.ꢀLATEꢀWRITEꢀandꢀREAD-MODIFY-WRITEꢀcyclesꢀmustꢀhaveꢀbothꢀtod and toeh met (OEꢀHIGHꢀduringꢀWRITEꢀcycle)ꢀinꢀorderꢀtoꢀ
ensureꢀthatꢀtheꢀoutputꢀbuffersꢀwillꢀbeꢀopenꢀduringꢀtheꢀWRITEꢀcycle.ꢀTheꢀI/OsꢀwillꢀprovideꢀtheꢀpreviouslyꢀwrittenꢀdataꢀifꢀCAS remains
LOWꢀandꢀOEꢀisꢀtakenꢀbackꢀtoꢀLOWꢀafterꢀtoeh is met.
19.ꢀTheꢀI/OsꢀareꢀinꢀopenꢀduringꢀREADꢀcyclesꢀonceꢀtod or toff occur.
20.ꢀTheꢀfirstꢀχCASꢀedgeꢀtoꢀtransitionꢀLOW.
21.ꢀTheꢀlastꢀχCASꢀedgeꢀtoꢀtransitionꢀHIGH.
22.ꢀTheseꢀparametersꢀareꢀreferencedꢀtoꢀCASꢀleadingꢀedgeꢀinꢀEARLYꢀWRITEꢀcyclesꢀandꢀWEꢀleadingꢀedgeꢀinꢀLATEꢀWRITEꢀorꢀREAD-
MODIFY-WRITEꢀcycles.
23.ꢀLastꢀfallingꢀχCAS edge to first rising χCAS edge.
24.ꢀLastꢀrisingꢀχCAS edge to next cycle’s last rising χCAS edge.
25.ꢀLastꢀrisingꢀχCAS edge to first falling χCAS edge.
26.ꢀEachꢀχCAS must meet minimum pulse width.
27.ꢀLastꢀχCASꢀtoꢀgoꢀLOW.
28.ꢀI/Osꢀcontrolled,ꢀregardlessꢀUCAS and LCAS.
29.ꢀTheꢀ3ꢀnsꢀminimumꢀisꢀaꢀparameterꢀguaranteedꢀbyꢀdesign.ꢀ
30.ꢀEnablesꢀon-chipꢀrefreshꢀandꢀaddressꢀcounters.
IS41LV16100D
AC TEST CONDITIONS
Output load: One TTL Load and 50 pF
Input timing reference levels:
Vih = 2.0V, Vil = 0.8V
Output timing reference levels: Voh = 2.4V, Vol = 0.4V
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-OnlyꢀorꢀCBR)ꢀbeforeꢀproperꢀdeviceꢀ
operationꢀisꢀassured.ꢀTheꢀeightꢀRAS cycles wake-up should be repeated any time the tref refresh requirement is exceeded.
2. Vih (MIN) and Vilꢀ(MAX)ꢀareꢀreferenceꢀlevelsꢀforꢀmeasuringꢀtimingꢀofꢀinputꢀsignals.ꢀTransitionꢀtimes,ꢀareꢀmeasuredꢀbetweenꢀVih
and Vil (or between Vil and Vih) and assume to be 1 ns for all inputs.
3. In addition to meeting the transition rate specification, all input signals must transit between Vih and Vil (or between Vil and Vih)
in a monotonic manner.
4. If CAS and RAS = Vih,ꢀdataꢀoutputꢀisꢀHigh-Z.
5. If CAS = Vil,ꢀdataꢀoutputꢀmayꢀcontainꢀdataꢀfromꢀtheꢀlastꢀvalidꢀREADꢀcycle.
ꢀ 6.ꢀMeasuredꢀwithꢀaꢀloadꢀequivalentꢀtoꢀoneꢀTTLꢀgateꢀandꢀ50ꢀpF.
ꢀ 7.ꢀAssumesꢀthatꢀtrcd ≤ trcdꢀ(MAX).ꢀIfꢀtrcd is greater than the maximum recommended value shown in this table, trac will increase
by the amount that trcd exceeds the value shown.
8. Assumes that trcd ≤ trcdꢀ(MAX).
9. If CASꢀisꢀLOWꢀatꢀtheꢀfallingꢀedgeꢀofꢀRAS,ꢀdataꢀoutꢀwillꢀbeꢀmaintainedꢀfromꢀtheꢀpreviousꢀcycle.ꢀToꢀinitiateꢀaꢀnewꢀcycleꢀandꢀclearꢀtheꢀ
data output buffer, CAS and RAS must be pulsed for tcp.
10.ꢀOperationꢀwithꢀtheꢀtrcdꢀ(MAX)ꢀlimitꢀensuresꢀthatꢀtracꢀ(MAX)ꢀcanꢀbeꢀmet.ꢀtrcdꢀ(MAX)ꢀisꢀspecifiedꢀasꢀaꢀreferenceꢀpointꢀonly;ꢀifꢀtrcd
is greater than the specified trcdꢀ(MAX)ꢀlimit,ꢀaccessꢀtimeꢀisꢀcontrolledꢀexclusivelyꢀbyꢀtcac.
11.ꢀOperationꢀwithinꢀtheꢀtradꢀ(MAX)ꢀlimitꢀensuresꢀthatꢀtrcdꢀ(MAX)ꢀcanꢀbeꢀmet.ꢀtradꢀ(MAX)ꢀisꢀspecifiedꢀasꢀaꢀreferenceꢀpointꢀonly;ꢀifꢀtrad
is greater than the specified trad (MAX)ꢀlimit,ꢀaccessꢀtimeꢀisꢀcontrolledꢀexclusivelyꢀbyꢀtaa.
12.ꢀEitherꢀtrch or trrhꢀmustꢀbeꢀsatisfiedꢀforꢀaꢀREADꢀcycle.
13. toffꢀ(MAX)ꢀdefinesꢀtheꢀtimeꢀatꢀwhichꢀtheꢀoutputꢀachievesꢀtheꢀopenꢀcircuitꢀcondition;ꢀitꢀisꢀꢀnotꢀaꢀreferenceꢀtoꢀVoh or Vol.
14. twcs, trwd, tawd and tcwdꢀareꢀrestrictiveꢀoperatingꢀparametersꢀinꢀLATEꢀWRITEꢀandꢀREAD-MODIFY-WRITEꢀcycleꢀonly.ꢀIfꢀtwcs ≤
twcsꢀ(MIN),ꢀtheꢀcycleꢀisꢀanꢀEARLYꢀWRITEꢀcycleꢀandꢀtheꢀdataꢀoutputꢀwillꢀremainꢀopenꢀcircuitꢀthroughoutꢀtheꢀentireꢀcycle.ꢀIfꢀtrwd ≤
trwd (MIN), tawd ≤ tawd (MIN) and tcwd ≤ tcwdꢀ(MIN),ꢀtheꢀcycleꢀisꢀaꢀREAD-WRITEꢀcycleꢀandꢀtheꢀdataꢀoutputꢀwillꢀcontainꢀdataꢀreadꢀ
fromꢀtheꢀselectedꢀcell.ꢀIfꢀneitherꢀofꢀtheꢀaboveꢀconditionsꢀisꢀmet,ꢀtheꢀstateꢀofꢀI/Oꢀ(atꢀaccessꢀtimeꢀandꢀuntilꢀCAS and RAS or OE go
back to Vih) is indeterminate. OEꢀheldꢀHIGHꢀandꢀWEꢀtakenꢀLOWꢀafterꢀCASꢀgoesꢀLOWꢀresultꢀinꢀaꢀLATEꢀWRITEꢀ(OE-controlled)
cycle.
15.ꢀOutputꢀparameterꢀ(I/O)ꢀisꢀreferencedꢀtoꢀcorrespondingꢀCASꢀinput,ꢀI/O0-I/O7ꢀbyꢀLCASꢀandꢀI/O8-I/O15ꢀbyꢀUCAS.
16.ꢀDuringꢀaꢀREADꢀcycle,ꢀifꢀOEꢀisꢀLOWꢀthenꢀtakenꢀHIGHꢀbeforeꢀCASꢀgoesꢀHIGH,ꢀI/Oꢀgoesꢀopen.ꢀIfꢀOEꢀisꢀtiedꢀpermanentlyꢀLOW,ꢀaꢀ
LATEꢀWRITEꢀorꢀREAD-MODIFY-WRITEꢀisꢀnotꢀpossible.
10
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 0A
3/29/2016
IS41LV16100D
READ CYCLE
tRC
t
RAS
t
RP
RAS
tCSH
t
RSH
t
RRH
tCRP
t
CAS CLCH
t
tRCD
UCAS/LCAS
t
AR
tRAD
tRAL
tASR
tRAH
tCAH
t
ASC
ADDRESS
Row
Column
Row
tRCS
t
RCH
WE
tAA
tRAC
(1)
OFF
tCAC
t
tCLC
Open
Open
Valid Data
I/O
tOE
tOD
OE
tOES
Undefined
Don’tꢀCare
Note:
1. toff is referenced from rising edge of RAS or CAS, whichever occurs last.
Integrated Silicon Solution, Inc. — www.issi.com
11
Rev. 0A
3/29/2016
IS41LV16100D
EARLY WRITE CYCLE (OEꢀ=ꢀDON'TꢀCARE)
t
RC
t
RAS
tRP
RAS
t
CSH
t
RSH
t
CRP
ASR
t
CAS CLCH
t
t
RCD
UCAS/LCAS
t
AR
t
RAD
t
t
t
RAL
CAH
ACH
t
t
RAH
t
ASC
ADDRESS
Row
Column
Row
t
t
CWL
RWL
t
WCR
tWCS
tWCH
t
WP
WE
t
DHR
t
DH
t
DS
I/O
Valid Data
Don’tꢀCare
12
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 0A
3/29/2016
IS41LV16100D
READ WRITE CYCLE (LATEꢀWRITEꢀandꢀREAD-MODIFY-WRITEꢀCycles)ꢀ
t
t
RWC
RAS
t
RP
RAS
t
CSH
t
RSH
t
CRP
ASR
t
CAS CLCH
t
t
RCD
UCAS/LCAS
tAR
t
RAD
tRAL
t
t
RAH
tCAH
tASC
tACH
ADDRESS
Row
Column
Row
t
RWD
tCWL
tRCS
tCWD
tRWL
tAWD
tWP
WE
tAA
t
RAC
tCAC
tCLZ
tDS
tDH
Open
Open
Valid DOUT
Valid DIN
I/O
tOD
tOEH
t
OE
OE
Undefined
Don’tꢀCare
Integrated Silicon Solution, Inc. — www.issi.com
13
Rev. 0A
3/29/2016
IS41LV16100D
EDO-PAGE-MODE READ CYCLE
t
RASP
t
RP
RAS
(1)
PC
t
CSH
t
t
RSH
t
CRP
t
CAS,
t
CP
t
CAS,
t
CP
t
CAS,
tCP
t
RCD
t
CLCH
t
CLCH
tCLCH
UCAS/LCAS
t
AR
t
RAD
tRAL
t
ASR
t
ASC
t
CAH
t
ASC
t
CAH
t
ASC
t
CAH
ADDRESS
Row
Column
Column
Column
Row
t
RAH
tRRH
t
RCS
t
RCH
WE
t
AA
t
AA
t
AA
t
RAC
CAC
CLZ
tCPA
t
CPA
t
t
t
CAC
t
t
CAC
CLZ
t
COH
t
OFF
Open
Open
Valid Data
Valid Data
Valid Data
I/O
t
OE
t
OEHC
tOE
tOD
t
OES
t
OD
t
OES
OE
t
OEP
Undefined
Don’tꢀCare
Note:
1. tpc can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both
measurements must meet the tpc specifications.
14
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 0A
3/29/2016
IS41LV16100D
EDO-PAGE-MODE EARLY-WRITE CYCLE
t
RASP
tRP
tRHCP
RAS
t
CSH
t
PC
t
RSH
tCRP
t
CAS,
t
CP
t
CAS,
t
CP
t
CAS,
tCP
tRCD
t
CLCH
t
CLCH
tCLCH
UCAS/LCAS
t
AR
tACH
t
ACH
tACH
t
RAD
t
RAL
t
ASR
tASC
t
CAH
t
ASC
tCAH
tASC
t
CAH
ADDRESS
Row
Column
Column
Column
Row
tRAH
t
CWL
WCS
WCH
t
CWL
tCWL
t
t
WCS
tWCS
t
tWCH
tWCH
t
WP
t
WP
tWP
WE
tWCR
tRWL
tDHR
tDS
tDS
tDS
t
DH
t
DH
tDH
I/O
Valid Data
Valid Data
Valid Data
OE
Don’tꢀCare
Integrated Silicon Solution, Inc. — www.issi.com
15
Rev. 0A
3/29/2016
IS41LV16100D
EDO-PAGE-MODE READ-WRITE CYCLEꢀ(LATEꢀWRITEꢀandꢀREAD-MODIFYꢀWRITEꢀCycles)
t
RASP
t
RP
RAS
(1)
tPC / tPRWC
t
CSH
tRSH
tCRP
t
RCD
t
CAS,
t
CLCH
t
CP
t
CAS,
t
CLCH
t
CP
t
CAS,
t
CLCH
tCP
UCAS/LCAS
t
AR
t
ASR
t
t
RAD
t
RAL
t
ASC
t
CAH
t
ASC
t
CAH
tASC
tCAH
RAH
ADDRESS
Row
Column
Column
Column
Row
t
RWD
t
t
RWL
CWL
t
RCS
t
CWL
WP
t
CWL
t
t
WP
t
WP
tAWD
tAWD
tAWD
t
CWD
t
CWD
tCWD
WE
t
AA
t
AA
CPA
t
AA
tCPA
t
t
RAC
t
DH
DS
t
DH
DS
t
DH
DS
t
t
t
t
CAC
CLZ
t
t
CAC
CLZ
t
t
CAC
CLZ
t
Open
Open
I/O
D
OUT
D
t
IN
DOUT
D
IN
DOUT
D
IN
OD
t
OD
t
OD
tOE
t
OE
tOE
tOEH
OE
Undefined
Don’tꢀCare
Note:
1. tpc can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both
measurements must meet the tpc specifications.
16
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 0A
3/29/2016
IS41LV16100D
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (PseudoꢀREAD-MODIFYꢀWRITE)
t
RASP
t
RP
RAS
t
CSH
tPC
tPC
tRSH
tCRP
t
RCD
t
CAS
t
CP
t
CAS
tCP
t
CAS
tCP
UCAS/LCAS
t
AR
t
ACH
RAL
CAH
tASR
t
RAD
t
t
ASC
t
CAH
t
ASC
t
CAH
tASC
t
tRAH
ADDRESS
Row
Column (A)
Column (B)
Column (N)
Row
t
RCS
t
RCH
t
WCS
tWCH
WE
t
WHZ
t
AA
t
AA
t
CPA
CAC
COH
t
RAC
tCAC
t
t
tDS
tDH
Open
Open
I/O
Valid Data (A)
Valid Data (B)
DIN
tOE
OE
Don’tꢀCare
Integrated Silicon Solution, Inc. — www.issi.comꢀ
17
Rev. 0A
3/29/2016
IS41LV16100D
AC WAVEFORMS
READ CYCLE (WithꢀWE-ControlledꢀDisable)
RAS
t
CSH
t
CRP
ASR
t
RCD
tCP
tCAS
UCAS/LCAS
t
AR
t
RAD
t
t
RAH
t
CAH
tASC
tASC
ADDRESS
Row
Column
Column
t
RCS
t
RCS
tRCH
t
WPZ
WE
tAA
t
RAC
t
t
CAC
CLZ
tWHZ
tCLZ
Open
Open
Valid Data
I/O
t
OE
tOD
OE
Undefined
Don’tꢀCare
RAS-ONLY REFRESH CYCLE (OE, WEꢀ=ꢀDON'TꢀCARE)
tRC
t
RAS
tRP
RAS
tCRP
t
RPC
UCAS/LCAS
tASR
tRAH
ADDRESS
I/O
Row
Row
Open
Don’tꢀCare
18
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 0A
3/29/2016
IS41LV16100D
CBR REFRESH CYCLE (Addresses; OEꢀ=ꢀDON'TꢀCARE)
tRP
tRAS
t
RP
tRAS
RAS
tCHR
tCHR
t
RPC
tRPC
t
CP
tCSR
tCSR
UCAS/LCAS
Open
I/O
WE
tWRH
t
WRP
t
WRH
t
WRP
HIDDEN REFRESH CYCLE(1) (WEꢀ=ꢀHIGH;ꢀOEꢀ=ꢀLOW)
t
RAS
tRAS
t
RP
RAS
t
CRP
tRCD
tRSH
tCHR
UCAS/LCAS
t
AR
tRAD
t
RAL
t
ASR
t
RAH
tCAH
tASC
ADDRESS
Row
Column
t
AA
tRAC
(2)
OFF
t
tCAC
tCLZ
Open
Open
Valid Data
I/O
tOE
tOD
tORD
OE
Undefined
Don’tꢀCare
Notes:
1.ꢀ AꢀHiddenꢀRefreshꢀmayꢀalsoꢀbeꢀperformedꢀafterꢀaꢀWriteꢀCycle.ꢀInꢀthisꢀcase,ꢀWEꢀ=ꢀLOWꢀandꢀOEꢀ=ꢀHIGH.
2. toff is referenced from rising edge of RAS or CAS, whichever occurs last.
Integrated Silicon Solution, Inc. — www.issi.com
19
Rev. 0A
3/29/2016
IS41LV16100D
ORDERING INFORMATION :
Industrial Range: -40oC to +85oC
Speed (ns)
Order Part No.
Package
IS41LV16100D-50KI
IS41LV16100D-50KLI
50
400-milꢀSOJ
400-milꢀSOJ,ꢀLead-free
400-mil TSOP (Type II)
400-mil TSOP (Type II), Lead-free
IS41LV16100D-50TI
IS41LV16100D-50TLI
Note:
Theꢀ-50ꢀspeedꢀoptionꢀsupportsꢀ50nsꢀandꢀ60nsꢀtimingꢀspecifications.
20
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 0A
3/29/2016
IS41LV16100D
Integrated Silicon Solution, Inc. — www.issi.com
21
Rev. 0A
3/29/2016
IS41LV16100D
22
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 0A
3/29/2016
相关型号：
©2020 ICPDF网 联系我们和版权申明