IS41LV8205-50J [ISSI]
2M x 8 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE; 2M ×8 （ 16兆位）动态RAM具有快速页面模式
| 型号： | IS41LV8205-50J |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 2M x 8 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE |
| 文件： | 总17页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
IS41C8205
IS41LV8205
2M x 8 (16-MBIT) DYNAMIC RAM
WITH FAST PAGE MODE
ISSI
JUNE, 2001
FEATURES
DESCRIPTION
• Fast Page Mode Access Cycle
• TTL compatible inputs and outputs
• Refresh Interval:
-- 2,048 cycles/32 ms
• Refresh Mode: RAS-Only,
TheISSI IS41C8205andIS41LV8205are2,097,152x8-bithigh-
performance CMOS Dynamic Random Access Memory.
The Fast Page Mode allows 2,048 random accesses
within a single row with access cycle time as short as 20
ns per 4-bit word.
CAS-before-RAS (CBR), and Hidden
• Single power supply:
5V 10ꢀ or 3.3V 10ꢀ
• Byte Write and Byte Read operation via two CAS
These features make the IS41C8205 and IS41LV8205
ideally suited for high-bandwidth graphics, digital signal
processing, high-performance computing systems, and
peripheral applications.
The IS41C8205 and IS41LV8205 are packaged in 28-pin
300-mil SOJ and 28-pin TSOP (Type II) with JEDEC
standard pinouts.
• Industrial temperature range -40°C to 85°C
PRODUCT SERIES OVERVIEW
KEY TIMING PARAMETERS
Part No.
Refresh
2K
Voltage
5V 10ꢀ
3.3V 10ꢀ
IS41C8205
IS41LV8205
Parameter
-50
50
13
25
20
84
-60
60
Unit
ns
2K
RAS Access Time (tRAC)
CAS Access Time (tCAC)
ColumnAddressAccessTime(tAA
15
ns
)
30
ns
FastPageModeCycleTime(tPC
)
25
ns
PIN CONFIGURATION
28 Pin SOJ, TSOP (Type II)
Read/Write Cycle Time (tRC)
104
ns
VCC
I/O0
I/O1
I/O2
I/O3
WE
RAS
NC
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
2
I/O7
I/O6
I/O5
I/O4
CAS
OE
A9
3
PIN DESCRIPTIONS
4
5
A0-A10
I/O0-7
WE
Address Inputs
6
Data Inputs/Outputs
Write Enable
7
8
OE
Output Enable
Row Address Strobe
Column Address Strobe
Power
A10
A0
9
A8
10
11
12
13
14
A7
RAS
CAS
Vcc
A1
A6
A2
A5
A3
A4
GND
NC
Ground
VCC
GND
No Connection
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
1
Rev. B
06/24/2001
IS41C8205
IS41LV8205
®
ISSI
FUNCTIONAL BLOCK DIAGRAM
OE
WE
WE
CONTROL
LOGIC
OE
CONTROL
LOGIC
CAS
CONTROL
LOGIC
CAS
CAS
WE
OE
RAS
DATA I/O BUS
RAS
RAS
CLOCK
GENERATOR
COLUMN DECODER
SENSE AMPLIFIERS
REFRESH
COUNTER
I/O0-I/O7
MEMORY ARRAY
2,097,152 x 8
ADDRESS
BUFFERS
A0-A10
TRUTHTABLE
Function
Standby
Read
RAS
CAS
WE
X
OE
X
Address tR/tC
X
I/O
High-Z
DOUT
H
L
L
L
H
L
L
L
H
L
ROW/COL
ROW/COL
ROW/COL
Write: Word (Early Write)
Read-Write
L
X
DIN
H→L
L→H
DOUT, DIN
Hidden Refresh Read
Write(1)
L→H→L
L→H→L
L
L
H
L
L
X
ROW/COL
ROW/COL
DOUT
DOUT
RAS-Only Refresh
L
H
L
X
X
X
X
ROW/NA
X
High-Z
High-Z
CBR Refresh
H→L
Note:
1. EARLY WRITE only.
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
06/24/01
IS41C8205
IS41LV8205
®
ISSI
Functional Description
Auto Refresh Cycle
The IS41C8205 and IS41LV8205 are CMOS DRAMs
optimizedforhigh-speedbandwidth, lowpowerapplications.
During READ or WRITE cycles, each bit is uniquely
addressed through the 11 address bits. These are entered
11 bits (A0-A10) at a time. The row address is latched by
the Row Address Strobe (RAS). The column address is
latched by the Column Address Strobe (CAS). RAS is
used to latch the first nine bits and CAS is used the latter
ten bits.
To retain data, 2,048 refresh cycles are required in each
32 ms period. There are two ways to refresh the memory:
1. By clocking each of the 2,048 row addresses (A0
through A10) with RAS at least once every 32 ms. Any
read,write,read-modify-writeorRAS-onlycyclerefreshes
the addressed row.
2. UsingaCAS-before-RAS refreshcycle.CAS-before-RAS
refresh is activated by the falling edge of RAS, while
holding CAS LOW. In CAS-before-RAS refresh cycle,
an internal 9-bit counter provides the row addresses
and the external address inputs are ignored.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum tRAS time has expired. A new
cycle must not be initiated until the minimum precharge
time tRP, tCP has elapsed.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Power-On
After application of the VCC supply, an initial pause of
200 µs is required followed by a minimum of eight
initialization cycles (any combination of cycles contain-
ing a RAS signal).
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The
columnaddressmustbeheldforaminimumtimespecified
by tAR. Data Out becomes valid only when tRAC, tAA, tCAC
and tOEA are all satisfied. As a result, the access time is
dependent on the timing relationships between these
parameters.
During power-on, it is recommended that RAS track with
VCC or be held at a valid VIH to avoid current surges.
Write Cycle
A write cycle is initiated by the falling edge of CAS and
WE, whichever occurs last. The input data must be valid
at or before the falling edge of CAS or WE, whichever
occurs last.
Integrated Silicon Solution, Inc. — 1-800-379-4774
3
Rev. B
06/24/01
IS41C8205
IS41LV8205
®
ISSI
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Parameters
Rating
Unit
VT
Voltage on Any Pin Relative to GND
5V
3.3V
–1.0 to +7.0
–0.5 to +4.6
V
VCC
Supply Voltage
5V
3.3V
–1.0 to +7.0
–0.5 to +4.6
V
IOUT
PD
Output Current
50
1
mA
W
Power Dissipation
TA
Commercial Operation Temperature
Industrial Operation Temperature
0 to +70
-40 to +85
°C
TSTG
Storage Temperature
–55 to +125
°C
Note:
1. StressgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGSmaycausepermanentdamagetothedevice.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated
intheoperationalsectionsofthisspecificationisnotimplied.Exposuretoabsolutemaximumratingconditionsforextended
periodsmayaffectreliability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)
Symbol
Parameter
Min.
Typ.
Max.
Unit
VCC
Supply Voltage
5V
3.3V
4.5
3.0
5.0
3.3
5.5
3.6
V
VIH
VIL
TA
Input High Voltage
Input Low Voltage
5V
3.3V
5V
3.3V
2.4
2.0
–1.0
–0.3
0
-40
—
—
—
—
—
—
VCC + 1.0
VCC + 0.3
V
V
0.8
0.8
70
85
Commercial Ambient Temperature
Industrial Ambient Temperature
°C
°C
CAPACITANCE(1,2)
Symbol
Parameter
Max.
Unit
CIN1
CIN2
CIO
Input Capacitance: A0-A10(A11)
Input Capacitance: RAS, CAS, WE, OE
Data Input/Output Capacitance: I/O0-I/O3
5
7
7
pF
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
06/24/01
IS41C8205
IS41LV8205
®
ISSI
ELECTRICALCHARACTERISTICS(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
VCC
Speed Min. Max. Unit
IIL
Input Leakage Current
Any input 0V ≤ VIN ≤ Vcc
–5
–5
2.4
—
5
µA
µA
V
Other inputs not under test = 0V
IIO
Output Leakage Current
OutputHighVoltageLevel
OutputLowVoltageLevel
Standby Current: TTL
Output is disabled (Hi-Z)
0V ≤ VOUT ≤ Vcc
5
VOH
VOL
ICC1
IOH = –5.0 mA, Vcc = 5V
IOH = –2.0 mA, Vcc = 3.3V
—
0.4
IOL = 4.2 mA, Vcc = 5V
IOL = 2 mA, Vcc = 3.3V
V
RAS, CAS ≥ VIH Commercial
5V
3.3V
5V
2
0.5
3
mA
—
—
—
Industrial
3.3V
2
ICC2
ICC3
Standby Current: CMOS
RAS, CAS ≥ VCC – 0.2V
5V
3.3V
—
—
1
0.5
mA
mA
Operating Current:
RAS, CAS,
Address Cycling, tRC = tRC (min.)
-50
-60
—
—
120
110
Random Read/Write(2,3)
AveragePowerSupplyCurrent
ICC4
ICC5
Operating Current:
RAS= VIL, CAS ≥ VIH
-50
-60
—
—
90
80
mA
mA
mA
Fast Page Mode(2,3,4)
AveragePowerSupplyCurrent
tRC = tRC (min.)
Refresh Current:
RAS Cycling, CAS ≥ VIH
tRC = tRC (min.)
-50
-60
—
—
120
110
RAS-Only(2,3)
AveragePowerSupplyCurrent
ICC6
Refresh Current:
CBR(2,3,5)
RAS, CAS Cycling
tRC = tRC (min.)
-50
-60
—
—
120
110
AveragePowerSupplyCurrent
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each Fast Page cycle.
5. Enables on-chip refresh and address counters.
Integrated Silicon Solution, Inc. — 1-800-379-4774
5
Rev. B
06/24/01
IS41C8205
IS41LV8205
®
ISSI
ACCHARACTERISTICS(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-50
-60
Symbol
Parameter
Min.
Max.
Min.
Max.
Units
tRC
Random READ or WRITE Cycle Time
Access Time from RAS(6, 7)
Access Time from CAS(6, 8, 15)
Access Time from Column-Address(6)
RAS Pulse Width
84
—
—
—
50
30
8
—
50
13
25
10K
—
104
—
—
—
60
40
10
9
—
60
15
30
10K
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRAC
tCAC
tAA
tRAS
tRP
RAS Precharge Time
CAS Pulse Width(23)
CAS Precharge Time(9)
CAS Hold Time (21)
RAS to CAS Delay Time(10, 20)
Row-Address Setup Time
Row-Address Hold Time
Column-Address Setup Time(20)
Column-Address Hold Time(20)
tCAS
tCP
10K
—
10K
—
9
tCSH
tRCD
tASR
tRAH
tASC
tCAH
tAR
38
12
0
—
40
14
0
—
37
—
45
—
8
—
10
0
—
0
—
—
8
—
10
40
—
Column-Address Hold Time
30
—
—
(referenced to RAS)
tRAD
tRAL
tRPC
tRSH
tRHCP
tCLZ
tCRP
tOD
RAS to Column-Address Delay Time(11)
Column-Address to RAS Lead Time
RAS to CAS Precharge Time
RAS Hold Time
10
25
5
25
—
—
—
—
—
—
15
12
—
—
—
—
—
—
12
30
5
30
—
—
—
—
—
—
15
15
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
10
35
0
RAS Hold Time from CAS Precharge
CAS to Output in Low-Z(15, 24)
CAS to RAS Precharge Time(21)
Output Disable Time(19, 24)
30
0
5
5
3
3
tOE
Output Enable Time(15, 16)
—
12
5
—
15
5
tOED
tOEHC
tOEP
tOES
tRCS
tRRH
Output Enable Data Delay (Write)
OE HIGH Hold Time from CAS HIGH
OE HIGH Pulse Width
10
5
10
5
OE LOW to CAS HIGH Setup Time
Read Command Setup Time(17, 20)
0
0
Read Command Hold Time
0
0
(referenced to RAS)(12)
tRCH
Read Command Hold Time
0
—
0
—
ns
(referenced to CAS)(12, 17, 21)
tWCH
tWCR
Write Command Hold Time(17)
8
—
—
10
50
—
—
ns
ns
Write Command Hold Time
40
(referenced to RAS)(17)
tWP
Write Command Pulse Width(17)
8
7
—
—
10
7
—
—
ns
ns
tWPZ
WE Pulse Widths to Disable Outputs
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
06/24/01
IS41C8205
IS41LV8205
®
ISSI
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-50
-60
Symbol
tRWL
Parameter
Min.
13
8
Max.
—
Min.
15
10
0
Max.
—
Units
ns
Write Command to RAS Lead Time(17)
Write Command to CAS Lead Time(17, 21)
Write Command Setup Time(14, 17, 20)
Data-in Hold Time (referenced to RAS)
tCWL
—
—
ns
tWCS
0
—
—
ns
tDHR
39
15
—
39
15
—
ns
tACH
Column-Address Setup Time to CAS
—
—
ns
Precharge during WRITE Cycle
tOEH
OE Hold Time from WE during
8
—
10
—
ns
READ-MODIFY-WRITE cycle(18)
tDS
Data-In Setup Time(15, 22)
Data-In Hold Time(15, 22)
READ-MODIFY-WRITE Cycle Time
0
8
108
64
—
—
—
—
0
10
133
77
—
—
—
—
ns
ns
ns
ns
tDH
tRWC
tRWD
RAS to WE Delay Time during
READ-MODIFY-WRITE Cycle(14)
tCWD
tAWD
tPC
CAS to WE Delay Time(14, 20)
26
39
20
—
—
—
32
47
25
—
—
—
ns
ns
ns
Column-Address to WE Delay Time(14)
Fast Page Mode READ or WRITE
Cycle Time
tRASP
tCPA
RAS Pulse Width
50
—
56
5
100K
30
—
—
12
60
—
68
5
100K
35
—
—
15
ns
ns
ns
ns
ns
Access Time from CAS Precharge(15)
READ-WRITE Cycle Time(24)
Data Output Hold after CAS LOW
tPRWC
tCOH
tOFF
Output Buffer Turn-Off Delay from
0
0
CAS or RAS(13,15,19, 24)
tWHZ
tCSR
tCHR
tORD
Output Disable Delay from WE
3
5
8
0
10
—
—
—
3
5
10
0
10
—
—
—
ns
ns
ns
ns
CAS Setup Time (CBR REFRESH)(20, 25)
CAS Hold Time (CBR REFRESH)( 21, 25)
OE Setup Time prior to RAS during
HIDDEN REFRESH Cycle
tREF
tT
Auto Refresh Period
2,048 Cycles
—
1
32
50
—
1
32
50
ms
ns
Transition Time (Rise or Fall)(2, 3)
AC TEST CONDITIONS
Output load: Two TTL Loads and 50 pF (Vcc = 5.0V 10ꢀ)
One TTL Load and 50 pF (Vcc = 3.3V 10ꢀ)
Input timing reference levels: VIH = 2.4V, VIL = 0.8V (Vcc = 5.0V 10ꢀ)ꢁ
VIH = 2.0V, VIL = 0.8V (Vcc = 3.3V 10ꢀ)
Output timing reference levels: VOH = 2.0V, VOL = 0.8V (Vcc = 5V 10ꢀ, 3.3V 10ꢀ)
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
Rev. B
06/24/01
IS41C8205
IS41LV8205
®
ISSI
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH and
VIL (or between VIL and VIH) and assume to be 1 ns for all inputs.
3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a
monotonicmanner.
4. If CAS and RAS = VIH, data output is High-Z.
5. If CAS = VIL, data output may contain data from the last valid READ cycle.
6. Measured with a load equivalent to one TTL gate and 50 pF.
7. AssumesthattRCD - tRCD (MAX). IftRCD isgreaterthanthemaximumrecommendedvalueshowninthistable, tRAC willincreasebythe
amount that tRCD exceeds the value shown.
8. Assumes that tRCD • tRCD (MAX).
9. IfCAS isLOWatthefallingedgeofRAS, dataoutwillbemaintainedfromthepreviouscycle. Toinitiateanewcycleandclearthedata
output buffer, CAS and RAS must be pulsed for tCP.
10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point onlyꢁ if tRCD is
greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC.
11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point onlyꢁ if tRAD is
greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA.
12. Either tRCH or tRRH must be satisfied for a READ cycle.
13. tOFF (MAX) defines the time at which the output achieves the open circuit conditionꢁ it is not a reference to VOH or VOL.
14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS • tWCS
(MIN),thecycleisanEARLYWRITEcycleandthedataoutputwillremainopencircuitthroughouttheentirecycle.IftRWD •tRWD (MIN),
tAWD •tAWD (MIN)andtCWD •tCWD (MIN), thecycleisaREAD-WRITEcycleandthedataoutputwillcontaindatareadfromtheselected
cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to VIH) is
indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle.
15. Output parameter (I/O) is referenced to corresponding CAS input.
16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE
WRITE or READ-MODIFY-WRITE is not possible.
17. Write command is defined as WE going low.
18. LATEWRITEandREAD-MODIFY-WRITEcyclesmusthavebothtOD andtOEH met(OE HIGHduringWRITEcycle)inordertoensure
thattheoutputbufferswillbeopenduringtheWRITEcycle. TheI/OswillprovidethepreviouslywrittendataifCAS remainsLOWand
OE is taken back to LOW after tOEH is met.
19. The I/Os are in open during READ cycles once tOD or tOFF occur.
20. Determined by falling edge of CAS.
21. Determined by rising edge of CAS.
22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or
READ-MODIFY-WRITE cycles.
23. CAS must meet minimum pulse width.
24. The 3 ns minimum is a parameter guaranteed by design.
25. Enables on-chip refresh and address counters.
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
06/24/01
IS41C8205
IS41LV8205
®
ISSI
READCYCLE
tRC
tRAS
tRP
RAS
tCSH
tRSH
tCAS tCLCH
tRRH
tCRP
tASR
tRCD
tASC
CAS
tAR
tRAD
tRAH
tRAL
tCAH
ADDRESS
WE
Row
Column
Row
tRCS
tRCH
tAA
tRAC
(1)
tOFF
tCAC
tCLC
Open
Open
Valid Data
I/O
OE
tOE
tOD
tOES
Don’t Care
Note:
1. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
Integrated Silicon Solution, Inc. — 1-800-379-4774
9
Rev. B
06/24/01
IS41C8205
IS41LV8205
®
ISSI
READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE CYCLES)
t
t
RWC
RAS
t
RP
RAS
CAS
t
CSH
t
RSH
t
CRP
ASR
t
CAS CLCH
t
t
RCD
t
AR
t
RAD
tRAL
t
t
RAH
tCAH
t
ASC
tACH
ADDRESS
WE
Row
Column
Row
t
RWD
tCWL
tRCS
t
CWD
t
RWL
t
AWD
t
WP
tAA
tRAC
t
t
CAC
CLZ
t
DS
tDH
Open
Open
Valid DOUT
Valid DIN
I/O
OE
tOD
tOEH
t
OE
Don’t Care
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
06/24/01
IS41C8205
IS41LV8205
®
ISSI
EARLY WRITE CYCLE (OE = DON'T CARE)
t
RC
t
RAS
tRP
RAS
tCSH
tRSH
t
CRP
ASR
t
CAS CLCH
t
t
RCD
CAS
t
AR
t
RAD
t
t
t
RAL
CAH
ACH
t
t
RAH
t
ASC
ADDRESS
Row
Column
Row
t
t
CWL
RWL
t
WCR
t
WCS
tWCH
t
WP
WE
I/O
t
t
DHR
t
DH
DS
Valid Data
Don’t Care
Integrated Silicon Solution, Inc. — 1-800-379-4774
11
Rev. B
06/24/01
IS41C8205
IS41LV8205
®
ISSI
FAST-PAGE-MODE READ CYCLE
t
RASP
t
RP
RAS
t
CSH
t
PRWC
t
t
RSH
CAS
t
CAS
t
CAS
tCRP
t
RCD
t
CRP
t
CP
tCP
CAS
t
CPWD
RAL
t
AR
t
CPWD
t
t
RAD
t
CAH
t
CAH
tCAH
tRAH
t
ASC
tASC
t
ASC
t
ASR
ADDRESS
Row
Column
Column
Column
t
RCS
WE
OE
t
AA
t
AA
tAA
t
CAC
t
CAC
tCAC
t
OE
tOE
tOE
tRAC
tOED
tOED
tOED
t
CLZ
t
CLZ
tCLZ
I/O
OUT
OUT
OUT
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
06/24/01
IS41C8205
IS41LV8205
®
ISSI
FAST-PAGE-MODE READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)
t
RASP
t
RP
RAS
CAS
t
CSH
t
PRWC
t
t
RSH
CAS
t
CAS
t
CAS
t
CRP
t
RCD
t
CRP
t
CP
tCP
t
CPWD
t
AR
t
CPWD
t
RAL
t
RAD
t
CAH
t
CAH
tCAH
t
RAH
t
ASC
tASC
t
ASC
t
ASR
ADDRESS
Row
Column
Column
Column
t
CWL
tCWL
tRWL
t
CWL
t
RWD
t
AWD
t
AWD
t
t
AWD
CWD
t
RCS
t
CWD
tCWD
t
WP
t
WP
tWP
WE
OE
t
AA
t
AA
tAA
t
CAC
t
CAC
tCAC
t
OEA
t
OEA
tOEA
t
OEZ
OED
t
OEZ
t
OEZ
OED
t
RAC
t
t
OED
t
t
DH
tDH
t
DH
CLZ
t
CLZ
t
DS
t
t
DS
t
CLZ
tDS
I/O
OUT
OUT
IN
IN
IN
OUT
Don’t Care
Integrated Silicon Solution, Inc. — 1-800-379-4774
13
Rev. B
06/24/01
IS41C8205
IS41LV8205
®
ISSI
FAST PAGE MODE EARLY WRITE CYCLE
t
RASP
t
RP
RAS
t
t
RHCP
RSH
CAS
t
CSH
t
PC
t
t
CAS
t
CAS
t
t
CRP
t
RCD
t
CRP
t
CP
t
CP
CAS
t
AR
RAL
t
RAD
t
CAH
t
CAH
tCAH
t
RAH
t
ASC
t
ASC
t
ASC
t
ASR
ADDRESS
Row
Column
Column
Column
t
t
CWL
WCH
t
CWL
WCH
CWL
WCH
t
WCS
t
WCS
t
t
WCS
t
t
t
WP
t
WP
tWP
WE
OE
t
WCR
t
DHR
t
DS
tDS
t
DS
t
DH
t
DH
tDH
Valid DIN
Valid DIN
Valid DIN
I/O
Don’t Care
14
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
06/24/01
IS41C8205
IS41LV8205
®
ISSI
RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE)
tRC
tRAS
tRP
RAS
CAS
tCRP
tRPC
tASR
tRAH
ADDRESS
I/O
Row
Row
Open
Don’t Care
Integrated Silicon Solution, Inc. — 1-800-379-4774
15
Rev. B
06/24/01
IS41C8205
IS41LV8205
®
ISSI
CBR REFRESH CYCLE (Addressesꢁ WE, OE = DON'T CARE)
t
RP
t
RAS
t
RP
tRAS
RAS
t
CHR
tCHR
t
RPC
CP
tRPC
t
t
CSR
tCSR
CAS
Open
I/O
Don’t Care
HIDDEN REFRESH CYCLE(1) (WE = HIGHꢁ OE = LOW)
tRAS
tRAS
t
RP
RAS
CAS
t
CRP
t
RCD
t
RSH
tCHR
t
AR
t
RAD
t
RAL
t
ASR
t
RAH
t
CAH
t
ASC
ADDRESS
Row
Column
t
AA
t
RAC
(2)
OFF
t
t
CAC
t
CLZ
Open
Open
Valid Data
I/O
t
OE
tOD
tORD
OE
Don’t Care
16
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
06/24/01
IS41C8205
IS41LV8205
®
ISSI
ORDERING INFORMATION
ORDERING INFORMATION
Commercial Range: 0°C to 70°C
Voltage: 5V
Industrial Range: -40°C to 85°C
Voltage: 5V
Speed (ns) Order Part No.
Package
Speed (ns) Order Part No.
Package
50
60
IS41C8205-50J
IS41C8205-60J
300-mil SOJ
300-mil SOJ
50
60
IS41C8205-50JI
IS41C8205-60JI
300-mil SOJ
300-mil SOJ
Voltage: 3.3V
Voltage: 3.3V
Speed (ns) Order Part No.
Package
Speed (ns) Order Part No.
Package
50
60
IS41LV8205-50J
IS41LV8205-60J
300-mil SOJ
300-mil SOJ
50
60
IS41LV8205-50JI
IS41LV8205-60JI
300-mil SOJ
300-mil SOJ
®
ISSI
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
Integrated Silicon Solution, Inc. — 1-800-379-4774
17
Rev. B
06/24/01
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