IS42LS32400AL-10BI [ISSI]
Synchronous DRAM, 4MX32, 7ns, CMOS, PBGA90, FBGA-90;
| 型号： | IS42LS32400AL-10BI |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Synchronous DRAM, 4MX32, 7ns, CMOS, PBGA90, FBGA-90 时钟 动态存储器 内存集成电路 |
| 文件： | 总66页 (文件大小：577K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS42S81600AL, IS42LS81600AL
IS42S16800AL, IS42LS16800AL
IS42S32400AL, IS42LS32400AL
16Meg x 8, 8Meg x16 & 4Meg x 32
128-MBIT LOW-POWER
SYNCHRONOUS DRAM
®
ISSI
PRELIMINARY INFORMATION
SEPTEMBER 2003
OVERVIEW
FEATURES
ISSI's 128Mb Low - Power Synchronous DRAM achieves
high-speed data transfer using pipeline architecture. All
inputs and outputs signals refer to the rising edge of the
clock input. The 128Mb SDRAM is organized as follows.
• Clock frequency: 133, 100, MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Internal bank for hiding row access/precharge
• Power supply
VDD
VDDQ
IS42LS81600AL
IS42S81600AL
4Mx8x4Banks
54-PinTSOPII
IS42LS16800AL
IS42S16800AL
2Mx16x4Banks
54-ball FBGA
IS42LS32400AL
IS42S32400AL
1Mx32x4Banks
90-ball FBGA
IS42LS81600AL
IS42LS16800AL
2.5V 1.8V (2.5V tolerant)
2.5V 1.8V (2.5V tolerant)
IS42LS32400AL
IS42S81600AL
2.5V 1.8V (2.5V tolerant)
3.3V 3.3V
54-pinTSOPII
86-pinTSOPII
IS42S16800AL
IS42S32400AL
3.3V 3.3V
3.3V 3.3V
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
KEY TIMING PARAMETERS
• Extended Mode Register
Parameter
-7
-10 Unit
• Programmable Power Reduction Feature by
partial array activation during Self-Refresh
Clk Cycle Time
CAS Latency = 3
CAS Latency = 2
7
10
10
10
ns
ns
• Auto Precharge and Auto refresh Modes
• Temp. Compensated Self Refresh.
Clk Frequency
CAS Latency = 3
CAS Latency = 2
133
100
100
100
Mhz
Mhz
• Self Refresh Mode: Standard and Low-Power
• 4096 refresh cycles every 64 ms
Access Time from Clock
CAS Latency = 3
5.4
6
7
9
ns
ns
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
CAS Latency = 2
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and Precharge
command
• Industrial Temperature Availability
• Lead-freeAvailability
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION, Rev. 00A
1
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
DEVICE OVERVIEW
nal banks to hide precharge time and the capability to
randomly change column addresses on each clock cycle
during burst access.
The 128Mb Low - Power SDRAM is a high speed CMOS,
dynamic random-access memory designed to operate in
2.5VVDD and1.8VVDDQ or3.3VVDD and3.3VVDDQ memory
systemscontaining134,217,728bits. Internallyconfigured
asaquad-bankDRAMwithasynchronousinterface. (Each
33,554,432-bit bank is organized as 4,096 rows by 512
columns by 16 bits.)
A self-timed row precharge initiated at the end of the burst
sequence is available with the AUTO PRECHARGE func-
tionenabled. Prechargeonebankwhileaccessingoneofthe
otherthreebankswillhidetheprechargecyclesandprovide
seamless,high-speed,random-accessoperation.
The 128Mb Low - Power SDRAM includes an AUTO RE-
FRESH MODE, and a power-saving, power-down mode.
All signals are registered on the positive edge of the clock
signal, CLK. All inputs and outputs are LVTTL compatible.
SDRAMreadandwriteaccessesareburstorientedstartingat
aselectedlocationandcontinuingforaprogrammednum-
ber of locations in a programmed sequence. The registra-
tionofanACTIVEcommandbeginsaccesses, followedby
a READ or WRITE command. The ACTIVE command in
conjunction with address bits registered are used to select
the bank and row to be accessed (BA0, BA1 select the
bank; A0-A11 select the row). The READ or WRITE
commands in conjunction with address bits registered are
used to select the starting column location for the burst
access.
Only partials of the memory array can be selected for Self-
Refresh and the refresh period during Self-Refresh is
programmablein4stepswhichdrasticallyreducestheself
refresh current, depending on the case temperature of the
components in the system application.
The128MbLow-PowerSDRAMhastheabilitytosynchro-
nouslyburstdataatahighdataratewithautomaticcolumn-
address generation, the ability to interleave between inter-
ProgrammableREADorWRITEburstlengthsconsistof1,
2, 4 and 8 locations or full page, with a burst terminate
option.
FUNCTIONAL BLOCK DIAGRAM (ONLY FOR 2MX16X4 BANKS)
CLK
CKE
CS
RAS
CAS
WE
DQML
DQMH
DATA IN
BUFFER
COMMAND
DECODER
&
CLOCK
GENERATOR
16
16
2
REFRESH
CONTROLLER
MODE
REGISTER
I/O 0-15
12
V
DD/VDDQ
ss/Vss
SELF
DATA OUT
BUFFER
REFRESH
V
Q
A10
A11
A9
CONTROLLER
16
16
A8
A7
A6
REFRESH
COUNTER
A5
A4
4096
A3
A2
A1
A0
BA0
BA1
4096
MEMORY CELL
ARRAY
4096
4096
12
BANK 0
ROW
ADDRESS
LATCH
ROW
ADDRESS
BUFFER
12
12
SENSE AMP I/O GATE
512
(x 16)
COLUMN
ADDRESS LATCH
BANK CONTROL LOGIC
9
BURST COUNTER
COLUMN DECODER
COLUMN
ADDRESS BUFFER
9
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
PIN CONFIGURATIONS
54-Pin TSOP - Type II for x8
V
DD
1
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
I/O0
2
I/O7
V
DD
Q
3
VSSQ
NC
4
NC
I/O6
I/O1
5
V
SS
Q
6
VDDQ
NC
I/O2
7
NC
I/O5
8
V
DD
Q
9
VSSQ
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
NC
I/O4
I/O3
V
SS
Q
VDDQ
NC
NC
V
DD
NC
WE
V
SS
NC
DQM
CLK
CKE
NC
A11
A9
CAS
RAS
CS
BA0
BA1
A10
A0
A8
A7
A1
A6
A2
A5
A3
A4
V
DD
VSS
PIN DESCRIPTIONS
A0-A11
A0-A9
BA0,BA1
I/O0toI/O15
CLK
Row Address Input
WE
WriteEnable
Column Address Input
Bank Select Address
Data I/O
DQM
VDD
x8LowerByte, Input/OutputMask
Power
Vss
VDDQ
VssQ
NC
Ground
System Clock Input
Clock Enable
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
CKE
CS
Chip Select
RAS
Row Address Strobe Command
Column Address Strobe Command
CAS
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
3
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
PIN CONFIGURATIONS
54-Ball FBGA for x16
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Vss
I/O14
I/O12
I/O10
I/O8
I/O15
I/O13
I/O11
I/O9
NC
VssQ
VDDQ
VssQ
VDDQ
Vss
VDDQ
VssQ
VDDQ
VssQ
VDD
CAS
BA0
I/O0
I/O2
I/O4
I/O6
DQML
RAS
BA1
A1
VDD
I/O1
I/O3
I/O5
I/O7
WE
DQMH
NC/A12
A8
CLK
A11
A7
CKE
A9
G
H
J
CS
A6
A0
A10
VDD
Vss
A5
A4
A3
A2
PIN DESCRIPTIONS
A0-A11
A0-A8
BA0,BA1
I/O0toI/O15
CLK
Row Address Input
Column Address Input
Bank Select Address
Data I/O
WE
WriteEnable
DQML
DQMH
VDD
x16 Lower Byte, Input/Output Mask
x16 Upper Byte, Input/Output Mask
Power
System Clock Input
Clock Enable
Vss
Ground
CKE
VDDQ
VssQ
NC
Power Supply for I/O Pin
Ground for I/O Pin
CS
Chip Select
RAS
Row Address Strobe Command
Column Address Strobe Command
NoConnection
CAS
4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
PIN CONFIGURATIONS
54-Pin TSOP - Type II for x16
V
DD
1
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
I/O0
2
I/O15
V
DD
Q
3
VSSQ
I/O1
I/O2
4
I/O14
I/O13
5
V
SS
Q
6
VDDQ
I/O3
I/O4
7
I/O12
I/O11
8
V
DD
Q
9
VSSQ
I/O5
I/O6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
I/O10
I/O9
V
SS
Q
VDDQ
I/O7
I/O8
V
DD
VSS
DQML
WE
CAS
RAS
CS
NC
DQMH
CLK
CKE
NC
A11
A9
BA0
BA1
A10
A0
A8
A7
A1
A6
A2
A5
A3
A4
V
DD
VSS
PIN DESCRIPTIONS
A0-A11
A0-A8
BA0,BA1
I/O0toI/O15
CLK
Row Address Input
WE
WriteEnable
Column Address Input
Bank Select Address
Data I/O
DQML
DQMH
VDD
x16 Lower Byte, Input/Output Mask
x16 Upper Byte, Input/Output Mask
Power
System Clock Input
Clock Enable
Vss
Ground
CKE
VDDQ
VssQ
NC
Power Supply for I/O Pin
Ground for I/O Pin
CS
Chip Select
RAS
Row Address Strobe Command
Column Address Strobe Command
NoConnection
CAS
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
5
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
PIN CONFIGURATIONS
86-Pin TSOP - Type II for x32
V
DD
1
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
VSS
I/O0
2
I/O15
V
DD
Q
3
VSSQ
I/O1
I/O2
4
I/O14
I/O13
5
V
SS
Q
6
VDDQ
I/O3
I/O4
7
I/O12
I/O11
8
V
DD
Q
9
VSSQ
I/O5
I/O6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
I/O10
I/O9
V
SS
Q
VDDQ
I/O7
NC
I/O8
NC
V
DD
VSS
DQM0
WE
DQM1
NC
CAS
RAS
CS
NC
CLK
CKE
A9
A11
BA0
BA1
A10
A0
A8
A7
A6
A5
A1
A4
A2
A3
DQM2
DQM3
VDD
VSS
NC
NC
I/O16
I/O31
V
SS
Q
VDDQ
I/O17
I/O18
I/O30
I/O29
V
DD
Q
VSSQ
I/O19
I/O20
I/O28
I/O27
V
SS
Q
VDDQ
I/O21
I/O22
I/O26
I/O25
V
DD
Q
VSSQ
I/O23
I/O24
V
DD
VSS
PIN DESCRIPTIONS
A10-A11
A0-A7
BA0,BA1
I/O0toI/O31
CLK
Row Address Input
WE
WriteEnable
Column Address Input
Bank Select Address
Data I/O
DQM0-DQM3
VDD
x32 Input/Output Mask
Power
Vss
Ground
System Clock Input
Clock Enable
VDDQ
Power Supply for I/O Pin
Ground for I/O Pin
NoConnection
CKE
VssQ
NC
CS
Chip Select
RAS
Row Address Strobe Command
Column Address Strobe Command
CAS
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
PIN CONFIGURATIONS
90-Ball FBGA for x32
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
I/O26
I/O28
VssQ
VssQ
VDDQ
Vss
I/O24
VDDQ
I/O27
I/O29
I/O31
DQM3
A5
Vss
VssQ
I/O25
I/O30
NC
VDD
VDDQ
I/O22
I/O17
NC
I/O23
VssQ
I/O20
I/O18
I/O16
DQM2
A0
I/O21
I/O19
VDDQ
VDDQ
VssQ
VDD
A3
A2
G
H
J
A4
A6
A10
A1
A7
A8
NC
NC
BA1
A11
CLK
CKE
NC
A9
BA0
CAS
VDD
I/O6
I/O1
VDDQ
VDD
CS
RAS
K
L
DQM1
VDDQ
VssQ
VssQ
I/O11
I/O13
NC
WE
DQM0
VssQ
VDDQ
VDDQ
I/O4
I/O8
Vss
I/O7
M
N
P
R
I/O10
I/O12
VDDQ
I/O15
I/O9
I/O14
VssQ
Vss
I/O5
I/O3
VssQ
I/O0
I/O2
PIN DESCRIPTIONS
WE
WriteEnable
A10-A11
A0-A7
BA0,BA1
I/O0toI/O31
CLK
Row Address Input
Column Address Input
Bank Select Address
Data I/O
DQM0-DQM3
VDD
x32 Input/Output Mask
Power
Vss
Ground
VDDQ
Power Supply for I/O Pin
Ground for I/O Pin
NoConnection
System Clock Input
Clock Enable
VssQ
NC
CKE
CS
Chip Select
RAS
Row Address Strobe Command
Column Address Strobe Command
CAS
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
7
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
PIN FUNCTIONS
Symbol
Type
Function (In Detail)
A0-A11
Input Pin
AddressInputs:A0-A11aresampledduringtheACTIVE
command(row-addressA0-A11)andREAD/WRITEcommand(A0-A9(x8);A0-A8
(x16); A0-A7 (x32)with A10 defining auto precharge) to select one location out of the
memoryarrayintherespectivebank. A10issampledduringaPRECHARGEcommand
to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0,
BA1 (A10 LOW). The address inputs also provide the op-code during a LOAD MODE
REGISTERcommand.
BA0, BA1
CAS
Input Pin
Input Pin
Input Pin
BankSelectAddress:BA0andBA1defineswhichbanktheACTIVE, READ, WRITEor
PRECHARGEcommandisbeingapplied.
CAS, inconjunctionwiththeRASand WE, formsthedevicecommand. Seethe
"CommandTruthTable"fordetailsondevicecommands.
CKE
TheCKEinputdetermineswhethertheCLKinputisenabled. Thenextrisingedgeofthe
CLKsignalwillbevalidwhenisCKEHIGHandinvalidwhenLOW. WhenCKEisLOW,
the device will be in either power-down mode, clock suspend mode, or self refresh
mode. CKE is an asynchronous input.
CLK
Input Pin
Input Pin
CLK is the master clock input for this device. Except for CKE, all inputs to this device
areacquiredinsynchronizationwiththerisingedgeofthispin.
CS
TheCSinputdetermineswhethercommandinputisenabledwithinthedevice.
Command input is enabled whenCSisLOW, anddisabledwithCSisHIGH. Thedevice
remains in the previous state when CS is HIGH.
DQML,
DQMH
Input Pin
DQML and DQMH control the lower and upper bytes of the I/O buffers. In read
mode,DQMLandDQMHcontroltheoutputbuffer. WhenDQMLorDQMHisLOW, the
correspondingbufferbyteisenabled, andwhenHIGH, disabled. Theoutputsgotothe
HIGH impedance state whenDQML/DQMH is HIGH. This function corresponds to OE
inconventionalDRAMs.Inwritemode,DQMLandDQMHcontroltheinputbuffer.
WhenDQML or DQMH is LOW, the corresponding buffer byte is enabled, and data can
be written to the device. WhenDQML or DQMH is HIGH, input data is masked and
cannot be written to the device.
DQM0-DQM3
DQM
Input Pin
Input Pin
Input Pin
For IS42S32400AL, IS42S32400AL only.
For IS42S81600AL, IS42S81600AL only.
RAS
RAS, in conjunction with CAS and WE, forms the device command. See the "Com-
mand Truth Table" item for details on device commands.
WE
Input Pin
WE, in conjunction with RAS and CAS, forms the device command. See the "Com-
mand Truth Table" item for details on device commands.
VDDQ
VDD
Power Supply Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
VDDQ is the output buffer power supply.
VDD is the device internal power supply.
VSSQ is the output buffer ground.
VSSQ
VSS
VSS is the device internal ground.
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
GENERAL DESCRIPTION
READ
burst mode. Upon completion of the READ or WRITE burst,
a precharge of the bank/row that is addressed is automati-
cally performed.
The READ command selects the bank from BA0, BA1
inputsandstartsaburstreadaccesstoanactiverow. Inputs
A0-A9(x8);A0-A8(x16);A0-A7(x32)providesthestarting
column location. When A10 is HIGH, this command func-
tionsasanAUTOPRECHARGEcommand. Whentheauto
precharge is selected, the row being accessed will be
precharged at the end of the READ burst. The row will
remain open for subsequent accesses when AUTO
PRECHARGE is not selected. DQ’s read data is subject
tothelogiclevelontheDQMinputstwoclocksearlier.When
agivenDQMsignalwasregisteredHIGH, thecorrespond-
ing DQ’s will be High-Z two clocks later. DQ’s will provide
valid data when the DQM signal was registered LOW.
AUTO REFRESH COMMAND
This command executes the AUTO REFRESH operation.
The row address and bank to be refreshed are automatically
generated during this operation. The stipulated period (tRC) is
required for a single refresh operation, and no other com-
mands can be executed during this period. This command is
executedatleast4096timesfor every64ms. DuringanAUTO
REFRESH command, address bits are “Don’t Care”. This
command corresponds to CBR Auto-refresh.
BURST TERMINATE
WRITE
The BURST TERMINATE command forcibly terminates the
burst read and write operations by truncating either fixed-
length or full-page bursts and the most recently registered
READ or WRITE command prior to the BURST TERMI-
NATE.
A burst write access to an active row is initiated with the
WRITE command. BA0, BA1 inputs selects the bank, and
the starting column location is provided by inputs A0-A9
(x8); A0-A8 (x16); A0-A7 (x32). Whether or not AUTO-
PRECHARGE is used is determined by A10.
The row being accessed will be precharged at the end of
the WRITE burst, if AUTO PRECHARGE is selected. If
AUTO PRECHARGE is not selected, the row will remain
open for subsequent accesses.
COMMAND INHIBIT
COMMAND INHIBIT prevents new commands from being
executed.Operationsinprogressarenotaffected,apartfrom
whether the CLK signal is enabled
Amemoryarrayiswrittenwithcorrespondinginputdataon
DQ’sandDQMinputlogiclevelappearingatthesametime.
Data will be written to memory when DQM signal is LOW.
When DQM is HIGH, the corresponding data inputs will be
ignored, and a WRITE will not be executed to that byte/
column location.
NO OPERATION
When CS is low, the NOP command prevents unwanted
commands from being registered during idle or wait states.
LOAD MODE REGISTER
During the LOAD MODE REGISTER command the mode
register is loaded from A0-A11. This command can only be
issued when all banks are idle.
PRECHARGE
ThePRECHARGEcommandisusedtodeactivatetheopen
row in a particular bank or the open row in all banks. BA0,
BA1canbeusedtoselectwhichbankisprechargedorthey
aretreatedas“Don’tCare”. A10determinedwhetheroneor
all banks are precharged. After executing this command,
the next command for the selected banks(s) is executed
afterpassageoftheperiodtRP, whichistheperiodrequired
for bank precharging. Once a bank has been precharged,
itisintheidlestateandmustbeactivatedpriortoanyREAD
or WRITE commands being issued to that bank.
ACTIVE COMMAND
When the ACTIVE COMMAND is activated, BA0, BA1 inputs
selectsabanktobeaccessed, andtheaddressinputsonA0-
A11 selects the row. Until a PRECHARGE command is
issued to the bank, the row remains open for accesses.
EXTENDED MODE REGISTER
The extended mode register defines low power functions.
DuringthiscommandA0-A11aredatainputpins. Afterpower
on, the extended mode register set command must be ex-
AUTO PRECHARGE
ecuted to fix low power functions. During t
command, they can not accept any other command. The
extended mode register has four fields:
following this
CSR
TheAUTOPRECHARGEfunctionensuresthattheprecharge
is initiated at the earliest valid stage within a burst. This
functionallowsforindividual-bankprechargewithoutrequir-
ing an explicit command. A10 to enable the AUTO
PRECHARGEfunctioninconjunctionwithaspecificREAD
orWRITEcommand. ForeachindividualREADorWRITE
command, auto precharge is either enabled or disabled.
AUTO PRECHARGE does not apply except in full-page
•
•
•
•
Options: A11-A7
Drive Strength: A6-A5
Temperature Compensated self Refresh: A4-A3
Partial Array Self Refresh: A2-A0
Following extended mode register programming, no com-
mand can be issued before at least 2 CLK have elapsed.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
9
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
COMMAND TRUTH TABLE
CKE
A11
Function Symbol
Device deselect
No operation
Burst stop
n–1
H
n
×
×
H
×
×
×
×
×
×
×
×
×
CS
H
L
RAS
×
CAS
×
WE
×
BA1
×
BA0
×
A10
A9 - A0
×
×
×
L
×
×
×
V
V
V
V
V
×
×
V
V
H
H
H
H
H
H
H
L
H
H
L
H
L
×
×
H
L
×
×
Read
H
L
H
H
L
V
V
V
V
V
V
×
V
V
V
V
V
V
×
Read with auto precharge H
Write
Write with auto precharge H
L
L
H
L
H
L
L
L
L
L
H
V
L
Bank activate
H
H
H
H
H
L
H
H
H
L
H
L
Precharge select bank
Precharge all banks
Mode register set
L
L
L
L
L
H
L
L
L
L
L
L
Extended mode reg set
L
L
L
L
H
L
L
Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data.
DQM TRUTH TABLE
CKE
n-1
H
DQM
U
Function Symbol
n
L
L
Data write / output enable
×
×
×
×
×
×
L
Data mask / output disable
H
H
H
×
L
Upper byte write enable / output enable
Lower byte write enable / output enable
Upper byte write inhibit / output disable
Lower byte write inhibit / output disable
H
L
H
×
H
H
×
H
H
×
Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data.
10
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
CKE TRUTH TABLE
CKE
CurrentState/Function
n – 1 n
CS
×
RAS
CAS WE
Address
Activating Clock suspend mode entry
Any Clock suspend mode
Clock suspend mode exit
Auto refresh command Idle
Self refresh entry Idle
H
L
L
×
×
×
L
×
×
×
×
H
H
×
×
×
L
×
×
L
H
H
L
×
×
H
H
L
L
L
×
L
L
×
Power down entry Idle
H
H
L
L
L
H
H
×
H
×
H
×
×
×
Deeppowerdownentry
Self refresh exit
H
L
L
H
H
L
×
L
L
H
H
L
H
H
×
H
×
H
×
×
×
Power down exit
L
L
H
H
L
H
H
×
H
×
H
×
×
×
Deeppowerdownexit
L
H
×
×
×
×
×
Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
11
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
FUNCTIONAL TRUTH TABLE
CS
H
L
RAS CAS
WE
Address
Command
DESL
Action
Nop
Idle
X
X
H
H
L
X
X
H
H
H
H
L
H
L
X
NOP
Nop
L
X
BST
Nop
L
H
L
BA,CA,A10
A,CA,A10
BA,RA
BA, A10
X
READ/READA
WRIT/WRITA
ACT
ILLEGAL (2)
ILLEGAL(2)
L
L
L
H
H
L
H
L
Row activating
L
L
PRE/PALL
REF
Nop
L
L
H
L
Auto refresh
L
L
L
OC, BA1=L
OC,BA1=H
X
MRS
Mode register set
L
L
L
L
EMRS
Extended mode register set
Row Active
H
L
X
H
H
H
H
L
X
H
H
L
X
H
L
DESL
Nop
Nop
Nop
X
NOP
L
X
BST
(3)
L
H
L
BA,CA,A10
BA,CA,A10
BA,RA
BA, A10
X
READ/READA
WRIT/WRITA
ACT
Begin read
(3)
L
L
Begin write
ILLEGAL (2)
Precharge/Precharge all banks(
L
H
H
L
H
L
L
L
PRE/PALL
REF
L
L
H
L
ILLEGAL
ILLEGAL
L
L
L
OC,BA
X
MRS/EMRS
DESL
Read
H
X
X
X
Continue burst to end to
Row active
L
H
H
H
X
NOP
Continue burst to end Row
Row active
L
L
H
H
H
L
L
X
BST
Burst stop Row active
Terminate burst,
begin new read
H
BA, CA, A10
READ/READA
(5)
L
H
L
L
BA, CA, A10
WRIT/WRITA
Terminate burst,
begin write
(5, 6)
L
L
L
L
H
H
H
L
BA, RA
ACT
ILLEGAL (2)
BA, A10
PRE/PALL
Terminate burst
Precharging
L
L
H
L
L
X
L
L
X
H
L
X
REF
ILLEGAL
ILLEGAL
OC, BA
X
MRS/EMRS
DESL
Write
X
Continue burst to end
Write recovering
L
H
H
H
X
NOP
Continue burst to end
Write recovering
L
L
H
H
H
L
L
X
BST
Burst stop Row active
H
BA, CA, A10
READ/READA
Terminate burst, start read :
Determine AP (5, 6)
L
H
L
L
BA, CA, A10
WRIT/WRITA
Terminate burst, new write :
Determine AP (5)
L
L
L
L
L
L
L
L
H
H
L
H
L
BA,RA
BA, A10
X
ACT
ILLEGAL (2)
(7)
PRE/PALL
REF
Terminate burst Precharging
ILLEGAL
H
L
L
OC,BA
MRS/EMRS
ILLEGAL
Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
FUNCTIONAL TRUTH TABLE Continued:
CS
RAS CAS
WE
Address
Command
Action
Read with auto
Precharging
H
×
×
×
×
DESL
Continue burst to end -
Precharge
L
H
H
H
x
NOP
Continue burst to end -
Precharging
L
L
L
L
L
L
L
H
H
H
H
L
H
L
L
×
BST
ILLEGAL
H
L
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
×
READ/READA
WRIT/WRITA
ACT
ILLEGAL (2)
ILLEGAL (2)
ILLEGAL (2)
ILLEGAL (2)
ILLEGAL
L
H
H
L
H
L
L
PRE/PALL
REF
L
H
L
L
L
OC, BA
×
MRS/EMRS
DESL
ILLEGAL
Write with Auto
Precharge
×
×
×
Continue burst to end -Write
recovering with auto precharge
L
H
H
H
×
NOP
Continue burst to end -Write
recoveringwith auto precharge
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
H
H
L
H
L
L
×
BST
ILLEGAL
ILLEGAL(2)
ILLEGAL (2)
ILLEGAL(2)
H
L
BA, CA, A10
READ/READA
WRIT/WRITA
ACT
L
BA, CA, A10
H
H
L
H
L
BA,RA
L
BA, A10
PRE/PALL
REF
ILLEGAL (2)
L
H
L
×
ILLEGAL
L
L
OC,BA
MRS/EMRS
DESL
ILLEGAL
Precharging
×
H
H
H
H
L
×
H
H
L
×
H
L
×
Nop Enter idle after tRP
Nop Enter idle after tRP
ILLEGAL
ILLEGAL (2)
ILLEGAL (2)
×
NOP
×
BST
H
L
BA,CA,A10
BA,CA,A10
BA,RA
BA, A10
×
READ/READA
WRIT/WRITA
ACT
L
H
H
L
H
L
ILLEGAL(2)
L
PRE/PALL
REF
Nop Enter idle after tRP
ILLEGAL
L
H
L
L
L
OC,BA
×
MRS/EMRS
DESL
ILLEGAL
Row Activating
×
H
H
H
H
L
×
H
H
L
×
H
L
Nop Enter bank active after tRCD
Nop Enter bank active after tRCD
ILLEGAL
ILLEGAL (2)
ILLEGAL (2)
ILLEGAL (2,8)
ILLEGAL (2)
×
NOP
×
BST
H
L
BA,CA,A10
BA,CA,A10
BA,RA
BA, A10
×
READ/READA
WRIT/WRITA
ACT
L
H
H
L
H
L
L
PRE/PALL
REF
L
H
L
ILLEGAL
L
L
OC,BA
MRS/EMRS
ILLEGAL
Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
13
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
FUNCTIONAL TRUTH TABLE Continued:
CS
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
RAS CAS
WE
Address
Command
DESL
Action
Write Recovering
×
H
H
H
H
L
×
H
H
L
×
×
Nop Enter row active after tDPL
Nop Enter row active after tDPL
Nop Enter row active after tDPL
Begin read (6)
H
L
×
NOP
×
BST
H
L
BA, CA, A10
READ/READA
WRIT/WRITA
ACT
L
BA, CA, A10
Begin new write
ILLEGAL (2)
ILLEGAL (2)
H
H
L
H
L
BA, RA
L
BA, A10
PRE/PALL
REF
L
H
L
×
ILLEGAL
L
L
OC, BA
MRS/EMRS
DESL
ILLEGAL
Write Recovering
with Auto
×
H
H
H
H
L
×
H
H
L
×
H
L
×
Nop Enter precharge after tDPL
Nop Enter precharge after tDPL
Nop Enter row active after tDPL
ILLEGAL
ILLEGAL (2, 6)
ILLEGAL (2)
×
NOP
Precharge
×
BST
H
L
BA, CA, A10
READ/READA
WRIT/WRITA
ACT
L
BA, CA, A10
H
H
L
H
L
BA, RA
L
BA, A10
PRE/PALL
REF
ILLEGAL (2)
L
H
L
×
ILLEGAL
L
L
OC, BA
MRS/EMRS
DESL
ILLEGAL
Refresh
×
H
H
H
H
L
×
H
H
L
×
H
L
×
Enter idle after tRC1
Nop Enter idle after tRC1
Nop Enter idle after tRC1
ILLEGAL
×
NOP
×
BST
H
L
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
×
EAD/READA
WRIT/WRITA
ACT
L
ILLEGAL
H
H
L
H
L
ILLEGAL
L
PRE/PALL
REF
ILLEGAL
L
H
L
ILLEGAL
L
L
OC, BA
×
MRS/EMRS
DESL
ILLEGAL
Mode Register
Accessing
×
H
H
H
H
L
×
H
H
L
×
H
L
Nop Enter idle after tRSC
Nop Enter idle after tRSC
Nop Enter idle after tRSC
ILLEGAL
×
NOP
×
BST
H
L
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
×
READ/READA
WRIT/WRITA
ACT
L
ILLEGAL
H
H
L
H
L
ILLEGAL
L
PRE/PALL
REF
ILLEGAL
L
H
L
ILLEGAL
L
L
OC, BA
MRS/EMRS
ILLEGAL
Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code
14
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
FUNCTIONAL TRUTH TABLE Continued:
Notes:
1. All entries assume that CKE is active (CKEn-1=CKEn=H).
2. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the
state of that bank.
3. Illegal if tRCD is not satisfied.
4. Illegal if tRAS is not satisfied.
5. Must satisfy burst interrupt condition.
6. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
7. Must mask preceding data which don’t satisfy tDPL.
8. Illegal if tRRD is not satisfied.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
15
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Parameters
Rating
Rating
Unit
42LSxxxxxxL 42SxxxxxxL
VDD MAX
VDDQ MAX
VIN
Maximum Supply Voltage
Maximum Supply Voltage for Output Buffer
Input Voltage
–0.5to+3.6
–0.5to+3.6
–0.5to+3.6
–0.5to+3.6
1
–0.5to+4.6
–0.5to+4.6
–0.5to+4.6
–0.5to+4.6
1
V
V
V
VOUT
Output Voltage
V
PD MAX
ICS
Allowable Power Dissipation
OutputShortedCurrent
W
mA
°C
50
50
TOPR
Operating Temperature
Com.
Ind.
0to+70
–40to+85
0to+70
–40to+85
TSTG
Storage Temperature
–55to+125
–55to+125
°C
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other condi-
tions above those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
2. All voltages are referenced to Vss.
DC RECOMMENDED OPERATING CONDITIONS(2) (At TA = 0 to +70°C)
42LSxxxxxxL
Typ.
42SxxxxxxL
Typ.
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
VDD
SupplyVoltage
2.3
1.65
1.25
-0.3
2.5
2.0
2.7
2.7
3.0
3.0
2.0
-0.3
3.3
3.3
3.6
3.6
V
V
V
V
VDDQ
I/O Supply Voltage
Input High Voltage
Input Low Voltage
(1)
VIH
—
—
VDDQ +0.3
+0.3
—
—
VDDQ +0.3
+0.8
(2)
VIL
Note:
1. VIH (max) = VDDQ +1.5V (PULSE WIDTH < 5NS).
2. VIL (min) = -1.5V (PULSE WIDTH < 5NS).
CAPACITANCE CHARACTERISTICS
(AtTA =0to+25°C, VDD =3.3V± 0.3Vor2.5V± 0.2V, VDDQ=3.3V± 0.3Vor2.5V± 0.2Vor1.8V± 0.15V, f=1MHz)
Symbol
Parameter
Typ.
Max.
Unit
CIN1
CIN2
CI/O
InputCapacitance:CLK
—
—
—
3.5
3.8
6.5
pF
pF
pF
Input Capacitance: All other input pins
Data Input/Output Capacitance: I/Os
16
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
DC ELECTRICAL CHARACTERISTICS (VDD = 3.3V ± 0.3V or 2.5V ± 0.2V , VDDQ = 3.3V ± 0.3V or 2.5V ± 0.2V or 1.8V± 0.15V)
Symbol Parameter
Test Condition
S p e e d Min.
Max.
Unit
I
IL
InputLeakageCurrent
0V ≤ VIN ≤ VDD, with pins other than
–5
5
µA
thetestedpinat0V
I
OL
OutputLeakageCurrent
OutputHighVoltageLevel
OutputLowVoltageLevel
OperatingCurrent(1,2)
Output is disabled, 0V ≤ VOUT ≤ VDD
–5
2.4
—
5
µA
V
V
V
OH
OL
I
OUT =–2mA
OUT = +2 mA
—
0.4
I
V
I
DD1
ActiveMode,
BurstLength=2
Com.
Ind.
Com.
Ind.
-7
-7
-10
-10
—
—
—
—
120
130
100
110
mA
mA
mA
mA
tRC ≥ tRC (min.)
IOUT = 0mA
I
I
DD2P
PrechargeStandbyCurrent
(InPower-DownMode)
CKE ≤ VIL
CKE ≥ VIH
CKE ≤ VIL
CKE ≥ VIH
(
MAX
)
t
CK = tCK
(MIN
(MIN
(MIN
(MIN
)
)
)
)
—
—
1.5
1.0
mA
mA
DD2PS
tCK = ∞
I
I
DD2N
PrechargeStandbyCurrent
(InNonPower-DownMode)
(
MIN)
tCK = tCK
—
—
25
15
mA
mA
DD2NS
tCK = ∞
I
I
DD3P
ActiveStandbyCurrent
(InPower-DownMode)
(
MAX
)
tCK = tCK
—
—
10
10
mA
mA
DD3PS
tCK = ∞
I
DD3N
ActiveStandbyCurrent
(
MIN)
tCK = tCK
Com
Ind.
Com
Ind.
—
—
—
—
35
45
30
35
mA
mA
mA
mA
I
DD3NS
(InNonPower-DownMode)
tCK = ∞
I
I
DD4
OperatingCurrent
(InBurstMode)(1)
t
CK = tCK
(
MIN
)
Com.
Ind.
Com.
Ind.
-7
-7
-10
-10
—
—
—
—
90
110
80
mA
mA
mA
mA
IOUT = 0mA
100
DD5
Auto-RefreshCurrent
tRC = tRC
(
MIN
)
Com.
Ind.
Com.
Ind.
-7
-7
-10
-10
—
—
—
—
210
240
190
200
mA
mA
mA
mA
Notes:
1. These are the values at the minimum cycle time. Since the currents are transient, these values decrease as the cycle time
increases. Also note that a bypass capacitor of at least 0.01 µF should be inserted between Vdd and Vss for each memory
chip to suppress power supply voltage noise (voltage drops) due to these transient currents.
2. IDD1 and IDD4 depend on the output load. The maximum values for Idd1 and Idd4 are obtained with the output open state.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
17
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
DC ELECTRICAL CHARACTERISTICS (Recommended Operation Conditions unless otherwise noted.)
Symbol Parameter
Self-RefreshCurrent
Test Condition
S p e e d Min. Max.
Unit
I
DD6
CKE≤0.2V,tCSR =00
PASR=000(full)
ts < 70OC
—
—
—
—
—
—
—
—
—
—
350
300
230
170
140
µA
µA
µA
µA
µA
PASR=001(2BK)
PASR=010(1BK)
PASR=101(1/2BK)
PASR=110(1/4BK)
I
DD6
DD6
DD6
Self-RefreshCurrent
PASR=000(full)
PASR=001(2BK)
PASR=010(1BK)
PASR=101(1/2BK)
PASR=110(1/4BK)
CKE≤0.2V,tCSR =01
ts < 45OC
—
—
—
—
—
—
—
—
—
—
300
250
200
150
130
µA
µA
µA
µA
µA
I
I
Self-RefreshCurrent
PASR=000(full)
PASR=001(2BK)
PASR=010(1BK)
PASR=101(1/2BK)
PASR=110(1/4BK)
CKE≤0.2V,tCSR =10
ts < 15OC
—
—
—
—
—
—
—
—
—
—
250
180
140
110
90
µA
µA
µA
µA
µA
Self-RefreshCurrent
PASR=000(full)
CKE ≤ 0.2V, , tCSR = 11
ts < 85OC
—
—
—
—
—
—
—
—
—
—
600
400
350
250
200
µA
µA
µA
µA
µA
PASR=001(2BK)
PASR=010(1BK)
PASR=101(1/2BK)
PASR=110(1/4BK)
I
DD7
StandbyCurrent in
CKE≤0.2V
—
—
10
µA
DeepPowerDownMode
18
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
(1,2,3)
AC ELECTRICAL CHARACTERISTICS
- 7
- 1 0
M i n .
S y m b o l
P a r a m e t e r
M i n . M a x .
M a x
U n i t s
tCK3
tCK2
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
7
10
—
—
10
10
—
—
ns
ns
tAC3
tAC2
Access Time From CLK(4)
CAS Latency = 3
CAS Latency = 2
—
—
5.4
6
—
—
7
9
ns
ns
tCHI
tCL
CLK HIGH Level Width
CLK LOW Level Width
Output Data Hold Time
2.5
2.5
—
—
3.5
3.5
—
—
ns
ns
tOH3
tOH2
CAS Latency = 3
CAS Latency = 2
2.5
2.5
—
—
2.5
2.5
—
—
ns
ns
tLZ
Output LOW Impedance Time
0
—
0
—
ns
tHZ3
tHZ2
Output HIGH Impedance Time(5)CAS Latency = 3
CAS Latency = 2
—
—
6
6
—
—
7
9
ns
ns
tDS
Input Data Setup Time
1.5
0.8
1.5
0.8
1.5
0.8
1CLK+3
1.5
0.8
63
—
—
2.0
1
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tDH
Input Data Hold Time
tAS
Address Setup Time
—
2.0
1
—
tAH
Address Hold Time
—
—
tCKS
tCKH
tCKA
tCS
CKE Setup Time
—
2.0
1
—
CKE Hold Time
—
—
CKE to CLK Recovery Delay Time
Command Setup Time (CS, RAS, CAS, WE, DQM)
Command Hold Time (CS, RAS, CAS, WE, DQM)
Command Period (REF to REF / ACT to ACT)
Command Period (ACT to PRE)
Command Period (PRE to ACT)
Active Command To Read / Write Command Delay Time
Command Period (ACT [0] to ACT[1])
—
1CLK+3
2.0
1
—
—
—
tCH
—
—
tRC
—
70
—
tRAS
tRP
37
120,000
—
44
120,000
—
18
20
tRCD
tRRD
tDPL3
18
—
20
—
14
—
15
—
Input Data To Precharge
Command Delay time
CAS Latency = 3
2CLK
—
2CLK
—
tDPL2
tDAL3
CAS Latency = 2
2CLK
—
—
2CLK
—
—
ns
ns
Input Data To Active / Refresh CAS Latency = 3
Command Delay time (During Auto-Precharge)
CAS Latency = 2
2CLK+tRP
2CLK+tRP
tDAL2
tT
2CLK+tRP
0.5
—
30
64
2CLK+tRP
0.5
—
30
64
ns
ns
Transition Time
tREF
Refresh Cycle Time (4096)
—
—
ms
Notes:
1. When power is first applied, memory operation should be started 100 µs after VDD and VDDQ reach their stipulated voltages.
Also note that the power-on sequence must be executed before starting memory operation.
2. Measured with tT = 1 ns.
3. The reference level is 0.9V when measuring input signal timing. Rise and fall times are measured between VIH (min.) and VIL
(max.).
4. Access time is measured at 0.9V with the load shown in the figure below.
5. The time tHZ (max.) is defined as the time required for the output voltage to transition by ± 200 mV from VOH (min.) or VOL (max.)
when the output is in the high impedance state.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
19
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
OPERATING FREQUENCY / LATENCY RELATIONSHIPS
SYMBOL PARAMETER
-7
7
-10.
UNITS
ns
—
Clock Cycle Time
10
100
1
—
OperatingFrequency
133
1
MHz
tCCD
tCKED
tPED
tDQD
tDQM
tDQZ
tDWD
tDAL
tDPL
tBDL
tCDL
tRDL
tMRD
READ/WRITE command to READ/WRITE command
CKE to clock disable or power-down entry mode
CKE to clock enable or power-down exit setup mode
DQM to input data delay
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
1
1
1
1
0
0
DQM to data mask during WRITEs
DQM to data high-impedance during READs
WRITE command to input data delay
Data-in to ACTIVE command
0
0
2
2
0
0
5
4
Data-intoPRECHARGEcommand
Last data-in to burst STOP command
Last data-in to new READ/WRITE command
Last data-in to PRECHARGE command
2
2
1
1
1
1
2
2
LOAD MODE REGISTER command
to ACTIVE or REFRESH command
2
2
tROH
Data-outtohigh-impedancefrom
PRECHARGEcommand
CL = 3
CL = 2
3
2
3
2
cycle
20
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
AC TEST CONDITIONS (VCCQ = 1.8V)
Input Load
Output Load
t
CK
t
CHI
t
CL
1.4V
0.9V
0.9V
0.4V
CLK
50Ω
Z = 50Ω
t
CS
t
CH
Output
1.4V
0.9V
30 pF
INPUT
0.4V
t
AC
t
OH
OUTPUT
0.9V
0.9V
AC TEST CONDITIONS
Parameter
Unit
AC High Level Input Voltage/Low Level Input Voltage
Input Rise and Fall Times
1.4Vto0.4V
1 ns
Input Timing Reference Level
0.9V
Output Timing Measurement Reference Level
0.9V
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
21
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
AC TEST CONDITIONS (VCCQ = 3.3V)
Output Load
Input Load
t
CK
t
CHI
t
CL
3.0V
1.5V
1.5V
0V
CLK
50Ω
Z = 50Ω
t
CS
t
CH
Output
3.0V
1.5V
30 pF
INPUT
0V
t
AC
t
OH
OUTPUT
1.5V
1.5V
AC TEST CONDITIONS
Parameter
Unit
AC High Level Input Voltage/Low Level Input Voltage
Input Rise and Fall Times
3.0Vto0V
1 ns
Input Timing Reference Level
1.5V
Output Timing Measurement Reference Level
1.5V
22
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
descriptions and device operation.
FUNCTIONAL DESCRIPTION
The 128Mb Low - Power SDRAMs are quad-bank DRAMs
which operate at 2.5V or 3.3V and include a synchronous
interface (all signals are registered on the positive edge of
the clock signal, CLK). Each of the 33,554,432-bit banks is
organized as 4,096 rows by 512 columns by 16 bits.
Initialization
SDRAMs must be powered up and initialized in a
predefinedmanner.
The128MSDRAMisinitializedafterthepowerisappliedto
VDD and VDDQ (simultaneously) and the clock is stable.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a
programmed number of locations in a programmed
sequence. Accesses begin with the registration of an AC-
TIVEcommandwhichisthenfollowedbyaREADorWRITE
command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to
A 200µs delay is required prior to issuing any command
other than a COMMAND INHIBIT or aNOP. The COMMAND
INHIBITorNOPmaybeappliedduringthe100usperiodand
should continue at least through the end of the period.
With at least one COMMAND INHIBIT or NOP command
havingbeenapplied,aPRECHARGEcommandshouldbe
appliedoncethe100µsdelayhasbeensatisfied. Allbanks
mustbeprecharged. Thiswillleaveallbanksinanidlestate
wheretwoAUTOREFRESHcyclesmustbeperformed. After
theAUTOREFRESHcyclesarecomplete,theSDRAMisthen
readyformoderegisterprogramming.
beaccessed(BA0andBA1selectthebank,A0-A11selecttherow)
.
TheaddressbitsA0-A9(x8);A0-A8(x16);A0-A7(x32)regis-
tered coincident with the READ or WRITE command are
used to select the starting column location for the burst
access.
Themoderegisterandextendedmoderegistersshouldbe
loadedpriortoapplyinganyoperationalcommandbecause
it will power up in an unknown state.
Prior to normal operation, the SDRAM must be initialized.
The following sections provide detailed information covering
device initialization, register definition, command
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
23
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
REGISTER DEFINITION
Mode Register
Mode register bits M0-M2 specify the burst length, M3
specifiesthetypeofburst (sequentialorinterleaved), M4-M6
specify the CAS latency, M7 and M8 specify the operating
mode, M9 specifies the WRITE burst mode, and M10 and
M11 are reserved for future use.
The mode register is used to define the specific mode of
operation of the SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS latency, an
operatingmodeandawriteburstmode,asshowninMODE
REGISTERDEFINITION.
The mode register must be loaded when all banks are idle,
and the controller must wait the specified time before
initiatingthesubsequentoperation.Violatingeitherofthese
requirements will result in unspecified operation.
The mode register is programmed via the LOAD MODE
REGISTER command and will retain the stored information
until it is programmed again or the device loses power.
MODE REGISTER DEFINITION
Address Bus
BA1 BA0 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Mode Register (Mx)
Reserved(1)
Burst Length
M2 M1 M0
M3=0
M3=1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
1
2
4
8
Reserved Reserved
Reserved Reserved
Reserved Reserved
Full Page Reserved
Burst Type
M3
Type
0
1
Sequential
Interleaved
Latency Mode
M6 M5 M4
CAS Latency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Operating Mode
M8 M7 M6-M0 Mode
0
0
Defined Standard Operation
All Other States Reserved
—
—
—
Write Burst Mode
M9
0
Mode
Programmed Burst Length
Single Location Access
1. To ensure compatibility with future devices,
should program BA1, BA0, A11, A10 = "0, 0"
1
24
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
REGISTER DEFINITION
Extended Mode Register
ExtendedModeregisterbitsM0-M2controlsPASRandM3-
M4 controls (TCSR). M5 - M11 must be programmed to 0.
The mode register is used to define the specific SDRAM
low-power features. This includes the Temperature Com-
pensated Self Refresh (TCSR) and Partial Array Self
Refresh (PASR) as shown in EXTENDED MODE REGIS-
TER DEFINITION.
The Extended Mode Register must be loaded when all
banksareidleandnoburstsareinprogress.Thecontroller
mustinitializetheoperationafterwaitingthespecifiedtime.
.Violatingeitheroftheserequirementswillresultinunspeci-
fied operation.
The extended mode register is programmed via the EX-
TENDED LOAD MODE REGISTER command (M13=1,
M12=0) and will retain the stored information until it is pro-
grammed again or the device loses power.
MODE REGISTER DEFINITION
Address Bus
BA1 BA0 A11 A10 A9 A8 A7 A6 A5
A4 A3
A2 A1 A0
Extended Mode
Register (Mx)
M11-M5
PASR
0
M12
0
M2 M1 M0 Self Refresh Coverage
M13
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
4 banks
2 banks (Bank 0,1)
1 bank (Bank 0)
Reserved
Reserved
1/2 bank (Bank 0)
1/4 bank (Bank 0)
Reserved
TCSR
M4 M3 Max. Case Temp.
1
0
0
1
0
1
0
1
15ο C
45ο C
70ο C
85ο C
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
25
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
INITIALIZE / LOAD MODE REGISTER AND EXTEND MODE REGISTER
Tp+5
Tp+6
Tp+4
T0
T1
Tn+1
To+1
t
CL
Tp+1
t
CK
t
CH
CLK
CKE
t
CKS tCKH
t
CMS
t
CMH
t
CMS
t
CMH
tCMS tCMH
AUTO
REFRESH
AUTO
Load MODE
REGISTER
Load MODE
REGISTER
COMMAND
ACTIVE
NOP
NOP
PRECHARGE
NOP
NOP
REFRESH
DQM/DQML
DQMH/DQM0-3
t
AS
tAH
A0-A9, A11
A10
ROW
ROW
BANK
CODE
CODE
CODE
ALL BANKS
CODE
t
AS
tAH
BA0=L
BA1=L
BA0=L
BA1=H
BA0, BA1
DQ
HighZ
T
t
RP
t
RFC
tRFC
MODE REGISTER
Power-up: VCC
Precharge AUTO REFRESH
AUTO REFRESH
Extended MODE REGISTER
and CLK stable all banks
DON'T CARE
T = 100µs Min.
Note: The Load Mode Register for both Mode Register / Extended Mode Register and two Auto Refresh Commands
can be in any order. However, all must occur prior to an Active Command.
26
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
AUTO-REFRESH CYCLE
T0
T1
T2
Tn+1
To+1
t
CK
t
CL
t
CH
CLK
CKE
t
CKS CKH
t
t
CMS
t
CMH
Auto
Refresh
Auto
COMMAND
PRECHARGE
NOP
NOP
NOP
ACTIVE
Refresh
DQM/DQML
DQMH/DQM0-3
A0-A9, A11
A10
ROW
ROW
BANK
ALL BANKS
SINGLE BANK
BANK(s)
BA0, BA1
DQ
t
AS
t
AH
High-Z
t
RFC
t
RP
t
RFC
DON'T CARE
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
27
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
SELF-REFRESH CYCLE
T0
T1
T2
Tn+1
To+1
To+2
t
CK
t
CH
t
CL
CLK
CKE
t
CKS
t
CKH
t
CKS
≥ tRAS
t
CKS
t
CMS
t
CMH
Auto
Auto
COMMAND
PRECHARGE
NOP
NOP
NOP
Refresh
Refresh
DQM/DQML
DQMH/DQM0-3
A0-A9, A11
A10
ALL BANKS
SINGLE BANK
t
AS
t
AH
BA0, BA1
DQ
BANK
High-Z
t
XSR
t
RP
Precharge all
active banks
Enter self
refresh mode
CLK stable prior to exiting
self refresh mode
Exit self refresh mode
(Restart refresh time base)
DON'T CARE
28
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
BURST LENGTH
ReadandwriteaccessestotheSDRAMareburstoriented,
with the burst length being programmable, as shown in
MODE REGISTER DEFINITION. The burst length deter-
mines the maximum number of column locations that can
be accessed for a given READ or WRITE command. Burst
lengths of 1, 2, 4 or 8 locations are available for both the
sequential and the interleaved burst types, and a full-page
burstisavailableforthesequentialtype.Thefull-pageburst
is used in conjunction with the BURST TERMINATE com-
mand to generate arbitrary burst lengths.
ing that the burst will wrap within the block if a boundary is
reached. The block is uniquely selected by A1-A7 (x32)
whentheburstlengthissettotwo;byA2-A7(x32)whenthe
burstlengthissettofour;andbyA3-A7(x32)whentheburst
length is set to eight. The remaining (least significant)
address bit(s) is (are) used to select the starting location
withintheblock.Full-pageburstswrapwithinthepageifthe
boundary is reached.
Burst Type
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
Reservedstatesshouldnotbeused,asunknownoperation
or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
columnsequaltotheburstlengthiseffectivelyselected.All
accesses for that burst take place within this block, mean-
Theorderingofaccesseswithinaburstisdeterminedbythe
burstlength,thebursttypeandthestartingcolumnaddress,
as shown in BURST DEFINITION table.
BURST DEFINITION
Burst
StartingColumn
Address
OrderofAccessesWithinaBurst
Length
Type=Sequential
Type=Interleaved
A0
2
4
0
1
0-1
1-0
0-1
1-0
A1
0
A0
0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0
1
1
0
1
1
A2
A1
0
A0
0
0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
NotSupported
0
0
1
0
1
0
8
0
1
1
1
0
0
1
0
1
1
1
1
0
1
1
Full
Page
(y)
n=A0-A7
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
…Cn-1,
(location0-y)
Cn…
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
29
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
CAS Latency
The CAS latency is the delay, in clock cycles, between the
registration of a READ command and the availability of the
first piece of output data. The latency can be set to two or
three clocks.
reserved for future use and/or test modes. The programmed
burst length applies to both READ and WRITE bursts.
Test modes and reserved states should not be used
because unknown operation or incompatibility with future
versions may result.
If a READ command is registered at clock edge n, and the
latencyismclocks, thedatawillbeavailablebyclockedge
n+m.TheDQswillstartdrivingasaresultoftheclockedge
one cycle earlier (n + m - 1), and provided that the relevant
access times are met, the data will be valid by clock edge
n + m. For example, assuming that the clock cycle time is
such that all relevant access times are met, if a READ
commandisregisteredatT0andthelatencyisprogrammed
totwoclocks,theDQswillstartdrivingafterT1andthedata
willbevalidbyT2,asshowninCASLatencydiagrams.The
AllowableOperatingFrequencytableindicatestheoperat-
ing frequencies at which each CAS latency setting can be
used.
Write Burst Mode
When M9 = 0, the burst length programmed via M0-M2
appliestobothREADandWRITEbursts;whenM9=1, the
programmedburstlengthappliestoREADbursts,butwrite
accesses are single-location (nonburst) accesses.
CAS Latency
Allowable Operating Frequency (MHz)
S p e e d
CAS Latency
100
=
2
CAS Latency
133
= 3
Reservedstatesshouldnotbeusedasunknownoperationor
incompatibility with future versions may result.
7
10
100
100
Operating Mode
ThenormaloperatingmodeisselectedbysettingM7andM8
to zero; the other combinations of values for M7 and M8 are
CAS LATENCY
T0
T1
T2
T3
CLK
READ
NOP
NOP
COMMAND
DQ
t
AC
DOUT
t
LZ
t
OH
CAS Latency - 2
T0
T1
T2
T3
T4
CLK
READ
NOP
NOP
NOP
COMMAND
DQ
t
AC
DOUT
t
LZ
t
OH
CAS Latency - 3
DON'T CARE
UNDEFINED
30
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
ACTIVATING
WITHIN SPECIFIC BANK
SPECIFIC
ROW
CHIP OPERATION
BANK/ROW ACTIVATION
BeforeanyREADorWRITEcommandscanbeissuedtoa
bankwithintheSDRAM,arowinthatbankmustbe“opened.”
This is accomplished via the ACTIVE command, which
selects both the bank and the row to be activated (see
Activating Specific Row Within Specific Bank).
CLK
HIGH
CKE
CS
After opening a row (issuing an ACTIVE command), a
READ or WRITE command may be issued to that row,
subject to the tRCD specification. Minimum tRCD should be
dividedbytheclockperiodandroundeduptothenextwhole
number to determine the earliest clock edge after the
ACTIVE command on which a READ or WRITE command
can be entered. For example, a tRCD specification of 20ns
with a 125 MHz clock (8ns period) results in 2.5 clocks,
rounded to 3. This is reflected in the following example,
which covers any case where 2 < [tRCD (MIN)/tCK] ≤ 3. (The
sameprocedureisusedtoconvertotherspecificationlimits
from time units to clock cycles).
RAS
CAS
WE
A0-A11
BA0, BA1
ROW ADDRESS
A subsequent ACTIVE command to a different row in the
samebankcanonlybeissuedafterthepreviousactiverow
hasbeen“closed”(precharged).Theminimumtimeinterval
betweensuccessiveACTIVEcommandstothesamebank
is defined by tRC.
BANK ADDRESS
A subsequent ACTIVE command to another bank can be
issuedwhilethefirstbankisbeingaccessed, whichresults
in a reduction of total row-access overhead. The minimum
time interval between successive ACTIVE commands to
different banks is defined by tRRD.
EXAMPLE: MEETING TRCD (MIN) WHEN 2 < [TRCD (MIN)/TCK] ≤ 3
T0
T1
T2
T3
T4
CLK
READ or
WRITE
ACTIVE
NOP
NOP
COMMAND
tRCD
DON'T CARE
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
31
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
READS
READ COMMAND
READ bursts are initiated with a READ command, as
shown in the READ COMMAND diagram.
CLK
CKE
The starting column and bank addresses are provided with
the READ command, and auto precharge is either enabled
ordisabledforthatburstaccess.Ifautoprechargeisenabled,
therowbeingaccessedisprechargedatthecompletionofthe
burst.ForthegenericREADcommandsusedinthefollowing
illustrations, auto precharge is disabled.
HIGH
CS
During READ bursts, the valid data-out element from the
startingcolumnaddresswillbeavailablefollowingtheCAS
latencyaftertheREADcommand. Eachsubsequent data-
outelementwillbevalidbythenextpositiveclockedge.The
CAS Latency diagram shows general timing
for each possible CAS latency setting.
RAS
CAS
WE
Upon completion of a burst, assuming no other commands
havebeeninitiated,theDQswillgoHigh-Z.Afull-pageburst
will continue until terminated. (At the end of the page, it will
wrap to column 0 and continue.)
COLUMN ADDRESS
A0-A7
A8, A9, A11
A10
Data from any READ burst may be truncated with a subse-
quentREADcommand, anddatafromafixed-lengthREAD
burst may be immediately followed by data from a READ
command. In either case, a continuous flow of data can be
maintained.Thefirstdataelementfromthenewburstfollows
eitherthelastelementofacompletedburstorthelastdesired
data element of a longer burst which is being truncated.
AUTO PRECHARGE
NO PRECHARGE
BANK ADDRESS
BA0, BA1
ThenewREADcommandshouldbeissuedxcyclesbefore
the clock edge at which the last desired data element is
valid, where x equals the CAS latency minus one. This is
shown in Consecutive READ Bursts for CAS latencies of
twoandthree;dataelementn+3iseitherthelastofaburst
of four or the last desired of a longer burst. The 128Mb
SDRAM uses a pipelined architecture and therefore does
not require the 2n rule associated with a prefetch architec-
ture. AREADcommandcanbeinitiatedonanyclockcycle
following a previous READ command. Full-speed random
readaccessescanbeperformedtothesamebank,asshown
in Random READ Accesses, or each subsequent READ
may be performed to a different bank.
TheDQMinputisusedtoavoidI/Ocontention,asshownin
FiguresRW1andRW2. TheDQMsignalmustbeasserted
(HIGH) at least two clocks prior to the WRITE command
(DQM latency is two clocks for output buffers) to suppress
data-out from the READ. Once the WRITE command is
registered, the DQs will go High-Z (or remain High-Z),
regardless of the state of the DQM signal, provided the
DQM was active on the clock just prior to the WRITE
command that truncated the READ command. If not, the
second WRITE will be an invalid WRITE. For example, if
DQMwasLOWduringT4inFigureRW2,thentheWRITEs
at T5 and T7 would be valid, while the WRITE at T6 would
be invalid.
Data from any READ burst may be truncated with a
subsequent WRITE command, and data from a fixed-length
READ burst may be immediately followed by data from a
WRITE command (subject to bus turnaround limitations).
The WRITE burst may be initiated on the clock edge
immediatelyfollowingthelast(orlastdesired)dataelement
from the READ burst, provided that I/O contention can be
avoided. In a given system design, there may be a possi-
bility that the device driving the input data will go Low-Z
before the SDRAM DQs go High-Z. In this case, at least a
single-cycledelayshouldoccurbetweenthelastreaddata
and the WRITE command.
The DQM signal must be de-asserted prior to the WRITE
command (DQM latency is zero clocks for input buffers) to
ensure that the written data is not masked. Figure RW1
shows the case where the clock frequency allows for bus
contention to be avoided without adding a NOP cycle, and
Figure RW2 shows the case where the additional NOP is
needed.
Afixed-lengthREADburstmaybefollowedby, ortruncated
with, aPRECHARGEcommandtothesamebank(provided
that auto precharge was not activated), and a full-page burst
may be truncated with a PRECHARGE command to the
32
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
same bank. The PRECHARGE command should be is-
suedxcyclesbeforetheclockedgeatwhichthelastdesired
dataelementisvalid,wherexequalstheCASlatencyminus
one.ThisisshownintheREADtoPRECHARGEdiagramfor
each possible CAS latency; data element n + 3 is either the
last of a burst of four or the last desired of a longer burst.
FollowingthePRECHARGEcommand,asubsequentcom-
mandtothesamebankcannotbeissueduntiltRP ismet.Note
that part of the row precharge time is hidden during the
access of the last data element(s).
Inthecaseofafixed-lengthburstbeingexecutedtocomple-
tion,aPRECHARGEcommandissuedattheoptimumtime
(as described above) provides the same operation that
would result from the same fixed-length burst with auto
precharge. The disadvantage of the PRECHARGE com-
mand is that it requires that the command and address
buses be available at the appropriate time to issue the
command;theadvantageofthePRECHARGEcommandis
that it can be used to truncate fixed-length or full-page
bursts.
Full-page READ bursts can be truncated with the BURST
TERMINATE command, and fixed-length READ bursts
may be truncated with a BURST TERMINATE command,
providedthatautoprechargewasnotactivated.TheBURST
TERMINATE command should be issued x cycles before
the clock edge at which the last desired data element is
valid, where x equals the CAS latency minus one. This is
shown in the READ Burst Termination diagram for each
possibleCASlatency;dataelementn+3isthelastdesired
data element of a longer burst.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
33
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
RW1 - READ TO WRITE
T0
T1
T2
T3
T4
CLK
DQM
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
WRITE
BANK,
COL n
BANK,
COL b
t
HZ
DOUT
n
DIN
b
t
DS
DON'T CARE
RW2 - READ TO WRITE WITH EXTRA CLOCK CYCLE
T0
T1
T2
T3
T4
T5
CLK
DQM
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
NOP
WRITE
BANK,
COL b
BANK,
COL n
t
HZ
DOUT
n
DIN
b
t
DS
DON'T CARE
34
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
CONSECUTIVE READ BURSTS
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
READ
NOP
NOP
x=1 cycle
BANK,
COL n
BANK,
COL b
DOUT
n
DOUT n+1
DOUT n+2
DOUT n+3
DOUT
b
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ
NOP
NOP
NOP
READ
NOP
NOP
NOP
x = 2 cycles
BANK,
COL n
BANK,
COL b
ADDRESS
DQ
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
DOUT b
CAS Latency - 3
DON'T CARE
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
35
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
RANDOM READ ACCESSES
T0
T1
T2
T3
T4
T5
CLK
COMMAND
ADDRESS
DQ
READ
READ
READ
READ
NOP
NOP
BANK,
COL n
BANK,
COL b
BANK,
COL m
BANK,
COL x
DOUT
n
DOUT
b
DOUT
m
DOUT
x
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
ADDRESS
DQ
READ
READ
READ
READ
NOP
NOP
NOP
BANK,
COL n
BANK,
COL b
BANK,
COL m
BANK,
COL x
DOUT
n
DOUT
b
DOUT
m
DOUT
x
CAS Latency - 3
DON'T CARE
36
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
READ BURST TERMINATION
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
ADDRESS
DQ
BURST
TERMINATE
READ
NOP
NOP
NOP
NOP
NOP
x = 1 cycle
BANK a,
COL n
DOUT
n
DOUT n+1
DOUT n+2
DOUT n+3
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
ADDRESS
DQ
BURST
TERMINATE
READ
NOP
NOP
NOP
NOP
x = 2 cycles
NOP
NOP
BANK,
COL n
DOUT
n
DOUT n+1
DOUT n+2
DOUT n+3
CAS Latency - 3
DON'T CARE
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
37
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
ALTERNATING BANK READ ACCESSES
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
t
CL
tCH
CLK
CKE
t
CKS tCKH
t
CMS
tCMH
COMMAND
ACTIVE
NOP
READ
NOP
ACTIVE
NOP
READ
NOP
ACTIVE
t
CMS tCMH
DQM/DQML
DQMH/DQM0-3
t
t
t
AS
tAH
COLUMN m(2)
ROW
ROW
COLUMN b(2)
ROW
ROW
A0-A9, A11
A10
ROW
AS
t
AH
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ROW
AS
tAH
BANK 0
BANK 3
BANK 3
BANK 0
BA0, BA1
BANK 0
t
LZ
t
OH
t
OH
t
OH
t
OH
t
OH
DQ
DOUT
m
D
OUT m+
1
DOUT m+
2
DOUT m+
3
DOUT
b
t
AC
t
AC
t
AC
t
AC
t
AC
t
AC
t
t
t
t
RCD - BANK 0
RRD
CAS Latency - BANK 0
t
RP - BANK 0
tRCD - BANK 0
t
RCD - BANK 3
CAS Latency - BANK 3
RAS - BANK 0
RC - BANK 0
DON'T CARE
Notes:
1) CAS latency = 2, Burst Length = 4
2) X16: A9 and A11 = "Don't Care"
X32: A8, A9, and A11 = "Don't Care"
38
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
READ - FULL-PAGE BURST
T0
T1
T2
T3
T4
T5
T6
Tn+1
Tn+2
Tn+3
Tn+4
t
CK
t
CL
tCH
CLK
CKE
t
CKS tCKH
t
CMS
t
CMH
COMMAND
ACTIVE
NOP
READ
CMS CMH
NOP
NOP
NOP
NOP
NOP
BURST TERM
NOP
NOP
t
t
DQM/DQML
DQMH/DQM0-3
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
AS
t
AH
ROW
AS
t
AH
BA0, BA1
BANK
BANK
t
AC
t
AC
t
AC
t
AC
t
AC
t
AC
tHZ
D
OUT
m
D
OUT m+
1
D
OUT m+
2
D
OUT m-
1
D
OUT
m
D
OUT m+
1
DQ
t
LZ
t
OH
t
OH
t
OH
t
OH
t
OH
tOH
t
RCD
CAS Latency
1024 (x8) location
DON'T CARE
UNDEFINED
within same row.
Full page Full-page burst not self-terminating.
completion Use BURST TERMINATE command.
Notes:
1) CAS latency = 2, Burst Length = Full Page
2) X16: A9 and A11 = "Don't Care"
X32: A8, A9, and A11 = "Don't Care"
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
39
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
READ - DQM OPERATION
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
t
CL
tCH
CLK
CKE
t
CKS tCKH
t
CMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
NOP
NOP
NOP
t
CMS
t
CMH
DQM/DQML
DQMH/DQM0-3
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
AS
t
AH
ENABLE AUTO PRECHARGE
ROW
DISABLE AUTO PRECHARGE
AS
t
AH
BA0, BA1
BANK
BANK
t
OH
t
OH
tOH
t
AC
tAC
D
OUT
m
D
OUT m+
2
D
OUT m+
3
DQ
t
LZ
tLZ
t
HZ
t
AC
t
HZ
DON'T CARE
UNDEFINED
t
RCD
CAS Latency
Notes:
1) CAS latency = 2, Burst Length = 4
2) X16: A9 and A11 = "Don't Care"
X32: A8, A9, and A11 = "Don't Care"
40
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
READ to PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
ADDRESS
DQ
t
RP
PRECHARGE
READ
NOP
NOP
NOP
NOP
NOP
ACTIVE
x = 1 cycle
BANK a,
COL n
BANK
(a or all)
BANK a,
ROW
DOUT
n
DOUT n+1
DOUT n+2
DOUT n+3
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
ADDRESS
DQ
t
RP
PRECHARGE
READ
NOP
NOP
NOP
NOP
x = 2 cycles
NOP
ACTIVE
BANK,
COL n
BANK,
COL b
BANK a,
ROW
DOUT
n
DOUT n+1
D
OUT n+2
DOUT n+3
CAS Latency - 3
DON'T CARE
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
41
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
WRITES
An example is shown in WRITE to WRITE diagram. Data n
+ 1 is either the last of a burst of two or the last desired of
a longer burst. The 128Mb Low - Power SDRAM uses a
pipelinedarchitectureandthereforedoesnotrequirethe2n
rule associated with a prefetch architecture. A WRITE com-
mand can be initiated on any clock cycle following a
previous WRITE command. Full-speed random write ac-
cesses within a page can be performed to the same bank,
as shown in Random WRITE Cycles, or each subsequent
WRITE may be performed to a different bank.
WRITE bursts are initiated with a WRITE command, as
showninWRITECommanddiagram.
WRITE COMMAND
CLK
HIGH
CKE
Data for any WRITE burst may be truncated with a subse-
quentREADcommand, anddataforafixed-length WRITE
burst may be immediately followed by a subsequent READ
command. Once the READ command is registered, the
data inputs will be ignored, and WRITEs will not be ex-
ecuted. An example is shown in WRITE to READ. Data n +
1 is either the last of a burst of two or the last desired of a
longerburst.
CS
RAS
CAS
Dataforafixed-lengthWRITEburstmaybefollowed by,or
truncatedwith,aPRECHARGEcommandtothesamebank
(providedthatautoprechargewasnotactivated),andafull-
page WRITE burst may be truncated with a PRECHARGE
commandtothesamebank.ThePRECHARGEcommand
should be issued tWR after the clock edge at which the last
desiredinputdataelementisregistered.Theautoprecharge
mode requires a tWR of at least one clock plus time,
regardless of frequency. In addition, when truncating a
WRITE burst, the DQM signal must be used to mask input
datafortheclockedgepriorto,andtheclockedgecoincident
with,thePRECHARGEcommand.Anexampleisshowninthe
WRITEtoPRECHARGEdiagram.Datan+1iseitherthelast
ofaburstoftwoorthelastdesiredofalongerburst.Following
thePRECHARGEcommand,asubsequentcommandtothe
same bank cannot be issued until tRP is met.
WE
(X16)A0-A8
(X32)A0-A7
(X8)A0-A9
COLUMN ADDRESS
AUTO PRECHARGE
A10
NO PRECHARGE
BANK ADDRESS
BA0, BA1
The starting column and bank addresses are provided with
theWRITEcommand,andautoprechargeiseitherenabled
ordisabledforthataccess. Ifautoprechargeisenabled, the
row being accessed is precharged at the completion of the
burst. For the generic WRITE commands used in the
following illustrations, auto precharge is disabled.
In the case of a fixed-length burst being executed to comple-
tion,aPRECHARGEcommandissuedattheoptimumtime(as
describedabove)providesthesameoperationthatwouldresult
from the same fixed-length burst with auto precharge. The
disadvantageofthePRECHARGEcommandisthatitrequires
that the command and address buses be available at the
appropriatetimetoissuethecommand;theadvantageofthe
PRECHARGE command is that it can be used to truncate
fixed-length or full-page bursts.
During WRITE bursts, the first valid data-in element will be
registeredcoincidentwiththeWRITEcommand. Subsequent
dataelementswillberegisteredoneachsuccessivepositive
clockedge.Uponcompletionofafixed-lengthburst,assum-
ing no other commands have been initiated, the DQs will
remain High-Z and any additional input data will be ignored
(see WRITE Burst). A full-page burst will continue until
terminated. (At the end of the page, it will wrap to column 0
andcontinue.)
Fixed-length or full-page WRITE bursts can be truncated
withtheBURSTTERMINATEcommand.Whentruncating
a WRITE burst, the input data applied coincident with the
BURST TERMINATE command will be ignored. The last
datawritten(providedthatDQMisLOWatthattime)willbe
the input data applied one clock previous to the BURST
TERMINATE command. This is shown in WRITE Burst
Termination, where data n is the last desired data element
of a longer burst.
Data for any WRITE burst may be truncated with a subse-
quent WRITE command, and data for a fixed-length WRITE
burst may be immediately followed by data for a WRITE
command. The new WRITE command can be issued on any
clock following the previous WRITE command, and the data
providedcoincidentwiththenewcommandappliestothenew
command.
42
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
WRITE BURST
T0
T1
T2
T3
CLK
COMMAND
ADDRESS
DQ
WRITE
NOP
NOP
NOP
BANK,
COL n
DIN
n
DIN n+1
DON'T CARE
WRITE TO WRITE
T0
T1
T2
CLK
COMMAND
ADDRESS
DQ
WRITE
NOP
WRITE
BANK,
COL n
BANK,
COL b
DIN
n
DIN n+1
DIN b
DON'T CARE
RANDOM WRITE CYCLES
T0
T1
T2
T3
CLK
COMMAND
ADDRESS
DQ
WRITE
WRITE
WRITE
WRITE
BANK,
COL n
BANK,
COL b
BANK,
COL m
BANK,
COL x
DIN
n
DIN
b
DIN
m
DIN x
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
43
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
WRITE TO READ
T0
T1
T2
T3
T4
T5
CLK
COMMAND
ADDRESS
DQ
WRITE
NOP
READ
NOP
NOP
NOP
BANK,
COL n
BANK,
COL b
DIN
n
DIN n+1
D
OUT
b
DOUT b+1
Latency = 2
DON'T CARE
WRITE TO PRECHARGE (TWR @ TCK ≥ 15NS)
T0
T1
T2
T3
T4
T5
T6
CLK
DQM
tRP
PRECHARGE
COMMAND
ADDRESS
DQ
WRITE
NOP
NOP
NOP
ACTIVE
NOP
BANK a,
COL n
BANK
(a or all)
BANK a,
ROW
tWR
DIN n+1
DIN n
DON'T CARE
44
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
WRITE to PRECHARGE (tWR @ tCK < 15ns)
T0
T1
T2
T3
T4
T5
T6
CLK
DQM
tRP
COMMAND
ADDRESS
DQ
WRITE
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
BANK a,
COL n
BANK
(a or all)
BANK a,
ROW
tWR
DIN
n
DIN n+1
DON'T CARE
WRITE Burst Termination
T0
T1
T2
CLK
BURST
TERMINATE
NEXT
COMMAND
ADDRESS
DQ
WRITE
COMMAND
BANK,
COL n
(ADDRESS)
DIN
n
(DATA)
DON'T CARE
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
45
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
WRITE - FULL PAGE BURST
T0
T1
T2
T3
T4
T5
Tn+1
Tn+2
t
CK
t
CL
t
CH
CLK
CKE
t
CKS CKH
t
t
CMS
t
CMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
BURST TERM
NOP
t
CMS
t
CMH
DQM/DQML
DQMH/DQM0-3
t
t
t
AS
t
AH
COLUMN m(2)
A0-A9, A11
A10
ROW
AS
t
AH
ROW
AS
t
AH
BA0, BA1
BANK
BANK
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
DIN
m
D
IN m+
1
DIN m+
2
DIN m+
3
DIN m-1
DQ
t
RCD
Full page completed
DON'T CARE
Notes:
1) Burst Length = Full Page
2) X16: A9 and A11 = "Don't Care"
X32: A8, A9, and A11 = "Don't Care"
46
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
WRITE - DQM OPERATION
T0
T1
T2
T3
T4
T5
T6
T7
t
CK
t
CL
t
CH
CLK
CKE
t
CKS CKH
t
t
CMS
t
CMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
t
CMS
t
CMH
DQM/DQML
DQMH/DQM0-3
t
t
t
AS
t
AH
COLUMN m(2)
A0-A9, A11
A10
ROW
AS
t
AH
ENABLE AUTO PRECHARGE
ROW
DISABLE AUTO PRECHARGE
AS
t
AH
BA0, BA1
BANK
BANK
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
DIN
m
D
IN m+
2
DIN m+3
DQ
t
RCD
DON'T CARE
Notes:
1) Burst Length = 4
2) X16: A9 and A11 = "Don't Care"
X32: A8, A9, and A11 = "Don't Care"
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
47
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
ALTERNATING BANK WRITE ACCESS
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
CK
t
CL
tCH
CLK
CKE
t
CKS tCKH
t
CMS
tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
ACTIVE
NOP
WRITE
NOP
NOP
ACTIVE
t
CMS tCMH
DQM/DQML
DQMH/DQM0-3
t
t
t
AS
tAH
COLUMN m(2)
ROW
ROW
COLUMN b(2)
ROW
ROW
A0-A9, A11
A10
ROW
AS
t
AH
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ROW
AS
tAH
BANK 0
BANK 1
BANK 1
BANK 0
BA0, BA1
BANK 0
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
DS
tDH
t
DS
tDH
DQ
DIN
m
D
IN m+
1
DIN m+
2
DIN m+
3
DIN
b
D
IN b+
1
DIN b+
2
DIN b+3
t
t
t
t
RCD - BANK 0
RRD
t
WR - BANK 0
t
RP - BANK 0
t
RCD - BANK 0
t
RCD - BANK 1
tWR - BANK 1
RAS - BANK 0
RC - BANK 0
DON'T CARE
Notes:
1) Burst Length = 4
2) X16: A9 and A11 = "Don't Care"
X32: A8, A9, and A11 = "Don't Care"
48
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
CLOCK SUSPEND
Any command or data present on the input pins at the time
of a suspended internal clock edge is ignored; any data
presentontheDQpinsremainsdriven;andburstcounters
are not incremented, as long as the clock is suspended.
(Seefollowingexamples.)
Clock suspend mode occurs when a column access/burst
is in progress and CKE is registered LOW. In the clock
suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic.
For each positive clock edge on which CKE is sampled
LOW, the next internal positive clock edge is suspended.
ClocksuspendmodeisexitedbyregisteringCKEHIGH;the
internal clock and related operation will resume on the
subsequent positive clock edge.
Clock Suspend During WRITE Burst
T0
T1
T2
T3
T4
T5
CLK
CKE
INTERNAL
CLOCK
COMMAND
ADDRESS
DQ
NOP
WRITE
NOP
NOP
BANK a,
COL n
DIN
n
DIN n+1
DIN n+2
DON'T CARE
Clock Suspend During READ Burst
T0
T1
T2
T3
T4
T5
T6
CLK
CKE
INTERNAL
CLOCK
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
NOP
NOP
BANK a,
COL n
Qn
Qn+1
Qn+2
Qn+3
DON'T CARE
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
49
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
CLOCK SUSPEND MODE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
CK
t
CL
t
CH
CLK
CKE
t
CKS
t
CKH
t
CKS CKH
t
t
CMS
t
CMH
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
WRITE
NOP
t
CMS
t
CMH
DQM/DQML
DQMH/DQM0-3
t
AS
t
AH
COLUMN n(2)
A0-A9, A11
A10
COLUMN m(2)
t
AS
t
AH
t
AS
t
AH
BA0, BA1
BANK
BANK
t
DS
t
DH
t
AC
t
AC
t
HZ
DQ
DOUT
m
DOUT m+1
DOUT
e
DOUT e+1
t
LZ
t
OH
DON'T CARE
UNDEFINED
Notes:
1) CAS latency = 3, Burst Length = 2
2) X16: A9 and A11 = "Don't Care"
X32: A8, A9, and A11 = "Don't Care"
50
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
PRECHARGE
PRECHARGE Command
The PRECHARGE command (see figure) is used to deac-
tivatetheopenrowinaparticularbankortheopenrowinall
banks. The bank(s) will be available for a subsequent row
access some specified time (tRP) after the PRECHARGE
command is issued. Input A10 determines whether one or
all banks are to be precharged, and in the case where only
one bank is to be precharged, inputs BA0, BA1 select the
bank. When all banks are to be precharged, inputs BA0,
BA1 are treated as “Don’t Care.” Once a bank has been
precharged,itisintheidlestateandmustbeactivatedprior
to any READ or WRITE commands being issued to that
bank.
CLK
HIGH
CKE
CS
RAS
CAS
WE
POWER-DOWN
Power-down occurs if CKE is registered LOW coincident
with a NOP or COMMAND INHIBIT when no accesses are
in progress. If power-down occurs when all banks are idle,
thismodeisreferredtoasprechargepower-down;ifpower-
down occurs when there is a row active in either bank, this
modeisreferredtoasactivepower-down.Enteringpower-
down deactivates the input and output buffers, excluding
CKE, for maximum power savings while in standby. The
devicemaynotremaininthepower-downstatelongerthan
the refresh period (64ms) since no refresh operations are
performed in this mode.
A0-A9, A11
ALL BANKS
A10
BANK SELECT
BANK ADDRESS
BA0, BA1
The power-down state is exited by registering a NOP or
COMMAND INHIBIT and CKE HIGH at the desired clock
edge (meeting tCKS). See figure below.
POWER-DOWN
CLK
t
CKS
≥ tCKS
CKE
COMMAND
NOP
NOP
ACTIVE
t
t
t
RCD
RAS
RC
All banks idle
Input buffers gated off
Enter power-down mode
Exit power-down mode
less than 64ms
DON'T CARE
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
51
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
POWER-DOWN MODE CYCLE
T0
T1
T2
Tn+1
Tn+2
t
CK
t
CL
t
CH
CLK
CKE
t
CKS
t
CKH
t
CKS
t
CKS
t
CMS
t
CMH
COMMAND
PRECHARGE
NOP
NOP
NOP
ACTIVE
DQM/DQML
DQMH/DQM0-3
A0-A9, A11
A10
ROW
ROW
ALL BANKS
SINGLE BANK
t
AS
t
AH
BA0, BA1
DQ
BANK
BANK
High-Z
Two clock cycles
Input buffers gated
All banks idle
off while in
Precharge all
active banks
All banks idle, enter
power-down mode
power-down mode
DON'T CARE
Exit power-down mode
52
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
BURST READ/SINGLE WRITE
Four cases where CONCURRENT AUTO PRECHARGE
occurs are defined below.
The burst read/single write mode is entered by programming
the write burst mode bit (M9) in the mode register to a logic 1.
In this mode, all WRITE commands result in the access of a
single column location (burst of one), regardless of the
programmed burst length. READ commands access
columns according to the programmed burst length and
sequence, just as in the normal mode of operation (M9 = 0).
READ with Auto Precharge
1. Interrupted by a READ (with or without auto precharge):
AREADtobankmwillinterruptaREADonbankn, CAS
latency later. The PRECHARGE to bank n will begin
when the READ to bank m is registered.
CONCURRENT AUTO PRECHARGE
2.InterruptedbyaWRITE(withorwithoutautoprecharge):
AWRITEtobankmwillinterruptaREADonbanknwhen
registered. DQM should be used two clocks prior to the
WRITE command to prevent bus contention. The
PRECHARGE to bank n will begin when the WRITE to
bank m is registered.
An access command (READ or WRITE) to another bank
while an access command with auto precharge enabled is
executing is not allowed by SDRAMs, unless the SDRAM
supports CONCURRENT AUTO PRECHARGE. ISSI
SDRAMs support CONCURRENT AUTO PRECHARGE.
READ With Auto Precharge interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ - AP
BANK n
READ - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
Idle
COMMAND
BANK n
Page Active
READ with Burst of 4
Page Active
Interrupt Burst, Precharge
tRP - BANK n
tRP - BANK m
Internal States
BANK m
READ with Burst of 4
Precharge
BANK n,
COL a
BANK n,
COL b
ADDRESS
DQ
DOUT
a
DOUT a+1
DOUT
b
DOUT b+1
CAS Latency - 3 (BANK n)
DON'T CARE
CAS Latency - 3 (BANK m)
READ With Auto Precharge interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ - AP
BANK n
WRITE - AP
BANK m
COMMAND
NOP
NOP
NOP
NOP
NOP
NOP
Idle
BANK n
READ with Burst of 4
Page Active
Interrupt Burst, Precharge
Page Active
t
RP - BANK n
tWR - BANK m
Internal States
BANK m
WRITE with Burst of 4
Write-Back
BANK n,
COL a
BANK m,
COL b
ADDRESS
DQM
DQ
DOUT
a
DIN
b
DIN b+1
DIN b+2
DIN b+3
CAS Latency - 3 (BANK n)
DON'T CARE
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
53
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
WRITE with Auto Precharge
4.InterruptedbyaWRITE(withorwithoutautoprecharge):
WRITE to bank m will interrupt aWRITE on banknwhen
3. Interrupted by a READ (with or without auto precharge):
AREADtobankmwillinterruptaWRITEonbanknwhen
registered,withthedata-outappearing(CASlatency) later.
The PRECHARGE to bank n will begin after tWR is met,
wheretWR beginswhentheREADtobankmisregistered.
ThelastvalidWRITEtobanknwillbedata-inregisteredone
clock prior to the READ to bank m.
A
registered.ThePRECHARGEtobanknwillbeginaftertWR
is met, where tWR begins when the WRITE to bank m is
registered.ThelastvaliddataWRITEtobanknwillbedata
registered one clock prior to a WRITE to bank m.
WRITE With Auto Precharge interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
WRITE - AP
BANK n
READ - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
Page Active
WRITE with Burst of 4 Interrupt Burst, Write-Back
WR - BANK n
Precharge
t
tRP - BANK n
Internal States
t
RP - BANK m
BANK m
Page Active
READ with Burst of 4
Precharge
BANK n,
COL a
BANK m,
COL b
ADDRESS
DQ
DIN
a
DIN a+1
DOUT
b
DOUT b+1
CAS Latency - 3 (BANK m)
DON'T CARE
WRITE With Auto Precharge interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
WRITE - AP
BANK n
WRITE - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back
WR - BANK n
Precharge
t
t
RP- BANKtWn R - BANK m
Write - Back
Internal States
BANK m
Page Active
WRITE with Burst of 4
BANK n,
COL a
BANK m,
COL b
ADDRESS
DQ
DIN
a
DIN a+1
DIN a+2
D
IN
b
DIN b+1
DIN b+2
DIN b+3
DON'T CARE
54
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
SINGLE READ WITH AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
t
CL
tCH
CLK
CKE
t
CKS tCKH
t
CMS
tCMH
COMMAND
ACTIVE
NOP
NOP
NOP
READ
NOP
NOP
ACTIVE
NOP
t
CMS
t
CMH
DQM/DQML
DQMH/DQM0-3
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
ROW
ROW
BANK
AS
t
AH
ENABLE AUTO PRECHARGE
ROW
AS
t
AH
BA0, BA1
BANK
BANK
t
OH
t
AC
DOUT m
DQ
t
HZ
DON'T CARE
UNDEFINED
t
t
t
RCD
RAS
RC
CAS Latency
t
RP
Notes:
1) CAS latency = 2, Burst Length = 1
2) X16: A9 and A11 = "Don't Care"
X32: A8, A9, and A11 = "Don't Care"
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
55
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
READ WITH AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
t
CL
tCH
CLK
CKE
t
CKS tCKH
t
CMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
NOP
NOP
ACTIVE
t
CMS
t
CMH
DQM/DQML
DQMH/DQM0-3
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
ROW
ROW
BANK
AS
t
AH
ENABLE AUTO PRECHARGE
ROW
AS
t
AH
BA0, BA1
DQ
BANK
BANK
t
AC
t
AC
t
AC
t
AC
tHZ
DOUT
m
D
OUT m+1
D
OUT m+2
D
OUT m+3
t
LZ
t
OH
t
OH
t
OH
tOH
t
t
t
RCD
RAS
RC
CAS Latency
DON'T CARE
UNDEFINED
t
RP
Notes:
1) CAS latency = 2, Burst Length = 4
2) X16: A9 and A11 = "Don't Care"
X32: A8, A9, and A11 = "Don't Care"
56
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
SINGLE READ WITHOUT AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
t
CL
t
CH
CLK
CKE
t
CKS CKH
t
t
CMS
t
CMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
PRECHARGE
NOP
ACTIVE
NOP
t
CMS
t
CMH
DQM/DQML
DQMH/DQM0-3
t
t
t
AS
t
AH
COLUMN m(2)
A0-A9, A11
A10
ROW
ROW
ROW
BANK
AS
t
AH
ALL BANKS
ROW
SINGLE BANK
BANK
AS
t
AH
DISABLE AUTO PRECHARGE
BA0, BA1
DQ
BANK
BANK
t
OH
t
AC
D
OUT
m
t
LZ
t
HZ
DON'T CARE
UNDEFINED
t
t
t
RCD
RAS
RC
CAS Latency
t
RP
Notes:
1) CAS latency = 2, Burst Length = 1
2) X16: A9 and A11 = "Don't Care"
X32: A8, A9, and A11 = "Don't Care"
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
57
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
READ WITHOUT AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
t
CL
tCH
CLK
CKE
t
CKS tCKH
t
CMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
PRECHARGE
NOP
ACTIVE
t
CMS
t
CMH
DQM/DQML
DQMH/DQM0-3
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
ROW
ROW
BANK
AS
t
AH
ALL BANKS
ROW
AS
t
AH
DISABLE AUTO PRECHARGE
SINGLE BANK
BANK
BA0, BA1
DQ
BANK
BANK
t
AC
t
AC
t
AC
t
AC
tHZ
DOUT
m
D
OUT m+1
DOUT m+2
D
OUT m+3
t
LZ
t
OH
t
OH
t
OH
tOH
tRCD
tRAS
t
RC
CAS Latency
DON'T CARE
UNDEFINED
t
RP
Notes:
1) CAS latency = 2, Burst Length = 4
2) X16: A9 and A11 = "Don't Care"
X32: A8, A9, and A11 = "Don't Care"
58
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
SINGLE WRITE - WITHOUT AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
t
CL
tCH
CLK
CKE
t
CKS tCKH
t
CMS
tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
PRECHARGE
NOP
ACTIVE
NOP
t
CMS tCMH
DQM/DQML
DQMH/DQM0-3
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
ROW
ROW
BANK
AS
t
AH
ALL BANKS
ROW
SINGLE BANK
AS
t
AH
DISABLE AUTO PRECHARGE
BANK
BA0, BA1
BANK
BANK
t
DS
t
DH
DQ
DIN
m
t
t
t
RCD
RAS
RC
tRP
DON'T CARE
t
WR
Notes:
1) Burst Length = 1
2) X16: A9 and A11 = "Don't Care"
X32: A8, A9, and A11 = "Don't Care"
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
59
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
WRITE - WITHOUT AUTO PRECHARGE
T9
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
t
CL
tCH
CLK
CKE
t
CKS tCKH
t
CMS tCMH
COMMAND
ACTIVE
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
PRECHARGE
NOP
t
CMS tCMH
DQM/DQML
DQMH/DQM0-3
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
ROW
ROW
BANK
AS
t
AH
ALL BANKS
ROW
AS
t
AH
SINGLE BANK
BANK
DISABLE AUTO PRECHARGE
BANK
BA0, BA1
BANK
t
DS
t
DH
t
DS
t
DH
t
DS
tDH
t
DS
tDH
DQ
DIN
m
DIN m+
1
DIN m+
2
DIN m+3
t
t
t
RCD
RAS
RC
t
WR
tRP
DON'T CARE
Notes:
1) Burst Length = 4
2) X16: A9 and A11 = "Don't Care"
X32: A8, A9, and A11 = "Don't Care"
60
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
SINGLE WRITE - WITH AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
t
CL
tCH
CLK
CKE
t
CKS tCKH
t
CMS
tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
PRECHARGE
NOP
ACTIVE
NOP
t
CMS tCMH
DQM/DQML
DQMH/DQM0-3
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
ROW
ROW
BANK
AS
t
AH
ALL BANKS
ROW
SINGLE BANK
AS
t
AH
DISABLE AUTO PRECHARGE
BANK
BA0, BA1
BANK
BANK
t
DS
t
DH
DQ
DIN
m
t
t
t
RCD
RAS
RC
tRP
DON'T CARE
t
WR
Notes:
1) Burst Length = 1
2) X16: A9 and A11 = "Don't Care"
X32: A8, A9, and A11 = "Don't Care"
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
61
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
WRITE - WITH AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
CK
t
CL
tCH
CLK
CKE
t
CKS tCKH
t
CMS
tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
ACTIVE
t
CMS tCMH
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(2)
ROW
ROW
BANK
A0-A9, A11
A10
ROW
AS
t
AH
ENABLE AUTO PRECHARGE
ROW
AS
t
AH
BA0, BA1
BANK
BANK
t
DS
t
DH
t
DS
t
DH
t
DS
tDH
t
DS
tDH
DQ
DIN
m
DIN m+1
DIN m+2
DIN m+3
t
t
t
RCD
RAS
RC
t
WR
tRP
DON'T CARE
Notes:
1) Burst Length = 4
2) X16: A9 and A11 = "Don't Care"
X32: A8, A9, and A11 = "Don't Care"
62
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
ORDERING INFORMATION - VDD = 2.5V
Commercial Range: 0°C to 70°C
Frequency Speed (ns) Order Part No.
Package
133MHz
100MHz
7
IS42LS81600AL-7T
IS42LS81600AL-10T
54-PinTSOPII
54-PinTSOPII
10
Frequency Speed (ns) Order Part No.Package
133MHz
7
IS42LS16800AL-7B
IS42LS16800AL-7T
54-PinBGA
54-PinTSOPII
100MHz
10
IS42LS16800AL-10B
IS42LS16800AL-10T
54-PinBGA
54-PinTSOPII
Frequency Speed (ns) Order Part No.Package
133MHz
7
IS42LS32400AL-7B
IS42LS32400AL-7T
90-Pin BGA
86-PinTSOPII
100MHz
10
IS42LS32400AL-10B 90-Pin BGA
IS42LS32400AL-10T 86-Pin TSOPII
ORDERING INFORMATION - VDD = 2.5V
Industrial Range: -40°C to 85°C
Frequency Speed (ns) Order Part No.
Package
54-Pin TSOPII
IS42LS81600AL-10TI 54-Pin TSOPII
133MHz
100MHz
7
IS42LS81600AL-7TI
10
Frequency
Speed(ns) Order Part No.
Package
133MHz
7
IS42LS16800AL-7BI
IS42LS16800AL-7TI
54-Pin BGA
54-Pin TSOPII
100MHz
10
IS42LS16800AL-10BI 54-Pin BGA
IS42LS16800AL-10TI 54-Pin TSOPII
Frequency
Speed(ns) Order Part No.
Package
133MHz
7
IS42LS32400AL-7BI
IS42LS32400AL-7TI
90-Pin BGA
86-Pin TSOPII
100MHz
10
IS42LS32400AL-10BI 90-Pin BGA
IS42LS32400AL-10TI 86-Pin TSOPII
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
63
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
ORDERING INFORMATION - VDD = 2.5V
Commercial Range: 0°C to 70°C
Frequency Speed (ns) Order Part No.
Package
133MHz
100MHz
7
IS42LS81600AL-7TL
54-Pin TSOPII, Lead-free
10
IS42LS81600AL-10TL 54-Pin TSOPII, Lead-free
Frequency Speed (ns) Order Part No.
Package
133MHz
7
IS42LS16800AL-7BL
IS42LS16800AL-7TL
54-Pin BGA, Lead-free
54-Pin TSOPII, Lead-free
100MHz
10
IS42LS16800AL-10BL
IS42LS16800AL-10TL
54-Pin BGA, Lead-free
54-Pin TSOPII, Lead-free
Frequency Speed (ns) Order Part No.
Package
133MHz
7
IS42LS32400AL-7BL
IS42LS32400AL-7TL
90-Pin BGA, Lead-free
86-Pin TSOPII, Lead-free
100MHz
10
IS42LS32400AL-10BL
IS42LS32400AL-10TL
90-Pin BGA, Lead-free
86-Pin TSOPII, Lead-free
ORDERING INFORMATION - VDD = 2.5V
Industrial Range: -40°C to 85°C
Frequency Speed (ns) Order Part No.
Package
54-Pin TSOPII, Lead-free
IS42LS81600AL-10TLI 54-Pin TSOPII, Lead-free
133MHz
100MHz
7
IS42LS81600AL-7TLI
10
Frequency Speed (ns) Order Part No.
Package
133MHz
7
IS42LS16800AL-7BLI
IS42LS16800AL-7TLI
54-Pin BGA, Lead-free
54-Pin TSOPII, Lead-free
100MHz
10
IS42LS16800AL-10BLI 54-PinBGA,Lead-free
IS42LS16800AL-10TLI 54-Pin TSOPII, Lead-free
Frequency Speed (ns) Order Part No.
Package
133MHz
7
IS42LS32400AL-7BLI
IS42LS32400AL-7TLI
90-Pin BGA, Lead-free
86-Pin TSOPII, Lead-free
100MHz
10
IS42LS32400AL-10BLI 90-PinBGA,Lead-free
IS42LS32400AL-10TLI 86-PinTSOPII, Lead-free
64
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
ORDERING INFORMATION - VDD = 3.3V
Commercial Range: 0°C to 70°C
Frequency Speed (ns) Order Part No.
Package
133MHz
100MHz
7
IS42S81600AL-7T
IS42S81600AL-10T
54-Pin TSOPII
54-Pin TSOPII
10
Frequency
Speed(ns) Order Part No.
Package
133MHz
7
IS42S16800AL-7B
IS42S16800AL-7T
54-Pin BGA
54-Pin TSOPII
100MHz
10
IS42S16800AL-10B
IS42S16800AL-10T
54-Pin BGA
54-Pin TSOPII
Frequency
Speed(ns) Order Part No.
Package
133MHz
7
IS42S32400AL-7B
IS42S32400AL-7T
90-Pin BGA
86-Pin TSOPII
100MHz
10
IS42S32400AL-10B
IS42S32400AL-10T
90-Pin BGA
86-Pin TSOPII
ORDERING INFORMATION - VDD = 3.3V
Industrial Range: -40°C to 85°C
Frequency Speed (ns) Order Part No.
Package
54-Pin TSOPII
IS42S81600AL-10TI 54-Pin TSOPII
133MHz
100MHz
7
IS42S81600AL-7TI
10
Frequency
Speed(ns) Order Part No.
Package
133MHz
7
IS42S16800AL-7BI
IS42S16800AL-7TI
54-Pin BGA
54-Pin TSOPII
100MHz
10
IS42S16800AL-10BI 54-Pin BGA
IS42S16800AL-10TI 54-Pin TSOPII
Frequency
Speed(ns) Order Part No.
Package
133MHz
7
IS42S32400AL-7BI
IS42S32400AL-7TI
90-PinBGA
86-Pin TSOPII
100MHz
10
IS42S32400AL-10BI 90-PinBGA
IS42S32400AL-10TI 86-Pin TSOPII
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
65
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
®
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
ISSI
ORDERING INFORMATION - VDD = 3.3V
Commercial Range: 0°C to 70°C
Frequency Speed (ns) Order Part No.
Package
133MHz
100MHz
7
IS42S81600AL-7TL
54-Pin TSOPII, Lead-free
10
IS42S81600AL-10TL 54-Pin TSOPII, Lead-free
Frequency Speed (ns) Order Part No.
Package
133MHz
7
IS42S16800AL-7BL
IS42S16800AL-7TL
54-Pin BGA, Lead-free
54-Pin TSOPII, Lead-free
100MHz
10
IS42S16800AL-10BL 54-Pin BGA, Lead-free
IS42S16800AL-10TL 54-Pin TSOPII
Frequency Speed (ns) Order Part No.
Package
133MHz
7
IS42S32400AL-7BL
IS42S32400AL-7TL
90-Pin BGA, Lead-free
86-Pin TSOPII, Lead-free
100MHz
10
IS42S32400AL-10BL 90-Pin BGA, Lead-free
IS42S32400AL-10TL 86-Pin TSOPII, Lead-free
ORDERING INFORMATION - VDD = 3.3V
Industrial Range: -40°C to 85°C
Frequency Speed (ns) Order Part No.
Package
133MHz
100MHz
7
IS42S81600AL-7TLI 54-Pin TSOPII, Lead-free
IS42S81600AL-10TLI 54-Pin TSOPII, Lead-free
10
Frequency Speed (ns) Order Part No.
Package
133MHz
7
IS42S16800AL-7BLI 54-PinBGA, Lead-free
IS42S16800AL-7TLI 54-Pin TSOPII , Lead-free
100MHz
10
IS42S16800AL-10BLI 54-Pin BGA, Lead-free
IS42S16800AL-10TLI 54-Pin TSOPII, Lead-free
Frequency Speed (ns) Order Part No.
Package
133MHz
7
IS42S32400AL-7BLI 90-PinBGA, Lead-free
IS42S32400AL-7TLI 86-Pin TSOPII, Lead-free
100MHz
10
IS42S32400AL-10BLI 90-Pin BGA, Lead-free
IS42S32400AL-10TLI 86-Pin TSOPII, Lead-free
66
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY
INFORMATION Rev. 00A
09/18/03
相关型号：
©2020 ICPDF网 联系我们和版权申明