IS42S16100C1_07 [ISSI]
512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM; 512K字×16位×2组（ 16兆位）同步动态RAM
| 型号： | IS42S16100C1_07 |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
| 文件： | 总81页 (文件大小：913K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
IS42S16100C1
512K Words x 16 Bits x 2 Banks (16-MBIT)
SYNCHRONOUS DYNAMIC RAM
ISSI
NOVEMBER 2006
FEATURES
DESCRIPTION
• Clock frequency: 200, 166, 143 MHz
ISSI’s 16Mb Synchronous DRAM IS42S16100C1 is
organized as a 524,288-word x 16-bit x 2-bank for
improvedperformance. ThesynchronousDRAMs
achieve high-speed data transfer using pipeline
architecture. All inputs and outputs signals refer to the
rising edge of the clock input.
• Fully synchronous; all signals referenced to a
positive clock edge
• Two banks can be operated simultaneously and
independently
• Dual internal bank controlled by A11
(bank select)
PIN CONFIGURATIONS
50-Pin TSOP (Type II)
• Single 3.3V power supply
• LVTTL interface
VDD
DQ0
DQ1
GNDQ
DQ2
DQ3
VDDQ
DQ4
DQ5
GNDQ
DQ6
DQ7
VDDQ
LDQM
WE
1
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
GND
DQ15
IDQ14
GNDQ
DQ13
DQ12
VDDQ
DQ11
DQ10
GNDQ
DQ9
DQ8
VDDQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
• Programmable burst length
– (1, 2, 4, 8, full page)
2
3
4
5
• Programmable burst sequence:
Sequential/Interleave
6
7
8
• 4096 refresh cycles every 64 ms
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
CAS
RAS
CS
• Burst termination by burst stop and
precharge command
A11
A10
A0
A1
• Byte controlled by LDQM and UDQM
• Industrial temperature up to 143 MHz
• Packages 400-mil 50-pin TSOP-II, 60-ball fBGA
• Lead-free package option
A2
A3
VDD
A4
GND
PIN DESCRIPTIONS
CAS
ColumnAddressStrobeCommand
WriteEnable
A0-A11
A0-A10
A11
Address Input
WE
Row Address Input
Bank Select Address
Column Address Input
DataDQ
LDQM
UDQM
VDD
Lower Bye, Input/Output Mask
Upper Bye, Input/Output Mask
Power
A0-A7
DQ0 to DQ15
CLK
GND
VDDQ
GNDQ
NC
Ground
System Clock Input
Clock Enable
Power Supply for DQ Pin
Ground for DQ Pin
NoConnection
CKE
CS
Chip Select
RAS
RowAddressStrobeCommand
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
1
Rev. D
11/03/06
®
IS42S16100C1
ISSI
PIN CONFIGURATION
PACKAGE CODE: B 60 BALL FBGA (Top View) (10.1 mm x 6.4 mm Body, 0.65 mm Ball Pitch)
1 2 3 4 5 6 7
A
VSS DQ15
DQ14 VSSQ
DQ13 VDDQ
DQ12 DQ11
DQ10 VSSQ
DQ9 VDDQ
DQ8 NC
DQ0 VDD
VDDQ DQ1
VSSQ DQ2
DQ4 DQ3
VDDQ DQ5
VSSQ DQ6
B
C
D
E
F
G
H
J
NC
NC
DQ7
NC
NC
NC UDQM
NC CLK
CKE NC
NC
LDQM WE
K
L
CAS
CS
RAS
NC
NC
A0
M
N
P
R
A11
A8
A9
A7
A5
A4
NC
A10
A1
A6
A2
VSS
VDD
A3
PIN DESCRIPTIONS
A0-A10
A0-A7
A11
Row Address Input
Column Address Input
Bank Select Address
Data I/O
WE
WriteEnable
LDQM,UDQM
x16 Input/Output Mask
Power
VDD
DQ0 to DQ15
CLK
Vss
VDDQ
VssQ
NC
Ground
System Clock Input
Clock Enable
Power Supply for I/O Pin
Ground for I/O Pin
NoConnection
CKE
CS
Chip Select
RAS
RowAddressStrobeCommand
ColumnAddressStrobeCommand
CAS
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
11/03/06
®
IS42S16100C1
ISSI
PIN FUNCTIONS
Pin No.
Symbol
Type
Function (In Detail)
20 to 24
27 to 32
A0-A10
Input Pin
A0 to A10 are address inputs. A0-A10 are used as row address inputs during active
command input and A0-A7 as column address inputs during read or write command
input. A10 is also used to determine the precharge mode during other commands. If
A10 is LOW during precharge command, the bank selected by A11 is precharged,
but if A10 is HIGH, both banks will be precharged.
When A10 is HIGH in read or write command cycle, the precharge starts
automatically after the burst access.
These signals become part of the OP CODE during mode register set command
input.
19
A11
Input Pin
A11 is the bank selection signal. When A11 is LOW, bank 0 is selected and when
high, bank 1 is selected. This signal becomes part of the OP CODE during mode
register set command input.
16
34
CAS
Input Pin
Input Pin
CAS, in conjunction with the RAS and WE, forms the device command. See the
“Command Truth Table” item for details on device commands.
CKE
The CKE input determines whether the CLK input is enabled within the device. When
is CKE HIGH, the next rising edge of the CLK signal will be valid, and when LOW,
invalid. When CKE is LOW, the device will be in either the power-down mode, the
clock suspend mode, or the self refresh mode. The CKE is an asynchronous input.
35
18
CLK
Input Pin
Input Pin
CLK is the master clock input for this device. Except for CKE, all inputs to this device
are acquired in synchronization with the rising edge of this pin.
CS
The CS input determines whether command input is enabled within the device.
Command input is enabled when CS is LOW, and disabled with CS is HIGH. The
device remains in the previous state when CS is HIGH.
2, 3, 5, 6, 8, 9, 11 DQ0 to
DQ Pin
DQ0 to DQ15 are DQ pins. DQ through these pins can be controlled in byte units
using the LDQM and UDQM pins.
12, 39, 40, 42, 43,
45, 46, 48, 49
DQ15
14, 36
LDQM,
UDQM
Input Pin
LDQM and UDQM control the lower and upper bytes of the DQ buffers. In read
mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW,
the corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go
to the HIGH impedance state when LDQM/UDQM is HIGH. This function
corresponds to OE in conventional DRAMs. In write mode, LDQM and UDQM control
the input buffer. When LDQM or UDQM is LOW, the corresponding buffer byte is
enabled, and data can be written to the device. When LDQM or UDQM is HIGH, input
data is masked and cannot be written to the device.
17
15
RAS
WE
Input Pin
Input Pin
RAS, in conjunction with CAS and WE, forms the device command. See the
“Command Truth Table” item for details on device commands.
WE, in conjunction with RAS and CAS, forms the device command. See the
“Command Truth Table” item for details on device commands.
7, 13, 38, 44
1, 25
VDDQ
VDD
Power Supply Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
VDDQ is the output buffer power supply.
VDD is the device internal power supply.
GNDQ is the output buffer ground.
GND is the device internal ground.
4, 10, 41, 47
26, 50
GNDQ
GND
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
3
Rev. D
11/03/06
®
IS42S16100C1
ISSI
FUNCTIONAL BLOCK DIAGRAM
CLK
CKE
CS
RAS
CAS
WE
COMMAND
DECODER
&
MEMORY CELL
ARRAY
ROW
ADDRESS
BUFFER
2048
CLOCK
MODE
REGISTER
BANK 0
11
GENERATOR
11
A11
DQM
DATA IN
BUFFER
11
SENSE AMP I/O GATE
256
16
16
A10
8
SELF
DQ 0-15
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
REFRESH
CONTROLLER
COLUMN DECODER
REFRESH
8
CONTROLLER
256
DATA OUT
BUFFER
SENSE AMP I/O GATE
REFRESH
COUNTER
16
16
MEMORY CELL
ARRAY
VDD/VDDQ
GND/GNDQ
2048
ROW
ADDRESS
BUFFER
BANK 1
ROW
ADDRESS
LATCH
11
11
11
S16BLK.eps
4
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Rev. D
11/03/06
®
IS42S16100C1
ISSI
(1)
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameters
Rating
Unit
VDD MAX
VDDQ MAX
VIN
Maximum Supply Voltage
Maximum Supply Voltage for Output Buffer
Input Voltage
–1.0 to +4.6 V
–1.0 to +4.6 V
–1.0 to +4.6 V
–1.0 to +4.6 V
VOUT
OutputVoltage
PD MAX
ICS
AllowablePowerDissipation
OutputShortedCurrent
OperatingTemperature
1
50
W
mA
TOPR
Com
Ind.
0 to +70
-40 to +85 °C
°C
TSTG
StorageTemperature
–55 to +150 °C
(2)
DC RECOMMENDED OPERATING CONDITIONS (At TA = 0 to +70°C)
Symbol
VDD,VDDQ
VIH
Parameter
Min.
3.0
2.0
Typ.
3.3
—
Max.
3.6
Unit
V
V
Supply Voltage
InputHighVoltage(3)
InputLowVoltage(4)
VDD + 0.3
+0.8
VIL
-0.3
—
V
(1,2)
CAPACITANCE CHARACTERISTICS
(At TA = 0 to +25°C, VDD = VDDQ = 3.3 0.3V, f = 1 MHz)
Symbol
CIN1
Parameter
Typ.
—
—
Max.
Unit
pF
pF
InputCapacitance:A0-A11
Input Capacitance: (CLK, CKE, CS, RAS, CAS, WE, LDQM, UDQM)
DataInput/OutputCapacitance:DQ0-DQ15
4
4
5
CIN2
CI/O
—
pF
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. All voltages are referenced to GND.
3. VIH (max) = VDDQ + 2.0V with a pulse width ≤ 3 ns.
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5
Rev. D
11/03/06
®
IS42S16100C1
ISSI
DC ELECTRICAL CHARACTERISTICS (Recommended Operation Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
Speed Min. Max. Unit
IIL
Input Leakage Current
0V ≤ VIN ≤ VDD, with pins other than
the tested pin at 0V
–5
5
µA
IOL
Output Leakage Current
Output is disabled, 0V ≤ VOUT ≤ VDD
–5
2.4
—
5
—
0.4
µA
V
V
VOH
VOL
ICC1
Output High Voltage Level IOUT = –2 mA
Output Low Voltage Level IOUT = +2 mA
Operating Current(1,2)
One Bank Operation, CAS latency = 3 Com.
-5
-6
-7
-7
—
—
—
—
170
160
140
160
mA
mA
mA
mA
Burst Length=1
tRC ≥ tRC (min.)
IOUT = 0mA
Com.
Com.
Ind.
ICC2P
Precharge Standby CurrentCKE ≤ VIL (MAX)
tCK = tCK (MIN)
Com.
Ind.
Com.
Ind.
—
—
—
—
—
—
—
—
3
4
2
3
mA
mA
mA
mA
ICC2PS
(In Power-Down Mode)
tCK = ∞
ICC3N
ICC3NS
Active Standby Current
(In Non Power-Down Mode)
CKE ≥ VIH (MIN)
tCK = tCK (MIN)
tCK = ∞
—
—
—
—
—
—
40
30
30
mA
mA
mA
Com.
Ind.
ICC4
Operating Current
(In Burst Mode)(1)
tCK = tCK (MIN)
IOUT = 0mA
CAS latency = 3 Com.
-5
-6
-7
-7
—
—
—
—
170
150
130
150
mA
mA
mA
mA
Com.
Com.
Ind.
CAS latency = 2 Com.
-5
-6
-7
-7
—
—
—
—
170
150
130
150
mA
mA
mA
m
Com.
Com.
Ind.
ICC5
Auto-Refresh Current
tRC = tRC (MIN)
CAS latency = 3 Com.
-5
-6
-7
-7
—
—
—
—
120
100
70
mA
mA
mA
mA
Com.
Com.
Ind.
90
CAS latency = 2 Com.
-5
-6
-7
-7
—
—
—
—
120
100
70
mA
mA
mA
mA
Com.
Com.
Ind.
90
ICC6
Self-Refresh Current
CKE ≤ 0.2V
—
—
1
mA
Notes:
1. These are the values at the minimum cycle time. Since the currents are transient, these values decrease as the cycle time
increases. Also note that a bypass capacitor of at least 0.01 µF should be inserted between VDD and GND for each
memory chip to suppress power supply voltage noise (voltage drops) due to these transient currents.
2. Icc1 and Icc4 depend on the output load. The maximum values for Icc1 and Icc4 are obtained with the output open state.
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
11/03/06
®
IS42S16100C1
ISSI
(1,2,3)
AC CHARACTERISTICS
-5
-6
-7
Symbol Parameter
Min. Max.
Min.
Max.
Min.
Max.
Units
tCK3
tCK2
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
5
8
—
—
6
8
—
—
7
8
—
—
ns
ns
tAC3
tAC2
Access Time From CLK(4)
CAS Latency = 3
CAS Latency = 2
—
—
5
6
—
—
5.5
6
—
—
5.5
6
ns
ns
tCHI
tCL
CLK HIGH Level Width
CLK LOW Level Width
Output Data Hold Time
2
2
—
—
2.5
2.5
—
—
2.5
2.5
—
—
ns
ns
tOH3
tOH2
CAS Latency = 3
CAS Latency = 2
2
2.5
—
—
2.0
2.5
—
—
2.0
2.5
—
—
ns
ns
tLZ
Output LOW Impedance Time
Output HIGH Impedance Time(5)
0
—
0
—
0
—
ns
tHZ3
tHZ2
tDS
CAS Latency = 3
CAS Latency = 2
—
—
1.5
4
6
—
—
—
1.5
5.5
6
—
—
—
2
5.5
6
—
ns
ns
ns
Input Data Setup Time
Input Data Hold Time
Address Setup Time
Address Hold Time
tDH
1
—
—
—
—
—
—
1
1.5
1
—
—
—
—
—
1
2
1
2
1
—
—
—
—
—
ns
ns
ns
ns
ns
tAS
1.5
tAH
1
1.5
tCKS
tCKH
CKE Setup Time
1.5
1
CKE Hold Time
1
tCKA
CKE to CLK Recovery Delay Time
1CLK+3
1CLK+3
—1CLK+3
— ns
tCS
Command Setup Time (CS, RAS, CAS, WE, DQM)
Command Hold Time (CS, RAS, CAS, WE, DQM)
Command Period (REF to REF / ACT to ACT)
Command Period (ACT to PRE)
1.5
1
—
—
1.5
1
—
—
—
2
1
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
tCH
tRC
48
32
16
16
11
—
—
54
63
tRAS
tRP
—
36 100,000
42 100,000
Command Period (PRE to ACT)
—
18
16
—
—
—
—
20
16
—
—
—
—
tRCD
tRRD
tDPL3
Active Command To Read / Write Command Delay Time
Command Period (ACT [0] to ACT[1])
—
—
12
14
Input Data To Precharge
Command Delay time
CAS Latency = 3
1CLK
1CLK
1CLK
tDPL2
tDAL3
CAS Latency = 2
CAS Latency = 3
—
1CLK
—
1CLK
—
—
1CLK
—
—
ns
ns
Input Data To Active / Refresh
1CLK+tRP
1CLK+tRP
1CLK+tRP
Command Delay time (During Auto-Precharge)
tDAL2
tT
CAS Latency = 2
1CLK+tRP
—
10
64
1CLK+tRP
—
10
64
1CLK+tRP
—
10
64
ns
ns
Transition Time
1
1
1
tREF
Refresh Cycle Time (4096)
—
—
—
ms
Notes:
1. When power is first applied, memory operation should be started 100 µs after VDD and VDDQ reach their stipulated voltages. Also note that the power-on
sequence must be executed before starting memory operation.
2. Measured with t = 1 ns.
T
3. The reference level is 1.4 V when measuring input signal timing. Rise and fall times are measured between VIH (min.) and VIL (max.).
4. Access time is measured at 1.4V with the load shown in the figure below.
5. The time tHZ (max.) is defined as the time required for the output voltage to transition by 200 mV from VOH (min.) or VOL (max.) when the
output is in the high impedance state.
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7
Rev. D
11/03/06
®
IS42S16100C1
ISSI
OPERATING FREQUENCY / LATENCY RELATIONSHIPS
SYMBOL PARAMETER
-5
-6
-7
UNITS
—
Clock Cycle Time
5
200
3
6
166
3
7
143
3
ns
—
Operating Frequency
MHz
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
tCAC
tRCD
tRAC
tRC
CAS Latency
Active Command To Read/Write Command Delay Time
RAS Latency (tRCD + tCAC)
3
3
3
6
6
6
Command Period (REF to REF / ACT to ACT)
Command Period (ACT to PRE)
Command Period (PRE to ACT)
Command Period (ACT[0] to ACT [1])
9
9
9
tRAS
tRP
6
6
6
3
3
3
tRRD
tCCD
3
3
3
Column Command Delay Time
(READ, READA, WRIT, WRITA)
1
1
1
tDPL
Input Data To Precharge Command Delay Time
1
4
1
4
1
4
cycle
cycle
tDAL
Input Data To Active/Refresh Command Delay Time
(During Auto-Precharge)
tRBD
tWBD
tRQL
tWDL
Burst Stop Command To Output in HIGH-Z Delay Time
(Read)
3
0
3
0
3
0
3
0
3
0
3
0
cycle
cycle
cycle
cycle
Burst Stop Command To Input in Invalid Delay Time
(Write)
Precharge Command To Output in HIGH-Z Delay Time
(Read)
Precharge Command To Input in Invalid Delay Time
(Write)
tPQL
tQMD
tDMD
tMCD
Last Output To Auto-Precharge Start Time (Read)
DQM To Output Delay Time (Read)
-2
2
–2
2
–1
2
cycle
cycle
cycle
cycle
DQM To Input Delay Time (Write)
0
0
0
Mode Register Set To Command Delay Time
2
2
2
AC TEST CONDITIONS (Input/Output Reference Level: 1.4V)
Output Load
Input
t
CK
t
CL
t
CHI
2.8V
1.4V
50 Ω
CLK
0.0V
+1.4V
t
CS
I/O
t
CH
2.8V
1.4V
0.0V
INPUT
50 pF
tAC
t
OH
1.4V
1.4V
OUTPUT
8
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Rev. D
11/03/06
®
IS42S16100C1
ISSI
COMMANDS
Active Command
Read Command
CLK
CLK
HIGH
HIGH
CKE
CS
CKE
CS
RAS
RAS
CAS
WE
CAS
WE
(1)
COLUMN
ROW
A0-A9
A0-A9
A10
AUTO PRECHARGE
ROW
A10
A11
NO PRECHARGE
BANK 1
BANK 1
A11
BANK 0
BANK 0
Write Command
Precharge Command
CLK
CLK
HIGH
HIGH
CKE
CKE
CS
CS
RAS
RAS
CAS
WE
CAS
WE
(1)
COLUMN
A0-A9
A10
A0-A9
AUTO PRECHARGE
BANK 0 AND BANK 1
A10
A11
NO PRECHARGE
BANK 1
BANK 0 OR BANK 1
BANK 1
A11
BANK 0
BANK 0
Don't Care
Notes:
1. A8-A9 = Don’t Care.
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9
Rev. D
11/03/06
®
IS42S16100C1
ISSI
COMMANDS (cont.)
No-Operation Command
Device Deselect Command
CLK
CLK
HIGH
HIGH
CKE
CS
CKE
CS
RAS
RAS
CAS
WE
CAS
WE
A0-A9
A0-A9
A10
A11
A10
A11
Mode Register Set Command
Auto-Refresh Command
CLK
CLK
HIGH
HIGH
CKE
CS
CKE
CS
RAS
RAS
CAS
WE
CAS
WE
A0-A9
OP-CODE
OP-CODE
OP-CODE
A0-A9
A10
A11
A10
A11
Don't Care
10
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Rev. D
11/03/06
®
IS42S16100C1
ISSI
COMMANDS (cont.)
Self-Refresh Command
Power Down Command
CLK
CLK
ALL BANKS IDLE
CKE
CS
CKE
CS
NOP
NOP
RAS
RAS
NOP
CAS
WE
CAS
WE
NOP
A0-A9
A0-A9
A10
A11
A10
A11
Clock Suspend Command
Burst Stop Command
CLK
CKE
CS
CLK
BANK(S) ACTIVE
HIGH
CKE
NOP
NOP
CS
RAS
RAS
NOP
CAS
WE
CAS
WE
NOP
A0-A9
A0-A9
A10
A11
A10
A11
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
11
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Mode Register Set Command
When the A10 pin is HIGH, this command functions as a
read with auto-precharge command. After the burst read
completes, the bank selected by pin A11 is precharged.
WhentheA10pinisLOW,thebankselectedbytheA11pin
remainsintheactivatedstateaftertheburstreadcompletes.
(CS, RAS, CAS, WE = LOW)
The IS42S16100C1 product incorporates a register that
defines the device operating mode. This command
functions as a data input pin that loads this register from
the pins A0 to A11. When power is first applied, the
stipulated power-on sequence should be executed and
thentheIS42S16100C1shouldbeinitializedbyexecuting
a mode register set command.
Write Command
(CS, CAS, WE = LOW, RAS = HIGH)
Notethatthemoderegistersetcommandcanbeexecuted
onlywhenbothbanksareintheidlestate(i.e.deactivated).
When burst write mode has been selected with the mode
register set command, this command selects the bank
specified by the A11 pin and starts a burst write operation
at the start address specified by pins A0 to A9. This first
data must be input to the DQ pins in the cycle in which this
command.
Another command cannot be executed after a mode
registersetcommanduntilafterthepassageoftheperiod
tMCD, which is the period required for mode register set
commandexecution.
Theselectedbankmustbeactivatedbeforeexecutingthis
command.
Active Command
When A10 pin is HIGH, this command functions as a write
with auto-precharge command. After the burst write
completes, the bank selected by pin A11 is precharged.
When the A10 pin is low, the bank selected by the A11 pin
remainsintheactivatedstateaftertheburstwritecompletes.
(CS, RAS = LOW, CAS, WE= HIGH)
The IS42S16100C1 includes two banks of 4096 rows
each. This command selects one of the two banks
according to the A11 pin and activates the row selected
by the pins A0 to A10.
After the input of the last burst write data, the application
mustwaitforthewriterecoveryperiod(tDPL,tDAL)toelapse
according to CAS latency.
This command corresponds to the fall of the RAS signal
from HIGH to LOW in conventional DRAMs.
Precharge Command
(CS, RAS, WE = LOW, CAS = HIGH)
Auto-Refresh Command
(CS, RAS, CAS = LOW, WE, CKE = HIGH)
This command starts precharging the bank selected by
pins A10 and A11. When A10 is HIGH, both banks are
prechargedatthesametime.WhenA10isLOW,thebank
selected by A11 is precharged. After executing this
command, the next command for the selected bank(s) is
executed after passage of the period tRP, which is the
periodrequiredforbankprecharging.
This command executes the auto-refresh operation. The
row address and bank to be refreshed are automatically
generatedduringthisoperation.
Bothbanksmustbeplacedintheidlestatebeforeexecuting
this command.
The stipulated period (tRC) is required for a single refresh
operation,andnoothercommandscanbeexecutedduring
this period.
This command corresponds to the RASsignal from LOW
to HIGH in conventional DRAMs
The device goes to the idle state after the internal refresh
operationcompletes.
Read Command
(CS, CAS = LOW, RAS, WE = HIGH)
Thiscommandmustbeexecutedatleast4096timesevery
128 ms.
This command selects the bank specified by the A11 pin
and starts a burst read operation at the start address
specified by pins A0 to A9. Data is output following CAS
latency.
This command corresponds to CBR auto-refresh in
conventionalDRAMs.
The selected bank must be activated before executing
this command.
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Self-Refresh Command
Power-Down Command
(CS, RAS, CAS, CKE = LOW, WE = HIGH)
(CKE = LOW)
This command executes the self-refresh operation. The
row address to be refreshed, the bank, and the refresh
interval are generated automatically internally during this
operation.Theself-refreshoperationisstartedbydropping
theCKEpinfromHIGHtoLOW.Theself-refreshoperation
continuesaslongastheCKEpinremainsLOWandthere
is no need for external control of any other pins. The
self-refreshoperationisterminatedbyraisingtheCKEpin
fromLOWtoHIGH.Thenextcommandcannotbeexecuted
untilthedeviceinternalrecoveryperiod(tRC)haselapsed.
After the self-refresh, since it is impossible to determine
theaddressofthelastrowtoberefreshed,anauto-refresh
shouldimmediatelybeperformedforalladdresses(4096
cycles).
When both banks are in the idle (inactive) state, or when
at least one of the banks is not in the idle (inactive) state,
this command can be used to suppress device power
dissipation by reducing device internal operations to the
absoluteminimum.Power-downmodeisstartedbydropping
the CKE pin from HIGH to LOW. Power-down mode
continuesaslongastheCKEpinisheldlow.Allpinsother
than the CKE pin are invalid and none of the other
commands can be executed in this mode. The power-
down operation is terminated by raising the CKE pin from
LOW to HIGH. The next command cannot be executed
until the recovery period (tCKA) has elapsed.
Sincethiscommanddiffersfromtheself-refreshcommand
described above in that the refresh operation is not
performed automatically internally, the refresh operation
must be performed within the refresh period (tREF). Thus
the maximum time that power-down mode can be held is
just under the refresh cycle time.
Both banks must be placed in the idle state before
executing this command.
Burst Stop Command
(CS, WE, = LOW, RAS, CAS = HIGH)
Clock Suspend
(CKE = LOW)
The command forcibly terminates burst read and write
operations. When this command is executed during a
burst read operation, data output stops after the CAS
latency period has elapsed.
This command can be used to stop the device internal
clock temporarily during a read or write cycle. Clock
suspend mode is started by dropping the CKE pin from
HIGHtoLOW. Clocksuspendmodecontinuesaslongas
theCKEpinisheldLOW.AllinputpinsotherthantheCKE
pin are invalid and none of the other commands can be
executed in this mode. Also note that the device internal
stateismaintained.Clocksuspendmodeisterminatedby
raising the CKE pin from LOW to HIGH, at which point
device operation restarts. The next command cannot be
executed until the recovery period (tCKA) has elapsed.
No Operation
(CS, = LOW, RAS, CAS, WE = HIGH)
This command has no effect on the device.
Device Deselect Command
(CS = HIGH)
Sincethiscommanddiffersfromtheself-refreshcommand
described above in that the refresh operation is not
performed automatically internally, the refresh operation
must be performed within the refresh period (tREF). Thus
the maximum time that clock suspend mode can be held
is just under the refresh cycle time.
This command does not select the device for an object of
operation. In other words, it performs no operation with
respect to the device.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
13
Rev. D
11/03/06
®
IS42S16100C1
ISSI
(1,2)
COMMAND TRUTH TABLE
CKE
Symbol Command
n-1
n
X
H
L
CS RAS CAS WEDQM A11 A10 A9-A0 I/On
MRS
REF
ModeRegisterSet(3,4)
Auto-Refresh(5)
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
H
X
X
X
L
L
L
L
L
L
L
L
H
H
H
L
L
L
L
H
H
X
X
X
X
L
H
H
L
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
OP CODE
X
X
X
BS
X
X
X
L
X
X
X
X
HIGH-Z
HIGH-Z
SREF
PRE
PALL
ACT
Self-Refresh(5,6)
Precharge Selected Bank
Precharge Both Banks
Bank Activate(7)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
BS Row Row
(18)
WRIT
WRITA
READ
READA
BST
Write
H
H
H
H
H
H
X
X
X
X
BS
BS
BS
BS
X
X
X
X
X
L Column
H Column
L Column
WriteWithAuto-Precharge(8)
Read(8)
ReadWithAuto-Precharge(8)
Burst Stop(9)
L
(18)
(18)
(18)
H
H
L
H
X
X
X
X
H Column
X
X
X
X
X
X
X
X
X
X
X
X
NOP
NoOperation
DESL
SBY
ENB
Device Deselect
Clock Suspend / Standby Mode
Data Write / Output Enable
Data Mask / Output Disable
X
H
H
Active
HIGH-Z
MASK
H
X
(1,2)
DQM TRUTH TABLE
CKE
DQM
Symbol Command
n-1
n
UPPER
LOWER
ENB
Data Write / Output Enable
Data Mask / Output Disable
Upper Byte Data Write / Output Enable
Lower Byte Data Write / Output Enable
H
H
H
H
H
H
X
L
H
L
X
H
X
L
H
X
L
X
H
MASK
ENBU
ENBL
X
X
X
X
X
MASKU Upper Byte Data Mask / Output Disable
MASKL Lower Byte Data Mask / Output Disable
(1,2)
CKE TRUTH TABLE
CKE
Symbol Command
CurrentState
Active
Other States
n-1
H
L
L
H
H
n
CS RAS CAS WE A11 A10 A9-A0
SPND Start Clock Suspend Mode
L
L
H
H
L
X
X
X
L
X
X
X
L
X
X
X
L
X
X
X
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
—
Clock Suspend
—
Terminate Clock Suspend Mode Clock Suspend
REF
SELF
Auto-Refresh
Start Self-Refresh Mode
Idle
Idle
L
L
L
SELFX TerminateSelf-RefreshMode
Self-Refresh
L
L
H
H
L
H
H
X
H
X
H
X
X
X
X
X
X
X
PDWN StartPower-DownMode
Idle
H
H
L
L
L
H
H
X
H
X
H
X
X
X
X
X
X
X
—
TerminatePower-DownMode
Power-Down
L
H
X
X
X
X
X
X
X
14
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
11/03/06
®
IS42S16100C1
ISSI
(1,2)
OPERATION COMMAND TABLE
Current State Command
Operation
CS RAS CAS WE A11 A10 A9-A0
Idl
e
DESL
No Operation or Power-Down(12)
No Operation or Power-Down(12)
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
X
H
H
H
H
L
X
H
H
L
X
H
L
X
X
X
V
V
V
V
X
X
X
X
X
NOP
X
BST
No Operation or Power-Down
X
(18)
READ / READA
WRIT/WRITA
ACT
Illegal
H
L
V
V
V
V
(18)
(18)
Illegal
L
V
Row Active
H
H
L
H
L
V
PRE/PALL
REF/SELF
MRS
No Operation
Auto-Refresh or Self-Refresh(13)
L
V
X
L
H
L
X
X
Mode Register Set
L
L
OP CODE
Row Active
DESL
No Operation
X
H
H
H
H
L
X
H
H
L
X
H
L
X
X
X
V
V
V
V
X
X
X
X
X
X
X
NOP
No Operation
BST
No Operation
Read Start(17)
Write Start(17)
Illegal(10)
(18)
READ/READA
WRIT/WRITA
ACT
H
L
V
V
(18)
(18)
L
V
V
V
H
H
L
H
L
V
PRE/PALL
REF/SELF
MRS
Precharge(15)
L
V
X
Illegal
L
H
L
X
X
Illegal
L
L
OP CODE
Read
DESL
Burst Read Continues, Row Active When Done
Burst Read Continues, Row Active When Done
Burst Interrupted, Row Active After Interrupt
Burst Interrupted, Read Restart After Interrupt(16)
Burst Interrupted Write Start After Interrupt(11,16)
Illegal(10)
X
H
H
H
H
L
X
H
H
L
X
H
L
X
X
X
V
V
V
V
X
X
X
X
X
X
X
NOP
BST
(18)
READ/READA
WRIT/WRITA
ACT
H
L
V
V
(18)
(18)
L
V
V
V
H
H
L
H
L
V
PRE/PALL
REF/SELF
MRS
Burst Read Interrupted, Precharge After Interrupt
Illegal
L
V
X
L
H
L
X
X
Illegal
L
L
OP CODE
Write
DESL
Burst Write Continues, Write Recovery When Done
Burst Write Continues, Write Recovery When Done
Burst Write Interrupted, Row Active After Interrupt
Burst Write Interrupted, Read Start After Interrupt(11,16)
Burst Write Interrupted, Write Restart After Interrupt(16)
Illegal(10)
X
H
H
H
H
L
X
H
H
L
X
H
L
X
X
X
V
V
V
V
X
X
X
X
X
X
X
NOP
BST
(18)
READ/READA
WRIT/WRITA
ACT
H
L
V
V
(18)
(18)
L
V
V
V
H
H
L
H
L
V
PRE/PALL
REF/SELF
MRS
Burst Write Interrupted, Precharge After Interrupt
Illegal
L
V
X
X
L
H
L
X
Illegal
L
L
OP CODE
Read With
Auto-
DESL
NOP
Burst Read Continues, Precharge When Done
Burst Read Continues, Precharge When Done
H
L
X
H
X
H
X
H
X
X
X
X
X
X
Precharge
BST
Illegal
L
L
L
L
L
L
L
H
H
H
L
H
L
L
H
L
X
V
V
V
V
X
X
X
(18)
READ/READA
WRIT/WRITA
ACT
Illegal
V
V
(18)
(18)
Illegal
L
V
V
V
Illegal(10)
Illegal(10)
Illegal
H
H
L
H
L
V
PRE/PALL
REF/SELF
MRS
L
V
X
X
L
H
L
X
Illegal
L
L
OP CODE
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
15
Rev. D
11/03/06
®
IS42S16100C1
ISSI
(1,2)
OPERATION COMMAND TABLE
Current State Command
Operation
CS RAS CAS WE A11 A10 A9-A0
Write With
Auto-Precharge
DESL
Burst Write Continues, Write Recovery And Precharge
When Done
H
X
X
X
X
X
X
NOP
Burst Write Continues, Write Recovery And Precharge
L
L
L
L
L
L
L
L
H
L
L
H
H
H
H
L
H
H
L
H
L
X
X
V
V
V
V
X
X
X
V
V
V
V
X
X
BST
Illegal
Illegal
Illegal
X
(18)
READ/READA
WRIT/WRITA
ACT
H
L
V
V
V
(18)
(18)
L
(10)
Illegal
H
H
L
H
L
(10)
PRE/PALL
REF/SELF
MRS
Illegal
L
X
X
Illegal
L
H
L
Illegal
L
L
OPCODE
Row Precharge
DESL
No Operation, Idle State After tRP Has Elapsed
No Operation, Idle State After tRP Has Elapsed
No Operation, Idle State After tRP Has Elapsed
X
H
H
H
H
L
X
H
H
L
X
H
L
X
X
X
V
V
V
V
X
X
X
X
X
X
NOP
BST
X
(18)
(10)
READ/READA
WRIT/WRITA
ACT
Illegal
L
L
L
L
L
L
H
L
V
V
V
V
X
V
V
V
(10)
(18)
(18)
Illegal
L
(10)
Illegal
H
H
L
H
L
(10)
PRE/PALL
REF/SELF
MRS
No Operation, Idle State After tRP Has Elapsed
L
X
X
Illegal
Illegal
L
H
L
L
L
OP CODE
Immediately
Following
DESL
NOP
No Operation, Row Active After tRCD Has Elapsed
No Operation, Row Active After tRCD Has Elapsed
H
L
X
H
X
H
X
H
X
X
X
X
X
X
Row Active
BST
No Operation, Row Active After tRCD Has Elapsed
L
L
H
H
H
L
L
L
L
H
L
L
H
L
H
L
H
L
X
V
X
X
(18)
(10)
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
Illegal
V
V
(10)
(18)
(18)
Illegal
L
L
L
L
L
L
H
H
L
L
V
V
V
X
V V
V V
V
(10,14)
Illegal
(10)
Illegal
X
X
Illegal
Illegal
X
OP CODE
Write
Recovery
DESL
NOP
No Operation, Row Active After tDPL Has ElapsedH
No Operation, Row Active After tDPL Has Elapsed L
X
H
X
H
X
H
X
X
X
X
X
X
BST
No Operation, Row Active After tDPL Has Elapsed L
H
H
H
L
L
L
H
L
L
H
H
L
L
H
L
H
L
X
V
V
V
V
X
X
X
(18)
(18)
(18)
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
ReadStart
L
L
L
L
L
L
V V
V V
V V
V
WriteRestart
(10)
Illegal
(10)
Illegal
X
X
Illegal
Illegal
H
L
X
L
L
OP CODE
16
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
11/03/06
®
IS42S16100C1
ISSI
(1,2)
OPERATION COMMAND TABLE
Current State Command
Operation
CS RAS CAS WE A11 A10 A9-A0
Write Recovery DESL
No Operation, Idle State After tDAL Has Elapsed
No Operation, Idle State After tDAL Has Elapsed
H
L
X
H
X
H
X
H
X
X
X
X
X
X
With Auto-
NOP
Precharge
BST
No Operation, Idle State After tDAL Has Elapsed
Illegal(10)
Illegal(10)
Illegal(10)
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
H
H
L
H
L
L
H
L
X
V
V
V
V
X
X
X
(18)
READ/READA
WRIT/WRITA
ACT
V
V
V
V
(18)
(18)
L
V
H
H
L
H
L
V
PRE/PALL
REF/SELF
MRS
Illegal(10)
L
V
X
Illegal
L
H
L
X
X
Illegal
L
L
OP CODE
Refresh
DESL
No Operation, Idle State After tRP Has Elapsed
X
H
H
H
H
L
X
H
H
L
X
H
L
X
X
X
V
V
V
V
X
X
X
X
X
X
X
NOP
No Operation, Idle State After tRP Has Elapsed
BST
No Operation, Idle State After tRP Has Elapsed
(18)
READ/READA
WRIT/WRITA
ACT
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
H
L
V
V
(18)
(18)
L
V
V
V
H
H
L
H
L
V
PRE/PALL
REF/SELF
MRS
L
V
X
X
L
H
L
X
L
L
OP CODE
Mode Register DESL
No Operation, Idle State After tMCD Has Elapsed
No Operation, Idle State After tMCD Has Elapsed
H
L
X
H
X
H
X
H
X
X
X
X
X
X
Set
NOP
BST
No Operation, Idle State After tMCD Has Elapsed
L
L
L
L
L
L
L
H
H
H
L
H
L
L
H
L
X
V
V
V
V
X
X
X
(18)
READ/READA
WRIT/WRITA
ACT
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
V
V
(18)
(18)
L
V
V
V
H
H
L
H
L
V
PRE/PALL
REF/SELF
MRS
L
V
X
X
L
H
L
X
L
L
OP CODE
Notes:
1. H: HIGH level input, L: LOW level input, X: HIGH or LOW level input, V: Valid data input
2. All input signals are latched on the rising edge of the CLK signal.
3. Both banks must be placed in the inactive (idle) state in advance.
4. The state of the A0 to A11 pins is loaded into the mode register as an OP code.
5. The row address is generated automatically internally at this time. The DQ pin and the address pin data is ignored.
6. During a self-refresh operation, all pin data (states) other than CKE is ignored.
7. The selected bank must be placed in the inactive (idle) state in advance.
8. The selected bank must be placed in the active state in advance.
9. This command is valid only when the burst length set to full page.
10. This is possible depending on the state of the bank selected by the A11 pin.
11. Time to switch internal busses is required.
12. The IS42S16100C1 can be switched to power-down mode by dropping the CKE pin LOW when both banks in the idle
state. Input pins other than CKE are ignored at this time.
13. The IS42S16100C1 can be switched to self-refresh mode by dropping the CKE pin LOW when both banks in the idle state.
Input pins other than CKE are ignored at this time.
14. Possible if tRRD is satisfied.
15. Illegal if tRAS is not satisfied.
16. The conditions for burst interruption must be observed. Also note that the IS42S16100C1 will enter the precharged state
immediately after the burst operation completes if auto-precharge is selected.
17. Command input becomes possible after the period tRCD has elapsed. Also note that the IS42S16100C1 will enter the
precharged state immediately after the burst operation completes if auto-precharge is selected.
18. A8,A9 = don’t care.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
17
Rev. D
11/03/06
®
IS42S16100C1
ISSI
(1)
CKE RELATED COMMAND TRUTH TABLE
CKE
n-1
Current State
Operation
n
X
H
H
H
H
L
CS RAS CAS W E A11 A10 A9-A0
Self-Refresh
Undefined
H
L
X
H
L
X
X
H
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Self-Refresh Recovery(2)
Self-Refresh Recovery(2)
Illegal(2)
L
L
L
Illegal(2)
L
L
X
X
X
H
L
Self-Refresh
L
X
H
L
X
X
H
H
L
Self-Refresh Recovery Idle State After tRC Has Elapsed
H
H
H
H
H
H
H
H
L
H
H
H
H
L
Idle State After tRC Has Elapsed
Illegal
L
Illegal
L
X
X
H
L
Power-Down on the Next Cycle
H
L
X
H
H
L
Power-Down on the Next Cycle
L
Illegal
Illegal
L
L
L
L
X
X
X
X
X
(2)
Clock Suspend Termination on the Next Cycle
H
L
X
X
X
X
X
X
X
X
Clock Suspend
Undefined
L
Power-Down
H
L
X
H
Power-Down Mode Termination, Idle After
That Termination(2)
Power-Down Mode
L
H
H
H
H
H
H
H
H
H
H
L
L
H
H
H
H
H
L
X
H
L
X
X
H
L
X
X
X
H
L
X
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
Both Banks Idle
No Operation
X
See the Operation Command Table
Bank Active Or Precharge
Auto-Refresh
X
L
X
L
L
X
Mode Register Set
L
L
L
OP CODE
See the Operation Command Table
See the Operation Command Table
See the Operation Command Table
Self-Refresh(3)
H
L
X
H
L
X
X
H
L
X
X
X
H
L
X
X
X
X
X
X
X
X
X
L
X
L
L
X
L
L
L
X
See the Operation Command Table
Power-Down Mode(3)
L
L
L
L
OP CODE
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Other States
See the Operation Command Table
Clock Suspend on the Next Cycle(4)
Clock Suspend Termination on the Next Cycle
H
H
L
H
L
Clock Suspend Termination on the Next CycleL
Notes:
1. H: HIGH level input, L: LOW level input, X: HIGH or LOW level input
2. The CLK pin and the other input are reactivated asynchronously by the transition of the CKE level from LOW to HIGH.
The minimum setup time (tCKA) required before all commands other than mode termination must be satisfied.
3. Both banks must be set to the inactive (idle) state in advance to switch to power-down mode or self-refresh mode.
4. The input must be command defined in the operation command table.
18
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
11/03/06
®
IS42S16100C1
ISSI
(1,2)
TWO BANKS OPERATION COMMAND TRUTH TABLE
Previous State
Next State
Operation
DESL
NOP
CS RAS CAS WE A11 A10 A9-A0
BANK0BANK1 BANK0BANK1
H
L
L
X
H
H
X
H
H
X
H
L
X
X
X
X
X
X
X
X
X
Any
Any
Any
Any
Any
Any
Any
Any
BST
R/W/A
I
I/A
I/A
I/A
R/W/A
I
A
I
I/A
I/A
I/A
I/A
A
I/A
I
READ/READA
WRIT/WRITA
L
L
H
H
L
L
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H CA(3)
H CA(3)
I/A
R/W
I/A
R/W
R/W/A
A
R/W/A
A
I/A
R/W
I/A
R/W
R/W/A
A
R/W/A
A
R/W/A
A
R/W/A
A
I/A
R/W
I/A
R/W
R/W/A
A
R/W/A
A
I/A
I/A
A
I/A
A
RP
RP
R
R
I/A
A
I/A
A
WP
WP
W
RP
RP
R
R
I/A
A
I/A
A
WP
WP
W
W
I/A
A
L
L
CA(3)
CA(3)
H CA(3)
H CA(3)
L
L
CA(3)
CA(3)
L
H CA(3)
H CA(3)
L
L
CA(3)
CA(3)
H CA(3)
H CA(3)
R/W
I/A
R/W
L
L
CA(3)
CA(3)
I/A
A
W
ACT
L
L
L
L
H
H
H
L
H
L
RA RA
RA RA
Any
I
I
Any
A
I
A
Any
I
I
I
I
Any
PRE/PALL
X
X
H
H
L
H
H
L
L
L
L
X
X
X
X
X
X
R/W/A/I I/A
I/A R/W/A/I
I/A R/W/A/I
R/W/A/I I/A
R/W/A/I I/A
I/A R/W/A/I
I
I/A
R/W/A/I
I
I
I/A
R/W/A/I
L
REF
MRS
L
L
L
L
L
L
H
L
X
X
X
I
I
I
I
I
I
I
I
OPCODE
Notes:
1. H: HIGH level input, L: LOW level input, X: HIGH or LOW level input, RA: Row Address, CA: Column Address
2. The device state symbols are interpreted as follows:
I
Idle (inactive state)
Row Active State
Read
A
R
W
Write
RP Read With Auto-Precharge
WP Write With Auto-Precharge
Any Any State
3. CA: A8,A9 = don’t care.
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19
Rev. D
11/03/06
®
IS42S16100C1
ISSI
SIMPLIFIED STATE TRANSITION DIAGRAM (One Bank Operation)
SELF
REFRESH
SREF entry
SREF exit
MRS
MODE
REGISTER
SET
AUTO
REF
IDLE
REFRESH
CKE_
CKE
IDLE
ACT
POWER
DOWN
ACTIVE
POWER
DOWN
CKE_
CKE
BANK
ACTIVE
BST
BST
READ
WRIT
WRIT
CKE_
READ
CKE_
WRITA
READA
READ
WRITE
READ
WRIT
CKE
READA
CKE_
CLOCK
SUSPEND
CKE
CLOCK
SUSPEND
WRITA
WRITA
READA
CKE_
CKE
CKE
WRITE WITH
AUTO
READ WITH
AUTO
PRECHARGE
PRECHARGE
PRE
PRE
PRE
PRE-
CHARGE
PRE
POWER APPLIED
POWER ON
Automatic transition following the
completion of command execution.
Transition due to command input.
20
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Rev. D
11/03/06
®
IS42S16100C1
ISSI
Device Initialization At Power-On
Burst Length
(Power-OnSequence)
When writing or reading, data can be input or output data
continuously. Intheseoperations, anaddressisinputonly
once and that address is taken as the starting address
internally by the device. The device then automatically
generates the following address. The burst length field in
themoderegisterstipulatesthenumberofdataitemsinput
or output in sequence. In the IS42S16100C1 product, a
burst length of 1, 2, 4, 8, or full page can be specified. See
the table on the next page for details on setting the mode
register.
AsisthecasewithconventionalDRAMs,theIS42S16100C1
productmustbeinitializedbyexecutingastipulatedpower-
on sequence after power is applied.
After power is applied and VDD and VDDQ reach their
stipulated voltages, set and hold the CKE and DQM pins
HIGHfor100µs.Then,executetheprechargecommandto
precharge both bank. Next, execute the auto-refresh
command twice or more and define the device operation
mode by executing a mode register set command.
The mode register set command can be also set before
auto-refreshcommand.
Burst Type
The burst data order during a read or write operation is
stipulated by the burst type, which can be set by the mode
registersetcommand.TheIS42S16100C1productsupports
sequentialmodeandinterleavedmodebursttypesettings.
See the table on the next page for details on setting the
moderegister.Seethe“BurstLengthandColumnAddress
Sequence” item for details on DQ data orders in these
modes.
Mode Register Settings
The mode register set command sets the mode register.
When this command is executed, pins A0 to A9, A10, and
A11 function as data input pins for setting the register, and
this data becomes the device internal OP code. This OP
code has four fields as listed in the table below.
Input Pin
A11, A10, A9, A8, A7
A6, A5, A4
Field
Write Mode
BurstwriteorsinglewritemodeisselectedbytheOPcode
(A11, A10, A9) of the mode register.
ModeOptions
CAS Latency
Burst Type
Burst Length
A3
A burst write operation is enabled by setting the OP code
(A11, A10, A9) to (0,0,0). A burst write starts on the same
cycle as a write command set. The write start address is
specified by the column address and bank select address
at the write command set cycle.
A2, A1, A0
Notethatthemoderegistersetcommandcanbeexecuted
only when both banks are in the idle (inactive) state. Wait
at least two cycles after executing a mode register set
command before executing the next command.
A single write operation is enabled by setting OP code
(A11, A10, A9) to (0, 0,1). In a single write operation, data
is only written to the column address and bank select
address specified by the write command set cycle without
regard to the bust length setting.
CAS Latency
During a read operation, the between the execution of the
read command and data output is stipulated as the CAS
latency. This period can be set using the mode register set
command. The optimal CAS latency is determined by the
clockfrequencyanddevicespeedgrade.Seethe“Operating
Frequency / Latency Relationships” item for details on the
relationship between the clock frequency and the CAS
latency.Seethetableonthenextpagefordetailsonsetting
the mode register.
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21
Rev. D
11/03/06
®
IS42S16100C1
ISSI
MODE REGISTER
Address Bus (Ax)
Mode Register (Mx)
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
WRITEMODE
LT MODE
BT
BL
M2 M1 M0
Sequential Interleaved
Burst Length
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
1
2
4
8
8
Reserved
Reserved
Reserved
Full Page
Reserved
Reserved
Reserved
Reserved
M3
0
1
Type
Burst Type
Sequential
Interleaved
M6 M5 M4 CASLatency
LatencyMode 0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
2
0
0
0
1
1
1
1
3
Reserved
Reserved
Reserved
Reserved
M11
0
0
M10
0
0
M9
M8
0
0
M7
WriteMode
1
0
0
0
Burst Read & Single Write
Burst Read & Burst Write
Note: Other values for these bits are reserved.
22
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
11/03/06
®
IS42S16100C1
ISSI
BURST LENGTH AND COLUMN ADDRESS SEQUENCE
Column Address
A2 A1 A0
Address Sequence
Burst Length
Sequential
Interleaved
2
X
X
X
X
0
1
0-1
1-0
0-1
1-0
4
8
X
X
X
X
0
0
1
1
0
1
0
1
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Full Page
(256)
n
n
n
Cn, Cn+1, Cn+2
Cn+3, Cn+4.....
...Cn-1(Cn+255),
Cn(Cn+256).....
None
Notes:
1. The burst length in full page mode is 256.
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23
Rev. D
11/03/06
®
IS42S16100C1
ISSI
BANK SELECT AND PRECHARGE ADDRESS ALLOCATION
Row
X0
X1
X2
X3
X4
X5
X6
X7
—
—
—
—
—
—
—
—
RowAddress
RowAddress
RowAddress
RowAddress
RowAddress
RowAddress
RowAddress
RowAddress
X8
—
RowAddress
X9
X10
—
0
1
0
1
RowAddress
Precharge of the Selected Bank (Precharge Command)
Precharge of Both Banks (Precharge Command)
Bank 0 Selected (Precharge and Active Command)
Bank 1 Selected (Precharge and Active Command)
RowAddress
(ActiveCommand)
X11
Column
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
—
—
—
—
—
—
—
—
—
—
0
ColumnAddress
ColumnAddress
ColumnAddress
ColumnAddress
ColumnAddress
ColumnAddress
ColumnAddress
ColumnAddress
Don’tCare
Don’tCare
Auto-Precharge-Disabled
Auto-Precharge-Enables
Bank 0 Selected (Read and Write Commands)
Bank 1 Selected (Read and Write Commands)
1
0
1
Y11
24
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Rev. D
11/03/06
®
IS42S16100C1
ISSI
Burst Read
The read cycle is started by executing the read command.
The address provided during read command execution is
usedasthestartingaddress.First,thedatacorresponding
to this address is output in synchronization with the clock
signalaftertheCASlatencyperiod.Next,datacorresponding
to an address generated automatically by the device is
output in synchronization with the clock signal.
is a full page is an exception. In this case the output
buffers must be set to the high impedance state by
executing a burst stop command.
Note that upper byte and lower byte output data can be
maskedindependentlyundercontrolofthesignalsapplied
totheU/LDQMpins.Thedelayperiod(tQMD)isfixedattwo,
regardless of the CAS latency setting, when this function
is used.
The output buffers go to the LOW impedance state CAS
latency minus one cycle after the read command, and go
to the HIGH impedance state automatically after the last
data is output. However, the case where the burst length
The selected bank must be set to the active state before
executing this command.
CLK
COMMAND
UDQM
READ A0
t
QMD=2
LDQM
DQ8-DQ15
DQ0-DQ 7
D
OUT A0
D
OUT A2
HI-Z
DOUT A3
HI-Z
HI-Z
DOUT A0
D
OUT A1
READ (CA=A, BANK 0)
DATA MASK (LOWER BYTE)
DATA MASK (UPPER BYTE)
CAS latency = 3, burst length = 4
Burst Write
a burst stop command. The latency for DQ pin data input
is zero, regardless of the CAS latency setting. However, a
wait period (write recovery: tDPL) after the last data input is
required for the device to complete the write operation.
The write cycle is started by executing the command. The
addressprovidedduringwritecommandexecutionisused
as the starting address, and at the same time, data for this
address is input in synchronization with the clock signal.
Note that the upper byte and lower byte input data can be
maskedindependentlyundercontrolofthesignalsapplied
totheU/LDQMpins.Thedelayperiod(tDMD)isfixedatzero,
regardless of the CAS latency setting, when this function
is used.
Next,dataisinputinotherinsynchronizationwiththeclock
signal. During this operation, data is written to address
generated automatically by the device. This cycle
terminates automatically after a number of clock cycles
determined by the stipulated burst length. However, the
case where the burst length is a full page is an exception.
Inthiscasethewritecyclemustbeterminatedbyexecuting
The selected bank must be set to the active state before
executing this command.
CLK
COMMAND
DQ
WRITE
DIN
0
DIN
1
DIN
2
DIN 3
BURST LENGTH
CAS latency = 2,3, burst length = 4
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25
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Read With Auto-Precharge
The read with auto-precharge command first executes a
burstreadoperationandthenputstheselectedbankinthe
precharged state automatically. After the precharge com-
pletes, thebankgoestotheidlestate. Thusthiscommand
performsareadcommandandaprechargecommandina
singleoperation.
three, the precharge operation starts on two clock cycles
before the last burst data is output (tPQL = –2). Therefore,
the selected bank can be made active after a delay of tRP
from the start position of this precharge operation.
The selected bank must be set to the active state before
executing this command.
During this operation, the delay period (tPQL) between the
last burst data output and the start of the precharge
operation differs depending on the CAS latency setting.
The auto-precharge function is invalid if the burst length is
set to full page.
When the CAS latency setting is two, the precharge
operation starts on one clock cycle before the last burst
data is output (tPQL = –1). When the CAS latency setting is
CAS Latency
3
2
tPQL
–2
–1
CLK
COMMAND
DQ
READA 0
ACT 0
t
PQL
DOUT
0
DOUT
1
D
OUT DOUT 3
2
t
RP
PRECHARGE START
READ WITH AUTO-PRECHARGE
(BANK 0)
CAS latency = 2, burstlength = 4
CLK
COMMAND
DQ
ACT 0
READA 0
t
PQL
D
OUT
0
D
OUT
1
D
OUT
2
DOUT 3
t
RP
READ WITH AUTO-PRECHARGE
(BANK 0)
PRECHARGE START
CAS latency = 3, burstlength = 4
26
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Write With Auto-Precharge
The write with auto-precharge command first executes a
burstwriteoperationandthenputstheselectedbankinthe
precharged state automatically. After the precharge
completes the bank goes to the idle state. Thus this
command performs a write command and a precharge
command in a single operation.
Therefore, the selected bank can be made active after a
delay of tDAL.
The selected bank must be set to the active state before
executing this command.
The auto-precharge function is invalid if the burst length is
set to full page.
During this operation, the delay period (tDAL) between the
last burst data input and the completion of the precharge
operation differs depending on the CAS latency setting.
The delay (tDAL) is tRP plus one CLK period. That is, the
precharge operation starts one clock period after the last
burst data input.
CAS Latency
3
2
tDAL
1CLK
1CLK
+tRP
+tRP
CLK
COMMAND
DQ
WRITE A0
DIN 0
ACT 0
PRECHARGE START
DIN 1
DIN 2
DIN 3
tRP
tDAL
WRITE WITH AUTO-PRECHARGE
(BANK 0)
CAS latency = 2, burstlength = 4
CLK
ACT 0
COMMAND
DQ
WRITE A0
DIN 0
PRECHARGE START
DIN 1
DIN 2
DIN 3
tRP
WRITE WITH AUTO-PRECHARGE
(BANK 0)
tDAL
CAS latency = 3, burstlength = 4
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27
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Interval Between Read Command
A new command can be executed while a read cycle is in
progress, i.e., before that cycle completes. When the
second read command is executed, after the CAS latency
haselapsed,datacorrespondingtothenewreadcommand
is output in place of the data due to the previous read
command.
The interval between two read command (tCCD) must be at
least one clock cycle.
The selected bank must be set to the active state before
executing this command.
CLK
COMMAND
DQ
READ A0
READ B0
tCCD
DOUT A0
DOUT B0
DOUT B1
DOUT B3
DOUT B2
READ (CA=A, BANK 0) READ (CA=B, BANK 0)
CAS latency = 2, burstlength = 4
Interval Between Write Command
A new command can be executed while a write cycle is in
progress,i.e.,beforethatcyclecompletes.Atthepointthe
secondwritecommandisexecuted,datacorrespondingto
the new write command can be input in place of the data
for the previous write command.
The interval between two write commands (tCCD) must be
at least one clock cycle.
The selected bank must be set to the active state before
executing this command.
CLK
tCCD
COMMAND
DQ
WRITE A0 WRITE B0
DIN A0
D
IN B0
D
IN B1
D
IN B2
DIN B3
WRITE (CA=A, BANK 0) WRITE (CA=B, BANK 0)
CAS latency = 3, burstlength = 4
28
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
11/03/06
®
IS42S16100C1
ISSI
IntervalBetweenWriteandReadCommands
A new read command can be executed while a write cycle
is in progress, i.e., before that cycle completes. Data
correspondingtothenewreadcommandisoutputafterthe
CAS latency has elapsed from the point the new read
command was executed. The I/On pins must be placed in
the HIGH impedance state at least one cycle before data
is output during this operation.
Theinterval(tCCD)betweencommandmustbeatleastone
clock cycle.
The selected bank must be set to the active state before
executing this command.
CLK
tCCD
COMMAND
DQ
WRITE A0 READ B0
DIN A0
D
OUT B0
DOUT B1
D
OUT B2
DOUT B3
HI-Z
WRITE (CA=A, BANK 0) READ (CA=B, BANK 0)
CAS latency = 2, burstlength = 4
CLK
tCCD
COMMAND
DQ
WRITE A0 READ B0
DIN A0
D
OUT B0
DOUT B1
D
OUT B2
DOUT B3
HI-Z
WRITE (CA=A, BANK 0) READ (CA=B, BANK 0)
CAS latency = 3, burstlength = 4
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29
Rev. D
11/03/06
®
IS42S16100C1
ISSI
IntervalBetweenReadandWriteCommands
A read command can be interrupted and a new write
command executed while the read cycle is in progress,
i.e., before that cycle completes. Data corresponding to
the new write command can be input at the point new
write command is executed. To prevent collision
between input and output data at the DQn pins during
this operation, the
output data must be masked using the U/LDQM pins. The
interval (tCCD) between these commands must be at least
one clock cycle.
The selected bank must be set to the active state before
executing this command.
CLK
t
CCD
WRITE B0
COMMAND
U/LDQM
DQ
READ A0
HI-Z
DIN B0
DIN B1
D
IN B2
DIN B3
READ (CA=A, BANK 0) WRITE (CA=B, BANK 0)
CAS latency = 2, 3, burstlength = 4
30
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Rev. D
11/03/06
®
IS42S16100C1
ISSI
Precharge
Read Cycle Interruption
TheprechargecommandsetsthebankselectedbypinA11
totheprechargedstate. Thiscommandcanbeexecutedat
atimetRAS followingtheexecutionofanactivecommandto
the same bank. The selected bank goes to the idle state at
atimetRP followingtheexecutionoftheprechargecommand,
and an active command can be executed again for that
bank.
Using the Precharge Command
A read cycle can be interrupted by the execution of the
precharge command before that cycle completes. The
delay time (tRQL) from the execution of the precharge
command to the completion of the burst output is the
clock cycle of CAS latency.
If pin A10 is low when this command is executed, the bank
selected by pin A11 will be precharged, and if pin A10 is
HIGH,bothbankswillbeprechargedatthesametime.This
input to pin A11 is ignored in the latter case.
CAS Latency
3
2
tRQL
3
2
CLK
t
RQL
PRE 0
COMMAND
DQ
READ A0
D
OUT A0
D
OUT A1
DOUT A2
HI-Z
READ (CA=A, BANK 0)
PRECHARGE (BANK 0)
CAS latency = 2, burstlength = 4
CLK
t
RQL
PRE 0
COMMAND
DQ
READ A0
D
OUT A0
D
OUT A1
D
OUT A2
HI-Z
READ (CA=A, BANK 0)
PRECHARGE (BANK 0)
CAS latency = 3, burstlength = 4
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31
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Write Cycle Interruption Using the
Precharge Command
A write cycle can be interrupted by the execution of the
precharge command before that cycle completes. The
delaytime(tWDL)fromtheprechargecommandtothepoint
where burst input is invalid, i.e., the point where input data
isnolongerwrittentodeviceinternalmemoryiszeroclock
cycles regardless of the CAS.
Inversely, to write all the burst data to the device, the
precharge command must be executed after the write
data recovery period (tDPL) has elapsed. Therefore, the
precharge command must be executed on one clock
cycle that follows the input of the last burst data item.
To inhibit invalid write, the DQM signal must be asserted
HIGH with the precharge command.
CAS Latency
3
2
tWDL
0
0
This precharge command and burst write command must
beofthesamebank,otherwiseitisnotprechargeinterrupt
but only another bank precharge of dual bank operation.
tDPL
1
1
CLK
t
WDL=0
PRE 0
COMMAND
WRITE A0
DQM
DQ
DIN A0
DIN A1
D
IN A2
DIN A3
MASKED BY DQM
PRECHARGE (BANK 0)
WRITE (CA=A, BANK 0)
CAS latency = 2, burstlength = 4
CLK
t
DPL
PRE 0
COMMAND
DQ
WRITE A0
DIN A0
D
IN A1
D
IN A2
DIN A3
WRITE (CA=A, BANK 0)
PRECHARGE (BANK 0)
CAS latency = 3, burstlength = 4
32
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Rev. D
11/03/06
®
IS42S16100C1
ISSI
Read Cycle (Full Page) Interruption Using
the Burst Stop Command
TheIS42S16100C1canoutputdatacontinuouslyfromthe
burststartaddress(a)tolocationa+255duringareadcycle
in which the burst length is set to full page. The
IS42S16100C1repeatstheoperationstartingatthe256th
cycle with the data output returning to location (a) and
continuing with a+1, a+2, a+3, etc. A burst stop command
must be executed to terminate this cycle. A precharge
command must be executed within the ACT to PRE
command period (tRAS max.) following the burst stop
command.
After the period (tRBD) required for burst data output to
stop following the execution of the burst stop command
has elapsed, the outputs go to the HIGH impedance
state. This period (tRBD) is two clock cycle when the
CAS latency is two and three clock cycle when the CAS
latency is three.
CAS Latency
3
2
tRBD
3
2
CLK
t
RBD
BST
COMMAND
DQ
READ A0
D
OUT A0
D
OUT A0
D
OUT A1
D
OUT A2
DOUT A3
HI-Z
BURST STOP
READ (CA=A, BANK 0)
CAS latency = 2, burstlength = 4
CLK
t
RBD
BST
COMMAND
DQ
READ A0
DOUT A0
D
OUT A0
D
OUT A2
D
OUT A3
D
OUT A1
HI-Z
READ (CA=A, BANK 0)
BURST STOP
CAS latency = 3, burstlength = 4
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33
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Write Cycle (Full Page) Interruption Using
the Burst Stop Command
must be executed within the ACT to PRE command
period (tRAS max.) following the burst stop command.
After the period (tWBD) required for burst data input to
stop following the execution of the burst stop command
has elapsed, the write cycle terminates. This period
(tWBD) is zero clock cycles, regardless of the CAS
latency.
The IS42S16100C1 can input data continuously from
the burst start address (a) to location a+255 during a
write cycle in which the burst length is set to full page.
The IS42S16100C1 repeats the operation starting at the
256th cycle with data input returning to location (a) and
continuing with a+1, a+2, a+3, etc. A burst stop
command must be executed to terminate this cycle. A
prechargecommand
CLK
t
WBD=0
BST
INVALID DATA
t
RP
PRE 0
COMMAND
DQ
WRITE A0
DIN A0
D
IN A1
D
IN
A
DIN A1
DIN A2
READ (CA=A, BANK 0)
BURST STOP PRECHARGE (BANK 0)
Don't Care
Burst Data Interruption Using the U/LDQM
Pins (Read Cycle)
control operates independently on a byte basis with the
UDQM pin controlling upper byte output (pins
DQ8-DQ15)andtheLDQMpincontrollinglowerbyteoutput
(pins DQ0 to DQ7).
Burstdataoutputcanbetemporarilyinterrupted(masked)
duringareadcycleusingtheU/LDQMpins. Regardlessof
theCASlatency, twoclockcycles(tQMD)afteroneoftheU/
LDQMpinsgoesHIGH,thecorrespondingoutputsgotothe
HIGH impedance state. Subsequently, the outputs are
maintained in the high impedance state as long as that U/
LDQM pin remains HIGH. When the U/LDQM pin goes
LOW, output is resumed at a time tQMD later. This output
Since the U/LDQM pins control the device output buffers
only, the read cycle continues internally and, in particular,
incrementing of the internal burst counter continues.
CLK
COMMAND
UDQM
READ A0
t
QMD=2
LDQM
DQ8-DQ15
DQ0-DQ 7
D
OUT A0
D
OUT A2
DOUT A3
HI-Z
HI-Z
DOUT A0
D
OUT A1
HI-Z
READ (CA=A, BANK 0)
DATA MASK (LOWER BYTE)
DATA MASK (UPPER BYTE)
CAS latency = 2, burstlength = 4
34
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Burst Data Interruption U/LDQM Pins (Write
Cycle)
Burst data input can be temporarily interrupted (muted )
duringawritecycleusingtheU/LDQMpins.Regardlessof
theCASlatency, assoonasoneoftheU/LDQMpinsgoes
HIGH, the corresponding externally applied input data will
no longer be written to the device internal circuits.
Subsequently, the corresponding input continues to be
muted as long as that U/LDQM pin remains HIGH.
that pin is dropped to LOW and data will be written to the
device.Thisinputcontroloperatesindependentlyonabyte
basis with the UDQM pin controlling upper byte input (pin
DQ8toDQ15)andtheLDQMpincontrollingthelowerbyte
input (pins DQ0 to DQ7).
Since the U/LDQM pins control the device input buffers
only, the cycle continues internally and, in particular,
incrementing of the internal burst counter continues.
The IS42S16100C1 will revert to accepting input as soon
as
CLK
COMMAND
UDQM
WRITE A0
t
DMD=0
LDQM
DQ8-DQ15
DQ0-DQ7
DIN A1
D
IN A3
DIN A2
D
IN A0
DIN A3
WRITE (CA=A, BANK 0)
DATA MASK (LOWER BYTE)
Don't Care
DATA MASK (UPPER BYTE)
CAS latency = 2, burstlength = 4
Burst Read and Single Write
The burst read and single write mode is set up using the
mode register set command. During this operation, the
burstreadcycleoperatesnormally,butthewritecycleonly
writes a single data item for each write cycle. The CAS
latencyandDQMlatencyarethesameasinnormalmode.
CLK
COMMAND
DQ
WRITE A0
D
IN A0
WRITE (CA=A, BANK 0)
CAS latency = 2, 3
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35
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Bank Active Command Interval
that bank within the ACT to PRE command period (tRAS
max). Also note that a precharge command cannot be
executedforanactivebankbeforetRAS (min)haselapsed.
When the selected bank is precharged, the period trp
has elapsed and the bank has entered the idle state, the
bank can be activated by executing the active
command. If the other bank is in the idle state at that
time, the active command can be executed for that bank
after the period tRRD has elapsed. At that point both
banks will be in the active state. When a bank active
command has been executed, a precharge command
must be executed for
After a bank active command has been executed and the
trcdperiodhaselapsed,readwrite(includingauto-precharge)
commands can be executed for that bank.
CLK
t
RRD
COMMAND
ACT 0
ACT 1
BANK ACTIVE (BANK 0)
BANK ACTIVE (BANK 1)
CLK
COMMAND
t
RCD
ACT 0
READ 0
BANK ACTIVE (BANK 0)
BANK ACTIVE (BANK 0)
CAS latency = 3
Clock Suspend
When the CKE pin is dropped from HIGH to LOW during a
read or write cycle, the IS42S16100C1 enters clock
suspendmodeonthenextCLKrisingedge.Thiscommand
reduces the device power dissipation by stopping the
device internal clock. Clock suspend mode continues as
long as the CKE pin remains low. In this state, all inputs
otherthanCKEpinareinvalidandnoothercommandscan
beexecuted.Also,thedeviceinternalstatesaremaintained.
WhentheCKEpingoesfromLOWtoHIGHclocksuspend
modeisterminatedonthenextCLKrisingedgeanddevice
operation resumes.
The next command cannot be executed until the recovery
period (tCKA) has elapsed.
Sincethiscommanddiffersfromtheself-refreshcommand
described previously in that the refresh operation is not
performed automatically internally, the refresh operation
mustbeperformedwithintherefreshperiod(tref).Thusthe
maximumtimethatclocksuspendmodecanbeheldisjust
under the refresh cycle time.
CLK
CKE
COMMAND
DQ
READ 0
DOUT
0
DOUT
1
DOUT
2
DOUT 3
READ (BANK 0)
CLOCK SUSPEND
CAS latency = 2, burstlength = 4
36
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Rev. D
11/03/06
®
IS42S16100C1
ISSI
OPERATION TIMING EXAMPLE
Power-On Sequence, Mode Register Set Cycle
T0
T1
T2
T3
T10
T17
T18
T19
T20
CLK
tCHI
tCK
tCL
HIGH
CKE
CS
t
CS
tCH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
t
AS
tAH
ROW
CODE
CODE
CODE
A0-A9
A10
t
AS
AS
tAH
tAS
tAH
ROW
BANK 0 & 1
t
tAH
BANK 1
A11
BANK 0
HIGH
DQM
DQ
WAIT TIME
T=100 µs
t
RAS
tMCD
tRP
t
RC
tRC
tRC
<
PALL>
<
REF>
<
REF>
<
MRS>
<ACT>
Undefined
Don't Care
CAS latency = 2, 3
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37
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Power-Down Mode Cycle
T0
T1
T2
T3
Tn
Tn+1
Tn+2
Tn+3
CLK
tCHI
t
CKH
tCKS
tCK
tCL
tCKS
CKE
CS
t
CKA
t
CKA
tCS
tCH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
tAS
tAH
ROW
A0-A9
A10
tAS
tAH
BANK 0 & 1
BANK 0 OR 1
BANK 1
ROW
BANK 1
A11
BANK 0
BANK 0
DQM
DQ
EXIT
t
RAS
RC
tRP
POWER DOWN MODE
POWER DOWN MODE
t
<
PRE
PALL
>
<
SBY>
<ACT>
<
>
Undefined
Don't Care
CAS latency = 2, 3
38
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Rev. D
11/03/06
®
IS42S16100C1
ISSI
Auto-Refresh Cycle
T0
T1
T2
T3
Tl
Tm
Tn
Tn+1
CLK
t
CHI
t
CK
t
CKS
tCL
CKE
CS
t
CS
tCH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
ROW
A0-A9
A10
t
AS
tAH
ROW
BANK 0 & 1
BANK 1
A11
BANK 0
DQM
DQ
t
RC
t
RAS
RC
t
RP
tRC
tRC
t
<
PALL
>
<REF>
<
REF>
<REF>
<ACT>
Undefined
Don't Care
CAS latency = 2, 3
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39
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Self-Refresh Cycle
T0
T1
T2
T3
Tm
Tm+1
Tm+2
Tn
CLK
tCHI
t
CKS
t
CK
tCKS
tCKS
tCL
CKE
CS
t
CKA
t
CKA
tCS
t
CH
tCS
tCH
RAS
t
CS
CS
tCH
CAS
WE
t
t
CH
A0-A9
A10
t
AS
tAH
BANK 0 & 1
A11
DQM
DQ
EXIT
SELF
REFRESH
t
RC
SELF REFRESH MODE
t
RC
t
RP
<PALL
>
<
SELF>
<REF>
Undefined
Don't Care
CAS latency = 2, 3
Note 1: A8,A9 = Don’t Care.
40
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Rev. D
11/03/06
®
IS42S16100C1
ISSI
Read Cycle
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
tCKS
t
CL
t
CK
CKE
CS
t
t
CKA
CH
tCS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
AS
AS
tAH
(1)
COLUMN m
ROW
ROW
ROW
A0-A9
A10
BANK 0 AND 1
BANK 0 OR 1
t
t
AH
AH
NO PRE
BANK 1
ROW
t
t
AS
BANK 1
BANK 1
BANK 0
BANK 1
BANK 0
A11
BANK 0
BANK 0
t
CH
tCS
tQMD
DQM
DQ
t
AC
t
AC
t
AC
t
AC
t
OH
t
OH
t
OH
tOH
D
OUT
m
D
OUT m+1
D
OUT m+2
D
OUT m+3
t
LZ
t
HZ
tRCD
tRCD
t
CAC
t
RQL
t
RAS
t
RAS
RC
t
RP
t
RC
t
<
PRE>
<ACT>
<ACT
>
<READ>
<
PALL>
Undefined
Don't Care
CAS latency = 2, burstlength = 4
Note 1: A8,A9 = Don’t Care.
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41
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Read Cycle / Auto-Precharge
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
tCKS
t
CL
t
CK
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
(1)
t
AS
AS
t
AH
COLUMN m
ROW
ROW
ROW
A0-A9
A10
t
t
t
AH
AH
AUTO PRE
BANK 1
ROW
t
AS
BANK 1
BANK 1
BANK 0
A11
BANK 0
BANK 0
t
CH
t
CS
t
QMD
DQM
DQ
t
AC
t
AC
t
AC
t
AC
t
OH
t
OH
t
OH
t
OH
D
OUT
m
D
OUT m+1
D
OUT m+2
D
OUT m+3
t
LZ
t
HZ
t
RCD
t
RCD
t
CAC
tPQL
t
RAS
t
RAS
RC
t
RP
tRC
t
<
ACT>
<ACT
>
<
READA
>
Undefined
Don't Care
CAS latency = 2, burstlength = 4
Note 1: A8,A9 = Don’t Care.
42
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Rev. D
11/03/06
®
IS42S16100C1
ISSI
Read Cycle / Full Page
T0
T1
T2
T3
T4
T5
T6
T260
T261
T262
T263
CLK
t
CHI
tCKS
t
CL
t
CK
CKE
CS
t
t
CKA
CH
tCS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
(1)
t
t
AS
AS
tAH
COLUMN
ROW
ROW
A0-A9
t
AH
AH
A10
A11
NO PRE
BANK 0
BANK 0 OR 1
BANK 0
t
t
AS
BANK 0
t
CH
t
CS
tQMD
DQM
DQ
t
AC
t
AC
t
AC
t
AC
t
AC
t
OH
t
OH
t
OH
t
OH
tOH
D
OUT 0m
D
OUT 0m+1
D
OUT 0m-1
D
OUT 0m
D
OUT 0m+1
t
LZ
t
HZ
t
RCD
t
CAC
tRBD
(BANK 0)
t
RP
t
RAS
(BANK 0)
t
RC
(BANK 0)
<BST>
<PRE 0>
<
ACT 0
>
<READ0>
Undefined
Don't Care
CAS latency = 2, burstlength = full page
Note 1: A8,A9 = Don’t Care.
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43
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Read Cycle / Ping-Pong Operation (Bank Switching)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCHI
tCKS
tCK
tCL
CKE
CS
t
t
CKA
CH
tCS
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
t
AS
AS
tAH
(1)
(1)
ROW
ROW
COLUMN
ROW
ROW
ROW
COLUMN
A0-A9
AUTO PRE
AUTO PRE
t
t
AH
AH
ROW
A10
A11
NO PRE
BANK 1
BANK 0 OR 1
BANK 0
BANK 0 OR 1
BANK 1
NO PRE
BANK 0
t
t
AS
BANK 0
BANK 0
BANK 1
tCH
tCS
t
QMD
DQM
tAC
tAC
tAC
tAC
tOH
t
OH
tOH
tOH
D
OUT 0m
D
OUT 0m+1
D
OUT 1m
D
OUT 1m+1
DQ
t
LZ
t
LZ
tHZ
tHZ
t
RRD
(BANK 0 TO 1)
RCD
(BANK 0)
t
t
CAC
t
CAC
t
RCD
(BANK 1)
t
RCD
(BANK 0)
RAS
(BANK 0)
(BANK 1)
(BANK 1)
t
RP
(BANK 0)
t
t
RAS
(BANK 0)
t
RC
t
RC
(BANK 0)
(BANK 0)
t
RAS
t
RP
(BANK 1)
(BANK1)
t
RC
(BANK 1)
<
ACT 0>
<ACT1>
<
READ 0
READA 0
>
<
READ 1
READA 1>
>
<
PRE 0>
<
ACT 0>
<PRE 1>
<
>
<
Undefined
Don't Care
CAS latency = 2, burstlength = 2
Note 1: A8,A9 = Don’t Care.
44
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Rev. D
11/03/06
®
IS42S16100C1
ISSI
Write Cycle
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCHI
tCKS
t
CK
t
CL
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
(1)
tAS
tAH
ROW
ROW
COLUMN m
ROW
A0-A9
BANK 0 AND 1
BANK 0 OR 1
t
AS
t
t
AH
AH
NO PRE
BANK 1
ROW
A10
A11
tAS
BANK 1
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
BANK 0
tCS
t
CH
DQM
DQ
t
DH
t
DS
t
DS
t
DH
tDS
t
DH
t
DS
tDH
D
IN m+2
D
IN
m
D
IN m+3
D
IN m+1
t
RCD
RAS
RC
tDPL
t
RCD
RAS
RC
t
RP
t
t
t
t
<
<
PRE
>
>
<
ACT>
<WRIT
>
<ACT>
PALL
Undefined
Don't Care
CAS latency = 2, burstlength = 4
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
45
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Write Cycle / Auto-Precharge
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCHI
tCKS
tCK
t
CL
CKE
CS
t
t
CKA
t
CS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
t
AS
tAH
(1)
ROW
ROW
COLUMN m
ROW
A0-A9
t
AS
t
AH
AH
ROW
AUTO PRE
BANK 1
A10
A11
t
t
AS
BANK 1
BANK 1
BANK 0
BANK 0
BANK 0
tCS
tCH
DQM
DQ
t
DH
t
DS
tDS
t
DH
tDS
t
DH
tDS
tDH
D
IN m+2
D
IN
m
D
IN m+3
D
IN m+1
t
RCD
RAS
RC
tDAL
t
RCD
RAS
RC
tRP
t
t
t
t
<
ACT>
<
WRITA
>
<ACT>
Undefined
Don't Care
CAS latency = 2, burstlength = 4
Note 1: A8,A9 = Don’t Care.
46
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Write Cycle / Full Page
T0
T1
T2
T3
T4
T5
T258
T259
T260
T261
T262
CLK
tCHI
tCKS
tCS
tCL
tCK
CKE
CS
tCKA
tCH
tCS
tCS
tCS
tAS
tAS
tCH
tCH
tCH
tAH
RAS
CAS
WE
(1)
COLUMN m
ROW
ROW
A0-A9
tAH
tAH
A10
A11
BANK 0 OR 1
BANK 0
NO PRE
BANK 0
tAS
BANK 0
tCH
tCS
DQM
DQ
tDH
tDS
tDS
tDH tDS
tDH tDS
tDH
D
IN 0m+2
D
IN 0m
D
IN 0m-1
DIN 0m
D
IN 0m+1
tDPL
tRCD
tRAS
tRP
tRC
<BST>
<PRE 0>
<ACT 0>
<WRIT0>
Undefined
Don't Care
CAS latency = 2, burst length = full page
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
47
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Write Cycle / Ping-Pong Operation
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
t
CKS
tCK
t
CL
CKE
CS
t
t
CKA
t
CS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
t
t
AS
AS
tAH
(1)
(1)
ROW
ROW
COLUMN
ROW
ROW
ROW
COLUMN
A0-A9
AUTO PRE
AUTO PRE
t
AH
AH
ROW
A10
A11
NO PRE
BANK 1
BANK 0 OR 1
BANK 0
NO PRE
BANK 0
t
t
AS
BANK 0
BANK 0
BANK 1
tCH
tCS
DQM
DQ
t
DS
tDS
t
DS
tDS
tDS
t
DS
t
DS
tDS
DH
t
DH
t
DH
t
DH
t
DH
t
DH
t
DH
t
t
DH
D
IN 0m
D
IN 0m+1
D
IN 0m+2
D
IN 0m+3
D
IN 1m
D
IN 1m+1
D
IN 1m+2
D
IN 1m+3
t
RRD
(BANK 0 TO 1)
RCD
(BANK 0)
t
DPL
t
DPL
t
t
RCD
t
RCD
(BANK 1)
(BANK 0)
t
RP
t
RAS
t
RAS
(BANK 0)
(BANK 0)
(BANK 0)
t
RC
t
RC
(BANK 0)
(BANK 0)
t
RAS
(BANK 1)
t
RC
(BANK 1)
<ACT 0
>
<
ACT 1>
<
WRIT 0
WRITA 0
>
<
WRIT 1
WRITA 1>
>
<
PRE 0>
<
ACT 0>
<
>
<
Undefined
Don't Care
CAS latency = 2, burst length = 2
Note 1: A8,A9 = Don’t Care.
48
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Read Cycle / Page Mode
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCHI
tCKS
tCK
t
CL
CKE
CS
t
t
CKA
t
CS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
t
AS
AS
tAH
(1)
(1)
(1)
COLUMN m
ROW
ROW
COLUMN n
COLUMN o
AUTO PRE
A0-A9
BANK 0 AND 1
t
t
t
AH
AH
NO PRE
BANK 1
NO PRE
BANK 1
A10
A11
NO PRE
BANK 0 OR 1
BANK 1
t
AS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
BANK 0
BANK 0
t
CH
t
CS
tQMD
DQM
DQ
tAC
t
AC
t
AC
t
AC
t
AC
t
AC
t
OH
t
OH
t
OH
t
OH
t
OH
tOH
D
OUT
m
D
OUT m+1
D
OUT
n
D
OUT n+1
D
OUT
o
D
OUT o+1
t
LZ
tHZ
tRCD
tCAC
t
CAC
tCAC
tRQL
t
RAS
tRP
tRC
<
ACT>
<
READ>
<READ
>
<
READ
READA
>
<
PRE>
<
>
<PALL>
Undefined
Don't Care
CAS latency = 2, burst length = 2
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
49
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Read Cycle / Page Mode; Data Masking
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCHI
t
CKS
t
CK
t
CL
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
t
t
AS
AS
tAH
(1)
(1)
(1)
COLUMN m
ROW
ROW
COLUMN n
COLUMN o
AUTO PRE
A0-A9
BANK 0 AND 1
BANK 0 OR 1
t
AH
AH
NO PRE
BANK 1
NO PRE
BANK 1
A10
A11
NO PRE
NO PRE
CH
t
t
AS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
BANK 0
t
tQMD
t
CS
t
QMD
DQM
DQ
tAC
t
AC
t
AC
tAC
t
AC
t
OH
t
OH
m
t
OH
t
OH
tOH
D
OUT
D
OUT m+1
D
OUT
n
D
OUT
o
D
OUT o+1
t
LZ
tLZ
t
HZ
tHZ
t
RCD
tCAC
t
CAC
t
CAC
tRQL
tRAS
tRP
tRC
<
ACT>
<
READ>
<MASK
>
<
READ, ENB
READA, ENB
>
<
PRE>
<
>
<PALL>
Undefined
Don't Care
CAS latency = 2, burst length = 2
Note 1: A8,A9 = Don’t Care.
50
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Write Cycle / Page Mode
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
tCKS
tCK
tCL
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
t
AS
AS
tAH
(1)
(1)
(1)
COLUMN m
ROW
ROW
COLUMN n
COLUMN o
AUTO PRE
A0-A9
BANK 0 AND 1
t
t
AH
AH
NO PRE
BANK 1
NO PRE
BANK 1
A10
A11
NO PRE
BANK 0 OR 1
BANK 1
t
t
AS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
BANK 0
BANK 0
t
CH
tCS
DQM
DQ
t
DH
tDS
t
DS
t
DH
tDH
tDS
t
DH
t
DS
t
DH
tDS
tDH
tDS
D
IN
m
D
IN n
D
IN n+1
D
IN
o
D
IN o+1
D
IN m+1
tRCD
tDPL
tRAS
tRP
t
RC
<
ACT>
<WRIT
>
<
WRIT>
<
WRIT
WRITA
>
<
PRE
PALL
>
<
>
<
>
Undefined
Don't Care
CAS latency = 2, burst length = 2
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
51
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Write Cycle / Page Mode; Data Masking
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCHI
tCKS
t
CK
t
CL
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
(1)
t
t
AS
AS
tAH
(1)
(1)
COLUMN m
ROW
ROW
COLUMN n
COLUMN o
AUTO PRE
A0-A9
BANK 0 AND 1
BANK 1OR 0
t
t
AH
AH
NO PRE
BANK 1
NO PRE
BANK 1
A10
A11
NO PRE
t
AS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
BANK 0
t
CS
tCH
DQM
DQ
t
DH
t
DH
tDH
t
DS
tDS
t
DH
t
DS
t
DH
tDS
tDS
D
IN n
D
IN
o
D
IN
m
D
IN o+1
D
IN m+1
tRCD
tDPL
t
RAS
tRP
tRC
<
ACT>
<
WRIT>
<
WRIT>
<MASK
>
<
WRIT
WRITA
>
<
PRE
PALL
>
<
>
<
>
Undefined
Don't Care
CAS latency = 2, burst length = 2
Note 1: A8,A9 = Don’t Care.
52
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Read Cycle / Clock Suspend
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCHI
t
CKS
t
CKS
tCKH
t
CL
t
CK
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
t
AS
AS
tAH
(1)
COLUMN m
AUTO PRE
ROW
ROW
ROW
A0-A9
BANK 0 AND 1
BANK 0 OR 1
t
t
AH
AH
ROW
A10
A11
NO PRE
BANK 1
t
t
AS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
tCH
t
CS
t
QMD
DQM
DQ
tAC
t
AC
t
OH
t
OH
D
OUT
m
D
OUT m+1
t
LZ
t
HZ
t
RCD
tCAC
t
RAS
t
RAS
RC
tRP
t
t
RC
<
SPND>
<
SPND>
<
PRE
PALL
>
<
ACT 0>
<
READ
>
<ACT >
<
>
<
READ A
>
Undefined
Don't Care
CAS latency = 2, burst length = 2
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
53
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Write Cycle / Clock Suspend
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
t
CKS
tCKS
CL
tCKH
t
t
CK
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
t
AS
AS
tAH
(1)
COLUMN m
AUTO PRE
ROW
ROW
ROW
A0-A9
BANK 0 AND 1
BANK 0 OR 1
t
t
AH
AH
ROW
A10
A11
NO PRE
BANK 1
t
AS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
t
CH
t
CS
DQM
DQ
t
DS
tDS
t
DH
tDH
DIN
m
DIN m+1
t
RCD
tDPL
t
RAS
t
RAS
RC
tRP
t
t
RC
<SPND
>
<
<
PRE
>
>
<ACT>
<
WRIT, SPND
>
<ACT >
<
WRITA, SPND
>
PALL
Undefined
Don't Care
CAS latency = 2, burst length = 2
Note 1: A8,A9 = Don’t Care.
54
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Read Cycle / Precharge Termination
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCHI
tCKS
tCL
tCK
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
t
AS
AS
tAH
(1)
(1)
COLUMN m
COLUMN n
ROW
ROW
ROW
A0-A9
AUTO PRE
t
t
AH
AH
ROW
A10
A11
NO PRE
BANK 0 OR 1
BANK 0
NO PRE
BANK 0
BANK 1
t
t
AS
BANK 1
BANK 0
BANK 0
BANK 0
t
CS
t
CH
t
QMD
DQM
DQ
t
AC
t
AC
t
AC
tHZ
t
OH
t
OH
tOH
D
OUT
m
D
OUT m+1
D
OUT m+2
tLZ
t
RCD
tCAC
t
RQL
tCAC
t
RCD
RAS
RC
tRAS
RC
t
t
RP
t
t
<
PRE 0>
<
<
READ
>
>
<
ACT 0>
<
READ 0
>
<ACT >
READA
Undefined
Don't Care
CAS latency = 2, burst length = 4
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
55
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Write Cycle / Precharge Termination
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCHI
tCKS
t
CL
tCK
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
t
t
AS
AS
tAH
(1)
(1)
COLUMN m
COLUMN n
ROW
ROW
ROW
A0-A9
AUTO PRE
t
AH
AH
ROW
A10
A11
NO PRE
BANK 1
BANK 0 OR 1
BANK 0
NO PRE
BANK 0
BANK 1
t
t
AS
BANK 0
BANK 0
tCS
tCH
BANK 0
CS
tCS
tCH
t
DQM
DQ
t
DH
DS
t
DH
DS
tDH
tDH
tDS
t
t
tDS
D
IN 0m+2
D
IN 0m+1
D
IN 0m
D
IN 0n
t
RCD
t
RCD
RAS
RC
t
t
RAS
t
t
RP
RC
t
<PRE 0
>
<
<
WRIT
>
>
<ACT 0
>
<
WRIT 0
>
<ACT >
WRITA
Undefined
Don't Care
CAS latency = 2, burst length = 4
Note 1: A8,A9 = Don’t Care.
56
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Read Cycle / Byte Operation
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCHI
t
CKS
tCL
tCK
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
(1)
t
t
AS
AS
tAH
COLUMN m
AUTO PRE
ROW
ROW
ROW
A0-A9
BANK 0 AND 1
BANK 0 OR 1
t
AH
AH
ROW
A10
A11
NO PRE
t
t
AS
BANK 1
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
tCH
t
CS
t
QMD
UDQM
t
QMD
t
CS
t
CH
LDQM
tAC
tHZ
tAC
tAC
tOH
tOH
tLZ
tOH
tLZ
DQ8-15
DOUT
m
D
OUT m+2
DOUT m+3
t
AC
t
t
AC
t
OH
tOH
LZ
D
OUT m+1
DOUT
m
DQ0-7
t
RCD
t
CAC
t
QMD
t
RQL
t
RCD
RAS
RC
tRAS
RC
t
RP
t
t
t
<
PRE>
<ACT>
<
READ
READA
>
<
MASKU
>
<ACT>
<
ENBU, MASKL
>
<MASKL>
<
PALL>
<
>
Undefined
Don't Care
CAS latency = 2, burst length = 4
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
57
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Write Cycle / Byte Operation
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
t
CKS
t
CL
t
CK
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
t
AS
AS
tAH
(1)
COLUMN m
AUTO PRE
ROW
ROW
ROW
A0-A9
BANK 0 AND 1
BANK 0 OR 1
t
t
AH
AH
ROW
A10
A11
NO PRE
t
AS
BANK 1
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
t
CH
t
CS
UDQM
t
CS
t
CH
LDQM
DQ8-15
DQ0-7
t
t
DS
tDH
t
DH
t
DS
DH
tDS
D
IN
m
m
DIN m+1
D
IN m+3
t
DS
t
DH
t
DS
tDH
D
IN
DIN m+3
t
RCD
t
DPL
t
RCD
t
RAS
RC
tRP
t
RAS
t
t
RC
<
PRE
PALL
>
<
ACT>
<
WRIT
WRITA
>
<MASKL
>
<ACT>
<
MASK>
<ENB>
<
>
<
>
Undefined
Don't Care
CAS latency = 2, burst length = 4
Note 1: A8,A9 = Don’t Care.
58
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Read Cycle, Write Cycle / Burst Read, Single Write
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCHI
t
CKS
tCL
tCK
CKE
CS
t
t
CKA
CH
tCS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
(1)
(1)
t
AS
AS
tAH
COLUMN m
COLUMN n
AUTO PRE
ROW
ROW
A0-A9
BANK 0 AND 1
BANK 0 OR 1
t
t
t
AH
AH
NO PRE
BANK 1
A10
A11
NO PRE
t
AS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
tCS
tCH
tQMD
DQM
DQ
tAC
t
AC
t
AC
t
AC
tDS
t
OH
t
OH
t
OH
tOH
tDH
D
OUT
m
D
OUT m+1
D
OUT m+2
D
OUT m+3
D
IN
n
tLZ
tHZ
tRCD
tCAC
tDPL
t
RAS
RC
t
RP
t
<
WRIT
WRITA
>
<
PRE
PALL
>
<ACT>
<READ>
<
>
<
>
Undefined
Don't Care
CAS latency = 2, burst length = 4
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
59
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Read Cycle
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CLK
tCHI
t
CKS
tCL
tCK
CKE
CS
t
t
CKA
CH
tCS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
AS
AS
tAH
(1)
COLUMN m
ROW
ROW
ROW
A0-A9
A10
BANK 0 AND 1
BANK 0 OR 1
t
t
t
AH
AH
NO PRE
BANK 1
ROW
t
AS
BANK 1
BANK 1
BANK 0
BANK 1
BANK 0
A11
BANK 0
BANK 0
tCH
t
CS
tQMD
DQM
DQ
t
AC
t
AC
t
AC
t
AC
t
OH
t
OH
t
OH
tOH
D
OUT
m
D
OUT m+1
D
OUT m+2
D
OUT m+3
t
LZ
t
HZ
t
RCD
t
RCD
t
CAC
t
RQL
t
RAS
t
RAS
RC
tRP
t
RC
t
<
PRE>
<ACT
>
<READ>
<
ACT>
<
PALL>
Undefined
Don't Care
CAS latency = 3, burst length = 4
Note 1: A8,A9 = Don’t Care.
60
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Read Cycle / Auto-Precharge
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CLK
t
CHI
t
CKS
t
CL
t
CK
CKE
CS
t
t
CKA
t
CS
CH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
(1)
t
AS
AS
tAH
COLUMN
ROW
ROW
ROW
A0-A9
A10
AUTO PRE
t
t
t
AH
AH
ROW
t
AS
BANK 1
BANK 0
BANK 1
BANK 1
BANK 0
A11
BANK 0
t
CH
tCS
t
QMD
DQM
DQ
t
AC
t
AC
t
AC
t
AC
t
OH
t
OH
t
OH
tOH
D
OUT
m
D
OUT m+1
D
OUT m+2
D
OUT m+3
t
LZ
t
HZ
t
RCD
RAS
t
RCD
tCAC
t
PQL
RP
t
t
RAS
RC
t
t
RC
t
<ACT>
<ACT
>
<READA>
Undefined
Don't Care
CAS latency = 3, burst length = 4
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
61
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Read Cycle / Full Page
T0
T1
T2
T3
T4
T5
T6
T7
T8
T262
T263
T264
T265
CLK
t
CHI
tCKS
tCL
tCK
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
t
AS
AS
tAH
(1)
COLUMN
ROW
ROW
A0-A9
t
t
AH
AH
NO PRE
BANK 0
A10
A11
BANK 0 OR 1
BANK 0
t
t
AS
BANK 0
tCH
tCS
DQM
DQ
t
AC
t
AC
t
AC
t
AC
t
AC
t
OH
t
OH
t
OH
t
OH
t
OH
D
OUT 0m
D
OUT 0m+1
D
OUT 0m-1
D
OUT 0m
D
OUT 0m+1
t
LZ
t
HZ
t
RCD
(BANK 0)
RAS
(BANK 0)
t
CAC
tRBD
(BANK 0)
t
RP
t
(BANK 0)
t
RC
(BANK 0)
>
<
BST>
<
PRE 0>
<
ACT 0
<READ0>
Undefined
Don't Care
CAS latency = 3, burst length = full page
Note 1: A8,A9 = Don’t Care.
62
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Read Cycle / Ping Pong Operation (Bank Switching)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CLK
t
CHI
tCKS
t
CK
t
CL
CKE
CS
t
t
CKA
CH
tCS
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
t
AS
AS
tAH
(1)
(1)
COLUMN
ROW
ROW
ROW
ROW
ROW
COLUMN
A0-A9
AUTO PRE
AUTO PRE
t
t
t
AH
AH
ROW
A10
A11
NO PRE
BANK 1
BANK 0 OR 1
BANK1
NO PRE
BANK 0
BANK 0 OR 1
BANK 0
t
AS
BANK 0
BANK 0
BANK 1
t
CH
t
CS
t
QMD
DQM
DQ
t
AC
t
AC
t
AC
t
AC
tLZ
t
OH
t
OH
t
OH
t
OH
D
OUT 0m
D
OUT 0m+1
D
OUT 1m
D
OUT 1m+1
t
CAC
t
RCD
t
HZ
t
RRD
(BANK 0 TO 1)
RCD
(BANK 0)
(BANK 1)
(BANK 1)
t
CAC
t
t
RQL
(BANK 0)
RP
(BANK 0)
t
RCD
(BANK 0)
(BtARNAKS0)
(BANK 0)
t
t
RAS
(BANK 0)
t
RC
t
RC
(BANK 0)
(BANK 0)
t
RAS
t
RP
(BANK 1)
(BANK1)
t
RC
(BANK 1)
<
ACT 0>
<ACT1
>
<
READ 0
READA 0
>
<
READ 1
READA 1>
>
<PRE 0
>
<PRE 1
>
<
ACT 0>
<
>
<
Undefined
Don't Care
CAS latency = 3, burst length = 2
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
63
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Write Cycle
T12
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CLK
tCHI
tCKS
t
CK
t
CL
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
AS
tAH
(1)
ROW
COLUMN
ROW
A0-A9
BANK 0 AND 1
BANK 0 OR 1
t
AS
t
t
AH
AH
NO PRE
BANK 1
ROW
ROW
A10
A11
t
AS
BANK 1
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
BANK 0
t
CS
t
CH
DQM
DQ
t
DH
tDS
tDS
t
DH
m
t
DS
t
DH
t
DS
tDH
D
IN
D
IN m+2
D
IN m+3
D
IN m+1
t
RCD
RAS
RC
t
DPL
t
RCD
RAS
RC
tRP
t
t
t
t
<
<
PRE
>
>
<ACT>
<
WRIT>
<ACT>
PALL
Undefined
Don't Care
CAS latency = 3, burst length = 4
Note 1: A8,A9 = Don’t Care.
64
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Write Cycle / Auto-Precharge
T11
T12
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
tCKS
t
CK
tCL
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
tAS
tAH
(1)
ROW
ROW
COLUMN
ROW
A0-A9
A10
AUTO PRE
t
AS
t
AH
AH
ROW
t
t
AS
BANK 1
BANK 0
BANK 1
BANK 1
BANK 0
A11
BANK 0
tCS
t
CH
DQM
DQ
t
DH
tDS
t
DS
t
DH
t
DS
t
DH
t
DS
tDH
D
IN
m
D
IN m+2
D
IN m+3
D
IN m+1
t
RCD
RAS
RC
t
DAL
t
RCD
RAS
RC
t
RP
t
t
t
t
<ACT>
<
WRITA
>
<ACT>
Undefined
Don't Care
CAS latency = 3, burst length = 4
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
65
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Write Cycle / Full Page
T0
T1
T2
T3
T4
T5
T6
T259
T260
T261
T262
T263
T264
CLK
t
CHI
tCKS
t
CL
t
CK
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
t
t
AS
AS
tAH
(1)
COLUMN
NO PRE
BANK 0
ROW
ROW
A0-A9
t
t
AH
AH
A10
A11
BANK 0 OR 1
BANK 0
t
AS
BANK 0
t
CH
tCS
DQM
DQ
t
DH
tDS
t
DS
t
DH
tDS
t
DH
t
DS
tDH
D
IN 0m
D
IN 0m+2
D
IN 0m-1
DIN 0m
D
IN 0m+1
t
RCD
tDPL
t
RAS
RC
tRP
t
<BST>
<PRE 0>
<ACT 0
>
<WRIT0>
Undefined
Don't Care
CAS latency = 3, burst length = full page
Note 1: A8,A9 = Don’t Care.
66
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Write Cycle / Ping-Pong Operation (Bank Switching)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CLK
t
CHI
t
CKS
tCK
t
CL
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
t
AS
AS
tAH
(1)
(1)
ROW
ROW
ROW
ROW
ROW
ROW
COLUMN
COLUMN
A0-A9
AUTO PRE
AUTO PRE
t
AH
AH
A10
A11
NO PRE
BANK 1
NO PRE
BANK 0
BANK 0 OR 1
BANK 0
t
t
AS
BANK 0
BANK 1
BANK 0
BANK 1
t
CH
t
CS
DQM
DQ
t
DS
tDS
t
DS
tDS
t
DS
t
DS
t
DS
tDS
DH
t
DH
t
DH
t
DH
t
DH
t
DH
t
DH
t
tDH
D
IN 0m
D
IN 0m+1
D
IN 0m+2
D
IN 0m+3
D
IN 1m
D
IN 1m+1
D
IN 1m+2
D
IN 1m+3
t
RRD
(BANK 0 TO 1)
RCD
(BANK 0)
t
DPL
tDPL
(BANK 0)
t
t
RCD
t
RCD
RAS
RC
(BANK 1)
t
RP
t
RAS
t
(BANK 0)
(BANK 0)
t
RC
t
(BANK 0)
t
RAS
(BANK 1)
t
RC
(BANK 1)
<ACT 0
>
<
ACT 1>
<
WRIT 0
WRITA 0
>
<
WRIT 1
WRITA 1>
>
<
PRE 0
>
<ACT 0>
<
>
<
Undefined
Don't Care
CAS latency = 3, burst length = 4
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
67
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Read Cycle / Page Mode
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CLK
tCHI
t
CKS
t
CK
tCL
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
(1)
(1)
t
t
AS
AS
tAH
(1)
COLUMN m
ROW
ROW
COLUMN n
COLUMN o
AUTO PRE
A0-A9
A10
BANK 0 AND 1
BANK 0 OR 1
t
AH
AH
NO PRE
BANK 1
NO PRE
NO PRE
t
t
AS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
A11
BANK 0
tCH
t
CS
tQMD
DQM
DQ
t
AC
t
AC
t
AC
t
AC
t
AC
t
AC
tLZ
t
OH
t
OH
t
OH
t
OH
t
OH
t
OH
D
OUT
m
D
OUT m+1
D
OUT
n
D
OUT n+1
D
OUT
o
D
OUT o+1
tCAC
tHZ
t
CAC
tRCD
t
CAC
t
t
RQL
RP
t
RAS
tRC
<ACT>
<READ
>
<
READ>
<
READ
READA
>
<
PRE>
<
>
<PALL>
Undefined
Don't Care
CAS latency = 3, burst length = 2
Note 1: A8,A9 = Don’t Care.
68
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Read Cycle / Page Mode; Data Masking
T11
T12
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCHI
tCKS
tCK
t
CL
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
t
AS
AS
tAH
(1)
(1)
(1)
COLUMN m
ROW
ROW
COLUMN n
COLUMN o
AUTO PRE
A0-A9
A10
BANK 0 AND 1
BANK 0 OR 1
t
t
AH
AH
NO PRE
NO PRE
NO PRE
t
t
AS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
A11
t
CH
tQMD
t
CS
t
QMD
DQM
DQ
t
AC
t
AC
t
AC
t
AC
t
AC
t
OH
t
LZ
t
OH
m
t
OH
t
OH
t
OH
D
OUT
D
OUT m+1
D
OUT
n
D
OUT
o
D
OUT o+1
t
HZ
t
CAC
t
CAC
tRCD
t
CAC
t
RQL
tRAS
t
RP
tRC
<ACT>
<
READ>
<
READ>
<
READ, MASK
READA, MASK
>
<
ENB>
<
PRE
PALL
>
<
>
<
>
Undefined
Don't Care
CAS latency = 3, burst length = 2
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
69
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Write Cycle / Page Mode
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CLK
t
CHI
t
CKS
t
CK
t
CL
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
t
AS
AS
t
AH
(1)
(1)
(1)
COLUMN m
ROW
ROW
COLUMN n
COLUMN o
AUTO PRE
A0-A9
BANK 0 AND 1
BANK 0 OR 1
t
t
AH
AH
NO PRE
BANK 1
NO PRE
BANK 1
A10
A11
NO PRE
t
AS
BANK 1
BANK 0
BANK 0
BANK 1
BANK 0
BANK 0
BANK 0
t
CH
t
CS
t
DQM
DQ
t
DH
t
DS
tDH
tDH
DS
t
DH
t
DS
t
DH
tDS
t
DS
DIN m
DIN n
DIN o
DIN o+1
DIN m+1
t
RCD
t
DPL
t
RAS
tRP
t
RC
<ACT>
<
WRIT>
<WRIT
>
<
MASK>
<
WRIT
WRITA
>
<
PRE
PALL
>
<
>
<
>
Undefined
Don't Care
CAS latency = 3, burst length = 2
Note 1: A8,A9 = Don’t Care.
70
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Write Cycle / Page Mode; Data Masking
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CLK
tCHI
tCKS
t
CK
tCL
CKE
CS
t
t
CKA
t
CS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
t
t
AS
AS
t
AH
(1)
(1)
(1)
COLUMN m
ROW
ROW
COLUMN n
COLUMN o
AUTO PRE
A0-A9
A10
BANK 0 AND 1
BANK 1OR 0
t
AH
AH
NO PRE
NO PRE
NO PRE
t
BANK 1
BANK 0
t
AS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
A11
t
CS
t
CH
DQM
DQ
t
DH
t
DH
t
DH
tDS
t
DS
t
DH
t
DS
t
DH
tDS
tDS
D
IN n
D
IN
o
D
IN
m
D
IN o+1
D
IN m+1
tRCD
t
DPL
t
RAS
tRP
tRC
<ACT>
<WRIT
>
<WRIT
>
<
MASK>
<
WRIT
WRITA
>
<
PRE
PALL
>
<
>
<
>
Undefined
Don't Care
CAS latency = 3, burst length = 2
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
71
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Read Cycle / Clock Suspend
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CLK
tCHI
tCKS
t
CKS
t
CKH
tCL
tCK
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
t
AS
AS
t
AH
(1)
COLUMN m
AUTO PRE
ROW
ROW
A0-A9
A10
BANK 0 AND 1
BANK 0 OR 1
t
t
t
AH
AH
NO PRE
t
AS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
A11
tCS
t
CH
tQMD
DQM
DQ
t
AC
t
AC
t
OH
t
OH
D
OUT
m
DOUT m+1
t
LZ
t
HZ
tRCD
tCAC
t
RAS
RC
t
RP
t
<SPND
>
<
SPND
>
<
PRE
PALL
>
<
ACT
>
<
READ
>
<
>
<
READ A
>
Undefined
Don't Care
CAS latency = 3, burst length = 2
Note 1: A8,A9 = Don’t Care.
72
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Write Cycle / Clock Suspend
T11
T12
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCHI
tCKS
t
CKS
tCKH
tCL
tCK
CKE
CS
t
t
CKA
t
CS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
t
t
AS
AS
tAH
(1)
COLUMN m
AUTO PRE
ROW
ROW
ROW
A0-A9
A10
BANK 0 AND 1
BANK 0 OR 1
t
AH
AH
ROW
NO PRE
BANK 1
t
t
AS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
A11
BANK 0
t
CH
t
CS
DQM
DQ
tDS
tDS
tDH
tDH
DIN
m
DIN m+1
tRCD
tDPL
t
RAS
t
RAS
RC
tRP
t
t
RC
<SPND
>
<
<
PRE
>
>
<ACT
>
<
WRIT, SPND
>
<ACT >
<
WRITA, SPND
>
PALL
Undefined
Don't Care
CAS latency = 3, burst length = 2
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
73
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Read Cycle / Precharge Termination
T11
T12
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
tCKS
tCL
tCK
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
t
AS
AS
tAH
(1)
COLUMN m
ROW
ROW
ROW
A0-A9
t
t
t
AH
AH
ROW
A10
A11
BANK 0 OR 1
BANK 0
NO PRE
BANK 0
t
AS
BANK 1
BANK 0
BANK 0
tCH
tCS
tQMD
DQM
DQ
t
AC
t
AC
t
AC
tHZ
t
OH
t
OH
tOH
D
OUT
m
D
OUT m+1
D
OUT m+2
tLZ
t
RCD
tCAC
t
RQL
RP
t
RCD
RAS
tRAS
RC
t
t
t
t
RP
<PRE 0>
<
ACT 0
>
<
READ 0
>
<ACT>
Undefined
Don't Care
CAS latency = 3, burst length = 2
Note 1: A8,A9 = Don’t Care.
74
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Write Cycle / Precharge Termination
T11
T12
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCHI
t
CKS
tCL
tCK
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
t
AS
AS
tAH
(1)
COLUMN m
ROW
ROW
ROW
A0-A9
A10
t
t
AH
AH
ROW
BANK 0 OR 1
BANK 0
NO PRE
BANK 0
t
AS
BANK 1
BANK 0
A11
t
CS
BANK 0
t
CS
tCH
tCH
DQM
DQ
t
DH
DS
t
DH
DS
tDH
t
DS
t
t
DIN 0m+2
D
IN 0m+1
D
IN 0m
t
RCD
tRCD
t
RAS
RC
t
RAS
t
RP
t
t
RP
<ACT >
<PRE 0>
<ACT 0
>
<WRIT 0>
Undefined
Don't Care
CAS latency = 3, burst length = 4
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
75
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Read Cycle / Byte Operation
T12
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CLK
t
CHI
tCKS
t
CL
t
CK
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
AS
AS
tAH
(1)
COLUMN m
AUTO PRE
ROW
ROW
ROW
A0-A9
t
BANK 0 AND 1
BANK 0 OR 1
t
t
AH
AH
ROW
A10
A11
NO PRE
t
AS
BANK 1
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
tCH
t
CS
t
QMD
QMD
UDQM
t
tCS
t
CH
LDQM
tAC
tHZ
tAC
t
AC
tHZ
t
OH
tLZ
t
OH
tLZ
DQ8-15
DOUT
m
DOUT m+2
DOUT m+3
t
AC
t
t
AC
t
HZ
LZ
t
OH
t
OH
DOUT m+1
D
OUT
m
DQ0-7
t
RCD
t
CAC
t
QMD
t
RQL
RP
t
RCD
RAS
RP
tRAS
RC
t
t
t
t
<
PRE>
<ACT>
<
READ
READA
>
<MASKU
>
<ACT>
<
ENBU, MASKL
>
<MASKL>
<
PALL>
<
>
Undefined
Don't Care
CAS latency = 3, burst length = 4
Note 1: A8,A9 = Don’t Care.
76
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Write Cycle / Byte Operation
T11
T12
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
t
CKS
tCL
t
CK
CKE
CS
t
t
CKA
t
CS
CH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
AS
AS
tAH
(1)
COLUMN m
AUTO PRE
ROW
ROW
ROW
A0-A9
t
BANK 0 AND 1
BANK 0 OR 1
t
t
AH
AH
ROW
A10
A11
NO PRE
BANK 1
t
AS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
t
CS
tCH
UDQM
tCS
t
CH
LDQM
DQ8-15
DQ0-7
t
t
DS
DH
tDH
t
DH
t
DS
tDS
D
IN
m
m
DIN m+1
D
IN m+3
t
DS
t
DH
t
DS
tDH
D
IN
D
IN m+3
t
RCD
t
DPL
t
RCD
RAS
RP
tRAS
RC
t
RP
t
t
t
<
PRE
PALL
>
<
ACT>
<
WRIT
WRITA
>
<
MASKL
>
<ACT>
<
MASK>
<ENB>
<
>
<
>
Undefined
Don't Care
CAS latency = 3, burst length = 4
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
77
Rev. D
11/03/06
®
IS42S16100C1
ISSI
Read Cycle, Write Cycle / Burst Read, Single Write
T11
T12
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
t
CKS
t
CL
t
CK
CKE
CS
t
t
CKA
t
CS
CH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
AS
AS
t
AH
(1)
(1)
COLUMN m
COLUMN n
AUTO PRE
ROW
ROW
A0-A9
A10
BANK 0 AND 1
BANK 0 OR 1
t
t
t
AH
AH
NO PRE
BANK 1
NO PRE
t
AS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
A11
BANK 0
t
CS
t
CH
t
QMD
DQM
DQ
t
AC
t
AC
t
DS
t
OH
t
OH
t
DH
D
OUT
m
D
OUT m+1
DIN
n
tLZ
t
HZ
t
RC
t
CAC
t
DPL
t
RAS
RC
t
RP
t
<
WRIT
WRITA
>
<
PRE
PALL
>
<
ACT>
<READ
>
<
>
<
>
Undefined
Don't Care
CAS latency = 3, burst length = 2
Note 1: A8,A9 = Don’t Care.
78
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
11/03/06
®
IS42S16100C1
ISSI
ORDERING INFORMATION
Commercial Range: 0°C to 70°C
Frequency
Speed(ns)
Order Part No.
Package
200 MHz
5
6
7
IS42S16100C1-5T
IS42S16100C1-5TL
IS42S16100C1-6T
IS42S16100C1-6TL
IS42S16100C1-7T
IS42S16100C1-7TL
IS42S16100C1-7B
IS42S16100C1-7BL
400-mil TSOP II
400-mil TSOP II, Lead-free
400-mil TSOP II
400-mil TSOP II, Lead-free
400-mil TSOP II
400-mil TSOP II, Lead-free
60-ball fBGA
166 MHz
143MHz
60-ballfBGA,Lead-free
Industrial Range: -40°C to 85°C
Frequency
Speed(ns)
Order Part No.
Package
143MHz
7
IS42S16100C1-7TI
400-mil TSOP II
IS42S16100C1-7TLI
IS42S16100C1-7BI
IS42S16100C1-7BLI
400-mil TSOP II, Lead-free
60-ball fBGA
60-ballfBGA,Lead-free
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
79
Rev. D
11/03/06
®
PACKAGING INFORMATION
ISSI
Mini Ball Grid Array
Package Code: B (60-Ball)
ø 0.40 + +/-0.05 (60X)
7
6
5
4
3
2 1
1
2 3 4 5 6 7
A
B
C
D
E
F
A
B
C
D
E
F
e
G
H
J
G
H
J
D
D1
K
L
K
L
M
N
P
R
M
N
P
R
e
E1
E
A1
A
Notes:
SEATING PLANE
1. Controlling dimensions are in millimeters.
2. 0.65 mm Ball Pitch
mBGA - 10.1mm x 6.4mm
MILLIMETERS
INCHES
Min. Typ. Max.
Sym. Min. Typ. Max.
No.
Leads
60
A
—
—
1.20
—
—
0.047
A1
D
0.23
0.28 0.33
0.009 0.011 0.013
0.394 0.398 0.402
10.00 10.10 10.20
D1
E
—
6.30
—
9.10
—
—
0.358
—
6.40 6.50
0.248 0.252 0.256
E1
e
3.90
0.65
—
—
—
—
0.154
0.026
—
—
—
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
02/16/06
®
PACKAGING INFORMATION
ISSI
Plastic TSOP
Package Code: T (Type II)
N
N/2+1
Notes:
1. Controlling dimension: millimieters,
unless otherwise specified.
2. BSC = Basic lead spacing
between centers.
3. Dimensions D and E1 do not
include mold flash protrusions and
should be measured from the
bottom of the package.
E
E1
4. Formed leads shall be planar with
respect to one another within
0.004 inches at the seating plane.
1
N/2
D
SEATING PLANE
A
ZD
.
L
α
e
b
C
A1
Plastic TSOP (T - Type II)
Millimeters Inches
Millimeters
Inches
Millimeters
Inches
Symbol Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Ref. Std.
No. Leads (N)
32
44
50
A
A1
b
C
D
E1
E
e
—
1.20
—
0.047
—
1.20
0.15
0.45
0.21
—
0.047
—
1.20
—
0.047
0.05 0.15
0.30 0.52
0.12 0.21
20.82 21.08
10.03 10.29
11.56 11.96
1.27 BSC
0.002 0.006
0.012 0.020
0.005 0.008
0.820 0.830
0.391 0.400
0.451 0.466
0.050 BSC
0.05
0.30
0.12
18.31 18.52
10.03 10.29
11.56 11.96
0.80 BSC
0.002 0.006
0.012 0.018
0.005 0.008
0.721 0.729
0.395 0.405
0.455 0.471
0.032 BSC
0.05 0.15
0.30 0.45
0.12 0.21
20.82 21.08
10.03 10.29
11.56 11.96
0.80 BSC
0.002 0.006
0.012 0.018
0.005 0.008
0.820 0.830
0.395 0.405
0.455 0.471
0.031 BSC
L
ZD
α
0.40 0.60
0.95 REF
0.016 0.024
0.037 REF
0.41
0.81 REF
0°
0.60
0.016 0.024
0.032 REF
0.40 0.60
0.88 REF
0.016 0.024
0.035 REF
0°
5°
0°
5°
5°
0°
5°
0°
5°
0°
5°
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
06/18/03
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